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XCR3032-8VQ44C

更新时间：2024-09-18 12:59:53

品牌：XILINX

描述：EE PLD, 10.5ns, CMOS, PQFP44, PLASTIC, VQFP-44

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XCR3032-8VQ44C 概述

EE PLD, 10.5ns, CMOS, PQFP44, PLASTIC, VQFP-44 可编程逻辑器件

XCR3032-8VQ44C 规格参数

生命周期：	Obsolete	零件包装代码：	QFP
包装说明：	TQFP,	针数：	44
Reach Compliance Code：	unknown	HTS代码：	8542.39.00.01
风险等级：	5.66	Is Samacsys：	N
最大时钟频率：	74 MHz	JESD-30 代码：	S-PQFP-G44
长度：	10 mm	专用输入次数：	2
I/O 线路数量：	32	端子数量：	44
最高工作温度：	70 °C	最低工作温度：
组织：	2 DEDICATED INPUTS, 32 I/O	输出函数：	MACROCELL
封装主体材料：	PLASTIC/EPOXY	封装代码：	TQFP
封装形状：	SQUARE	封装形式：	FLATPACK, THIN PROFILE
可编程逻辑类型：	EE PLD	传播延迟：	10.5 ns
认证状态：	Not Qualified	座面最大高度：	1.2 mm
最大供电电压：	3.6 V	最小供电电压：	3 V
标称供电电压：	3.3 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子形式：	GULL WING	端子节距：	0.8 mm
端子位置：	QUAD	宽度：	10 mm
Base Number Matches：	1

XCR3032-8VQ44C 数据手册

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XCR3032: 32 Macrocell CPLD

14*

DS038 (v1.3) October 9, 2000

Product Specification

CMOS process technology and the patented full CMOS

FZP design technique. For 5V applications, Xilinx also

offers the high speed XCR5032 CPLD that offers pin-to-pin

speeds of 6 ns.

Features

•

Industry's first TotalCMOS™ PLD - both CMOS design

and process technologies

•

Fast Zero Power (FZP™) design technique provides

ultra-low power and very high speed

High speed pin-to-pin delays of 8ns

Ultra-low static power of less than 35 µA

100% routable with 100% utilization while all pins and

all macrocells are fixed

The Xilinx FZP CPLDs utilize the patented XPLA

(eXtended Programmable Logic Array) architecture. The

XPLA architecture combines the best features of both PLA

and PAL type structures to deliver high speed and flexible

logic allocation that results in superior ability to make

design changes with fixed pinouts. The XPLA structure in

each logic block provides a fast 8 ns PAL path with five ded-

icated product terms per output. This PAL path is joined by

an additional PLA structure that deploys a pool of 32 prod-

uct terms to a fully programmable OR array that can allo-

cate the PLA product terms to any output in the logic block.

This combination allows logic to be allocated efficiently

throughout the logic block and supports as many as 37

product terms on an output. The speed with which logic is

allocated from the PLA array to an output is only 2.5 ns,

regardless of the number of PLA product terms used, which

results in worst case t_PD's of only 10.5 ns from any pin to

any other pin. In addition, logic that is common to multiple

outputs can be placed on a single PLA product term and

shared across multiple outputs via the OR array, effectively

increasing design density.

•

Deterministic timing model that is extremely simple to

use

•

Two clocks available

Programmable clock polarity at every macrocell

Support for asynchronous clocking

Innovative XPLA™ architecture combines high speed

with extreme flexibility

•

1000 erase/program cycles guaranteed

20 years data retention guaranteed

Logic expandable to 37 product terms

PCI compliant

•

Advanced 0.5µ E²CMOS process

Security bit prevents unauthorized access

Design entry and verification using industry standard

and Xilinx CAE tools

•

Reprogrammable using industry standard device

programmers

Innovative Control Term structure provides either sum

terms or product terms in each logic block for:

The XCR3032 CPLDs are supported by industry standard

CAE tools (Cadence/OrCAD, Exemplar Logic, Mentor,

Synopsys, Synario, Viewlogic, and Synplicity), using text

(ABEL, VHDL, Verilog) and/or schematic entry. Design ver-

ification uses industry standard simulators for functional

and timing simulation. Development is supported on per-

sonal computer, Sparc, and HP platforms. Device fitting

uses a Xilinx developed tool, XPLA Professional (available

on the Xilinx web site).

Programmable 3-state buffer

Asynchronous macrocell register preset/reset

•

Programmable global 3-state pin facilitates ‘bed of nails'

testing without using logic resources

Available in both PLCC and VQFP packages

Description

The XCR3032 CPLD is reprogrammable using industry

standard device programmers from vendors such as Data

I/O, BP Microsystems, SMS, and others.

The XCR3032 CPLD (Complex Programmable Logic

Device) is the first in a family of CoolRunner^®CPLDs from

Xilinx. These devices combine high speed and zero power

in a 32 macrocell CPLD. With the FZP design technique,

the XCR3032 offers true pin-to-pin speeds of 8 ns, while

simultaneously delivering power that is less than 35 µA at

standby without the need for “turbo bits” or other power

down schemes. By replacing conventional sense amplifier

methods for implementing product terms (a technique that

has been used in PLDs since the bipolar era) with a cas-

caded chain of pure CMOS gates, the dynamic power is

also substantially lower than any competing CPLD. These

devices are the first TotalCMOS PLDs, as they use both a

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XCR3032: 32 Macrocell CPLD

configured as either SUM or PRODUCT terms, and are

XPLA Architecture

used to control the preset/reset and output enables of the

16 macrocells’ flip-flops. The PAL array consists of a pro-

grammable AND array with a fixed OR array, while the PLA

array consists of a programmable AND array with a pro-

grammable OR array. The PAL array provides a high speed

path through the array, while the PLA array provides

increased product term density.

Figure 1 shows a high level block diagram of a 32 macro-

cell device implementing the XPLA architecture. The XPLA

architecture consists of logic blocks that are interconnected

by a Zero-power Interconnect Array (ZIA). The ZIA is a vir-

tual crosspoint switch. Each logic block is essentially a

36V16 device with 36 inputs from the ZIA and 16 macro-

cells. Each logic block also provides 32 ZIA feedback paths

from the macrocells and I/O pins.

Each macrocell has five dedicated product terms from the

PAL array. The pin-to-pin t_PDof the XCR3032 device

through the PAL array is 8 ns. If a macrocell needs more

than five product terms, it simply gets the additional product

terms from the PLA array. The PLA array consists of 32

product terms, which are available for use by all 16 macro-

cells. The additional propagation delay incurred by a mac-

rocell using one or all 32 PLA product terms is just 2.5 ns.

So the total pin-to-pin t_PDfor the XCR3032 using six to 37

product terms is 10.5 ns (8 ns for the PAL + 2.5 ns for the

PLA).

From this point of view, this architecture looks like many

other CPLD architectures. What makes the CoolRunner

family unique is what is inside each logic block and the

design technique used to implement these logic blocks.

The contents of the logic block will be described next.

Logic Block Architecture

Figure 3 illustrates the logic block architecture. Each logic

block contains control terms, a PAL array, a PLA array, and

16 macrocells. The six control terms can individually be

MC1

MC2

LOGIC

BLOCK

LOGIC

BLOCK

I/O

MC16

ZIA

MC1

MC2

MC1

MC2

LOGIC

BLOCK

LOGIC

BLOCK

I/O

MC16

SP00439

Figure 1: Xilinx XPLA CPLD Architecture

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XCR3032: 32 Macrocell CPLD

36 ZIA INPUTS

CONTROL

PAL

ARRAY

PLA

ARRAY

(32)

SP00435A

Figure 2: Xilinx XPLA Logic block Architecture

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XCR3032: 32 Macrocell CPLD

This pin is provided to support "In-Circuit Testing" or

"Bed-of-Nails” testing.

Macrocell Architecture

Figure 3 shows the architecture of the macrocell used in

the CoolRunner family. The macrocell consists of a flip-flop

that can be configured as either a D- or T-type. A D-type

flip-flop is generally more useful for implementing state

machines and data buffering. A T-type flip-flop is generally

more useful in implementing counters. All CoolRunner™

family members provide both synchronous and asynchro-

nous clocking and provide the ability to clock off either the

falling or rising edges of these clocks. These devices are

designed such that the skew between the rising and falling

edges of a clock are minimized for clocking integrity. There

are two clocks (CLK0 and CLK1) available on the

XCR3032 device. Clock 0 (CLK0) is designated as the

"synchronous" clock and must be driven by an external

source. Clock 1 (CLK1) can either be used as a synchro-

nous clock (driven by an external source) or as an asyn-

chronous clock (driven by a macrocell equation). The

timing for asynchronous clocks is different in that the t_CO

time is extended by the amount of time that it takes for the

signal to propagate through the array and reach the clock

network, and the t_SUtime is reduced.

There are two feedback paths to the ZIA: one from the

macrocell, and one from the I/O pin. The ZIA feedback path

before the output buffer is the macrocell feedback path,

while the ZIA feedback path after the output buffer is the I/O

pin ZIA path. When the macrocell is used as an output, the

output buffer is enabled, and the macrocell feedback path

can be used to feedback the logic implemented in the mac-

rocell. When the I/O pin is used as an input, the output

buffer will be 3-stated and the input signal will be fed into

the ZIA via the I/O feedback path, and the logic imple-

mented in the buried macrocell can be fed back to the ZIA

via the macrocell feedback path. It should be noted that

unused inputs or I/Os should be properly terminated.

Terminations

The CoolRunner XCR3032 CPLDs are TotalCMOS

devices. As with other CMOS devices, it is important to

consider how to properly terminate unused inputs and I/O

pins when fabricating a PC board. The XCR3032 devices

do not have on-chip termination circuits, so it is recom-

mended that unused inputs and I/O pins be properly termi-

nated. Allowing unused inputs and I/O pins to float can

cause the voltage to be in the linear region of the CMOS

input structures, which can increase the power consump-

tion of the device. Xilinx recommends the use of 10KΩ

pull-up resistors for the termination. Using pull-up resistors

allows the flexibility of using these pins should late design

changes require additional I/O. These unused pins may

also be tied directly to V_CC, but this will make it more diffi-

cult to reclaim the use of the pin, should this be needed by

a subsequent design revision. See the application note Ter-

minating Unused I/O Pins in Xilinx XPLA1 and XPLA2

CoolRunner CPLDs for more information.

Two of the control terms (CT0 and CT1) are used to control

the Preset/Reset of the macrocell's flip-flop. The Pre-

set/Reset feature for each macrocell can also be disabled.

Note that the Power-on Reset leaves all macrocells in the

"zero" state when power is properly applied. The other four

control terms (CT2-CT5) can be used to control the Output

Enable of the macrocell's output buffers. The reason there

are as many control terms dedicated for the Output Enable

of the macrocell is to insure that all CoolRunner devices are

PCI compliant. The macrocell's output buffers can also be

always enabled or disabled. All CoolRunner devices also

provide a Global 3-state (GTS) pin, which, when enabled

and pulled Low, will 3-state all the outputs of the device.

TO ZIA

PAL

PLA

D/T

INIT

(P or R)

GTS

CLK0

CLK1

GND

CT0

CT1

CT2

CT3

CT4

CT5

GND

SP00440

Figure 3: XCR3032 Macrocell Architecture

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XCR3032: 32 Macrocell CPLD

t_SU= 6.5 ns, and the t_CO= 7.5 ns. If an output is using six to

37 product terms, an additional 2.5 ns must be added to the

t_PDand t_SUtiming parameters to account for the time to

propagate through the PLA array.

Simple Timing Model

Figure 5 shows the CoolRunner Timing Model. The Cool-

Runner timing model looks very much like a 22V10 timing

model in that there are three main timing parameters,

including t_PD, t_SU, and t_CO. In other architectures, the user

may be able to fit the design into the CPLD, but is not sure

whether system timing requirements can be met until after

the design has been fit into the device. This is because the

timing models of competing architectures are very complex

and include such things as timing dependencies on the

number of parallel expanders borrowed, sharable expand-

ers, varying number of X and Y routing channels used, etc.

In the XPLA architecture, the user knows up front whether

the design will meet system timing requirements. This is

due to the simplicity of the timing model. For example, in

the XCR3032 device, the user knows up front that if a given

output uses five product terms or less, the t_PD= 8 ns, the

TotalCMOS Design Technique for Fast Zero

Power

Xilinx is the first to offer a TotalCMOS CPLD, both in pro-

cess technology and design technique. Xilinx employs a

cascade of CMOS gates to implement its Sum of Products

instead of the traditional sense amp approach. This CMOS

gate implementation allows Xilinx to offer CPLDs which are

both high performance and low power, breaking the para-

digm that to have low power, you must have low perfor-

mance. Refer to Figure 6 and Table 1 showing the I_CCvs.

Frequency of our XCR3032 TotalCMOS CPLD.

= COMBINATORIAL PAL ONLY

= COMBINATORIAL PAL + PLA

PD_PAL

PD_PLA

INPUT PIN

OUTPUT PIN

REGISTERED

= PAL ONLY

REGISTERED

SU_PAL

= PAL + PLA

SU_PLA

INPUT PIN

OUTPUT PIN

SP00441

GLOBAL CLOCK PIN

Figure 4: CoolRunner Timing Model

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XCR3032: 32 Macrocell CPLD

TYPICAL

(mA)

100

110

120

130

FREQUENCY (MHz)

SP00443

Figure 5: I_CCvs. Frequency at V_CC= 3.3V, 25°C

Table 1: I_CCvs. Frequency (V_CC= 3.3V, 25°C)

Frequency (MHz)

100

110

120

130

Typical I_CC(mA)

0.01 2.37 4.65 6.80 9.06 11.1 13.5 15.5 17.4 20.0 22.1 24.4 26.6 28.5

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XCR3032: 32 Macrocell CPLD

Absolute Maximum Ratings¹

Symbol

V_CC

Parameter

Min.

-0.5

-1.2

-0.5

-30

Max.

7.0

Unit

Supply voltage²

V_I

Input voltage

V_CC+0.5

V_OUT

I_IN

I_OUT

T_J

Output voltage

Input current

°C

Output current

-100

-40

100

Maximum junction temperature

Storage temperature

150

T_str

Notes:

-65

150

1. Stresses above those listed may cause malfunction or permanent damage to the device. This is a stress rating only.

Functional operation at these or any other condition above those indicated in the operational and programming specification

is not implied.

2. The chip supply voltage must be monotonic.

Operating Range

Product Grade

Commercial

Industrial

Temperature

0 to +70°C

Voltage

3.3V ± 10%

-40 to +85°C

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XCR3032: 32 Macrocell CPLD

DC Electrical Characteristics For Commercial Grade Devices

Commercial: 0°C ≤ T_AMB≤ +70°C; 3.0V ≤ V_CC≤ 3.6V

Symbol

V_IL

Parameter

Input voltage low

Test Conditions

V_CC= 3.0V

V_CC= 3.6V

Min.

Max.

Unit

0.8

V_IH

V_I

Input voltage high

2.0

Input clamp voltage

V_CC= 3.0V, I_IN= -18 mA

V_CC= 3.0V, I_OL= 8 mA

-1.2

0.5

V_OL

V_OH

I_IL

Output voltage low

Output voltage high

V_CC= 3.0V, I_OH= -8 mA

V_CC= 3.6V (except CKO), V_IN= 0V

V_CC= 3.6V, V_IN= 3.0V

2.4

-10

Input leakage current low

Input leakage current high

Clock input leakage current

µA

I_IH

I_IL

V_CC= 3.6V, V_IN= 0.4V

I_OZL

I_OZH

I_CCQ

I_CCD

3-stated output leakage current low V_CC= 3.6V, V_IN= 0.4V

3-stated output leakage current high V_CC= 3.6V, V_IN= 3.0V

Standby current

Dynamic current

V_CC= 3.6V, T_AMB= 0°C

1, 2

V_CC= 3.6V, T_AMB= 0°C at 1 MHz

V_CC= 3.6V, T_AMB= 0°C at 50 MHz

0.5

I_OS

C_IN

Short circuit output current³

One pin at a time for no longer than 1

second

-5

-100

Input pin capacitance³

Clock input capacitance³

I/O pin capacitance³

T_AMB= 25°C, f = 1 MHz

C_CLK

C_I/O

Notes:

1. See Table 1 on page 6 for typical values.

2. This parameter measured with a 16-bit, loadable up/down counter loaded into every logic block, with all outputs enabled and

unloaded. Inputs are tied to V_CCor ground. This parameter guaranteed by design and characterization, not testing.

3. Typical values, not tested.

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XCR3032: 32 Macrocell CPLD

AC Electrical Characteristics¹For Commercial Grade Devices

Commercial: 0°C ≤ T_AMB≤ + 70°C; 3.0V ≤ V_CC≤ 3.6V

Symbol

Parameter

Unit

Min. Max. Min. Max. Min. Max.

t_{PD_PAL}Propagation delay time, input (or feedback node) to output through

PAL

10.5

t_{PD_PLA}Propagation delay time, input (or feedback node) to output through

PAL + PLA

t_CO

Clock to out (global synchronous clock from pin)

6.5

t_{SU_PAL}Setup time (from input or feedback node) through PAL

8.5

10.5

13.5

t_{SU_PLA}Setup time (from input or feedback node) through PAL + PLA

11.5

t_H

Hold time

t_CH

Clock High time

t_CL

Clock Low time

t_R

Input rise time

t_F

Input fall time

Maximum FF toggle rate²(1/t_CH+ t_CL

Maximum internal frequency²(1/t_SUPAL+ t_CF

Maximum external frequency²(1/t_SUPAL+ t_CO

f_MAX1

f_MAX2

f_MAX3

t_BUF

)

167

125

100

MHz

)

Output buffer delay time

1.5

6.5

1.5

8.5

1.5

t_{PDF_PAL}Input (or feedback node) to internal feedback node delay time

through PAL

10.5

t_{PDF_PLA}Input (or feedback node) to internal feedback node delay time

through PAL + PLA

11.5

13.5

t_CF

Clock to internal feedback node delay time

Delay from valid V_CCto valid reset

Input to output disable³

5.5

7.5

9.5

µs

t_INIT

t_ER

t_EA

Input to output valid

t_RP

Input to register preset

t_RR

Input to register reset

Notes:

1. Specifications measured with one output switching. See Figure 6 and Table 2 for derating.

2 . This parameter guaranteed by design and characterization, not by test.

3. Output C_L= 5 pF.

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XCR3032: 32 Macrocell CPLD

DC Electrical Characteristics For Industrial Grade Devices

Industrial: -40°C ≤ T_AMB≤ +85°C; 3.0V ≤ V_CC≤ 3.6V

Symbol

V_IL

Parameter

Input voltage low

Test Conditions

Min.

Max.

Unit

V_CC= 3.0V

V_CC= 3.6V

0.8

V_IH

V_I

Input voltage high

2.0

Input clamp voltage

V_CC= 3.0V, I_IN= -18 mA

V_CC= 3.0V, I_OL= 8 mA

-1.2

0.5

V_OL

V_OH

I_IL

Output voltage low

Output voltage high

V_CC= 3.0V, I_OH= -8 mA

V_CC= 3.6V (except CKO), V_IN= 0.4V

V_CC= 3.6V, V_IN= 3.0V

2.4

-10

Input leakage current low

Input leakage current high

Clock input leakage current

µA

I_IH

I_IL

V_CC= 3.6V, V_IN= 0.4V

I_OZL

I_OZH

I_CCQ

I_CCD

3-stated output leakage current low V_CC= 3.6V, V_IN= 0.4V

3-stated output leakage current high V_CC= 3.6V, V_IN= 3.0V

Standby current

Dynamic current

V_CC= 3.6V, T_AMB= -40°C

1, 2

V_CC= 3.6V, T_AMB= -40°C at 1 MHz

V_CC= 3.6V, T_AMB= -40°C at 50 MHz

0.5

I_OS

C_IN

Short circuit output current³

One pin at a time for no longer than

1 second

-5

-120

Input pin capacitance³

Clock input capacitance³

I/O pin capacitance³

T_AMB= 25°C, f = 1 MHz

C_CLK

C_I/O

Notes:

1. See Table 1 on page 6 for typical values.

2. This parameter measured with a 16-bit, loadable up/down counter loaded into every logic block, with all outputs enabled and

unloaded. Inputs are tied to V_CCor ground. This parameter guaranteed by design and characterization, not testing.

3. Typical values, not tested.

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XCR3032: 32 Macrocell CPLD

AC Electrical Characteristics¹For Industrial Grade Devices

Industrial: -40°C ≤ T_AMB≤ +85°C; 3.0V ≤ V_CC≤ 3.6V

Symbol

Parameter

UNIT

Min. Max. Min. Max.

t_{PD_PAL}

t_{PD_PLA}

Propagation delay time, input (or feedback node) to output through PAL

Propagation delay time, input (or feedback node) to output through

PAL + PLA

12.5

t_CO

Clock to out (global synchronous clock from pin)

t_{SU_PAL}

t_{SU_PLA}

t_H

Setup time (from input or feedback node) through PAL

10.5

13.5

Setup time (from input or feedback node) through PAL + PLA

10.5

Hold time

t_CH

Clock High time

Clock Low time

Input rise time

Input fall time

t_CL

t_R

t_F

f_MAX1

f_MAX2

f_MAX3

t_BUF

Maximum FF toggle rate²(1/t_CH+ t_CL

Maximum internal frequency²(1/t_SUPAL+ t_CF

)

125

64.5

58.8

100

MHz

)

Maximum external frequency²(1/t_SUPAL+ t_CO

)

Output buffer delay time

1.5

t_{PDF_PAL}Input (or feedback node) to internal feedback node delay time through PAL

10.5

13.5

t_{PDF_PLA}Input (or feedback node) to internal feedback node delay time through PAL

+ PLA

10.5

t_CF

t_INIT

t_ER

t_EA

t_RP

t_RR

Clock to internal feedback delay time

Delay from valid V_CCto valid reset

Input to output disable³

7.5

9.5

µs

Input to output valid

Input to register preset

Input to register reset

Notes:

1. Specifications measured with one output switching. See Figure 6 and Table 2 for derating.

2. This parameter guaranteed by design and characterization, not by test.

3. Output C_L= 5 pF.

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XCR3032: 32 Macrocell CPLD

Switching Characteristics

The test load circuit and load values for the AC Electrical Characteristics are illustrated below.

COMPONENT

VALUES

390Ω

35 pF

OUT

MEASUREMENT

Open

Closed

PZH

Closed

PZL

Note: For tPHZ and tPLZ C = 5 pF, and 3-state levels are

measured 0.5V from steady-state active level.

SP00477

= 3.3V, 25°C

9.50

8.50

7.50

6.50

5.50

4.50

+3.0V

90%

10%

1.5ns

TYPICAL

SP00368

MEASUREMENTS:

All circuit delays are measured at the +1.5V level of

inputs and outputs, unless otherwise specified.

Input Pulses

Figure 7: Voltage Waveform

Table 2: t_{PD_PAL}vs # of Outputs Switching

(V_CC= 3.3 V, T = 25°C)

SP00449A

# of Outputs

Typical (ns)

6.2

6.4

6.6

6.9

7.2

7.5

Figure 6: t_{PD_PAL}vs. Output Switching

DS038 (v1.3) October 9, 2000

www.xilinx.com

1-800-255-7778

This product has been discontinued. Please see www.xilinx.com/partinfo/notify/pdn0007.htm for details.

XCR3032: 32 Macrocell CPLD

XCR3032 Global, Power, and Ground Pins

Pin Function and Layout

Pin Type

IN0

PC44

VQ44

Notes

XCR3032 I/O Pins

Function

Block

IN1

Macrocell

PC44

VQ44

Notes

IN2

IN3

gtsn

(1)

CLK0

CLK1

Vcc

3, 15, 23, 35 9, 17, 29, 41

GND

10, 22, 30, 4, 16, 24, 36

(1) Global 3-State pin facilitates bed of nails testing without

using logic resources.

XCR3032 - 44-pin PLCC

PLCC

SP00420A

XCR3032 - 44-pin VQFP

TQFP

SP00433A

www.xilinx.com

1-800-255-7778

DS038 (v1.3) October 9, 2000

This product has been discontinued. Please see www.xilinx.com/partinfo/notify/pdn0007.htm for details.

XCR3032: 32 Macrocell CPLD

Ordering Information

Example: XCR3032 -8 PC 44 C

Temperature Range

Number of Pins

Package Type

Device Type

Speed Options

Temperature Range

Speed Options

C = Commercial, T_A= 0°C to +70°C

I = Industrial, T_A= –40°C to +85°C

-12: 12 ns pin-to-pin delay

-10: 10 ns pin-to-pin delay

-8: 8 ns pin-to-pin delay

Packaging Options

VQ44: 44-pin VQFP

PC44: 44-pin PLCC

Component Availability

Pins

Type

Plastic VQFP

Plastic PLCC

Code

VQ44

C, I

PC44

C, I

XCR3032

-12

-10

-8

Revision History

Date

8/4/99

Version #

1.0

Revision

Initial Xilinx release.

2/7/00

1.1

Converted to Xilinx format and updated

Updated pinout table and features.

Added Discontinuation Notice.

8/10/00

10/09/00

1.2

1.3

DS038 (v1.3) October 9, 2000

www.xilinx.com

1-800-255-7778

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