Z89304 [ZILOG]
Digital Television Controller; 数字电视控制器
| 型号： | Z89304 |
| 厂家： | 
ZILOG, INC. |
| 描述： | Digital Television Controller |
| 文件： | 总8页 (文件大小：76K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
P R E L I M I N A R Y
CUSTOMER PROCUREMENT SPECIFICATION
Z89302/04/06
1
DIGITAL TELEVISION CONTROLLER
FEATURES
■ 0°C to +70°C Temperature Range
■ Fully Customized Character Set
■ Character-Control and Closed-Caption Modes
■ Keypad User Control
ROM
(KB)
RAM*
(Bytes)
Speed
MHz
Device
Z89302
Z89304
Z89306
24
16
12
640
640
640
12
12
12
Note: * General-Purpose
■ TV Tuner Serial Interface
■ 40-Pin DIP Packages
■ Direct Video Signals
■ 4.75- to 5.25-Volt Operating Range
GENERAL DESCRIPTION
The Z89302/04/06 Digital Television Controllers are
designed to provide complete audio and video control of
television receivers, video recorders, and advanced on-
screen display facilities. The Television Controllers feature
a Z89C00 RISC processor core that controls the on-board
peripheral functions and registers using the standard
processor instruction set.
Serial interfacing with the television tuner is provided
through the tuner serial port. Other serial devices, such as
digital channel tuning adjustments, may be accessed
through the industry-standard I2C port.
User control can be monitored through the keypad
scanning port, or the 16-bit remote control capture
register. Receiver functions such as color and volume can
be directly controlled by eight 8-bit pulse width modulated
ports.
Character attributes can be controlled through two modes:
the on-screen display Character-Control Mode and the
Closed-Caption Mode. The Character-Control Mode
provides access to the full set of attribute controls, allowing
the modification of attributes on a character-by-character
basis. The insertion of control characters permits direction
of other character attributes.
The Z89302/04/06 has two internal 12 MHz VCOs that are
referenced to a 32 kHz internal oscillator to provide the
system clock. In Sleep Mode, the controller uses the
32 kHz clock for the system clock to reduce power
consumption. The processor can be suspended by placing
it into STOP Mode when main power is not available for
low-power consumption.
The fully customized 512 character set, formatted in two
256 character banks, can be displayed with a host of
display attributes that include underlining, italics, blinking,
eight foreground/background colors, character position
offset delay, and background transparency.
CP96TEL1803 (9/96)
1
Z89302/04/06
Digital Television Controller
P R E L I M I N A R Y
GENERAL DESCRIPTION (Continued)
PWM
Capture
IRIN
PWM1
PWM2
PWM3
PWM4
PWM5
PWM6
PWM7
PWM8
PWM9
ADC
ADC0
Port 17
ADC1
ADC2
ADC3
Port 00
Port1
Port 0
Port 00
Port 01
Port 02
Port 03
Port 04
Port 05
Port 06
Port 07
Port 08
Port 09
Port 0A
Port 0B
Port 0C
Port 0D
Port 0E
Port 0F
Port 10
Port 11
Port 12
Port 13
Port 14
Port 15
Port 16
Port 17
Port 18
Port 19
Note: Dotted pin functions
not available on 40-pin device.
I2C
Control
SCL
SCD
Port 01/11
Port 02/12
XTAL1
XTAL2
LPF
HSYNC
VSYNC
/Reset
OSD
Register Addr/Data
V1
V2
V3
BLANK
HALFBLNK
CPU
Port0F
RAM
640 x 16
Address
ROM
ROM Addr
ROM Data
Note: Z89306 has
12K words of ROM.
Z89304 has 16K.
Z89302 has 24K.
12K x 16
16K x 16
24K x 16
Data
Figure 1. Z8930X Functional Block Diagram
2
Z89302/04/06
Digital Television Controller
P R E L I M I N A R Y
PIN DESCRIPTION
1
PWM9
IRIN
1
2
3
4
5
6
7
8
9
40
PWM6
PWM5
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
PWM4
PWM3
Port 18/G<0>
Port 00/ADC2
Port 01/I2SSC
PWM2
PWM1
Port 02/I2SSD
Port 03
CVI/ADC0
LPF
Port 04/ADC4
Port 05/ADC3
Z89302
Z89304
Z89306
XTAL2
10
11
GND
Port 06/Counter
Port 07/C Sync
Port 08/R<1>
40-Pin
DIP
XTAL1
VCC
12
13
14
15
16
17
18
19
20
/Reset
Port 09
Port 17/ADC1
VBlank
Port 10/R<0>
Port 11/I2MSC
Port 12/I2MSD
V1
V2
Port 13/G<1>
Port 14/B<0>
Port 15/B<1>
Port 16/SCLK
V3
VSync
HSync
Figure 2. 40-Pin DIP Configuration
3
Z89302/04/06
Digital Television Controller
P R E L I M I N A R Y
PIN DESCRIPTIONS
Z89302/03/06/07
Reset
Pin Name
Function
40-Pin, Z89302/04/06
Direction
Configuration
VCC
+5V
29,–
PWR–
GND
IRIN
0V
31,–
2
PWR–
Infrared Remote Capture Input
4-Bit Analog to Digital
Converter Input
I
I
I
–,9,8,4,27,34
nAI
ADC[5:0]
OD/Oa
OD/Oa
B
PWM9
14-Bit Pulse Width Modulator
Output
1
O
O
I
8-Bit Pulse Width Modulator
Output
–,–,40,39,38
PWM[8:1]
Port0[F:0]
Port1[9:0]
Bit Programmable Input/Output –,–,–,–,–,–,13,12,11,10,9,8,7,6,5,4
Ports
Bit Programmable Input/Output
Ports
–,3,27,20,19,18,17,16,15,14
B
I
SCLb
SCDc
I2C Clock I/O
I2C Data I/O
5 or 15
6 or 16
30
BOD
BOD
AI
XTAL1
XTAL2
LPF
Crystal Oscillator Input
Crystam Oscillator Output
Loop Filter
I
O
O
I
32
AO
AB
B
33
HSYNC
VSYNC
/RESET
V[3:1]
H_Sync
21
V_Sync
22
B
I
Device Reset
28
I
I
OSD Video Output (Typically
Drive B, G, and R Outputs)
23,24,25
O
O
Blank
OSD Blank Output
26
O
O
O
O
I
Half Blankd
RGB Digital
Outputse
OSD Half Blank Output
–
R[1:0],G[1:0], and B[1:0]
Outputs of the RGB Matrix
19,18,17,14,12,3
SCLKf
Internal Processor SCLK
O
Notes:
a) Port19 is not available on the 40-pin DIP Version, Revision D is Push-Pull.
b) SCL I/O pin is shared with Port01 or Port11
c) SCD I/O pin is shared with Port02 or Port12
d) Half Blank output is a function shared with Port0F. Half Blank output is not available on the 40-pin DIP version.
e) Digital RGB outputs and the internal SCLK are shared with Port1[5:0].
f) Internal processor SCLK is shared with Port16.
4
Z89302/04/06
Digital Television Controller
P R E L I M I N A R Y
ABSOLUTE MAXIMUM RATINGS
Symbol
VCC
VID
Parameter
Power Supply Voltage
Input Voltage
Min
Max
7
Units
Conditions
1
0
V
V
V
V
V
–0.3
–0.3
–0.3
–0.3
VCC +0.3
VCC +0.3
VCC +0.3
VCC +0.3
Digital Inputs
VIA
Input Voltage
Analog Inputs (A/D0-A/D4)
All Push-Pull Digital Output
VO
Output Voltage
Output Voltage
VO
Open-Drain/Push-Pull PWM
Outputs (PWM1-PWM8)
IOH
IOH
IOL
IOL
TA
TA
Output Current High
Output Current High
Output Current Low
Output Current Low
Operating Temperature
Storage Temperature
–10
–100
20
mA
mA
mA
mA
°C
One Pin
All Pins
One Pin
All Pins
200
70
0
–65
150
°C
Note: Revision D and later have push-pull PWM outputs.
DC CHARACTERISTICS
TA = 0°C to + 70°C; VCC = 4.5 V to + 5.5 V; FOSC = 32.768 kHz
Symbol
VIL
Parameter
Input Voltage Low
Input Voltage High
Max. Pull-Up Voltage
Output Voltage Low
Output Voltage High
Input Voltage XTAL1 Low
Input Voltage XTAL1 High
Schmitt Hysteresis
Reset Input Current
Input Leakage
Min
0
Max
0.2 VCC
VCC
Typical
Units
Conditions
0.4
3.6
V
V
VIH
0.6 VCC
VPU
VOL
VOL
VXL
VXH
VHY
IIR
5
V
All Pins
0.4
0.16
4.75
1.0
3.5
0.5
90
V
@ IOL = 1 mA
VCC–0.9
V
@ IOL = 0.75 mA
External Clock
Generator Driven
On XTAL1 Input Pin
VRL = 0V
0.3 VCC
V
VCC–2.0
3.0
V
0.75
150
3.0
100
700
300
10
V
mA
mA
mA
mA
mA
mA
mA
mA
IIL
–3.0
0.01
60
@ 0 V and VCC
ICC
Supply Current
ICC1E
ICC1
Supply Current of the OTP
Supply Current
300
100
5
Sleep Mode @ 32 kHz
Sleep Mode @ 32 kHz
Sleep Mode
ICC2
Supply Current
IADC
IADC
Input Current
0.5
10
C Revision
Input Current
D Revision
5
Z89302/04/06
Digital Television Controller
P R E L I M I N A R Y
V1,V2,V3 ANALOG OUTPUT
Condition
4.75 V
5.25 V
11
10
3.6 – 4.4
4.0 – 5.0
VII
79% of VII ±5%
01
50% of VII ±5%
00
0.0 – 0.8V
Notes:
Maximum Variance Between V1, V2, V3 is 100 mV
Settling Time 70% of DC Level, 10pF Load <50n Sec
XTAL1
47 pF
32.768K
27 K
10 MOhm
XTAL2
68 pF
32K Oscillator Recomended Circuit
Figure 3. 32K Oscillator Recommended Circuit
Z893XX
510 W
0.1 mF
10 mF
Figure 4. Low Pass Filter
6
Z89302/04/06
Digital Television Controller
P R E L I M I N A R Y
AC CHARACTERISTICS
TA = 0°C to + 70°C; VCC = 4.5 V to 5.5 V; FOSC = 32.768 kHz
1
Symbol
TPC
Parameter
Input Clock Period
Min
Max
Typical
32
Units
ms
16
100
TRC,TFC
TDPOR
Clock Input Rise and Fall
Power-On Reset Delay
12
ms
0.8
1.2
s
AC CHARACTERISTICS
TA = 0°C to + 70°C; VCC = 4.5 V to 5.5 V; FOSC = 32.768 kHz
Symbol
TWRES
Parameter
Power-On Reset Min. Width
H_Sync Incoming Signal Width
V_Sync Incoming Signal Width
Min.
Max.
5TPC
12.5
1.5
Typical
Units
ms
TDHS
TDVS
TDES
5.5
0.15
–12
11
1.0
0
ms
ms
ms
Time Delay Between Leading Edge of
V_Sync and H_Sync on Even Field
+12
TDOS
Time Delay Between Leading Edge of
H_Sync in Odd Field
20
44
32
ms
ms
TWHVS
H_Sync/V_Sync Edge Width
2.0
0.5
Note: All timing of the I2C bus interface is defined by related specifications of the I2C bus interface.
ANALOG INPUT
ADC0
ADC1
Step
Min.
Max
Step
Min.
Max
1
1.45
1.55
1
0.2
0.4
15
Step 1 + 0.468
Step 1 + 0.532
15
Step_1 + 4.95
Step_1 + 5.15
Note: VCC = 5V
7
Z89302/04/06
Digital Television Controller
P R E L I M I N A R Y
Development Projects:
Customer is cautioned that while reasonable efforts will be
employed to meet performance objectives and milestone
dates, development is subject to unanticipated problems
and delays. No production release is authorized or
committed until the Customer and Zilog have agreed upon
a Customer Procurement Specification for this project.
Pre-Characterization Product:
The product represented by this CPS is newly introduced
and Zilog has not completed the full characterization of the
product. The CPS states what Zilog knows about this
product at this time, but additional features or non-
conformance with some aspects of the CPS may be found,
either by Zilog or its customers in the course of further
application and characterization work. In addition, Zilog
cautions that delivery may be uncertain at times, due to
start-up yield issues.
© 1996 by Zilog, Inc. All rights reserved. No part of this document
may be copied or reproduced in any form or by any means with-
out the prior written consent of Zilog, Inc. The information in this
document is subject to change without notice. Devices sold by
Zilog, Inc. are covered by warranty and patent indemnification
provisions appearing in Zilog, Inc. Terms and Conditions of Sale
only. Zilog, Inc. makes no warranty, express, statutory, implied or
by description, regarding the information set forth herein or re-
garding the freedom of the described devices from intellectual
property infringement. Zilog, Inc. makes no warranty of mer-
chantability or fitness for any purpose. Zilog, Inc. shall not be re-
sponsible for any errors that may appear in this document. Zilog,
Inc. makes no commitment to update or keep current the informa-
tion contained in this document.
Zilog’s products are not authorized for use as critical components
in life support devices or systems unless a specific written agree-
ment pertaining to such intended use is executed between the
customer and Zilog prior to use. Life support devices or systems
are those which are intended for surgical implantation into the
body, or which sustains life whose failure to perform, when prop-
erly used in accordance with instructions for use provided in the
labeling, can be reasonably expected to result in significant injury
to the user.
Zilog, Inc., 210 East Hacienda Ave.
Campbell, CA 95008-6600
Telephone (408) 370-8000
FAX: (408) 370-8056
Internet: http://www.zilog.com
8
相关型号：
©2020 ICPDF网 联系我们和版权申明