IDT7007S25JB8中文资料_数据手册_规格书

HIGH-SPEED

IDT7007S/L

32K x 8 DUAL-PORT

STATIC RAM

Features

◆

using the Master/Slave select when cascading more than

one device

M/S = H for BUSY output flag on Master,

M/S = L for BUSY input on Slave

Interrupt Flag

On-chip port arbitration logic

True Dual-Ported memory cells which allow simultaneous

reads of the same memory location

High-speed access

◆

– Military:25/35/55ns(max.)

◆

– Industrial:20/25/35/55ns(max.)

– Commercial:15/20/25/35/55ns(max.)

Low-power operation

◆

Full on-chip hardware support of semaphore signaling

between ports

– IDT7007S

◆

Fully asynchronous operation from either port

TTL-compatible, single 5V (±10%) power supply

Available in 68-pin PGA and PLCC and a 80-pin TQFP

Industrial temperature range (–40°C to +85°C) is available

for selected speeds

Active:850mW(typ.)

Standby: 5mW (typ.)

– IDT7007L

Active:850mW(typ.)

Standby: 1mW (typ.)

IDT7007 easily expands data bus width to 16 bits or more

◆

Green parts available, see ordering information

FunctionalBlockDiagram

OER

OEL

CEL

CER

R/WR

R/W

L

I/O0L- I/O7L

I/O0R-I/O7R

I/O

Control

(1,2)

BUSY ^(1,2)

L

BUSY

R

A

14R

0R

A

14L

Address

Decoder

MEMORY

ARRAY

Address

Decoder

A

0L

A

15

ARBITRATION

INTERRUPT

SEMAPHORE

LOGIC

CE

L

CE

OE

R/W

R

OE

R

R/W

L

SEM

R

SEM

L

M/S

(2)

INT

R

INTL

2940 drw 01

NOTES:

1. (MASTER): BUSY is output; (SLAVE): BUSY is input.

2. BUSY and INT outputs are non-tri-stated push-pull.

JANUARY 2006

1

DSC 2940/12

IDT7007S/L

High-Speed 32K x 8 Dual-Port Static RAM

Military, Industrial and Commercial Temperature Ranges

Description

The IDT7007 is a high-speed 32K x 8 Dual-Port Static RAM. The featurecontrolledbyCEpermitstheon-chipcircuitryofeachporttoenter

IDT7007isdesignedtobeusedasastand-alone256K-bitDual-PortRAM a very LOW standby power mode.

orasacombinationMASTER/SLAVEDual-PortRAMfor16-bit-or-more FabricatedusingIDT’sCMOShigh-performancetechnology,these

wordsystems.UsingtheIDTMASTER/SLAVEDual-PortRAMapproach devices typicallyoperate ononly850mWofpower.

in16-bitorwidermemorysystemapplicationsresultsinfull-speed,error-

freeoperationwithouttheneedforadditionaldiscretelogic.

The IDT7007 is packaged in a 68-pin pin PGA, a 68-pin PLCC,

and an 80-pin thin quad flatpack, TQFP. Military grade product is

This device provides two independent ports with separate control, manufacturedincompliancewiththelatestrevisionofMIL-PRF-38535

address,andI/Opinsthatpermitindependent,asynchronousaccessfor QML,ClassB,makingitideallysuitedtomilitarytemperatureapplications

reads or writes to any location in memory. An automatic power down demandingthehighestlevelofperformanceandreliability.

PinConfigurations^(1,2,3)

11/06/01

INDEX

9

8

7

6

5

4

3

2

1 68 67 66 65 64 63 62 61

60

I/O2L

I/O3L

I/O4L

I/O5L

GND

I/O6L

I/O7L

A

5L

4L

3L

2L

1L

0L

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

59

58

57

56

55

IDT7007J

J68-1

54

53

52

51

50

49

48

47

46

45

44

INT

BUSY

L

(4)

L

VCC

GND

I/O0R

I/O1R

I/O2R

GND

M/S

BUSY

68-Pin PLCC

(5)

Top View

R

INT

R

VCC

A

0R

I/O3R

I/O4R

I/O5R

I/O6R

1R

2R

3R

4R

27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43

2940 drw 02

NOTES:

1. All Vcc pins must be connected to power supply.

2. All GND pins must be connected to ground.

3. Package body is approximately .95 in x .95 in x .17 in.

4. This package code is used to reference the package diagram.

5. This text does not indicate orientation of the actual part marking.

2

IDT7007S/L

High-Speed 32K x 8 Dual-Port Static RAM

Military, Industrial and Commercial Temperature Ranges

Pin Configurations^(1,2,3)(con't.)

11/06/01

INDEX

1

2

N/C

I/O2L

I/O3L

I/O4L

I/O5L

GND

I/O6L

I/O7L

60

A

5L

4L

3L

2L

1L

0L

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

3

4

5

6

7

7007PF

8

INT

L

PN80-1⁽⁴⁾

9

BUSY

GND

M/S

L

VCC

10

11

12

13

14

15

16

17

18

19

20

N/C

GND

I/O0R

I/O1R

I/O2R

80-Pin TQFP

Top View⁽⁵⁾

BUSY

R

,

INT

R

A

0R

1R

2R

3R

4R

VCC

I/O3R

I/O4R

I/O5R

I/O6R

N/C

2940 drw 03

NOTES:

1. All Vcc pins must be connected to power supply.

2. All GND pins must be connected to ground.

3. Package body is approximately 14mm x 14mm x 1.4mm.

4. This package code is used to reference the package diagram.

5. This text does not indicate orientation of the actual part marking.

3

IDT7007S/L

High-Speed 32K x 8 Dual-Port Static RAM

Military, Industrial and Commercial Temperature Ranges

Pin Configurations^(1,2,3)(con't.)

51

50

48

A

46

A

44

BUSY

42

M/S

40

INT

38

36

11/06/01

11

10

09

08

07

A4L

2L

0L

A1R

A3R

L

R

A

5L

53

52

49

47

45

INT

43

GND

41

BUSYR

39

37

35

34

L

A4R

A

7L

A3L

A

1L

A0R

A2R

A

5R

6R

8R

A

6L

55

54

32

33

A

A7R

A

9L

A

8L

57

A

56

A

30

31

A

A9R

11L

10L

12L

13L

59

58

A

28

29

A

A11R

10R

12R

13R

IDT7007G

G68-1

V

CC

(4)

61

60

A

26

GND

27

A

06

05

04

03

02

01

A14L

68-Pin PGA

Top View

63

62

24

25

A

(5)

SEM

L

A14R

CE

L

65

64

22

SEM

23

R

CER

OE

L

R/W

L

67

I/O0L

66

20

OE

21

R/WR

,

R

N/C

1

3

5

GND

7

9

68

11

13

V

15

18

I/O7R

19

N/C

GND

I/O7L

CC

I/O1L

I/O4L

I/O2L

I/O1R

I/O4R

2

4

6

8

10

12

14

16

17

I/O5L

I/O0R I/O2R I/O3R I/O5R I/O6R

V

CC

I/O6L

I/O3L

K

A

B

C

D

E

F

G

H

J

L

INDEX

2940 drw 04

NOTES:

1. All Vcc pins must be connected to power supply

2. All GND pins must be connected to ground.

3. Package body is approximately 1.8 in x 1.8 in x .16 in.

4. This package code is used to reference the package diagram.

5. This text does not indicate orientation of the actual part marking.

PinNames

Left Port

Right Port

Names

Chip Enables

Read/Write Enable

Output Enable

Address

CE

R/W

OE

L

CE

R/W

OE

R

L

R

L

R

A0L - A14L

A0R - A14R

I/O0L - I/O7L

I/O0R - I/O7R

Data Input/Output

Semaphore Enable

Interrupt Flag

Busy Flag

SEM

INT

BUSY

L

SEM

INT

BUSY

M/S

R

L

R

L

R

Master or Slave Select

Power

V

CC

GND

Ground

2940 tbl 01

4

IDT7007S/L

High-Speed 32K x 8 Dual-Port Static RAM

Military, Industrial and Commercial Temperature Ranges

Truth Table I: Non-Contention Read/Write Control

Inputs⁽¹⁾

R/W

Outputs

I/O^0-7

Mode

CE

H

L

OE

X

L

SEM

H

X

L

High-Z

DATAIN

Deselected: Power-Down

Write to Memory

H

L

H

X

H

DATA^OUTRead Memory

High-Z Outputs Disabled

X

H

X

2940 tbl 02

NOTE:

1. A^0L— A14L ≠ A0R — A14R

Truth Table II: Semaphore Read/Write Control⁽¹⁾

Inputs

Outputs

R/W

I/O^0-7

Mode

-I/O

CE

OE

SEM

H

L

DATAOUT Read Semaphore Flag Data Out (I/O

0

7)

H

L

↑

X

L

DATAIN

Write I/O

0 into Semaphore Flag

______

X

Not Allowed

2940 tbl 03

NOTE:

1. There are eight semaphore flags written to via I/O⁰and read from all I/O's. These eight semaphores are addressed by A0 - A2.

AbsoluteMaximumRatings⁽¹⁾

MaximumOperatingTemperature

andSupplyVoltage⁽¹⁾

Symbol

Rating

Commercial

& Industrial

Military

Unit

Ambient

(2)

Grade

Temperature

-55^OC to+125^OC

0^OC to +70^OC

-40^OC to +85^OC

GND

0V

Vcc

V

TERM

Terminal Voltage

with Respect

to GND

-0.5 to +7.0

V

Military

5.0V

+

10%

Te mp e rature

Under Bias

-55 to +125

-65 to +150

50

-65 to +135

-65 to +150

50

^oC

Commercial

Industrial

0V

5.0V

T

BIAS

0V

10%

Storage

Te mp e rature

TSTG

2940 tbl 05

NOTES:

1. This is the parameter T^A. This is the "instant on" case temperature.

IOUT

DC Output

Current

mA

2940 tbl 04

NOTES:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM

RATINGS

RecommendedDCOperating

Conditions

may cause permanent damage to the device. This is a stress rating only and

functional operation of the device at these or any other conditions above those

indicated in the operational sec-tions of this specification is not implied. Exposure

to absolute maxi-mum rating conditions for extended periods may affect

reliability.

Symbol

Parameter

Supply Voltage

GND Ground

Min.

Typ.

Max. Unit

VCC

4.5

5.0

5.5

0

V

2. V^TERMmust not exceed Vcc + 10% for more than 25% of the cycle time or 10ns

maximum, and is limited to < 20mA for the period of VTERM > Vcc + 10%.

0

(2)

____

V

IH

Input High Voltage

Input Low Voltage

2.2

6.0

Capacitance(TA = +25°C, f = 1.0Mhz)

VIL

-0.5⁽¹⁾

0.8

V

____

Symbol

Parameter⁽¹⁾

Input Capacitance

Output Capacitance

Conditions⁽²⁾

Max.

Unit

2940 tbl 06

NOTES:

CIN

VIN = 3dV

9

pF

1. V^IL> -1.5V for pulse width less than 10ns.

2. V^TERMmust not exceed Vcc + 10%.

COUT

VOUT = 3dV

10

pF

2940 tbl 07

NOTES:

1. This parameter is determined by device characterization but is not production

tested. TQFP package only.

2. 3dV represents the interpolated capacitance when the input and output signals

switch from 0V to 3V or from 3V to 0V.

5

IDT7007S/L

High-Speed 32K x 8 Dual-Port Static RAM

Military, Industrial and Commercial Temperature Ranges

DC Electrical Characteristics Over the Operating

Temperature and Supply Voltage Range (VCC = 5.0V ± 10%)

7007S

7007L

Symbol

|I^LI

|I^LO

Parameter

Test Conditions

Min.

Max.

10

Min.

Max.

5

Unit

µA

V

(1)

___

|

Input Leakage Current

Output Leakage Current

Output Low Voltage

V

CC = 5.5V, VIN = 0V to VCC

___

|

10

5

CE = V^IH, VOUT = 0V to VCC

VOL

I

OL = 4mA

0.4

___

VOH

Output High Voltage

IOH = -4mA

2.4

V

2940 tbl 08

NOTE:

1. At Vcc < 2.0V, input leakages are undefined.

DC Electrical Characteristics Over the Operating

Temperature and Supply Voltage Range⁽¹⁾(VCC = 5.0V ± 10%)

7007X15

7007X20

Com'l & Ind

7007X25

Com'l, Ind

& Military

Com'l Only

Symbol

Parameter

Test Condition

Version

COM'L

Typ.⁽²⁾

Max.

Typ.⁽²⁾

Max.

Typ.⁽²⁾

Max.

Unit

ICC

Dynamic Operating

Current

(Both Ports Active)

S

L

190

325

285

180

315

275

170

305

265

mA

CE = VIL, Outputs Disabled

SEM = VIH

(3)

f = fMAX

___

MIL &

IND

S

L

170

345

305

180

315

I

SB1

Standby Current

(Both Ports - TTL Level

Inputs)

COM'L

S

L

35

85

60

30

85

60

25

85

60

mA

CE

SEM

f = fMAX

L

= CE

R

= VIH

R

= SEM

L

(3)

___

MIL &

IND

S

L

25

100

80

30

80

(5)

ISB2

Standby Current

(One Port - TTL Level

Inputs)

COM'L

S

L

125

220

190

115

210

180

105

200

170

CE^"A"= VIL and CE"B" = VIH

Active Port Outputs Disabled,

(3)

f=fMAX

___

MIL &

IND

S

L

105

230

200

SEMR = SEML = VIH

115

210

I

SB3

Full Standby Current

(Both Ports - All CMOS

Level Inputs)

Both Ports CE

CE > VCC - 0.2V

IN > VCC - 0.2V or

VIN < 0.2V, f = 0⁽⁴⁾

SEM = SEM > VCC - 0.2V

L

and

COM'L

S

L

1.0

0.2

15

5

1.0

0.2

15

5

1.0

0.2

15

5

mA

R

V

___

MIL &

IND

S

L

1.0

0.2

30

10

0.2

10

R

L

ISB4

Full Standby Current

(One Port - All CMOS

Level Inputs)

COM'L

S

L

120

190

160

110

185

160

100

175

160

CE^"A"< 0.2V and

(5)

CE^"B"> VCC - 0.2V

SEM = SEM > VCC - 0.2V

IN > VCC - 0.2V or VIN < 0.2V

R

L

___

MIL &

IND

S

L

100

200

175

V

110

185

Active Port Outputs Disabled

(3)

f = fMAX

2940 tbl 09

NOTES:

1. 'X' in part numbers indicates power rating (S or L)

2. V^CC= 5V, TA = +25°C, and are not production tested. ICCDC = 120mA (Typ.)

3. At f = f^MAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC, and using “AC Test Conditions” of input

levels of GND to 3V.

4. f = 0 means no address or control lines change.

5. Port "A" may be either left or right port. Port "B" is the opposite from port "A".

6

IDT7007S/L

High-Speed 32K x 8 Dual-Port Static RAM

Military, Industrial and Commercial Temperature Ranges

DC Electrical Characteristics Over the Operating

Temperature and Supply Voltage Range⁽¹⁾(con't.) (VCC = 5.0V ± 10%)

7007X35

Com'l, Ind

& Military

7007X55

Com'l, Ind

& Military

Symbol

Parameter

Test Condition

Version

COM'L

Typ.⁽²⁾

Max.

Typ.⁽²⁾

Max.

Unit

ICC

Dynamic Operating Current

(Both Ports Active)

S

L

160

295

255

150

270

230

mA

CE = VIL, Outputs Disabled

SEM = VIH

(3)

f = fMAX

MIL &

IND

S

L

160

335

295

150

310

270

I

SB1

Standby Current

(Both Ports - TTL Level

Inputs)

COM'L

S

L

20

85

60

20

85

60

mA

CE

SEM

f = fMAX

L

= CE

R

= VIH

R

= SEM

L

(3)

MIL &

IND

S

L

20

100

80

13

100

80

(5)

ISB2

Standby Current

(One Port - TTL Level Inputs)

COM'L

S

L

95

185

155

85

165

135

CE^"A"= VIL and CE"B" = VIH

Active Port Outputs Disabled,

(3)

f=fMAX

MIL &

IND

S

L

95

215

185

85

195

165

SEM

R

= SEML = VIH

I

SB3

Full Standby Current (Both

Ports - All CMOS Level

Inputs)

Both Ports CE

CE > VCC - 0.2V

IN > VCC - 0.2V or

VIN < 0.2V, f = 0⁽⁴⁾

SEM = SEM > VCC - 0.2V

L

and

COM'L

S

L

1.0

0.2

15

5

1.0

0.2

15

5

mA

R

V

MIL &

IND

S

L

1.0

0.2

30

10

1.0

0.2

30

10

R

L

ISB4

Full Standby Current

(One Port - All CMOS Level

Inputs)

COM'L

S

L

90

160

135

80

135

110

CE^"A"< 0.2V and

(5)

CE^"B"> VCC - 0.2V

SEM = SEM > VCC - 0.2V

IN > VCC - 0.2V or VIN < 0.2V

R

L

MIL &

IND

S

L

90

190

165

80

165

140

V

Active Port Outputs Disabled

(3)

f = fMAX

2940 tbl 10

NOTES:

1. 'X' in part numbers indicates power rating (S or L)

2. V^CC= 5V, TA = +25°C, and are not production tested. ICCDC = 120mA (Typ.)

3. At f = f^MAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC, and using

“AC Test Conditions” of input levels of GND to 3V.

4. f = 0 means no address or control lines change.

5. Port "A" may be either left or right port. Port "B" is the opposite from port "A".

7

IDT7007S/L

High-Speed 32K x 8 Dual-Port Static RAM

Military, Industrial and Commercial Temperature Ranges

5V

AC Test Conditions

Input Pulse Levels

GND to 3.0V

5ns Max.

1.5V

893Ω

Input Rise/Fall Times

Input Timing Reference Levels

Output Reference Levels

Output Load

DATAOUT

BUSY

INT

DATAOUT

30pF

5pF*

347Ω

1.5V

Figures 1 and 2

2940 tbl 11

2940 drw 05

2940 drw 06

Figure 1. AC Output Test Load

Figure 2. Output Test Load

(for tLZ, tHZ, tWZ, tOW)

* Including scope and jig.

AC Electrical Characteristics Over the

OperatingTemperatureandSupplyVoltageRange⁽⁴⁾

7007X15

7007X20

Com'l & Ind

7007X25

Com'l, Ind

& Military

Com'l Only

Symbol

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Unit

READ CYCLE

____

t

RC

AA

ACE

AOE

OH

LZ

HZ

PU

PD

SOP

SAA

Read Cycle Time

15

20

25

ns

____

t

Address Access Time

15

20

25

Chip Enable Access Time⁽³⁾

Output Enable Access Time

Output Hold from Address Change

Output Low-Z Time^(1,2)

____

t

10

12

13

____

t

3

____

t

3

Output High-Z Time^(1,2)

10

12

15

____

t

Chip Enable to Power Up Time⁽²⁾

Chip Disable to Power Down Time⁽²⁾

0

____

t

15

20

25

____

t

Semaphore Flag Update Pulse (OE or SEM)

10

12

____

t

Semaphore Address Access Time

15

20

25

ns

2940 tbl 12a

7007X35

Com'l, Ind

& Military

7007X55

Com'l, Ind

& Military

Symbol

READ CYCLE

Parameter

Min.

Max.

Min.

Max.

Unit

____

t

RC

AA

ACE

AOE

OH

LZ

HZ

PU

PD

SOP

SAA

Read Cycle Time

35

55

ns

____

t

Address Access Time

35

55

Chip Enable Access Time⁽³⁾

Output Enable Access Time

Output Hold from Address Change

Output Low-Z Time^(1,2)

____

t

20

30

____

t

3

____

t

3

Output High-Z Time^(1,2)

15

25

____

t

Chip Enable to Power Up Time⁽²⁾

Chip Disable to Power Down Time⁽²⁾

Semaphore Flag Update Pulse (OE or SEM)

Semaphore Address Access Time

0

____

t

35

50

____

t

15

____

t

35

55

ns

2940 tbl 12b

NOTES:

1. Transition is measured 0mV from Low- or High-impedance voltage with Output Test Load (Figure 2).

2. This parameter is guaranteed by device characterization, but is not production tested.

3. To access RAM, CE = V^ILand SEM = VIH. To access semaphore, CE = VIH and SEM = VIL.

4. 'X' in part numbers indicates power rating (S or L).

8

IDT7007S/L

High-Speed 32K x 8 Dual-Port Static RAM

Military, Industrial and Commercial Temperature Ranges

Waveform of Read Cycles⁽⁵⁾

tRC

ADDR

(4)

t

AA

(4)

ACE

CE

OE

(4)

tAOE

R/W

(1)

tOH

tLZ

VALID DATA⁽⁴⁾

DATAOUT

(2)

tHZ

BUSYOUT

(3,4)

2940 drw 07

tBDD

NOTES:

1. Timing depends on which signal is asserted last, OE or CE.

2. Timing depends on which signal is de-asserted first CE or OE.

3. t^BDDdelay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY

has no relation to valid output data.

4. Start of valid data depends on which timing becomes effective last t^AOE, tACE, tAA or tBDD.

5. SEM = V^IH.

Timing of Power-Up Power-Down

CE

tPU

tPD

I

CC

50%

I

SB

,

2940 drw 08

9

IDT7007S/L

High-Speed 32K x 8 Dual-Port Static RAM

Military, Industrial and Commercial Temperature Ranges

AC Electrical Characteristics Over the

OperatingTemperatureandSupplyVoltage⁽⁵⁾

7007X15

7007X20

Com'l & Ind

7007X25

Com'l, Ind

& Military

Com'l Only

Symbol

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Unit

WRITE CYCLE

____

t

WC

EW

AW

AS

WP

WR

DW

HZ

DH

WZ

OW

SWRD

SPS

Write Cycle Time

15

12

0

20

15

0

25

20

0

ns

t

Chip Enable to End-of-Write⁽³⁾

Address Valid to End-of-Write

Address Set-up Time⁽³⁾

Write Pulse Width

t

12

0

15

0

20

0

t

Write Recovery Time

Data Valid to End-of-Write

Output High-Z Time^(1,2)

Data Hold Time⁽⁴⁾

t

10

15

____

t

10

12

15

____

t

0

(1,2)

____

t

Write Enable to Output in High-Z

Output Active from End-of-Write^{(1, 2,4)}

SEM Flag Write to Read Time

SEM Flag Contention Window

10

12

15

____

t

0

5

0

5

0

5

____

t

ns

2940 tbl 13a

7007X35

Com'l, Ind

& Military

7007X55

Com'l, Ind

& Military

Symbol

WRITE CYCLE

Parameter

Min.

Max.

Min.

Max.

Unit

____

t

WC

EW

AW

AS

WP

WR

DW

HZ

DH

WZ

OW

SWRD

SPS

Write Cycle Time

35

30

0

55

45

0

ns

t

Chip Enable to End-of-Write⁽³⁾

Address Valid to End-of-Write

Address Set-up Time⁽³⁾

Write Pulse Width

t

25

0

40

0

t

Write Recovery Time

Data Valid to End-of-Write

Output High-Z Time^(1,2)

Data Hold Time⁽⁴⁾

t

15

30

____

t

12

25

____

t

0

(1,2)

____

t

Write Enable to Output in High-Z

Output Active from End-of-Write^(1,2,4)

SEM Flag Write to Read Time

SEM Flag Contention Window

12

25

____

t

0

5

0

5

____

t

ns

2940 tbl 13b

NOTES:

1. Transition is measured 0mV from Low- or High-impedance voltage with Output Test Load (Figure 2).

2. This parameter is guaranteed by device characterization, but is not production tested.

3. To access RAM, CE = V^ILand SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. Either condition must be valid for the entire tEW time.

4. The specification for t^DHmust be met by the device supplying write data to the RAM under all operating conditions. Although tDH and tOW values will vary over voltage

and temperature, the actual t^DHwill always be smaller than the actual tOW.

5. 'X' in part numbers indicates power rating (S or L).

10

IDT7007S/L

High-Speed 32K x 8 Dual-Port Static RAM

Military, Industrial and Commercial Temperature Ranges

Timing Waveform of Write Cycle No. 1, R/W Controlled Timing^(1,5,8)

tWC

ADDRESS

(7)

t

HZ

OE

tAW

CE or SEM⁽⁹⁾

(3)

(2)

(6)

t

WP

t

WR

tAS

R/W

DATAOUT

DATAIN

(7)

t

WZ

tOW

(4)

t

DW

tDH

2940 drw 09

Timing Waveform of Write Cycle No. 2, CE Controlled Timing^(1,5)

t

WC

ADDRESS

t

AW

CE or SEM⁽⁹⁾

(6)

AS

(3)

(2)

t

WR

t

tEW

R/W

t

DW

tDH

DATAIN

2940 drw 10

NOTES:

1. R/W or CE must be HIGH during all address transitions.

2. A write occurs during the overlap (t^EWor tWP) of a LOW CE and a LOW R/W for memory array writing cycle.

3. t^WRis measured from the earlier of CE or R/W (or SEM or R/W) going HIGH to the end of write cycle.

4. During this period, the I/O pins are in the output state and input signals must not be applied.

5. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the High-impedance state.

6. Timing depends on which enable signal is asserted last, CE or R/W.

7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test Load (Figure

2).

8. If OE is LOW during R/W controlled write cycle, the write pulse width must be the larger of t^WPor (tWZ + tDW) to allow the I/O drivers to turn off and data to be

placed on the bus for the required t^DW. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as

the specified t^WP.

9. To access RAM, CE = V^ILand SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. tEW must be met for either condition.

11

IDT7007S/L

High-Speed 32K x 8 Dual-Port Static RAM

Military, Industrial and Commercial Temperature Ranges

Timing Waveform of Semaphore Read after Write Timing, Either Side⁽¹⁾

tSAA

tOH

A0-A2

VALID ADDRESS

tAW

tWR

tACE

t

EW

SEM

tSOP

tDW

DATAOUT

DATAIN VALID

DATA

0

VALID⁽²⁾

t

AS

WP

tDH

R/W

tSWRD

tAOE

OE

tSOP

Write Cycle

Read Cycle

2940 drw 11

NOTE:

1. CE = V^IHfor the duration of the above timing (both write and read cycle).

Timing Waveform of Semaphore Write Contention^(1,3,4)

A0"A"-A2"A"

MATCH

SIDE⁽²⁾"A"

R/W"A"

SEM"A"

tSPS

A0"B"-A2"B"

MATCH

SIDE⁽²⁾

"B"

R/W"B"

SEM"B"

2940 drw 12

NOTES:

1. D^OR= DOL = VIL, CER = CEL = VIH.

2. All timing is the same for left and right ports. Port "A" may be either left or right port. "B" is the opposite from port "A".

3. This parameter is measured from R/W^Aor SEMA going HIGH to R/WB or SEMB going HIGH.

4. If t^SPSis not satisfied, the semaphore will fall positively to one side or the other, but there is no guarantee which side will obtain the flag.

12

IDT7007S/L

High-Speed 32K x 8 Dual-Port Static RAM

Military, Industrial and Commercial Temperature Ranges

AC Electrical Characteristics Over the

OperatingTemperatureandSupplyVoltageRange⁽⁶⁾

7007X15

7007X20

Com'l & Ind

7007X25

Com'l, Ind

& Military

Com'l Only

Symbol

BUSY TIMING (M/S=VIH

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Unit

)

____

t

BAA

BDA

BAC

BDC

APS

BDD

WH

15

20

ns

BUSY Access Time from Address Match

t

BUSY Disable Time from Address Not Matched

BUSY Access Time from Chip Enable Low

BUSY Access Time from Chip Enable High

Arbitration Priority Set-up Time⁽²⁾

t

15

17

____

t

5

____

BUSY Disable to Valid Data⁽³⁾

Write Hold After BUSY⁽⁵⁾

t

18

30

____

t

12

15

17

BUSY TIMING (M/S=VIL

)

____

BUSY Input to Write⁽⁴⁾

Write Hold After BUSY⁽⁵⁾

t

WB

0

ns

tWH

12

15

17

PORT-TO-PORT DELAY TIMING

____

t

WDD

Write Pulse to Data Delay⁽¹⁾

30

25

45

30

50

35

ns

tDDD

Write Data Valid to Read Data Delay⁽¹⁾

ns

2940 tbl 14a

7007X35

Com'l, Ind

& Military

7007X55

Com'l, Ind

& Military

Symbol

Parameter

Min.

Max.

Min.

Max.

Unit

BUSY TIMING (M/S=VIH

)

____

t

BAA

BDA

BAC

BDC

APS

BDD

WH

20

45

40

ns

BUSY Access Time from Address Match

t

BUSY Disable Time from Address Not Matched

BUSY Access Time from Chip Enable Low

BUSY Access Time from Chip Enable High

Arbitration Priority Set-up Time⁽²⁾

t

20

35

____

t

5

____

BUSY Disable to Valid Data⁽³⁾

Write Hold After BUSY⁽⁵⁾

t

35

40

____

t

25

BUSY TIMING (M/S=VIL

)

____

BUSY Input to Write⁽⁴⁾

Write Hold After BUSY⁽⁵⁾

t

WB

0

ns

tWH

25

PORT-TO-PORT DELAY TIMING

____

t

WDD

Write Pulse to Data Delay⁽¹⁾

60

45

80

65

ns

tDDD

Write Data Valid to Read Data Delay⁽¹⁾

ns

2940 tbl 14b

NOTES:

1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Write with Port-to-Port Read and BUSY (M/S = V^IH)".

2. To ensure that the earlier of the two ports wins.

3. t^BDDis a calculated parameter and is the greater of 0, tWDD – tWP (actual) or tDDD – tDW (actual).

4. To ensure that the write cycle is inhibited on port "B" during contention on port "A".

5. To ensure that a write cycle is completed on port "B" after contention on port "A".

6. 'X' in part numbers indicates power rating (S or L).

13

IDT7007S/L

High-Speed 32K x 8 Dual-Port Static RAM

Military, Industrial and Commercial Temperature Ranges

Timing Waveform of Write with Port-to-Port Read and BUSY^(2,5)

(M/S = VIH)⁽⁴⁾

tWC

MATCH

ADDR"A"

t

WP

R/W"A"

t

DW

t

DH

VALID

DATAIN "A"

(1)

tAPS

MATCH

ADDR"B"

tBDA

tBDD

BUSY"B"

t

WDD

VALID

DATAOUT "B"

(3)

tDDD

2940 drw 13

NOTES:

1. To ensure that the earlier of the two ports wins. t^APSis ignored for M/S = VIL (SLAVE).

2. CE^L= CER = VIL

3. OE = VIL for the reading port.

4. If M/S = V^IL(SLAVE), then BUSY is an input (BUSY"A" = VIH and BUSY"B" = "don't care", for this example).

5. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A".

Timing Waveform of Write with BUSY (M/S = VIL)

tWP

R/W"A"

t

WB

BUSY"B"

(1)

t

WH

R/W"B"

(2)

,

2940 drw 14

NOTES:

1. t^WHmust be met for both BUSY input (SLAVE) and output (MASTER).

2. BUSY is asserted on port "B" blocking R/W"B", until BUSY"B" goes HIGH.

14

IDT7007S/L

High-Speed 32K x 8 Dual-Port Static RAM

Military, Industrial and Commercial Temperature Ranges

Waveform of BUSY Arbitration Controlled by CE Timing⁽¹⁾(M/S = VIH)

ADDR"A"

ADDRESSES MATCH

and "B"

CE"A"

(2)

tAPS

CE"B"

tBAC

tBDC

BUSY"B"

2940 drw 15

Waveform of BUSY Arbitration Cycle Controlled by Address Match

Timing⁽¹⁾(M/S = VIH)

ADDR"A"

ADDR"B"

BUSY"B"

ADDRESS "N"

(2)

tAPS

MATCHING ADDRESS "N"

t

BAA

tBDA

2940 drw 16

NOTES:

1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”.

2. If t^APSis not satisfied, the BUSY signal will be asserted on one side or another but there is no guarantee on which side BUSY will be asserted.

AC Electrical Characteristics Over the

OperatingTemperatureandSupplyVoltageRange^(1,2)

7007X15

7007X20

7007X25

Com'l, Ind

& Military

Com'l Only

Com'l & Ind

Symbol

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Unit

INTERRUPT TIMING

____

t

AS

WR

INS

INR

Address Set-up Time

Write Recovery Time

Interrupt Set Time

0

ns

t

0

____

t

15

20

____

t

Interrupt Reset Time

ns

2940 tbl 15a

7007X35

Com'l, Ind

& Military

7007X55

Com'l, Ind

& Military

Symbol

INTERRUPT TIMING

Parameter

Min.

Max.

Min.

Max.

Unit

____

t

AS

WR

INS

INR

Address Set-up Time

Write Recovery Time

Interrupt Set Time

0

ns

t

0

____

t

25

40

____

t

Interrupt Reset Time

ns

2940 tbl 15b

NOTES:

1. 'X' in part numbers indicates power rating (S or L).

15

IDT7007S/L

High-Speed 32K x 8 Dual-Port Static RAM

Military, Industrial and Commercial Temperature Ranges

Waveform of Interrupt Timing⁽¹⁾

tWC

INTERRUPT SET ADDRESS ⁽²⁾

ADDR"A"

CE"A"

(4)

(3)

tAS

tWR

R/W"A"

INT"B"

(3)

tINS

2940 drw 17

tRC

ADDR"B"

CE"B"

INTERRUPT CLEAR ADDRESS ⁽²⁾

(3)

tAS

OE"B"

(3)

tINR

INT"B"

2940 drw 18

NOTES:

1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”.

2. See Interrupt Truth Table III.

3. Timing depends on which enable signal (CE or R/W) is asserted last.

4. Timing depends on which enable signal (CE or R/W) is de-asserted first.

Truth Table III — Interrupt Flag⁽¹⁾

Left Port

Right Port

R/W

L

A

14L-A0L

R/W

R

A

14R-A0R

Function

Set Right INT Flag

Reset Right INT Flag

Set Left INT Flag

Reset Left INT Flag

CE

L

OE

L

INT

L

CE

R

OE

R

INT

R

(2)

L

X

L

X

L

X

L

7FFF

X

L

X

L

X

L

X

7FFF

7FFE

X

L

R

(3)

X

H

R

(3)

X

L

X

L

(2)

7FFE

H

X

L

2940 tbl 16

NOTES:

1. Assumes BUSY^L= BUSYR =VIH.

2. If BUSY^L= VIL, then no change.

3. If BUSY^R= VIL, then no change.

16

IDT7007S/L

High-Speed 32K x 8 Dual-Port Static RAM

Military, Industrial and Commercial Temperature Ranges

Truth Table IV — Address BUSY

Arbitration

Inputs

Outputs

A

OL-A14L

(1)

A

OR-A14R

Function

Normal

CE

L

CE

R

BUSY

L

BUSY

R

X

H

X

L

X

H

L

NO MATCH

MATCH

H

MATCH

H

(3)

MATCH

(2)

Write Inhibit

2940 tbl 17

NOTES:

1. Pins BUSY^Land BUSYR are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSY outputs on the IDT7007 are

push-pull, not open drain outputs. On slaves the BUSY input internally inhibits writes.

2. "L" if the inputs to the opposite port were stable prior to the address and enable inputs of this port. "H" if the inputs to the opposite port became stable after the address

and enable inputs of this port. If t^APSis not met, either BUSYL or BUSYR = LOW will result. BUSYL and BUSYR outputs can not be LOW simultaneously.

3. Writes to the left port are internally ignored when BUSY^Loutputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are internally ignored

when BUSY^Routputs are driving LOW regardless of actual logic level on the pin.

Truth Table V — Example of Semaphore Procurement Sequence^(1,2,3)

Functions

D0

- D7

Left

D0

- D7

Right

Status

No Action

1

0

1

0

1

0

1

0

1

0

1

Semaphore free

Left Port Writes "0" to Semaphore

Right Port Writes "0" to Semaphore

Left Port Writes "1" to Semaphore

Left Port Writes "0" to Semaphore

Right Port Writes "1" to Semaphore

Left Port Writes "1" to Semaphore

Right Port Writes "0" to Semaphore

Right Port Writes "1" to Semaphore

Left Port Writes "0" to Semaphore

Left Port Writes "1" to Semaphore

Left port has semaphore token

No change. Right side has no write access to semaphore

Right port obtains semaphore token

No change. Left port has no write access to semaphore

Left port obtains semaphore token

Semaphore free

Right port has semaphore token

Semaphore free

Left port has semaphore token

Semaphore free

2940 tbl 18

NOTES:

1. This table denotes a sequence of events for only one of the eight semaphores on the IDT7007.

2. There are eight semaphore flags written to via I/O⁵(I/O0 - I/O7) and read from all I/O0. These eight semaphores are addressed by A0 - A2.

3. CE = V^IH, SEM = VIL to access the semaphores. Refer to the Semaphore Read/Write Control Truth Table.

FunctionalDescription

when CE^R= OER = VIL, R/W is a "don't care". Likewise, the right port

interruptflag(INTR)isassertedwhentheleftportwritestomemorylocation

7FFF(HEX)andtocleartheinterruptflag(INTR),therightportmustread

thememorylocation7FFF. Themessage(8bits)at7FFEor7FFFisuser-

definedsinceitisanaddressableSRAMlocation.Iftheinterruptfunction

isnotused,addresslocations7FFEand7FFFarenotusedasmailboxes,

butaspartoftherandomaccessmemory.RefertoTableIIIfortheinterrupt

operation.

TheIDT7007providestwoportswithseparatecontrol,addressand

I/Opinsthatpermitindependentaccessforreadsorwritestoanylocation

inmemory.TheIDT7007hasanautomaticpowerdownfeaturecontrolled

by CE. The CE controls on-chip power down circuitry that permits the

respectiveporttogointoastandbymodewhennotselected(CEHIGH).

Whenaportisenabled,accesstotheentirememoryarrayispermitted.

INTERRUPTS

Iftheuserchoosestheinterruptfunction,amemorylocation(mailbox

ormessagecenter)is assignedtoeachport. Theleftportinterruptflag

(INTL) is asserted when the right port writes to memory location 7FFE

(HEX), where a write is defined as CE = R/W=VIL per the Truth Table.

Theleftportclearstheinterruptthroughaccessofaddresslocation7FFE

BusyLogic

BusyLogicprovidesahardwareindicationthatbothportsoftheRAM

haveaccessedthesamelocationatthesametime. Italsoallowsoneof

thetwoaccesses toproceedandsignals theothersidethattheRAMis

17

IDT7007S/L

High-Speed 32K x 8 Dual-Port Static RAM

Military, Industrial and Commercial Temperature Ranges

“busy”. The BUSY pin can then be used to stall the access until the

operationon the otherside is completed. Ifa write operationhas been

attemptedfromthesidethatreceivesaBUSYindication,thewritesignal

isgatedinternallytopreventthewritefromproceeding.

Semaphores

TheIDT7007isanextremelyfastDual-Port 16Kx8CMOSStaticRAM

withanadditional8addresslocationsdedicatedtobinarysemaphoreflags.

TheseflagsalloweitherprocessorontheleftorrightsideoftheDual-Port

RAMtoclaimaprivilegeovertheotherprocessorforfunctionsdefinedby

thesystemdesigner’ssoftware.Asanexample,thesemaphorecanbe

usedbyoneprocessortoinhibittheotherfromaccessingaportionofthe

Dual-Port RAM or any other shared resource.

TheuseofBUSYlogicisnotrequiredordesirableforallapplications.

InsomecasesitmaybeusefultologicallyORtheBUSYoutputstogether

anduse anyBUSYindicationas aninterruptsource toflagthe eventof

anillegalorillogicaloperation.IfthewriteinhibitfunctionofBUSYlogicis

notdesirable,theBUSYlogiccanbedisabledbyplacingthepartinslave

modewiththeM/Spin.OnceinslavemodetheBUSYpinoperatessolely

asawriteinhibitinputpin.Normaloperationcanbeprogrammedbytying

the BUSY pins HIGH. If desired, unintended write operations

can be prevented to a port by tying the BUSY pin for that port LOW.

TheBUSYoutputsontheIDT7007RAMinmastermode,arepush-

pulltypeoutputsanddonotrequirepullupresistorstooperate.Ifthese

RAMs are being expanded in depth, then the BUSY indication for the

resulting array requires the use of an external AND gate.

The Dual-PortRAMfeatures a fastaccess time, andbothports are

completelyindependentofeachother.Thismeansthattheactivityonthe

leftportinnowayslows theaccess timeoftherightport.Bothports are

identicalinfunctiontostandardCMOSStaticRAMandcanbereadfrom,

orwrittento,atthesametimewiththeonlypossibleconflictarisingfromthe

simultaneous writing of, or a simultaneous READ/WRITE of, a non-

semaphorelocation.Semaphoresareprotectedagainstsuchambiguous

situationsandmaybeusedbythesystemprogramtoavoidanyconflicts

inthenon-semaphoreportionoftheDual-PortRAM.Thesedeviceshave

anautomaticpower-downfeaturecontrolledbyCE,theDual-PortRAM

enable,andSEM,thesemaphoreenable.TheCEandSEMpinscontrol

on-chippowerdowncircuitrythatpermits the respective porttogointo

standbymodewhennotselected. Thisistheconditionwhichisshownin

Truth Table I where CE and SEM are both HIGH.

Width Expansion with Busy Logic

Master/SlaveArrays

Systems which can best use the IDT7007 contain multiple proces-

sors or controllers and are typically very high-speed systems which

are software controlled or software intensive. These systems can

benefitfromaperformanceincreaseofferedbytheIDT7007hardware

semaphores, which provide a lockout mechanism without requiring

complexprogramming.

Softwarehandshakingbetweenprocessors offers themaximumin

systemflexibilitybypermittingsharedresourcestobeallocatedinvarying

configurations.TheIDT7007doesnotuseitssemaphoreflagstocontrol

anyresourcesthroughhardware,thusallowingthesystemdesignertotal

flexibilityinsystemarchitecture.

CE

MASTER

Dual Port

RAM

SLAVE

Dual Port

RAM

BUSY (L) BUSY (R)

BUSY (R)

BUSY (L)

MASTER

Dual Port

RAM

SLAVE

Dual Port

RAM

CE

BUSY (R)

BUSY (L) BUSY (R)

BUSY (L)

2940 drw 19

An advantage of using semaphores rather than the more common

methodsofhardwarearbitrationisthatwaitstatesareneverincurredin

either processor. This can prove to be a major advantage in very high-

speedsystems.

Figure 3. Busy and chip enable routing for both width and depth

expansion with IDT7007 RAMs.

WhenexpandinganIDT7007RAMarrayinwidthwhileusingBUSY

logic,onemasterpartisusedtodecidewhichsideoftheRAMsarraywill

receiveaBUSYindication,andtooutputthatindication.Anynumberof

slavestobeaddressedinthesameaddressrangeasthemaster,usethe

How the Semaphore Flags Work

Thesemaphorelogicisasetofeightlatcheswhichareindependent

BUSYsignalasawriteinhibitsignal.ThusontheIDT7007RAMtheBUSY oftheDual-PortRAM.Theselatchescanbeusedtopassaflag,ortoken,

pinisanoutputifthepartisusedasamaster(M/Spin=H),andtheBUSY fromoneporttotheothertoindicatethatasharedresourceisinuse.The

pin is an input if the part used as a slave (M/S pin = L) as shown in semaphores provide a hardware assist for a use assignment method

Figure 3.

Iftwoormoremasterpartswereusedwhenexpandinginwidth,asplit

called“TokenPassingAllocation.”Inthismethod,thestateofasemaphore

latchisusedasatokenindicatingthatsharedresourceisinuse.Iftheleft

processorwantstousethisresource,itrequeststhetokenbysettingthe

latch.Thisprocessorthenverifiesitssuccessinsettingthelatchbyreading

it. If it was successful, it proceeds to assume control over the shared

resource.Ifitwasnotsuccessfulinsettingthelatch,itdeterminesthatthe

rightsideprocessorhassetthelatchfirst,hasthetokenandisusingthe

sharedresource.Theleftprocessorcantheneitherrepeatedlyrequest

thatsemaphore’sstatusorremoveitsrequestforthatsemaphoretoperform

anothertaskandoccasionallyattemptagaintogaincontrolofthetokenvia

thesetandtestsequence.Oncetherightsidehasrelinquishedthetoken,

theleftsideshouldsucceedingainingcontrol.

decisioncouldresultwithonemasterindicatingBUSYononesideofthe

arrayandanothermasterindicatingBUSYononeothersideofthearray.

Thiswouldinhibitthewriteoperationsfromoneportforpartofawordand

inhibitthewriteoperationsfromtheotherportfortheotherpartoftheword.

TheBUSYarbitration,onamaster,isbasedonthechipenableand

address signals only. Itignores whetheranaccess is a readorwrite. In

a master/slave array, bothaddress andchipenable mustbe validlong

enoughforaBUSYflagtobeoutputfromthemasterbeforetheactualwrite

pulsecanbeinitiatedwiththeR/Wsignal.Failuretoobservethistimingcan

resultina glitchedinternalwrite inhibitsignalandcorrupteddata inthe

slave.

ThesemaphoreflagsareactiveLOW.Atokenisrequestedbywriting

18

IDT7007S/L

High-Speed 32K x 8 Dual-Port Static RAM

Military, Industrial and Commercial Temperature Ranges

azerointoasemaphorelatchandisreleasedwhenthesamesidewrites overtotheothersideassoonasaoneiswrittenintothefirstside’srequest

aonetothatlatch. latch.Thesecondside’sflagwillnowstaylowuntilitssemaphorerequest

The eightsemaphore flags reside withinthe IDT7007ina separate latchiswrittentoaone.Fromthisitiseasytounderstandthat,ifasemaphore

memoryspacefromtheDual-PortRAM.This addressspaceisaccessed is requestedandthe processorwhichrequesteditnolongerneeds the

byplacingaLOWinputontheSEMpin(whichactsasachipselectforthe resource, the entire system can hang up until a one is written into that

semaphore flags) and using the other control pins (Address, OE, and semaphorerequestlatch.

R/W)as theywouldbeusedinaccessingastandardStaticRAM.Each

The criticalcase ofsemaphore timingis whenbothsides requesta

oftheflagshasauniqueaddresswhichcanbeaccessedbyeitherside single token by attempting to write a zero into it at the same time. The

throughaddresspinsA0–A2.Whenaccessingthesemaphores,noneof semaphorelogicisspeciallydesignedtoresolvethisproblem.Ifsimulta-

theotheraddresspinshasanyeffect.

neousrequestsaremade,thelogicguaranteesthatonlyonesidereceives

Whenwritingtoasemaphore,onlydatapinD0isused.IfaLOWlevel thetoken.Ifonesideis earlierthantheotherinmakingtherequest,the

iswrittenintoanunusedsemaphorelocation,thatflagwillbesettoazero firstsidetomaketherequestwillreceivethetoken.Ifbothrequestsarrive

on that side and a one on the other side (see Truth Table V). That at the same time, the assignment will be arbitrarily made to one port or

semaphorecannowonlybemodifiedbythesideshowingthezero.When

aoneiswrittenintothesamelocationfromthesameside,theflagwillbe

L PORT

R PORT

settoaoneforbothsides(unlessasemaphorerequestfromtheotherside

ispending)andthencanbewrittentobybothsides.Thefactthattheside

whichisabletowriteazerointoasemaphoresubsequentlylocksoutwrites

fromtheothersideiswhatmakessemaphoreflagsusefulininterprocessor

communications.(Athoroughdiscussionontheuseofthisfeaturefollows

shortly.)Azerowrittenintothesamelocationfromtheothersidewillbe

storedinthesemaphorerequestlatchforthatsideuntilthesemaphoreis

freedbythefirstside.

SEMAPHORE

REQUEST FLIP FLOP

SEMAPHORE

REQUEST FLIP FLOP

0

D

Q

WRITE

SEMAPHORE

READ

SEMAPHORE

READ

2940 drw 20

Whenasemaphoreflagisread,itsvalueisspreadintoalldatabitsso

thataflagthatisaonereadsasaoneinalldatabitsandaflagcontaining

azeroreadsasallzeros.Thereadvalueislatchedintooneside’soutput

registerwhenthatside'ssemaphoreselect(SEM)andoutputenable(OE)

signalsgoactive.Thisservestodisallowthesemaphorefromchanging

stateinthemiddleofareadcycleduetoawritecyclefromtheotherside.

Becauseofthislatch,arepeatedreadofasemaphoreinatestloopmust

cause either signal (SEM or OE) to go inactive or the output will never

change.

AsequenceWRITE/READmustbeusedbythesemaphoreinorder

to guarantee that no system level contention will occur. A processor

requestsaccesstosharedresourcesbyattemptingtowriteazerointoa

semaphorelocation.Ifthesemaphoreisalreadyinuse,thesemaphore

requestlatchwillcontainazero,yetthesemaphoreflagwillappearasone,

afactwhichtheprocessorwillverifybythesubsequentread(seeTruth

TableV).Asanexample,assumeaprocessorwritesazerototheleftport

atafreesemaphorelocation.Onasubsequentread,theprocessorwill

verifythatithaswrittensuccessfullytothatlocationandwillassumecontrol

overtheresourceinquestion.Meanwhile,ifaprocessorontherightside

attempts towriteazerotothesamesemaphoreflagitwillfail,as willbe

verifiedbythefactthataonewillbereadfromthatsemaphoreontheright

side during subsequent read. Had a sequence of READ/WRITE been

usedinstead,systemcontentionproblemscouldhaveoccurredduringthe

gap between the read and write cycles.

Figure 4. IDT7007 Semaphore Logic

theother.

One caution that should be noted when using semaphores is that

semaphoresalonedonotguaranteethataccesstoaresourceissecure.

Aswithanypowerfulprogrammingtechnique,ifsemaphoresaremisused

ormisinterpreted, a software errorcaneasilyhappen.

Initializationofthesemaphoresisnotautomaticandmustbehandled

viatheinitializationprogramatpower-up.Sinceanysemaphorerequest

flagwhichcontainsazeromustberesettoaone,allsemaphoresonboth

sidesshouldhaveaonewrittenintothematinitializationfrombothsides

to assure that they will be free when needed.

Using Semaphores—Some Examples

Perhapsthesimplestapplicationofsemaphoresistheirapplicationas

resourcemarkersfortheIDT7007’sDual-PortRAM. Saythe32Kx8RAM

was tobedividedintotwo16Kx8blocks whichweretobededicatedat

anyonetimetoservicingeithertheleftorrightport.Semaphore0could

be used to indicate the side which would control the lower section of

memory,andSemaphore1couldbedefinedastheindicatorfortheupper

sectionofmemory.

Totakearesource,inthisexamplethelower16KofDual-PortRAM,

the processor on the left port could write and then read a zero in to

Semaphore0.Ifthistaskweresuccessfullycompleted(azerowasread

backratherthana one), the leftprocessorwouldassume controlofthe

lower16K.Meanwhiletherightprocessorwasattemptingtogaincontrol

ofthe resourceaftertheleftprocessor,itwouldreadbackaoneinresponse

tothezeroithadattemptedtowriteintoSemaphore0.Atthis point,the

softwarecouldchoosetotryandgaincontrolofthesecond16Ksection

bywriting,thenreadingazerointoSemaphore1.Ifitsucceededingaining

control,itwouldlockouttheleftside.

Itisimportanttonotethatafailedsemaphorerequestmustbefollowed

byeitherrepeatedreadsorbywritingaoneintothesamelocation.The

reasonforthisiseasilyunderstoodbylookingatthesimplelogicdiagram

ofthesemaphoreflaginFigure4.Twosemaphorerequestlatchesfeed

into a semaphore flag. Whichever latch is first to present a zero to the

semaphoreflagwillforceitssideofthesemaphoreflagLOWandtheother

sideHIGH.Thisconditionwillcontinueuntilaoneiswrittentothesame

semaphorerequestlatch.Shouldtheotherside’ssemaphorerequestlatch

havebeenwrittentoazerointhemeantime,thesemaphoreflagwillflip

19

IDT7007S/L

High-Speed 32K x 8 Dual-Port Static RAM

Military, Industrial and Commercial Temperature Ranges

Once the left side was finished with its task, it would write a one to was“off-limits”totheCPU,boththeCPUandtheI/Odevicescouldaccess

Semaphore 0 and may then try to gain access to Semaphore 1. If theirassignedportionsofmemorycontinuouslywithoutanywaitstates.

Semaphore1wasstilloccupiedbytherightside,theleftsidecouldundo

Semaphoresarealsousefulinapplicationswherenomemory“WAIT”

itssemaphorerequestandperformothertasksuntilitwasabletowrite,then stateisavailableononeorbothsides.Onceasemaphorehandshakehas

readazerointoSemaphore1.Iftherightprocessorperformsasimilartask been performed, both processors can access their assigned RAM

withSemaphore0,thisprotocolwouldallowthetwoprocessorstoswap segmentsatfullspeed.

16Kblocks ofDual-PortRAMwitheachother.

Anotherapplicationisintheareaofcomplexdatastructures.Inthis

The blocks do not have to be any particular size and can even be case,blockarbitrationisveryimportant.Forthisapplicationoneprocessor

variable, depending upon the complexity of the software using the mayberesponsibleforbuildingandupdatingadatastructure.Theother

semaphoreflags.AlleightsemaphorescouldbeusedtodividetheDual- processorthenreadsandinterpretsthatdatastructure.Iftheinterpreting

PortRAMorothersharedresources intoeightparts. Semaphores can processorreadsanincompletedatastructure,amajorerrorconditionmay

evenbeassigneddifferentmeaningsondifferentsidesratherthanbeing exist.Therefore,somesortofarbitrationmustbeusedbetweenthetwo

given a common meaning as was shown in the example above.

differentprocessors.Thebuildingprocessorarbitratesfortheblock,locks

Semaphores are a useful form of arbitration in systems like disk itandthenisabletogoinandupdatethedatastructure.Whentheupdate

interfaceswheretheCPUmustbelockedoutofasectionofmemoryduring is completed, the data structure block is released. This allows the

atransferandtheI/Odevicecannottolerateanywaitstates.Withtheuse interpretingprocessortocomebackandreadthecompletedatastructure,

ofsemaphores,oncethetwodeviceshasdeterminedwhichmemoryarea therebyguaranteeingaconsistentdatastructure.

20

IDT7007S/L

High-Speed 32K x 8 Dual-Port Static RAM

Military, Industrial and Commercial Temperature Ranges

OrderingInformation

IDT XXXXX

A

999

A

Device

Type

Power Speed Package

Process/

Temperature

Range

Blank

I ⁽¹⁾

B

Commercial (0°C to +70°C)

Industrial (-40°C to +85°C)

Military (-55°C to +125°C)

Compliant to MIL-PRF-38535 QML

G⁽²⁾

Green

PF

G

J

80-pin TQFP (PN80-1)

68-pin PGA (G68-1)

68-pin PLCC (J68-1)

,

Commercial Only

Commercial & Industrial

Commercial, Industrial & Military

15

20

25

35

55

Speed in nanoseconds

S

L

Standard Power

Low Power

256K (32K x 8) Dual-Port RAM

7007

2940 drw 21

NOTES:

1. Contact your local sales office for industrial temp. range for other speeds, packages and powers.

2. Green parts available. For specific speeds, packages and powers contact your local sales office.

DatasheetDocumentHistory

01/05/99:

Initiateddatasheetdocumenthistory

Convertedtonewformat

Cosmeticandtypographicalcorrections

Addedadditionalnotestopinconfigurations

Changeddrawingformat

AddedIndustrialTemperatureRangesandremovedrelatednotes

Replaced IDT logo

Pages 2, 3, 4

06/03/99:

03/24/00:

Changed±200mVto0mVinnotes

Addedcopyrightinfo

FixedAbsoluteMaximumRatingschart,correctedtypos

Updateddrawings

Correctedwaveformdrawing

Increasedstoragetemperatureparameter

ClarifiedTAparameter

05/08/00:

Page 1

Page 5

Page 9

Page 12

Page 5

Pages 6, 7

Page 2 - 4

Page 6

DCElectricalparameters–changedworkingfromopentodisabled

Addeddaterevisionforpinconfigurations

RemovedstandardpowerofferingforIndustrialtempfor20nsfromDCElectricalCharacteristics

Addedgreenavailabilitytofeatures

09/11/01:

01/31/06:

Page 1

Page 21

Addedgreenindicatortoorderinginformation

CORPORATE HEADQUARTERS

6024 Silver Creek Valley Road

San Jose, CA 95138

for SALES:

for Tech Support:

408-284-2794

DualPortHelp@idt.com

800-345-7015 or 408-284-8200

fax: 408-284-2775

www.idt.com

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

21

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Obsolete	Reach Compliance Code：	not_compliant
风险等级：	5.29	最长访问时间：	25 ns
I/O 类型：	COMMON	JESD-30 代码：	S-PQCC-J68
JESD-609代码：	e0	内存密度：	262144 bit
内存集成电路类型：	MULTI-PORT SRAM	内存宽度：	8
湿度敏感等级：	1	端口数量：	2
端子数量：	68	字数：	32768 words
字数代码：	32000	工作模式：	ASYNCHRONOUS
最高工作温度：	125 °C	最低工作温度：	-55 °C
组织：	32KX8	输出特性：	3-STATE
封装主体材料：	PLASTIC/EPOXY	封装代码：	QCCJ
封装等效代码：	LDCC68,1.0SQ	封装形状：	SQUARE
封装形式：	CHIP CARRIER	并行/串行：	PARALLEL
峰值回流温度（摄氏度）：	225	电源：	5 V
认证状态：	Not Qualified	筛选级别：	38535Q/M;38534H;883B
最大待机电流：	0.03 A	最小待机电流：	4.5 V
子类别：	SRAMs	最大压摆率：	0.345 mA
标称供电电压 (Vsup)：	5 V	表面贴装：	YES
技术：	CMOS	温度等级：	MILITARY
端子面层：	Tin/Lead (Sn85Pb15)	端子形式：	J BEND
端子节距：	1.27 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	30	Base Number Matches：	1

型号	制造商	描述	价格	文档
IDT7007S25JG	IDT	Dual-Port SRAM, 32KX8, 25ns, CMOS, PQCC68, 0.950 X 0.950 INCH, 0.170 INCH HEIGHT, GREEN, PLASTIC, LCC-68	获取价格
IDT7007S25JG8	IDT	Multi-Port SRAM, 32KX8, 25ns, CMOS, PPGA68	获取价格
IDT7007S25JGB	IDT	Dual-Port SRAM, 32KX8, 25ns, CMOS, PQCC68, 0.950 X 0.950 INCH, 0.170 INCH HEIGHT, GREEN, PLASTIC, LCC-68	获取价格
IDT7007S25JGB8	IDT	Multi-Port SRAM, 32KX8, 25ns, CMOS, PPGA68	获取价格
IDT7007S25JGI	IDT	Dual-Port SRAM, 32KX8, 25ns, CMOS, PQCC68, 0.950 X 0.950 INCH, 0.170 INCH HEIGHT, GREEN, PLASTIC, LCC-68	获取价格
IDT7007S25JGI8	IDT	Multi-Port SRAM, 32KX8, 25ns, CMOS, PPGA68	获取价格
IDT7007S25JI	IDT	HIGH-SPEED 32K x 8 DUAL-PORT STATIC RAM	获取价格
IDT7007S25JI8	IDT	Multi-Port SRAM, 32KX8, 25ns, CMOS, PQCC68	获取价格
IDT7007S25PF	IDT	HIGH-SPEED 32K x 8 DUAL-PORT STATIC RAM	获取价格
IDT7007S25PFB	IDT	HIGH-SPEED 32K x 8 DUAL-PORT STATIC RAM	获取价格

IDT7007S25JB8

IDT7007S25JB8 概述

IDT7007S25JB8 规格参数

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