概述
规格参数
数据手册IS25C08-3GI 概述
EEPROM, 1KX8, Serial, CMOS, PDSO8, SOIC-8 EEPROM
IS25C08-3GI 规格参数
| 是否无铅： | 含铅 | 是否Rohs认证： | 不符合 |
| 生命周期： | Obsolete | 零件包装代码： | SOIC |
| 包装说明： | SOP, SOP8,.25 | 针数： | 8 |
| Reach Compliance Code： | not_compliant | ECCN代码： | EAR99 |
| HTS代码： | 8542.32.00.51 | 风险等级： | 5.41 |
| Is Samacsys： | N | 最大时钟频率 (fCLK)： | 5 MHz |
| 数据保留时间-最小值： | 100 | 耐久性： | 1000000 Write/Erase Cycles |
| JESD-30 代码： | R-PDSO-G8 | JESD-609代码： | e0 |
| 长度： | 4.9 mm | 内存密度： | 8192 bit |
| 内存集成电路类型： | EEPROM | 内存宽度： | 8 |
| 功能数量： | 1 | 端子数量： | 8 |
| 字数： | 1024 words | 字数代码： | 1000 |
| 工作模式： | SYNCHRONOUS | 最高工作温度： | 85 °C |
| 最低工作温度： | -40 °C | 组织： | 1KX8 |
| 封装主体材料： | PLASTIC/EPOXY | 封装代码： | SOP |
| 封装等效代码： | SOP8,.25 | 封装形状： | RECTANGULAR |
| 封装形式： | SMALL OUTLINE | 并行/串行： | SERIAL |
| 峰值回流温度（摄氏度）： | 240 | 电源： | 3/5 V |
| 认证状态： | Not Qualified | 座面最大高度： | 1.75 mm |
| 串行总线类型： | SPI | 最大待机电流： | 0.000001 A |
| 子类别： | EEPROMs | 最大压摆率： | 0.005 mA |
| 最大供电电压 (Vsup)： | 5.5 V | 最小供电电压 (Vsup)： | 2.5 V |
| 标称供电电压 (Vsup)： | 5 V | 表面贴装： | YES |
| 技术： | CMOS | 温度等级： | INDUSTRIAL |
| 端子面层： | Tin/Lead (Sn/Pb) | 端子形式： | GULL WING |
| 端子节距： | 1.27 mm | 端子位置： | DUAL |
| 处于峰值回流温度下的最长时间： | 30 | 宽度： | 3.9 mm |
| 最长写入周期时间 (tWC)： | 5 ms | 写保护： | HARDWARE/SOFTWARE |
| Base Number Matches： | 1 |
IS25C08-3GI 数据手册
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IS25C08
IS25C16
ISSI
8,192/16,384-BIT SPI SERIAL
ELECTRICALLY ERASABLE PROM
AdvancedInformation
February2004
FEATURES
DESCRIPTION
TheIS25C08andIS25C16areelectricallyerasable
PROM devices that use the Serial Peripheral Interface
(SPI) for communications. The IS25C08 is 8Kbit
(1024x 8) and the IS25C16 is 16Kbit (2048 x 8). The
IS25C08/16EEPROMsareofferedinwideoperating
voltages of 1.8V to 5.5V and 2.5V to 5.5V compatible
with most application voltages. ISSI designed the
IS25C08/16 to be an efficient SPI EEPROM solution.
The devices are packaged in 8-pin PDIP and 8-pin
SOIC.
• SerialPeripheralInterface(SPI)Compatible
— Supports SPI Modes 0 (0,0) and 3 (1,1)
• LowpowerCMOS
— Active current less than 3.0 mA (2.5V)
— Standby current less than 1 µA (2.5V)
• Low-voltage Operation
— Vcc = 2.5V to 5.5V -3
— Vcc = 1.8V to 5.5V -2
• Block Write Protection
— Protect 1/4, 1/2, or Entire Array
•
16bytepagewritemode
The functional features of the IS25C08/16 allow them to
beamongthemostadvancedserialnon-volatilememo-
ries available. Each device has a Chip-Select (CS) pin,
and a 3-wire interface of Serial Data In (SI), Serial Data
Out (SO), and Serial Clock (SCK). While the 3-wire
interfaceoftheIS25C08/16providesforhigh-speed
access, a HOLD pin allows the memories to ignore the
interface in a suspended state; later the HOLD pin re-
activates communication without re-initializing the serial
sequence. A Status Register facilitates a flexible write
— Partial page writes allowed
• 10 MHz Clock Rate (5V)
• Self timed write cycles (5 ms Typical)
• High-reliability
— Endurance: 1 million cycles per byte
— Data retention: 100 years
8-pinPDIPand 8-pinSOIC packagesareavailable
•
protectionmechanism,andadevice-readybit(RDY).
Copyright © 2004 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
IntegratedSiliconSolution,Inc.—1-800-379-4774
Advanced Information Rev. 00E
1
02/13/04
IS25C08
IS25C16
®
ISSI
PIN CONFIGURATION
8-Pin DIP and SOIC
CS
SO
1
2
3
4
8
7
6
5
VCC
HOLD
SCK
SI
WP
GND
PIN DESCRIPTIONS
Chip Select (CS): The CS pin activates the device.
Upon power-up, CS should follow Vcc. When the device
is to be enabled for instruction input, the signal requires
a High-to-Low transition. While CS is stable Low, the
master and slave will communicate via SCK, SI, and SO
signals. Upon completion of communication, CS must
be driven High. At this moment, the slave device may
start its internal write cycle. When CS is high, the
device enters a power-saving standby mode, unless an
internal write operation is underway. During this mode,
the SO pin becomes high impedance.
CS
Chip Select
SCK
SI
Serial Data Clock
Serial Data Input
Serial Data Output
Ground
SO
GND
VCC
WP
HOLD
NC
Power
Write Protect
Suspends Serial Input
NoConnect
Write Protect (WP): The purpose of this input signal is
to initiate Hardware Write Protection mode. This mode
prevents the Block Protection bits and the WPEN bit in
the Status Register from being altered. To cause
Hardware Write Protection, WP must be Low at the same
time WPEN is 1. WP may be hardwired to Vcc or GND.
PIN DESCRIPTIONS
Serial Clock (SCK): This timing signal provides syn-
chronizationbetweenthemicrocontrollerandIS25C08/
16. Op-Codes, byte addresses, and data are latched on
SI with a rising edge of the SCK. Data on SO is re-
freshed on the falling edge of SCK for SPI modes (0,0)
and(1,1).
HOLD (HOLD): This input signal is used to suspend the
device in the middle of a serial sequence and temporarily
ignore further communication on the bus (SI, SO, SCK).
Together with Chip Select, the HOLD signal allows
Serial Data Input (SI): This is the input pin for all data
multiple slaves to share the bus. The HOLD signal
transitions must occur only when SCK is Low, and be
held stable during SCK transitions. (See Figure 8 for
Hold timing) To disable this feature, HOLD may be
that the IS25C08/16 is required to receive.
Serial Data Output (SO): This is the output pin for all
datatransmittedfromtheIS25C08/16.
hardwired to Vcc.
2
IntegratedSiliconSolution,Inc.—1-800-379-4774
AdvancedInformation Rev. 00E
02/13/04
IS25C08
IS25C16
®
ISSI
SERIAL INTERFACE DESCRIPTION
MASTER: The device that provides a clock signal.
SLAVE: The IS25C08/16 is a slave because the clock
signal is an input.
TRANSMITTER/RECEIVER: TheIS25C08/16hasboth
data input (SI) and data output (SO).
MSB: The most significant bit. It is always the first bit
transmittedorreceived.
OP-CODE: The first byte transmitted to the slave
following CS transition to LOW. If the OP-CODE is a
valid member of the IS25C08/16 instruction set (Table 3),
then it is decoded appropriately. If the OP-CODE is not
valid, and the SO pin remains in high impedance.
BLOCK DIAGRAM
VCC
GND
STATUS
1024 x 8/2048 x 8
REGISTER
MEMORY ARRAY
DATA
REGISTER
OUTPUT
BUFFER
ADDRESS
DECODER
SI
MODE
DECODE
LOGIC
CS
WP
SO
CLOCK
SCK
HOLD
IntegratedSiliconSolution,Inc.—1-800-379-4774
AdvancedInformation Rev. 00E
3
02/13/04
IS25C08
IS25C16
®
ISSI
STATUS REGISTER
The status register contains 8-bits for write protection
control and write status. (See Table 1). It is the only
region of memory other than the main array that is
accessible by the user.
Block Protect (BP1, BP0), Bits 2-3: Together, these
bits represent one of four block protection configurations
implemented for the memory array. (See Table 2 for
details.)
BP0 and BP1 are non-volatile cells similar to regular
array cells, and factory programmed to 0. The block of
memory defined by these bits is always protected,
regardless of the setting of WPEN, WP , or WEN.
Table 1. Status Register Format
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit1 Bit 0
WPEN
X
X
X
BP1 BP0 WEN RDY
Table 2. Block Protection
Notes:
1. X = Don't care bit.
Status
Register
2. During internal write cycle, bits 0 to 7 are temporarily 1's.
Bits
ArrayAddressesProtected
Level
0
BP1 BP0
IS25C08
IS25C16
The Status Register is Read-Only if either: a) Hardware
Write Protection is enabled or b) WEN is set to 1. If
neither is true, it can be modified by a valid instruction.
0
0
0
1
None
None
1(1/4)
0300h
03FFh
0600h
07FFh
2(1/2)
3(All)
1
1
0
1
0200h
03FFh
0400h
07FFh
Ready (RDY), Bit 0: When RDY = 1, it indicates that
the device is busy with a write cycle. RDY = 0 indi-
cates that the device is ready for an instruction. If RDY
= 1, the only command that will be handled by the
device is Read Status Register.
0000h
03FFh
0000h
07FFh
Don’t Care, Bits 4-6: Each of these bits can receive
either 0 or 1, but values will not be retained. When
these bits are read from the register, they are always 0.
Write Enable (WEN), Bit 1: This bit represents the
status of device write protection. If WEN = 0, the Status
Register and the entire array is protected from modifica-
tion, regardless of the setting of WPEN, WP pin, or block
protection. The only way to set WEN to 1 is via the
Write Enable command (WREN). WEN is reset to 0
uponpower-up.
Write Protect Enable (WPEN), Bit 7: This bit can be
used in conjunction with WP pin to enable Hardware
Write Protection, which causes the Status Register to
be read-only. The memory array is not protected by this
mode. Hardware Write Protection requires that WP = 0
and WPEN = 1; it is disabled otherwise. Note: WPEN
cannot be changed from 1 to 0 if the WP pin is already
set to Low. (See Table 4 for data protection relationship)
4
IntegratedSiliconSolution,Inc.—1-800-379-4774
AdvancedInformation Rev. 00E
02/13/04
IS25C08
IS25C16
®
ISSI
DEVICE OPERATION
The operations of the IS25C08/16 are controlled by a set of instructions that are clocked-in serially SI pin. (See Table
3). To begin an instruction, the chip select (CS) should be dropped Low. Subsequently, each Low-to-High transition
of the clock (SK) will latch a stable value on the SI pin. After the 8-bit op-code, it may be appropriate to continue to
input an address or data to SI, or to output data from SO. During data output, values appear on the falling edge of SK.
All bits are transferred with MSB first. Upon the last bit of communication, but prior to any following Low-to-High
transition of SK, CS should be raised High to end the transaction. The device then would enter Standby Mode if no
internalprogrammingwereunderway.
Table 3. Instruction Set
Name Op-code
Operation
Address
Data(SI)
Data (SO)
WREN 0000 X110
Set Write Enable Latch
Reset Write Enable Latch
Read Status Register
Write Status Register
Read Data from Array
Write Data to Array
-
-
-
WRDI
0000 X100
-
-
-
RDSR 0000 X101
WRSR 0000 X001
READ 0000 X011
WRITE 0000 X010
-
-
D7-D0,...
-
D7-D0
-
-
A15-A0
A15-A0
D7-D0,...
-
D7-D0,...
1. X = Don’t care bit. For consistency, it is best to use “0”.
2. Some address bits are don’t care. See Table 5.
3. If the bits clocked-in for an op-code are invalid, SO remains high impedance, and upon CS going High there is no
affect. A valid op-code with an invalid number of bits clocked-in for address or data will cause an attempt to modify the
array or Status Register to be ignored.
READSTATUSREGISTER(RDSR)
WRITEENABLE(WREN)
The Read Status instruction tells the user the status of
Write Protect Enable, the Block Protection setting (see
Table 2), the Write Enable state, and the RDY status.
RDSR is the only instruction accepted when a write
cycle is underway. It is recommended that the status of
Write Enable and RDY be checked, especially prior to
an attempted modification of data. The 8 bits of the
Status Register can be repeatedly output on SO after
the initial Op-code. (See Figure 4 for timing).
When Vcc is initially applied, the device powers up with
both status register and entire array in a write-disabled
state. Upon completion of Write Disable (WRDI), Write
Status Register (WRSR), or Write Data to Array
(WRITE), the device resets the WEN bit in the Status
Register to 0. Prior to any data modification, a WREN
instruction is necessary to set WEN to 1. (See Figure 2
fortiming).
WRITEDISABLE(WRDI)
The device can be completely protected from modifica-
tion by resetting WEN to 0 through the WRDI instruc-
tion. (See Figure 3 for timing).
IntegratedSiliconSolution,Inc.—1-800-379-4774
AdvancedInformation Rev. 00E
5
02/13/04
IS25C08
IS25C16
®
ISSI
WRITEDATA(WRITE)
WRITESTATUSREGISTER(WRSR)
The WRITE instruction begins with the op-code, the 16-
bit address of the first byte to be modified, and the first
This instruction lets the user choose a Block Protection
setting, and set or reset the WPEN bit. The values of
the other data bits incorporated into WRSR can be 0 or
1, and are not stored in the Status Register. WRSR will
be ignored unless both the following are true: a) WEN =
1, due to a prior WREN instruction; and b) Hardware
Write Protection is not enabled. (See Table 4 for de-
tails). Except for the RDY status, the values in the
Status Register remain unchanged until the moment
when the write cycle is complete and the register is
updated. Note: WPEN can be changed from 1 to 0 only
if WP is already set High. Once completed, WEN is
reset for complete chip write protection. (See Figure 5
fortiming).
data byte. Additional data bytes may be written sequen-
tially to the array after the first byte. Each WRITE
instruction can affect the contents of a 16 byte page, but
nomore.ThepagebeginsataddressXXXXXXXX
XXXX0000,andendswithXXXXXXXXXXXX1111.Ifthelast
byte of the page is input, the address rolls over to the
beginning of the same page. More than 16 data bytes
can be input during the same instruction, but upon a
completed write cycle, a page would only contain the
last 16 bytes.
The region of the array defined within Block Protection
cannot be modified as long as that block configuration is
selected. The region of the array outside the Block
Protection can only be modified if Write Enable (WEN) is
set to 1. Therefore, it may be necessary that a WREN
instruction occur prior to WRITE. Hardware Write
Protection has no affect on the memory array. Once
Write is completed, WEN is reset for complete chip
write protection. (See Figure 7 for timing).
READDATA(READ)
This instruction begins with the op-code and the 16-bit
address, and causes the selected data byte to be
shifted out on SO. Following this first data byte, addi-
tional sequential bytes are output. If the data byte in the
highest address is output, the address rolls-over to the
lowest address in the array, and the output could loop
indefinitely. At any time, a rising CS signal completes
the operation. (See Figure 6 for timing).
Table 5. Address Key
Name
IS25C08
IS25C16
AN
A9-A0
A10-A0
Don't
Care Bits
A15-A10
A15-A11
Table 4. Write Protection
WPEN
WP
HardwareWrite
Protection
WEN
Inside Block
OutsideBlock
StatusRegister
(WPEN, BP1, BP0)
0
X
Not Enabled
0
Read-only
Read-only
Read-only
0
1
1
X
0
Not Enabled
Enabled
1
0
1
Read-only
Read-only
Read-only
Unprotected
Read-only
Unprotected
Read-only
Read-only
0
Enabled
Unprotected
X
X
1
Not Enabled
0
1
Read-only
Read-only
Read-only
Read-only
1
Not Enabled
Unprotected
Unprotected
Note: X = Don't care bit.
6
IntegratedSiliconSolution,Inc.—1-800-379-4774
AdvancedInformation Rev. 00E
02/13/04
IS25C08
IS25C16
®
ISSI
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Parameter
Value
Unit
V
VS
SupplyVoltage
-0.5 to + 6.5
–0.5 to + 6.5
–55 to +125
–65 to +150
VP
Voltage on Any Pin
TemperatureUnderBias
StorageTemperature
V
TBIAS
TSTG
°C
°C
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause perma-
nentdamagetothedevice. Thisisastressratingonlyandfunctionaloperationofthedeviceat
these or any other conditions outside those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
OPERATING RANGE (IS25C16-2 and IS25C08-2)
Range
Ambient Temperature
0°C to +70°C
VCC
Commercial
Industrial
1.8V to 5.5V
1.8V to 5.5V
–40°Cto+85°C
OPERATING RANGE (IS25C16-3 and IS25C08-3)
Range
Ambient Temperature
0°C to +70°C
VCC
Commercial
Industrial
Automotive
2.5V to 5.5V
2.5V to 5.5V
2.5V to 5.5V
–40°Cto+85°C
–40°Cto+125°C
CAPACITANCE(1,2)
Symbol Parameter
Conditions
Max.
Unit
pF
CIN
Input Capacitance
Output Capacitance
VIN = 0V
6
8
COUT
VOUT = 0V
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters and not 100%
tested.
2. Test conditions: TA = 25°C, f = 1 MHz, Vcc = 5.0V.
IntegratedSiliconSolution,Inc.—1-800-379-4774
AdvancedInformation Rev. 00E
7
02/13/04
IS25C08
IS25C16
®
ISSI
DC ELECTRICAL CHARACTERISTICS
TA = 0°C to +70°C for Commercial, TA = –40°C to +85°C for Industrial, TA = –40°C to +125°C for Automotive.
Symbol Parameter
TestConditions
Min.
—
Max.
Unit
V
VOL1
VOL2
VOL3
VOH1
VOH2
VOH3
VIH
OutputLOWVoltage
VCC = 5V, IOL = 2 mA
VCC = 2.5V, IOL = 1.5 mA
VCC = 1.8V, IOL = 0.15 mA
VCC = 5V, IOH = -2 mA
VCC = 2.5V, IOH = -0.4mA
VCC = 1.8V, IOH = -0.1mA
0.4
OutputLOWVoltage
OutputLOWVoltage
OutputHIGHVoltage
OutputHIGHVoltage
OutputHIGHVoltage
Input HIGH Voltage
Input LOW Voltage
—
0.4
V
—
0.2
V
0.8 X VCC
0.8 X VCC
0.8 X VCC
0.7X VCC
-0.3
—
V
—
V
—
VCC + 1
0.3 X VCC
2
V
V
VIL
V
ILI
InputLeakageCurrent
OutputLeakageCurrent
VIN = 0V TO VCC
-2
µA
µA
ILO
VOUT = 0V TO VCC, CS = VCC
-2
2
POWER SUPPLY CHARACTERISTICS
TA = 0°C to +70°C for Commercial, TA = –40°C to +85°C for Industrial.
Symbol Parameter
TestConditions
Min. Max.
Unit
mA
mA
mA
µA
ICC1
ICC2
ICC3
ISB1
VccOperatingCurrent
Read/Write at 10 MHz (Vcc = 5V)
Read/Write at 5 MHz (Vcc = 2.5V)
Read/Write at 2 MHz (Vcc = 1.8V)
—
—
—
—
5.0
3.0
1.0
2
VccOperatingCurrent
VccOperatingCurrent
StandbyCurrent
Vcc = 5.0V, VIN = VCC or GND
CS = Vcc
ISB2
ISB3
StandbyCurrent
StandbyCurrent
Vcc = 2.5V, VIN = VCC or GND
CS = Vcc
—
—
1
µA
µA
Vcc = 1.8V, VIN = VCC or GND
0.5
CS = Vcc
POWER SUPPLY CHARACTERISTICS
TA = –40°C to +125°C for Automotive.
Symbol Parameter
TestConditions
Min. Max.
Unit
mA
mA
µA
ICC1
ICC2
ISB1
VccOperatingCurrent
VccOperatingCurrent
StandbyCurrent
Read/Write at 5 MHz (Vcc = 5V)
Read/Write at 5 MHz (Vcc = 2.5V)
—
—
—
4.0
3.0
5.0
Vcc = 5.0V, VIN = VCC or GND
CS = Vcc
ISB2
StandbyCurrent
Vcc =2.5V, VIN = VCC or GND
—
2.0
µA
CS = Vcc
8
IntegratedSiliconSolution,Inc.—1-800-379-4774
AdvancedInformation Rev. 00E
02/13/04
IS25C08
IS25C16
®
ISSI
AC Characteristics
TA = 0°C to +70°C for Commercial, TA = –40°C to +85°C for Industrial.
1.8V to 5.5V
2.5V to 5.5V
4.5V to 5.5V
Min Max
Symbol
fSCK
tRI
Parameter
SCK Clock Frequency
InputRiseTime
Min
Max
Min
Max
Units
MHz
µs
0
2
0
5
0
10
2
—
2
—
—
90
90
100
90
90
20
30
50
50
0
2
—
—
40
40
40
15
25
15
15
25
25
0
tFI
InputFallTime
—
2
2
2
µs
tWH
tWL
tCS
SCK High Time
200
200
200
200
200
40
—
—
—
—
—
—
—
—
—
—
60
—
50
100
100
5
—
—
—
—
—
—
—
—
—
25
—
25
25
25
5
ns
SCK Low Time
—
ns
CS High Time
—
ns
tCSS
tCSH
tSU
CS Setup Time
—
ns
CS Hold Time
—
ns
Data In Setup Time
Data In Hold Time
Hold Setup Time
Hold Hold Time
Output Valid
—
ns
tH
50
—
ns
tHD
tCD
tV
100
100
0
—
ns
—
ns
150
—
ns
tHO
tLZ
OutputHoldTime
Hold to Output Low Z
Hold to Output High Z
OutputDisableTime
Write Cycle Time
0
0
0
ns
0
100
250
250
10
0
0
ns
tHZ
—
—
—
—
—
—
—
ns
tDIS
tWC
—
ns
—
ms
CL = 100pF
IntegratedSiliconSolution,Inc.—1-800-379-4774
AdvancedInformation Rev. 00E
9
02/13/04
IS25C08
IS25C16
®
ISSI
AC Characteristics
TA = –40°C to +125°C for Automotive.
2.5V to 5.5V
4.5V to 5.5V
Min Max
Symbol
fSCK
tRI
Parameter
SCK Clock Frequency
InputRiseTime
Min
Max
Units
MHz
µs
0
5
2
0
10
2
—
—
90
90
100
90
90
20
30
50
50
0
—
—
40
40
40
15
25
15
15
25
25
0
tFI
InputFallTime
2
2
µs
tWH
tWL
tCS
SCK High Time
—
—
—
—
—
—
—
—
—
60
—
50
100
100
5
—
—
—
—
—
—
—
—
—
25
—
25
25
25
5
ns
SCK Low Time
ns
CS High Time
ns
tCSS
tCSH
tSU
CS Setup Time
ns
CS Hold Time
ns
Data In Setup Time
Data In Hold Time
Hold Setup Time
Hold Hold Time
Output Valid
ns
tH
ns
tHD
tCD
tV
ns
ns
ns
tHO
tLZ
OutputHoldTime
Hold to Output Low Z
Hold to Output High Z
OutputDisableTime
Write Cycle Time
0
0
ns
0
0
ns
tHZ
—
—
—
—
—
—
ns
tDIS
tWC
ns
ms
CL = 100pF
10
IntegratedSiliconSolution,Inc.—1-800-379-4774
AdvancedInformation Rev. 00E
02/13/04
IS25C08
IS25C16
®
ISSI
TIMING DIAGRAMS
Figure 1. Synchronous Data Timing
t
CS
V
IH
IL
CS
SK
V
t
CSH
t
CSS
V
IH
IL
t
WH
tWL
V
t
SU
tH
V
V
IH
IL
DIN
VALID IN
t
V
t
HO
tDIS
V
OH
OL
HIGH-Z
HIGH-Z
DOUT
V
Figure 2. WREN Timing
CS
SK
D
IN
WREN OP-CODE
HIGH-Z
DOUT
Figure 3. WRDI Timing
CS
SK
D
IN
WRDI OP-CODE
HIGH-Z
DOUT
IntegratedSiliconSolution,Inc.—1-800-379-4774
AdvancedInformation Rev. 00E
11
02/13/04
IS25C08
IS25C16
®
ISSI
Figure 4. RDSR Timing
CS
SK
Instruction
Din
Dout
DATA OUT
7
6
5
4
3
2
1
0
Figure 5. WRSR Timing
CS
SK
DATA IN
7 6
Instruction
5
4
3
2
1
0
Din
Dout
Figure 6. READ Timing
CS
SK
Instruction
Din
BYTE Address
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
DATA OUT
Dout
7
6
5
4
3
2
1
0
12
IntegratedSiliconSolution,Inc.—1-800-379-4774
AdvancedInformation Rev. 00E
02/13/04
IS25C08
IS25C16
®
ISSI
Figure 7. WRITE Timing
CS
SK
Instruction
Din
BYTE Address
DATA IN
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Dout
Figure8.HOLDTiming
CS
t
CD
t
CD
SCK
HOLD
t
HD
t
HD
t
HZ
DOUT
t
LZ
IntegratedSiliconSolution,Inc.—1-800-379-4774
AdvancedInformation Rev. 00E
13
02/13/04
IS25C08
IS25C16
®
ISSI
ORDERING INFORMATION
Commercial Range: 0°C to +70°C
Voltage
Frequency Range
Part Number Package
2 MHz
1.8V
to 5.5V
IS25C08-2P
IS25C08-2G
300-mil Plastic DIP
SmallOutline(JEDECSTD)
2 MHz
1.8V
to 5.5V
IS25C16-2P
IS25C16-2G
300-mil Plastic DIP
SmallOutline(JEDECSTD)
5 MHz
5 MHz
2.5V
to 5.5V
IS25C08-3P
IS25C08-3G
300-mil Plastic DIP
SmallOutline(JEDECSTD)
2.5V
to 5.5V
IS25C16-3P
IS25C16-3G
300-mil Plastic DIP
SmallOutline(JEDECSTD)
ORDERING INFORMATION
Industrial Range: –40°C to +85°C
Voltage
Frequency Range
Part Number Package
2 MHz
2 MHz
5 MHz
5 MHz
1.8V
to 5.5V
IS25C08-2PI
IS25C08-2GI
300-mil Plastic DIP
SmallOutline(JEDECSTD)
1.8V
to 5.5V
IS25C16-2PI
IS25C16-2GI
300-mil Plastic DIP
SmallOutline(JEDECSTD)
2.5V
to 5.5V
IS25C08-3PI
IS25C08-3GI
300-mil Plastic DIP
SmallOutline(JEDECSTD)
2.5V
to 5.5V
IS25C16-3PI
IS25C16-3GI
300-mil Plastic DIP
SmallOutline(JEDECSTD)
®
ISSI
IntegratedSiliconSolution, Inc.
2231 Lawson Lane
Santa Clara, CA 95054
Tel: 1-800-379-4774
Fax: (408) 588-0806
E-mail: sales@issi.com
www.issi.com
14
IntegratedSiliconSolution,Inc.—1-800-379-4774
AdvancedInformation Rev. 00E
02/13/04
IS25C08-3GI 相关器件
| 型号 | 制造商 | 描述 | 价格 | 文档 |
| IS25C08-3GLA3 | ISSI | 8K-BIT/16K-BIT SPI SERIAL ELECTRICALLY ERASABLE PROM | 获取价格 |
|
| IS25C08-3PLA3 | ISSI | 8K-BIT/16K-BIT SPI SERIAL ELECTRICALLY ERASABLE PROM | 获取价格 |
|
| IS25C08-3ZLA3 | ISSI | 8K-BIT/16K-BIT SPI SERIAL ELECTRICALLY ERASABLE PROM | 获取价格 |
|
| IS25C08B | ISSI | 8K-BIT SPI SERIAL ELECTRICALLY ERASABLE PROM | 获取价格 |
|
| IS25C08B-2CLI-TR | ISSI | 8K-BIT SPI SERIAL ELECTRICALLY ERASABLE PROM | 获取价格 |
|
| IS25C08B-2GLI | ISSI | EEPROM, 1KX8, Serial, CMOS, PDSO8, 0.150 INCH, GREEN, SOIC-8 | 获取价格 |
|
| IS25C08B-2GLI-TR | ISSI | 8K-BIT SPI SERIAL ELECTRICALLY ERASABLE PROM | 获取价格 |
|
| IS25C08B-2UDLI | ISSI | EEPROM, 1KX8, Serial, CMOS, PDSO8, 2 X 3 MM, 0.55 MM HEIGHT, GREEN, UDFN-8 | 获取价格 |
|
| IS25C08B-2UDLI-TR | ISSI | 8K-BIT SPI SERIAL ELECTRICALLY ERASABLE PROM | 获取价格 |
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| IS25C08B-2ZLI-TR | ISSI | 8K-BIT SPI SERIAL ELECTRICALLY ERASABLE PROM | 获取价格 |
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