CAT24WC01LAREV-C

更新时间:2024-11-30 13:48:32
品牌:ONSEMI
描述:IC,SERIAL EEPROM,128X8,CMOS,DIP,8PIN,PLASTIC

CAT24WC01LAREV-C 概述

IC,SERIAL EEPROM,128X8,CMOS,DIP,8PIN,PLASTIC EEPROM

CAT24WC01LAREV-C 规格参数

是否Rohs认证: 符合生命周期:Obsolete
包装说明:DIP, DIP8,.3Reach Compliance Code:compliant
风险等级:5.84数据保留时间-最小值:100
耐久性:1000000 Write/Erase CyclesI2C控制字节:1010DDDR
JESD-30 代码:R-PDIP-T8内存密度:1024 bit
内存集成电路类型:EEPROM内存宽度:8
端子数量:8字数:128 words
字数代码:128最高工作温度:70 °C
最低工作温度:组织:128X8
封装主体材料:PLASTIC/EPOXY封装代码:DIP
封装等效代码:DIP8,.3封装形状:RECTANGULAR
封装形式:IN-LINE并行/串行:SERIAL
电源:3/5 V认证状态:Not Qualified
串行总线类型:I2C最大待机电流:0.000001 A
子类别:EEPROMs最大压摆率:0.003 mA
表面贴装:NO技术:CMOS
温度等级:COMMERCIAL端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
写保护:HARDWAREBase Number Matches:1

CAT24WC01LAREV-C 数据手册

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CAT24WC01/02/04/08/16  
1K/2K/4K/8K/16K-Bit Serial EEPROM  
FEATURES  
Self-Timed Write Cycle with Auto-Clear  
1,000,000 Program/Erase Cycles  
100 Year Data Retention  
400 kHz I2C Bus Compatible*  
1.8 to 5.5Volt Operation  
Low Power CMOS Technology  
8-pin DIP, SOIC, TSSOP and MSOP packages  
- "Green" package option available  
Write Protect Feature  
— Entire Array Protected When WP at VIH  
Commercial, Industrial, Automotive and  
Page Write Buffer  
Extended Temperature Ranges  
DESCRIPTION  
08/16 feature a 16-byte page write buffer. The device  
operates via the I2C bus serial interface, has a special  
write protection feature, and is available in 8-pin DIP,  
SOIC, TSSOP and MSOP packages.  
The CAT24WC01/02/04/08/16 is a 1K/2K/4K/8K/16K-  
bit Serial CMOS EEPROM internally organized as 128/  
256/512/1024/2048 words of 8 bits each. Catalyst’s  
advanced CMOS technology substantially reduces de-  
vice power requirements. The the CAT24WC01/02/04/  
PIN CONFIGURATION  
DIP Package (P, L, GL)  
BLOCK DIAGRAM  
SOIC Package (J, W, GW)  
EXTERNAL LOAD  
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
A
A
A
V
A
A
A
0
1
2
CC  
0
1
2
V
CC  
WP  
SENSE AMPS  
SHIFT REGISTERS  
D
OUT  
WP  
ACK  
SCL  
SDA  
SCL  
SDA  
V
V
V
SS  
CC  
SS  
WORD ADDRESS  
BUFFERS  
COLUMN  
DECODERS  
V
SS  
5020 FHD F01  
TSSOP Package (U, Y, GY)  
START/STOP  
(MSOP and TSSOP available for CAT24WC01,  
CAT24WC02 and CAT24WC04 only)  
MSOP Package (R, Z, GZ)  
SDA  
WP  
LOGIC  
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
V
A0  
A1  
A2  
A
A
A
CC  
0
1
2
V
CC  
WP  
WP  
E2PROM  
XDEC  
SCL  
SDA  
SCL  
SDA  
CONTROL  
LOGIC  
V
V
SS  
SS  
PIN FUNCTIONS  
DATA IN STORAGE  
Pin Name  
Function  
A0, A1, A2  
SDA  
Device Address Inputs  
Serial Data/Address  
Serial Clock  
HIGH VOLTAGE/  
TIMING CONTROL  
SCL  
SCL  
STATE COUNTERS  
WP  
Write Protect  
SLAVE  
ADDRESS  
COMPARATORS  
A
0
A1  
A2  
VCC  
+1.8V to +5.5V Power Supply  
Ground  
VSS  
2
* Catalyst Semiconductor is licensed by Philips Corporation to carry the I C Bus Protocol.  
© Catalyst Semiconductor, Inc.  
Characteristics subject to change without notice  
Doc. No. 1022, Rev. O  
1
CAT24WC01/02/04/08/16  
ABSOLUTE MAXIMUM RATINGS*  
*COMMENT  
Temperature Under Bias ................. 55°C to +125°C  
Storage Temperature....................... 65°C to +150°C  
Stresses above those listed under Absolute Maximum  
Ratingsmay cause permanent damage to the device.  
These are stress ratings only, and functional operation of  
the device at these or any other conditions outside of those  
listed in the operational sections of this specification is not  
implied. Exposure to any absolute maximum rating for  
extended periods may affect device performance and  
reliability.  
Voltage on Any Pin with  
Respect to Ground(1) ........... 2.0V to +VCC + 2.0V  
VCC with Respect to Ground ............... 2.0V to +7.0V  
Package Power Dissipation  
Capability (Ta = 25°C)................................... 1.0W  
Lead Soldering Temperature (10 secs) ............ 300°C  
Output Short Circuit Current(2) ........................ 100mA  
RELIABILITY CHARACTERISTICS  
Symbol  
Parameter  
Endurance  
Min.  
1,000,000  
100  
Max.  
Units  
Cycles/Byte  
Years  
(3)  
NEND  
(3)  
TDR  
Data Retention  
ESD Susceptibility  
Latch-up  
(3)  
VZAP  
2000  
Volts  
(3)(4)  
ILTH  
100  
mA  
D.C. OPERATING CHARACTERISTICS  
V
= +1.8V to +5.5V, unless otherwise specified.  
CC  
Limits  
Typ.  
Symbol  
Parameter  
Min.  
Max.  
Units  
mA  
µA  
µA  
µA  
V
Test Conditions  
fSCL = 100 KHz  
ICC  
Power Supply Current  
3
(5)  
ISB  
Standby Current (VCC = 5.0V)  
Input Leakage Current  
1
10  
VIN = GND or VCC  
VIN = GND to VCC  
VOUT = GND to VCC  
ILI  
ILO  
Output Leakage Current  
Input Low Voltage  
10  
VIL  
1  
VCC x 0.3  
VCC + 0.5  
0.4  
VIH  
Input High Voltage  
VCC x 0.7  
V
VOL1  
VOL2  
Output Low Voltage (VCC = 3.0V)  
Output Low Voltage (VCC = 1.8V)  
V
IOL = 3 mA  
0.5  
V
IOL = 1.5 mA  
CAPACITANCE T = 25°C, f = 1.0 MHz, V  
= 5V  
A
CC  
Symbol  
Test  
Input/Output Capacitance (SDA)  
Input Capacitance (A0, A1, A2, SCL, WP)  
Max.  
Units  
Conditions  
VI/O = 0V  
VIN = 0V  
(3)  
CI/O  
8
6
pF  
pF  
(3)  
CIN  
Note:  
(1) The minimum DC input voltage is 0.5V. During transitions, inputs may undershoot to 2.0V for periods of less than 20 ns. Maximum DC  
voltage on output pins is V +0.5V, which may overshoot to V + 2.0V for periods of less than 20ns.  
CC  
CC  
(2) Output shorted for no more than one second. No more than one output shorted at a time.  
(3) These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100  
and JEDEC test methods.  
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from 1V to V +1V.  
CC  
(5) Maximum standby current (I ) = 10µA for the Automotive and Extended Automotive temperature range.  
SB  
© Catalyst Semiconductor, Inc.  
Characteristics subject to change without notice  
Doc. No. 1022, Rev. O  
2
CAT24WC01/02/04/08/16  
A.C. CHARACTERISTICS  
V
= +1.8V to +5.5V, unless otherwise specified.  
CC  
Read & Write Cycle Limits  
CAT24WCXX-1.8  
1.8V-5.5V  
CAT24WCXX  
2.5V-5.5V 4.5V-5.5V  
Min.  
Max.  
Min.  
Max.  
Min.  
Max.  
Symbol Parameter  
Units  
FSCL  
TI(1)  
Clock Frequency  
100  
100  
400  
kHz  
Noise Suppression Time Constant at  
SCL, SDA Inputs  
200  
3.5  
200  
200  
ns  
µs  
µs  
SCL Low to SDA Data Out and ACK  
Out  
tAA  
3.5  
1
Time the Bus Must be Free Before  
a New Transmission Can Start  
(1)  
tBUF  
4.7  
4.7  
1.2  
µs  
µs  
µs  
tHD:STA  
tLOW  
Start Condition Hold Time  
Clock Low Period  
4
4.7  
4
4
4.7  
4
0.6  
1.2  
0.6  
tHIGH  
Clock High Period  
Start Condition Setup Time  
(for a Repeated Start Condition)  
µs  
tSU:STA  
4.7  
4.7  
0.6  
tHD:DAT  
tSU:DAT  
Data In Hold Time  
0
0
0
ns  
ns  
µs  
ns  
µs  
ns  
Data In Setup Time  
50  
50  
50  
(1)  
tR  
SDA and SCL Rise Time  
SDA and SCL Fall Time  
Stop Condition Setup Time  
Data Out Hold Time  
1
1
0.3  
(1)  
tF  
300  
300  
300  
tSU:STO  
tDH  
4
4
0.6  
100  
100  
100  
Power-Up Timing(1)(2)  
Symbol  
tPUR  
Parameter  
Max.  
Units  
ms  
Power-up to Read Operation  
Power-up to Write Operation  
1
1
tPUW  
ms  
Write Cycle Limits  
Symbol  
Parameter  
Write Cycle Time  
Min.  
Typ.  
Max  
Units  
tWR  
10  
ms  
interface circuits are disabled, SDA is allowed to remain  
high, and the device does not respond to its slave  
address.  
The write cycle time is the time from a valid stop  
condition of a write sequence to the end of the internal  
program/erase cycle. During the write cycle, the bus  
Note:  
(1) This parameter is tested initially and after a design or process change that affects the parameter.  
(2) t and t are the delays required from the time V is stable until the specified operation can be initiated.  
PUR  
PUW  
CC  
© Catalyst Semiconductor, Inc.  
Characteristics subject to change without notice  
Doc. No. 1022, Rev. O  
3
CAT24WC01/02/04/08/16  
FUNCTIONAL DESCRIPTION  
PIN DESCRIPTIONS  
The CAT24WC01/02/04/08/16 supports the I2C Bus  
data transmission protocol. This Inter-Integrated Circuit  
Bus protocol defines any device that sends data to the  
bus to be a transmitter and any device receiving data to  
be a receiver. Data transfer is controlled by the Master  
device which generates the serial clock and all START  
andSTOPconditionsforbusaccess.TheCAT24WC01/  
02/04/08/16 operates as a Slave device. Both the Mas-  
ter and Slave devices can operate as either transmitter  
or receiver, but the Master device controls which mode  
isactivated. Amaximumof8devices(CAT24WC01and  
CAT24WC02), 4 devices (CAT24WC04), 2 devices  
(CAT24WC08) and 1 device (CAT24WC16) may be  
connected to the bus as determined by the device  
address inputs A0, A1, and A2.  
SCL: Serial Clock  
The CAT24WC01/02/04/08/16 serial clock input pin is  
used to clock all data transfers into or out of the device.  
This is an input pin.  
SDA: Serial Data/Address  
The CAT24WC01/02/04/08/16 bidirectional serial data/  
address pin is used to transfer data into and out of the  
device. The SDA pin is an open drain output and can be  
wire-ORed with other open drain or open collector  
outputs.  
A0, A1, A2: Device Address Inputs  
These inputs set device address when cascading mul-  
tiple devices. When these pins are left floating the  
default values are zeros.  
A maximum of eight devices can be cascaded when  
Figure 1. Bus Timing  
t
t
t
F
HIGH  
R
t
t
LOW  
LOW  
SCL  
t
t
SU:STA  
HD:DAT  
t
t
t
t
HD:STA  
SU:DAT  
SU:STO  
BUF  
SDA IN  
t
t
AA  
DH  
SDA OUT  
5020 FHD F03  
Figure 2. Write Cycle Timing  
SCL  
SDA  
8TH BIT  
BYTE n  
ACK  
t
WR  
STOP  
CONDITION  
START  
CONDITION  
ADDRESS  
5020 FHD F04  
Figure 3. Start/Stop Timing  
SDA  
SCL  
5020 FHD F05  
START BIT  
STOP BIT  
© Catalyst Semiconductor, Inc.  
Characteristics subject to change without notice  
Doc. No. 1022, Rev. O  
4
CAT24WC01/02/04/08/16  
using either CAT24WC01 or CAT24WC02 device. All  
three address pins are used for these densities. If only  
one CAT24WC01 or CAT24WC02 is addressed on the  
bus, all three address pins (A0, A1and A2) can be left  
floating or connected to VSS.  
stable whenever the clock line is high. Any changes  
in the data line while the clock line is high will be  
interpreted as a START or STOP condition.  
START Condition  
The START Condition precedes all commands to the  
device, and is defined as a HIGH to LOW transition of  
SDAwhenSCLisHIGH. TheCAT24WC01/02/04/08/16  
monitortheSDAandSCLlinesandwillnotresponduntil  
this condition is met.  
A total of four devices can be addressed on a single bus  
when using CAT24WC04 device. Only A1 and A2  
address pins are used with this device. The A0 address  
pin is a no connect pin and can be tied to VSS or left  
floating. If only one CAT24WC04 is being addressed on  
thebus, theaddresspins(A1andA2)canbeleftfloating  
or connected to VSS.  
STOP Condition  
A LOW to HIGH transition of SDA when SCL is HIGH  
determinestheSTOPcondition.Alloperationsmustend  
with a STOP condition.  
Only two devices can be cascaded when using  
CAT24WC08. The only address pin used with this  
device is A2. The A0 and A1 address pins are no  
connectpinsandcanbetiedtoVSS orleftfloating. Ifonly  
one CAT24WC08 is being addressed on the bus, the  
addresspin(A2)canbeleftfloatingorconnected toVSS.  
DEVICE ADDRESSING  
The bus Master begins a transmission by sending a  
START condition. The Master then sends the address  
of the particular slave device it is requesting. The four  
most significant bits of the 8-bit slave address are fixed  
as 1010 for the CAT24WC01/02/04/08/16 (see Fig. 5).  
Thenextthreesignificantbits(A2,A1,A0)arethedevice  
addressbitsanddefinewhichdeviceorwhichpartofthe  
devicetheMasterisaccessing. UptoeightCAT24WC01/  
02, four CAT24WC04, two CAT24WC08, and one  
CAT24WC16 may be individually addressed by the  
system. The last bit of the slave address specifies  
whether a Read or Write operation is to be performed.  
When this bit is set to 1, a Read operation is selected,  
and when set to 0, a Write operation is selected.  
The CAT24WC16 is a stand alone device. In this case,  
all address pins (A0, A1and A2) are no connect pins and  
can be tied to VSS or left floating.  
WP: Write Protect  
If the WP pin is tied to VCC the entire memory array  
becomes Write Protected (READ only). When the WP  
pin is tied to VSS or left floating normal read/write  
operations are allowed to the device.  
I2C Bus Protocol  
ThefollowingdefinesthefeaturesoftheI2Cbusprotocol:  
After the Master sends a START condition and the slave  
address byte, the CAT24WC01/02/04/08/16 monitors  
the bus and responds with an acknowledge (on the SDA  
line) when its address matches the transmitted slave  
(1) Data transfer may be initiated only when the bus is  
not busy.  
(2) During a data transfer, the data line must remain  
Figure 4. Acknowledge Timing  
SCL FROM  
MASTER  
1
8
9
DATA OUTPUT  
FROM TRANSMITTER  
DATA OUTPUT  
FROM RECEIVER  
START  
ACKNOWLEDGE  
5020 FHD F06  
© Catalyst Semiconductor, Inc.  
Characteristics subject to change without notice  
Doc. No. 1022, Rev. O  
5
CAT24WC01/02/04/08/16  
Figure 5. Slave Address Bits  
CAT24WC01/02  
1
0
1
0
A2  
A1 A0  
R/W  
CAT24WC04  
CAT24WC08  
CAT24WC16  
1
1
1
0
0
0
1
1
1
0
0
0
A2  
A1 a8 R/W  
A2  
a9  
a8  
R/W  
a10 a9  
a8 R/W  
*
A0, A1 and A2 correspond to pin 1, pin 2 and pin 3 of the device.  
** a8, a9 and a10 correspond to the address of the memory array address word.  
*** A0, A1 and A2 must compare to its corresponding hard wired input pins (pins 1, 2 and 3).  
address. The CAT24WC01/02/04/08/16 then performs  
a Read or Write operation depending on the state of the  
WRITE OPERATIONS  
Byte Write  
R/W bit.  
In the Byte Write mode, the Master device sends the  
START condition and the slave address information  
(with the R/W bit set to zero) to the Slave device. After  
the Slave generates an acknowledge, the Master sends  
the byte address that is to be written into the address  
pointer of the CAT24WC01/02/04/08/16. After receiving  
another acknowledge from the Slave, the Master device  
transmits the data byte to be written into the addressed  
memory location. The CAT24WC01/02/04/08/16 ac-  
knowledge once more and the Master generates the  
STOP condition, at which time the device begins its  
internalprogrammingcycletononvolatilememory.While  
this internal cycle is in progress, the device will not  
respond to any request from the Master device.  
Acknowledge  
Afterasuccessfuldatatransfer, eachreceivingdeviceis  
requiredtogenerateanacknowledge.TheAcknowledg-  
ing device pulls down the SDA line during the ninth clock  
cycle, signaling that it received the 8 bits of data.  
The CAT24WC01/02/04/08/16 responds with an ac-  
knowledge after receiving a START condition and its  
slave address. If the device has been selected along  
with a write operation, it responds with an acknowledge  
after receiving each 8-bit byte.  
When the CAT24WC01/02/04/08/16 is in a READ mode  
it transmits 8 bits of data, releases the SDA line, and  
monitors the line for an acknowledge. Once it receives  
this acknowledge, the CAT24WC01/02/04/08/16 will  
continue to transmit data. If no acknowledge is sent by  
theMaster, thedeviceterminatesdatatransmissionand  
waits for a STOP condition.  
Page Write  
The CAT24WC01/02/04/08/16 writes up to 16 bytes of  
data in a single write cycle, using the Page Write  
operation. The Page Write operation is initiated in the  
same manner as the Byte Write operation, however  
insteadofterminatingaftertheinitialwordistransmitted,  
© Catalyst Semiconductor, Inc.  
Characteristics subject to change without notice  
Doc. No. 1022, Rev. O  
6
CAT24WC01/02/04/08/16  
the Master is allowed to send up to fifteen additional  
bytes. After each byte has been transmitted the  
CAT24WC01/02/04/08/16 will respond with an  
acknowledge, and internally increment the low order  
address bits by one. The high order bits remain  
unchanged.  
WRITE PROTECTION  
The Write Protection feature allows the user to protect  
against inadvertent programming of the memory array.  
If the WP pin is tied to VCC, the entire memory array is  
protected and becomes read only. The CAT24WC01/  
02/04/08/16 will accept both slave and byte addresses,  
but the memory location accessed is protected from  
programming by the devices failure to send an  
acknowledge after the first byte of data is received.  
If the Master transmits more than sixteen bytes prior to  
sendingtheSTOPcondition,theaddresscounterwraps  
around, and previously transmitted data will be  
overwritten.  
Once all sixteen bytes are received and the STOP  
condition has been sent by the Master, the internal  
programmingcyclebegins.Atthispointallreceiveddata  
is written to the CAT24WC01/02/04/08/16 in a single  
write cycle.  
READ OPERATIONS  
The READ operation for the CAT24WC01/02/04/08/16  
is initiated in the same manner as the write operation  
with the one exception that the R/W bit is set to a one.  
ThreedifferentREADoperationsarepossible:Immediate  
AddressREAD, SelectiveREADandSequentialREAD.  
Acknowledge Polling  
Thedisablingoftheinputscanbeusedtotakeadvantage  
of the typical write cycle time. Once the stop condition  
isissuedtoindicatetheendofthehostswriteoperation,  
the CAT24WC01/02/04/08/16 initiates the internal write  
cycle. ACK polling can be initiated immediately. This  
involves issuing the start condition followed by the slave  
addressforawriteoperation. IftheCAT24WC01/02/04/  
08/16isstillbusywiththewriteoperation, noACKwillbe  
returned. IftheCAT24WC01/02/04/08/16hascompleted  
thewriteoperation, an ACKwillbereturnedandthehost  
Immediate Address Read  
The CAT24WC01/02/04/08/16s address counter  
contains the address of the last byte accessed,  
incremented by one. In other words, if the last READ or  
WRITEaccesswastoaddressN,theREADimmediately  
following would access data from address N+1. If N=E  
(where E = 255 for 24WC02, 511 for 24WC04, 1023 for  
24WC08, and 2047 for 24WC16), then the counter will  
'wrap around' to address 0 and continue to clock out  
data. If N = E (where E = 127 for the CAT24WC01) the  
counter will not 'wrap around'.  
can then proceed with the next read or write operation.  
Figure 6. Byte Write Timing  
S
T
A
R
T
S
T
O
P
BUS ACTIVITY:  
MASTER  
SLAVE  
ADDRESS  
BYTE  
ADDRESS  
DATA  
*
SDA LINE  
S
P
A
C
K
A
C
K
A
C
K
5020 FHD F08  
Figure 7. Page Write Timing  
S
T
A
R
T
S
T
O
P
BUS ACTIVITY:  
MASTER  
SLAVE  
ADDRESS  
BYTE  
ADDRESS (n)  
DATA n  
DATA n+1  
DATA n+P  
SDA LINE  
S
P
*
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
NOTE: IN THIS EXAMPLE n = XXXX 0000(B); X = 1 or 0  
P=7 for CAT24WC01 and P=15 for CAT24WC02/04/08/16  
* = Don't care for CAT24WC01  
24WCXX F09  
© Catalyst Semiconductor, Inc.  
Characteristics subject to change without notice  
Doc. No. 1022, Rev. O  
7
CAT24WC01/02/04/08/16  
Selective Read  
operations. After the 24WC01/02/04/08/16 sends initial  
8-bit byte requested, the Master will respond with an  
acknowledge which tells the device it requires more  
data. The CAT24WC01/02/04/08/16 will continue to  
output an 8-bit byte for each acknowledge sent by the  
Master. The operation is terminated when the Master  
fails to respond with an acknowledge, thus sending the  
STOP condition.  
Selective READ operations allow the Master device to  
select at random any memory location for a READ  
operation. The Master device first performs a dummy’  
write operation by sending the START condition, slave  
address and byte address of the location it wishes to  
read. After the CAT24WC01/02/04/08/16 acknowledge  
thewordaddress,theMasterdeviceresendstheSTART  
condition and the slave address, this time with the R/W  
bit set to one. The CAT24WC01/02/04/08/16 then  
responds with its acknowledge and sends the 8-bit byte  
requested. The master device does not send an  
acknowledge but will generate a STOP condition.  
The data being transmitted from the CAT24WC01/02/  
04/08/16isoutputtedsequentiallywithdatafromaddress  
N followed by data from address N+1. The READ  
operation address counter increments all of the  
CAT24WC01/02/04/08/16addressbitssothattheentire  
memory array can be read during one operation. If more  
thantheE (whereE=255for24WC02,511for24WC04,  
1023for24WC08,and2047for24WC16)bytesareread  
out, the counter will wrap aroundand continue to clock  
out data bytes. If N = E (where E = 127 for the  
CAT24WC01) the counter will not 'wrap around'.  
Sequential Read  
The Sequential READ operation can be initiated by  
either the immediate Address READ or Selective READ  
Figure 8. Immediate Address Read Timing  
S
T
A
R
T
S
T
O
P
BUS ACTIVITY:  
MASTER  
SLAVE  
ADDRESS  
SDA LINE  
S
P
A
C
K
N
O
DATA  
A
C
K
SCL  
SDA  
8
9
8TH BIT  
DATA OUT  
NO ACK  
STOP  
5020 FHD F10  
© Catalyst Semiconductor, Inc.  
Characteristics subject to change without notice  
Doc. No. 1022, Rev. O  
8
CAT24WC01/02/04/08/16  
Figure 9. Selective Read Timing  
S
T
A
R
T
S
T
A
R
T
S
T
O
P
BUS ACTIVITY:  
MASTER  
SLAVE  
ADDRESS  
BYTE  
ADDRESS (n)  
SLAVE  
ADDRESS  
SDA LINE  
S
S
P
*
A
C
K
A
C
K
A
C
K
N
DATA n  
O
A
C
K
24WCXX F11  
Figure 10. Sequential Read Timing  
S
T
O
P
BUS ACTIVITY:  
MASTER  
SLAVE  
ADDRESS  
DATA n  
DATA n+1  
DATA n+2  
DATA n+x  
SDA LINE  
P
A
C
K
A
C
K
A
C
K
A
C
K
N
O
A
C
K
5020 FHD F12  
© Catalyst Semiconductor, Inc.  
Characteristics subject to change without notice  
Doc. No. 1022, Rev. O  
9
CAT24WC01/02/04/08/16  
8-LEAD 300 MIL WIDE PLASTIC DIP (P, L, GL)  
0.245 (6.17)  
0.295 (7.49)  
0.300 (7.62)  
0.325 (8.26)  
0.355 (9.02)  
0.400 (10.16)  
0.120 (3.05)  
0.180 (4.57) MAX  
0.150 (3.81)  
0.015 (0.38)  
0.110 (2.79)  
0.150 (3.81)  
0.100 (2.54)  
BSC  
0.310 (7.87)  
0.380 (9.65)  
0.045 (1.14)  
0.060 (1.52)  
0.014 (0.36)  
0.022 (0.56)  
Notes:  
1. Complies with JEDEC Publication 95 MS001 dimensions; however, some of the dimensions may be more stringent.  
2. All linear dimensions are in inches and parenthetically in millimeters.  
8-LEAD 150 MIL WIDE SOIC (J, W, GW)  
0.1497 (3.80) 0.2284 (5.80)  
0.1574 (4.00) 0.2440 (6.20)  
0.1890 (4.80)  
0.1968 (5.00)  
0.0099 (0.25)  
X 45  
0.0196 (0.50)  
0.0075 (0.19)  
0.0098 (0.25)  
0.0532 (1.35)  
0.0688 (1.75)  
0 8  
0.050 (1.27) BSC  
0.013 (0.33)  
0.020 (0.51)  
0.0040 (0.10)  
0.0098 (0.25)  
0.016 (0.40)  
0.050 (1.27)  
Notes:  
1. Complies with JEDEC publication 95 MS-012 dimensions; however, some dimensions may be more stringent.  
2. All linear dimensions are in inches and parenthetically in millimeters.  
© Catalyst Semiconductor, Inc.  
Characteristics subject to change without notice  
Doc. No. 1022, Rev. O  
10  
CAT24WC01/02/04/08/16  
8 LEAD MSOP (R, Z, GZ)  
0.38  
0.28  
0.0150  
0.0110  
0.1970  
0.1890  
5.00  
4.80  
S
0.0256 [0.65] BSC  
3.10  
2.90  
0.1220  
0.1142  
0.0374  
0.0295  
0.95  
0.75  
0.0433 [1.10] MAX.  
0.0059  
0.0020  
0.15  
0.05  
0.039 [0.10] MAX.  
S
S
0.0150  
0.0110  
0.38  
0.28  
WITH PLATING  
0.0091 0.23  
0.0051 0.13  
0.0050 [0.127]  
BASE METAL  
0.1220  
0.1142  
3.10  
2.90  
0.0276  
0.0157  
0.70  
0.40  
0˚ - 6˚  
WITH PLATING  
0.0118 [0.30] REF.  
SECTION A - A  
Notes:  
(1) All dimensions are in mm Angles in degrees.  
2
3
4
Does not include Mold Flash, Protrusion or Gate Burrs. Mold Flash, Protrusions or Gate Burrs shall not exceed 0.15 mm. per side.  
Does not include Interlead Flash orProtrusion. Interlead Flash or Protrusion shall not exceed 0.25 mm per side.  
Does not include Dambar Protrusion, allowable Dambar Protrusion shall be 0.08 mm.  
(5) This part is compliant with JEDEC Specification MO-187 Variations AA.  
(6) Lead span/stand off height/coplanarity are considered as special characteristics. (S)  
(7) Controlling dimensions in inches. [mm]  
© Catalyst Semiconductor, Inc.  
Characteristics subject to change without notice  
Doc. No. 1022, Rev. O  
11  
CAT24WC01/02/04/08/16  
8-LEAD TSSOP (U, Y, GY)  
© Catalyst Semiconductor, Inc.  
Characteristics subject to change without notice  
Doc. No. 1022, Rev. O  
12  
CAT24WC01/02/04/08/16  
ORDERING INFORMATION  
Prefix  
Device #  
24WC02  
Suffix  
CAT  
J
I
-1.8  
REV-E  
TE13  
Temperature Range  
Product Number  
24WC01: 1K  
24WC02: 2K  
24WC04: 4K  
24WC08: 8K  
24WC16: 16K  
Tape & Reel  
Optional  
Company ID  
Blank = Commercial (0°C to 70°C)  
I = Industrial (-40°C to 85°C)  
A = Automotive (-40°C to 105°C)  
E = Extended (-40°C to 125°C)  
Die Revision  
24WC01: C, E, F  
24WC02: C, E, F  
24WC04: F  
24WC08: F  
24WC16: D, F  
Operating Voltage  
Blank: 2.5V - 5.5V  
1.8: 1.8V - 5.5V  
Package  
P: PDIP  
J: SOIC, JEDEC  
U: TSSOP**  
R: MSOP**  
L: PDIP (Lead-free, Halogen-free)  
W: SOIC (Lead-free, Halogen-free)  
Z: MSOP (Lead-free, Halogen-free)**  
Y: TSSOP (Lead-free, Halogen-free)**  
GL: PDIP (Lead-free, Halogen-free, NiPdAu lead plating)  
GW: SOIC, JEDEC (Lead-free, Halogen-free, NiPdAu lead plating)  
GZ: MSOP (Lead-free, Halogen-free, NiPdAu lead plating)**  
GY: TSSOP (Lead-free, Halogen-free, NiPdAu lead plating)**  
** Available for CAT24WC01, CAT24WC02 and CAT24WC04  
Notes:  
(1) The device used in the above example is a CAT24WC02JI-1.8TE13REV-E (SOIC, Industrial Temperature, 1.8 Volt to 5.5 Volt  
Operating Voltage, Tape & Reel, Die Revision E)  
© Catalyst Semiconductor, Inc.  
Characteristics subject to change without notice  
Doc. No. 1022, Rev. O  
13  
REVISION HISTORY  
Date  
Rev.  
Reason  
2/3/2004  
H
Added: CAT24WC01/02/16 not recommended for  
new designs. See CAT24FC01, CAT24FC02 and  
CAT24FC16 data sheets  
5/28/2004  
7/28/2004  
1/27/2005  
2/28/2005  
3/18/2005  
8/12/2005  
I
Added Die Revision to ordering information  
Update DC operating characteristics and notes  
Added Die Revision E to ordering information  
Edit Ordering Information  
J
K
L
M
N
Edit Features  
Edit Features  
Edit Pin Functions  
Edit Reliability Characteristics  
Edit D.C. Operating Characteristics  
Edit A.C. Characteristics  
Add Package Dimensions  
Edit Ordering Information  
8/22/2008  
O
Archived data sheet.  
Copyrights, Trademarks and Patents  
© Catalyst Semiconductor, Inc.  
Trademarks and registered trademarks of Catalyst Semiconductor include each of the following:  
Beyond Memory ™, DPP ™, EZDim ™, LDD ™, MiniPot™ and Quad-Mode™  
Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. For a complete list of patents  
issued to Catalyst Semiconductor contact the Company’s corporate office at 408.542.1000.  
CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS  
PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE  
RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING  
OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES.  
Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or  
other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a  
situation where personal injury or death may occur.  
Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets  
labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale.  
Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate  
typical semiconductor applications and may not be complete.  
Catalyst Semiconductor, Inc.  
Corporate Headquarters  
2975 Stender Way  
Santa Clara, CA 95054  
Publication #: 1022  
Phone: 408.542.1000  
Fax: 408.542.1200  
www.catsemi.com  
Revison:  
O
Issue date:  
08/22/08  

CAT24WC01LAREV-C 相关器件

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CAT24WC01LATE13F CATALYST 1K/2K/4K/8K/16K-Bit Serial EEPROM 获取价格
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CAT24WC01LE-1.8REV-E ONSEMI 暂无描述 获取价格
CAT24WC01LE-1.8TE13C CATALYST 1K/2K/4K/8K/16K-Bit Serial E2PROM 获取价格
CAT24WC01LE-1.8TE13F CATALYST 1K/2K/4K/8K/16K-Bit Serial E2PROM 获取价格
CAT24WC01LE-REV-C CATALYST EEPROM, 128X8, Serial, CMOS, PDIP8, 0.300 INCH, GREEN, PLASTIC, MS-001, DIP-8 获取价格

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