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NCP3418DR2G

更新时间：2025-06-28 12:51:56
品牌：ONSEMI
描述：Dual Bootstrapped 12 V MOSFET Driver with Output Disable

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NCP3418DR2G 概述

Dual Bootstrapped 12 V MOSFET Driver with Output Disable 双自举12 V MOSFET驱动器输出禁用 MOSFET 驱动器

NCP3418DR2G 规格参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：SOIC包装说明：SOP, SOP8,.25
针数：8Reach Compliance Code：unknown
ECCN代码：EAR99HTS代码：8542.39.00.01
风险等级：5.61高边驱动器：YES
接口集成电路类型：HALF BRIDGE BASED MOSFET DRIVERJESD-30 代码：R-PDSO-G8
JESD-609代码：e3长度：4.9 mm
湿度敏感等级：1功能数量：1
端子数量：8最高工作温度：85 °C
最低工作温度：封装主体材料：PLASTIC/EPOXY
封装代码：SOP封装等效代码：SOP8,.25
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
峰值回流温度（摄氏度）：260电源：12 V
认证状态：Not Qualified座面最大高度：1.75 mm
子类别：MOSFET Drivers最大供电电压：13.2 V
最小供电电压：4.6 V标称供电电压：12 V
表面贴装：YES温度等级：COMMERCIAL EXTENDED
端子面层：Tin (Sn)端子形式：GULL WING
端子节距：1.27 mm端子位置：DUAL
处于峰值回流温度下的最长时间：40断开时间：0.06 µs
接通时间：0.06 µs宽度：3.9 mm
Base Number Matches：1

NCP3418DR2G 数据手册

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NCP3418, NCP3418A  
Dual Bootstrapped 12 V  
MOSFET Driver with  
Output Disable  
The NCP3418 and NCP3418A are dual MOSFET gate drivers  
optimized to drive the gates of both high--side and low--side power  
MOSFETs in a synchronous buck converter. Each of the drivers is  
capable of driving a 3000 pF load with a 25 ns propagation delay and a  
20 ns transition time.  
With a wide operating voltage range, high or low side MOSFET  
gate drive voltage can be optimized for the best efficiency. Internal,  
adaptive nonoverlap circuitry further reduces switching losses by  
preventing simultaneous conduction of both MOSFETs.  
The floating top driver design can accommodate VBST voltages as  
high as 30 V, with transient voltages as high as 35 V. Both gate outputs  
can be driven low by applying a low logic level to the Output Disable  
(OD) pin. An Undervoltage Lockout function ensures that both driver  
outputs are low when the supply voltage is low, and a Thermal  
Shutdown function provides the IC with overtemperature protection.  
The NCP3418A is identical to the NCP3418 except that there is no  
internal charge pump diode.  
http://onsemi.com  
MARKING  
DIAGRAMS  
8
SO--8  
D SUFFIX  
CASE 751  
341x  
AYWW  
G
8
1
1
8
SO--8 EP  
PD SUFFIX  
CASE 751AC  
341x  
ALYW  
8
The NCP3418 is pin--to--pin compatible with Analog Devices  
ADP3418 with the following advantages:  
1
1
Features  
• Faster Rise and Fall Times  
341x  
= Device Code  
x = 8 or 8A  
= Assembly Location  
= Wafer Lot  
• Internal Charge Pump Diode Reduces Cost and Parts Count  
• Thermal Shutdown for System Protection  
• Integrated OVP  
• Internal Pulldown Resistor Suppresses Transient Turn On of Either  
MOSFET  
A
L
Y
= Year  
WW, W = Work Week  
= Pb--Free Package  
G
• Anti Cross--Conduction Protection Circuitry  
• Floating Top Driver Accommodates Boost Voltages of up to 30 V  
• One Input Signal Controls Both the Upper and Lower Gate Outputs  
• Output Disable Control Turns Off Both MOSFETs  
• Complies with VRM 10.x Specifications  
• Undervoltage Lockout  
PIN CONNECTIONS  
1
8
BST  
IN  
DRVH  
SW  
OD  
PGND  
DRVL  
• Thermally Enhanced Package Available  
• Pb--Free Packages are Available  
V
CC  
ORDERING INFORMATION  
Seedetailedorderingandshippinginformationinthepackage  
dimensions section on page 2 of this data sheet.  
©
Semiconductor Components Industries, LLC, 2007  
1
Publication Order Number:  
April, 2007 -- Rev. 13  
NCP3418/D  
NCP3418, NCP3418A  
ORDERING INFORMATION  
†
Device  
NCP3418D  
Package  
SO--8  
Shipping  
98 Units / Rail  
NCP3418DR2  
SO--8  
2500 / Tape & Reel  
2500 / Tape & Reel  
NCP3418DR2G  
SO--8  
(Pb--Free)  
NCP3418ADR2  
SO--8  
2500 / Tape & Reel  
2500 / Tape & Reel  
NCP3418ADR2G  
SO--8  
(Pb--Free)  
NCP3418PDR2  
NCP3418APDR2  
SO--8 EP  
SO--8 EP  
2500 / Tape & Reel  
2500 / Tape & Reel  
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging  
Specifications Brochure, BRD8011/D.  
V
CC  
4
Not present in  
the NCP3418A  
BST  
1
2
IN  
8
7
DRVH  
SW  
100 k  
--  
+
Nonoverlap  
1.5 V  
--  
+
5
6
DRVL  
PGND  
4 V  
120 k  
3
OD  
Figure 1. NCP3418/A Block Diagram  
Description  
PIN DESCRIPTION  
Pin  
Symbol  
1
BST  
Upper MOSFET Floating Bootstrap Supply. A capacitor connected between BST and SW pins holds this boot-  
strap voltage for the high--side MOSFET as it is switched. The recommended capacitor value is between  
100 nF and 1.0 mF. An external diode will be needed with the NCP3418A.  
2
3
4
5
6
7
8
IN  
Logic--Level Input. This pin has primary control of the drive outputs.  
Output Disable. When low, normal operation is disabled forcing DRVH and DRVL low.  
Input Supply. A 1.0 mF ceramic capacitor should be connected from this pin to PGND.  
Output drive for the lower MOSFET.  
OD  
V
CC  
DRVL  
PGND  
SW  
Power Ground. Should be closely connected to the source of the lower MOSFET.  
Switch Node. Connect to the source of the upper MOSFET.  
Output drive for the upper MOSFET.  
DRVH  
http://onsemi.com  
2
NCP3418, NCP3418A  
MAXIMUM RATINGS  
Rating  
Value  
0 to 85  
0 to 150  
Unit  
°C  
Operating Ambient Temperature, T  
A
Operating Junction Temperature, T (Note 1)  
°C  
J
Package Thermal Resistance: SO--8  
Junction--to--Case, R  
45  
123  
°C/W  
°C/W  
θ
JC  
Junction--to--Ambient, R  
(2--Layer Board)  
θ
JA  
Package Thermal Resistance: SO--8 EP  
Junction--to--Ambient, R  
(Note 2)  
50  
°C/W  
°C  
θ
JA  
Storage Temperature Range, T  
--65 to 150  
S
Lead Temperature Soldering (10 sec): Reflow (SMD styles only)  
Standard (Note 3)  
Lead Free (Note 4)  
240 peak  
260 peak  
°C  
JEDEC Moisture Sensitivity Level  
SO--8 (240 peak profile)  
SO--8 (260 peak profile)  
SO--8 EP (240 peak profile)  
SO--8 EP (260 peak profile)  
1
1
1
3
--  
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the  
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect  
device reliability.  
1. Internally limited by thermal shutdown, 150°C min.  
2. Rating applies when soldered to an appropriate thermal area on the PCB.  
3. 60 -- 180 seconds minimum above 183°C.  
4. 60 -- 180 seconds minimum above 237°C.  
NOTE: This device is ESD sensitive. Use standard ESD precautions when handling.  
MAXIMUM RATINGS  
Pin Symbol  
Pin Name  
V
V
MIN  
MAX  
V
Main Supply Voltage Input  
Bootstrap Supply Voltage Input  
15 V  
-- 0 . 3 V  
CC  
BST  
30 V wrt/PGND  
35 V ≤ 50 ns wrt/PGND, 15 V wrt/SW  
--0.3 V wrt/SW  
SW  
Switching Node  
(Bootstrap Supply Return)  
30 V  
-- 1 . 0 V D C  
--10 V< 200 ns  
DRVH  
DRVL  
High--Side Driver Output  
Low--Side Driver Output  
BST + 0.3 V  
--0.3 V wrt/SW  
35 V ≤ 50 ns wrt/PGND, 15 V wrt/SW  
V
+ 0.3 V  
-- 0 . 3 V D C  
--2.0 V < 200 ns  
CC  
IN  
OD  
DRVH and DRVL Control Input  
Output Disable  
V
V
+ 0.3 V  
+ 0.3 V  
0 V  
-- 0 . 3 V  
-- 0 . 3 V  
0 V  
CC  
CC  
PGND  
Ground  
NOTE: All voltages are with respect to PGND except where noted.  
http://onsemi.com  
3
NCP3418, NCP3418A  
NCP3418--SPECIFICATIONS (Note 5) (V = 12 V, T = 0°C to +85°C, T = 0°C to +125°C unless otherwise noted.).  
CC  
A
J
Parameter  
Conditions  
Symbol  
Min  
Typ  
Max  
Unit  
SUPPLY  
Supply Voltage Range  
Supply Current  
--  
V
4.6  
--  
--  
13.2  
6.0  
V
CC  
BST = 12 V, IN = 0 V  
I
2.0  
mA  
SYS  
OD INPUT  
Input Voltage High  
--  
--  
--  
--  
2.0  
--  
--  
--  
--  
--  
V
V
Input Voltage Low  
--  
0.8  
+1.0  
Input Current  
--  
-- 1 . 0  
mA  
Propagation Delay Time (Note 6)  
See Figure 2  
t
--  
--  
40  
40  
60  
60  
ns  
ns  
pdlOD  
t
pdhOD  
PWM INPUT  
Input Voltage High  
--  
--  
--  
--  
--  
--  
2.0  
--  
--  
--  
--  
--  
V
V
Input Voltage Low  
Input Current  
0.8  
+1.0  
-- 1 . 0  
mA  
HIGH--SIDE DRIVER  
Output Resistance,  
Sourcing Current  
V
V
-- V  
-- V  
= 12 V (Note 8)  
= 12 V (Note 8)  
--  
--  
1.8  
1.0  
3.0  
2.5  
Ω
Ω
BST  
BST  
SW  
SW  
--  
--  
Output Resistance,  
Sinking Current  
Transition Times (Note 6)  
V
-- V  
= 12 V, C  
= 3.0 nF,  
t
t
--  
--  
18  
10  
25  
15  
ns  
ns  
BST  
SW  
LOAD  
rDRVH  
fDRVH  
See Figure 3  
Propagation Delay  
(Notes 6 & 7)  
V
-- V  
= 12 V  
t
pdhDRVH  
pdlDRVH  
--  
--  
30  
25  
60  
45  
ns  
ns  
BST  
SW  
t
LOW--SIDE DRIVER  
Output Resistance,  
Sourcing Current  
--  
--  
V
= 12 V  
--  
--  
1.8  
1.0  
3.0  
2.5  
Ω
Ω
CC  
(Note 8)  
Output Resistance,  
Sinking Current  
V
CC  
-- V = 12 V  
SW  
(Note 8)  
= 3.0 nF,  
LOAD  
Transition Times  
t
t
C
--  
--  
16  
11  
25  
15  
ns  
ns  
rDRVL  
fDRVL  
See Figure 3  
Propagation Delay  
t
t
See Figure 3  
--  
--  
30  
20  
60  
30  
ns  
ns  
pdhDRVL  
pdlDRVL  
UNDERVOLTAGE LOCKOUT  
UVLO  
--  
--  
--  
3.9  
4.3  
0.5  
4.6  
V
V
Hysteresis  
(Note 8)  
THERMAL SHUTDOWN  
Over Temperature Protection  
(Note 8)  
(Note 8)  
--  
150  
170  
20  
°C  
°C  
Hysteresis  
5. All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC).  
6. AC specifications are guaranteed by characterization, but not production tested.  
7. For propagation delays, “t ’’ refers to the specified signal going high; “t ’’ refers to it going low.  
pdh  
pdl  
8. GBD: Guaranteed by design; not tested in production. Specifications subject to change without notice.  
http://onsemi.com  
4
NCP3418, NCP3418A  
OD  
t
pdlOD  
t
pdhOD  
10%  
90%  
DRVH  
or  
DRVL  
Figure 2. Output Disable Timing Diagram  
IN  
t
t
fDRVL  
pdlDRVL  
t
pdlDRVH  
t
rDRVL  
DRVL  
90%  
1.5 V  
90%  
10%  
10%  
t
fDRVH  
t
t
rDRVH  
pdhDRVH  
90%  
90%  
DRVH--SW  
SW  
10%  
10%  
t
pdhDRVL  
4 V  
Figure 3. Nonoverlap Timing Diagram (timing is referenced to the 90% and 10% points unless otherwise noted)  
http://onsemi.com  
5
NCP3418, NCP3418A  
APPLICATIONS INFORMATION  
IN  
IN  
DRVH  
DRVH  
DRVL  
DRVL  
Figure 4. DRVH Rise and DRVL Fall Times  
Figure 5. DRVH Fall and DRVL Rise Times  
15  
10  
5
40  
30  
20  
trTG  
trBG  
trTG  
trBG  
10  
0
0
1
2
4
1
2
4
3
5
3
5
LOAD CAPACITANCE (nF)  
LOAD CAPACITANCE (nF)  
Figure 6. Rise Time vs. Load Capacitance  
Figure 7. Fall Time vs. Load Capacitance  
60  
50  
40  
30  
20  
I
CC  
T
V
C
= 25 °C  
A
10  
0
= 12 V  
CC  
= 3.3 nF  
1000  
1200  
load  
0
400  
IN FREQUENCY (kHz)  
200  
600  
800  
Figure 8. VCC Supply Current vs. IN Frequency  
http://onsemi.com  
6
NCP3418, NCP3418A  
APPLICATIONS INFORMATION  
Theory of Operation  
threshold, DRVL will go high after a propagation delay  
(tpdhDRVL), turning the low--side MOSFET on. However, if  
SW does not fall below 4.0 V in 300 ns, the safety timer  
circuit will override the normal control scheme and drive  
DRVL high. This will help insure that if the high--side  
MOSFET fails to turn off it will not produce an over--voltage  
at the output.  
Similarly, to prevent cross conduction during the low--side  
MOSFET’s turn--off and the high--side MOSFET’s turn--on,  
the overlap circuit monitors the voltage at the gate of the  
low--side MOSFET through the DRVL pin. When the PWM  
signal goes high, DRVL will go low after a propagation delay  
(tpdlDRVL), turning the low--side MOSFET off. However,  
before the high--side MOSFET can turn on, the overlap  
protection circuitwaits for thevoltageatDRVL to dropbelow  
1.5 V. Once this has occurred, DRVH will go high after a  
propagation delay (tpdhDRVH), turning the high--side  
MOSFET on.  
TheNCP3418andNCP3418AaresinglephaseMOSFET  
drivers optimized for driving two N--channel MOSFETs in  
a synchronous buck converter topology. The NCP3418  
features an internal diode, while the NCP3418A requires an  
external BST diode for the floating top gate driver. A single  
PWM input signal is all that is required to properly drive the  
high--side and the low--side MOSFETs. Each driver is  
capableofdrivinga3.3nFloadatfrequenciesupto500kHz.  
Low--Side Driver  
The low--side driver is designed to drive  
a
ground--referenced low RDS(on) N--Channel MOSFET. The  
voltagerailfor thelow--sidedriver isinternally connected to  
the VCC supply and PGND.  
When the NCP3418 is enabled, the low--side driver’s  
output is 180_ out of phase with the PWM input. When the  
device is disabled, the low--side gate is held low.  
High--Side Driver  
The high--side driver is designed to drive a floating low  
Application Information  
Supply Capacitor Selection  
RDS(on) N--channel MOSFET. The bias voltage for the high  
Forthesupplyinput(VCC)oftheNCP3418,alocalbypass  
capacitor is recommended to reduce noise and supply peak  
currents during operation. Use a 1.0 to 4.7 mF, low ESR  
capacitor. Multilayer ceramic chip (MLCC) capacitors  
provide the best combination of low ESR and small size.  
Keep the ceramic capacitor as close as possible to the VCC  
and PGND pins.  
side driver is developed by a bootstrap circuit referenced to  
SW. The bootstrap capacitor should be connected between  
the BST and SW pins.  
The bootstrap circuit comprises an internal or external  
diode, D1 (in which the anode is connected to VCC), and an  
external bootstrap capacitor, CBST. When the NCP3418 is  
starting up, the SW pin is at ground, so the bootstrap capacitor  
willcharge up to VCC through D1. When thePWMinputgoes  
high, the high--side driver will begin to turn on the high--side  
MOSFET by pulling charge out of CBST. As the high--side  
MOSFET turns on, the SW pin will rise to VIN, forcing the  
BST pin to VIN + VCC, which is enough gate--to--source  
voltage to hold the MOSFET on. To complete the cycle, the  
high--side MOSFET is switched off by pulling the gate down  
to the voltage at the SW pin. When low--side MOSFET turns  
on, the SW pin is held at ground. This allows the bootstrap  
capacitor to charge up to VCC again.  
Bootstrap Circuit  
The bootstrap circuit uses a charge storage capacitor  
(CBST) and the internal (or an external) diode. Selection of  
these components can be done after the high--side MOSFET  
has been chosen.  
The bootstrap capacitor must have a voltage rating that is  
able to withstand twice the maximum supply voltage. A  
minimum 50 V rating is recommended. The capacitance is  
determined using the following equation:  
Q
GATE  
ΔV  
The high--side driver’s output is in phase with the PWM input.  
When the device is disabled, the high side gate is held low.  
C
=
BST  
(eq. 1)  
BST  
where QGATE is the total gate charge of the high--side  
MOSFET, and ΔVBST is the voltage droop allowed on the  
high--side MOSFET drive. For example, a NTD60N03 has  
a total gate charge of about 30 nC. For an allowed droop of  
300 mV, the required bootstrap capacitance is 100 nF. A  
good quality ceramic capacitor should be used.  
If an external Schottky diode will be used for bootstrap,  
it must be rated to withstand the maximum supply voltage  
plus any peak ringing voltages that may be present on SW.  
The average forward current can be estimated by:  
Safety Timer and Overlap Protection Circuit  
Theoverlapprotectioncircuitpreventsboth thehigh--side  
MOSFET and the low--side MOSFET from being on at the  
same time, and minimizes the associated off times. This will  
reduce power losses in the switching elements. The overlap  
protection circuit accomplishes this by controlling the delay  
from turning off the high--side MOSFET to turning on the  
low--side MOSFET.  
To prevent cross conduction during the high--side  
MOSFET’s turn--off and the low--side MOSFET’s turn--on,  
the overlap circuit monitors the voltage at the SW pin. When  
the PWM input signal goes low, DRVH will go low after a  
propagation delay (tpdlDRVH), turning the high--side  
MOSFET off. However, before the low--side MOSFET can  
turn on, the overlap protection circuit waits for the voltage at  
the SW pin to fall below 4.0 V. OnceSW fallsbelow the4.0 V  
I
= Q  
× f  
GATE MAX  
(eq. 2)  
F(AVG)  
where fMAX is the maximum switching frequency of the  
controller. The peak surge current rating should be checked  
in--circuit, since this is dependent on the source impedance  
of the 12 V supply and the ESR of CBST.  
http://onsemi.com  
7
NCP3418, NCP3418A  
PACKAGE DIMENSIONS  
SOIC--8 NB  
CASE 751--07  
ISSUE AH  
NOTES:  
1. DIMENSIONING AND TOLERANCING PER  
ANSI Y14.5M, 1982.  
2. CONTROLLING DIMENSION: MILLIMETER.  
3. DIMENSION A AND B DO NOT INCLUDE  
MOLD PROTRUSION.  
-- X --  
A
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)  
PER SIDE.  
8
5
4
5. DIMENSION D DOES NOT INCLUDE DAMBAR  
PROTRUSION. ALLOWABLE DAMBAR  
PROTRUSION SHALL BE 0.127 (0.005) TOTAL  
IN EXCESS OF THE D DIMENSION AT  
MAXIMUM MATERIAL CONDITION.  
6. 751--01 THRU 751--06 ARE OBSOLETE. NEW  
STANDARD IS 751--07.  
S
M
M
B
0.25 (0.010)  
Y
1
K
-- Y --  
G
MILLIMETERS  
DIM MIN MAX  
INCHES  
MIN  
MAX  
0.197  
0.157  
0.069  
0.020  
A
B
C
D
G
H
J
K
M
N
S
4.80  
3.80  
1.35  
0.33  
5.00 0.189  
4.00 0.150  
1.75 0.053  
0.51 0.013  
C
N X 45  
_
SEATING  
PLANE  
-- Z --  
1.27 BSC  
0.050 BSC  
0.10 (0.004)  
0.10  
0.19  
0.40  
0.25 0.004  
0.25 0.007  
1.27 0.016  
0.010  
0.010  
0.050  
M
J
H
D
0
0.25  
5.80  
8
0
8
_
_
_
_
0.50 0.010  
6.20 0.228  
0.020  
0.244  
M
S
S
0.25 (0.010)  
Z
Y
X
SOLDERING FOOTPRINT*  
1.52  
0.060  
7.0  
4.0  
0.275  
0.155  
0.6  
0.024  
1.270  
0.050  
mm  
inches  
SCALE 6:1  
*For additional information on our Pb--Free strategy and soldering  
details, please download the ON Semiconductor Soldering and  
Mounting Techniques Reference Manual, SOLDERRM/D.  
http://onsemi.com  
8
NCP3418, NCP3418A  
PACKAGE DIMENSIONS  
SOIC--8 EP  
CASE 751AC--01  
ISSUE B  
NOTES:  
2 X  
1. DIMENSIONS AND TOLERANCING PER  
ASME Y14.5M, 1994.  
2. DIMENSIONS IN MILLIMETERS (ANGLES  
IN DEGREES).  
3. DIMENSION b DOES NOT INCLUDE  
DAMBAR PROTRUSION. ALLOWABLE  
DAMBAR PROTRUSION SHALL BE  
0.08 MM TOTAL IN EXCESS OF THE “b”  
DIMENSION AT MAXIMUM MATERIAL  
CONDITION.  
0.10  
C A--B  
D
DETAIL A  
D
A
8
EXPOSED  
PAD  
F
5
5
8
4. DATUMS A AND B TO BE DETERMINED  
AT DATUM PLANE H.  
G
E1  
E
MILLIMETERS  
2 X  
DIM MIN  
MAX  
1.75  
0.10  
1.65  
0.51  
0.48  
0.25  
0.23  
A
A1  
A2  
b
b1  
c
1.35  
0.00  
1.35  
0.31  
0.28  
0.17  
0.17  
h
0.10 C D  
2 X  
1
e
4
4
1
0.20  
C
PIN ONE  
LOCATION  
BOTTOM VIEW  
8 X b  
A
A
B
0.25  
C A--B D  
c1  
D
END VIEW  
c
4.90 BSC  
E
E1  
e
6.00 BSC  
3.90 BSC  
1.27 BSC  
TOP VIEW  
H
A
0.10  
C
L
L1  
F
0.40  
1.04 REF  
2.24  
1.27  
A2  
8 X  
(b)  
b1  
3.20  
2.51  
0.50  
GAUGE  
PLANE  
0.10  
C
G
h
θ
1.55  
0.25  
SEATING  
PLANE  
L
0
8
_
_
θ
0.25  
c1  
(L1)  
DETAIL A  
A1  
SIDE VIEW  
C
SECTION A--A  
SOLDERING FOOTPRINT*  
2.72  
0.107  
1.52  
0.060  
Exposed  
Pad  
4.0  
0.155  
2.03  
0.08  
7.0  
0.275  
0.6  
0.024  
1.270  
0.050  
mm  
inches  
SCALE 6:1  
*For additional information on our Pb--Free strategy and soldering  
details, please download the ON Semiconductor Soldering and  
Mounting Techniques Reference Manual, SOLDERRM/D.  
ON Semiconductor and  
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice  
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability  
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.  
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All  
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights  
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications  
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should  
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,  
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death  
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal  
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.  
PUBLICATION ORDERING INFORMATION  
LITERATURE FULFILLMENT:  
N. American Technical Support: 800--282--9855 Toll Free  
USA/Canada  
Europe, Middle East and Africa Technical Support:  
Phone: 421 33 790 2910  
Japan Customer Focus Center  
Phone: 81--3--5773--3850  
ON Semiconductor Website: www.onsemi.com  
Order Literature: http://www.onsemi.com/orderlit  
Literature Distribution Center for ON Semiconductor  
P.O. Box 5163, Denver, Colorado 80217 USA  
Phone: 303--675--2175 or 800--344--3860 Toll Free USA/Canada  
Fax: 303--675--2176 or 800--344--3867 Toll Free USA/Canada  
Email: orderlit@onsemi.com  
For additional information, please contact your local  
Sales Representative  
NCP3418/D  

NCP3418DR2G CAD模型

原理图符号

PCB 封装图

3D模型

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