概述
数据手册DRV8838 概述
具有相位/使能控制的 11V、1.8A H 桥电机驱动器
DRV8838 数据手册
通过下载DRV8838数据手册来全面了解它。这个PDF文档包含了所有必要的细节，如产品概述、功能特性、引脚定义、引脚排列图等信息。
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DRV883x 低压H 桥驱动器
1 特性
3 说明
• H 桥电机驱动器
DRV883x 器件系列为摄像机、消费类产品、玩具和其
他低电压或者电池供电的运动控制类应用提供了一个集
成的电机驱动器解决方案。此器件能够驱动一个直流电
机或其他器件（如螺线管）。输出驱动器模块由配置为
H 桥的 N 沟道功率 MOSFET 组成，用以驱动电机绕
组。一个内部电荷泵被用来生成所需的栅极驱动电压。
– 驱动直流电机或其他负载
– 低MOSFET 导通电阻：HS + LS 280mΩ
• 1.8A 最大驱动电流
• 独立的电机和逻辑电源引脚：
– 电机VM：0 至11 V
– 逻辑VCC：1.8 至7 V
• PWM 或PH-EN 接口
DRV883x 器件系列能够提供高达
1.8A 的输出电流。它运行在 0 至 11V 之间的电机电源
电压，以及1.8V 至7 V 范围内的器件电源电压上。
– DRV8837: PWM、IN1 和IN2
– DRV8838：PH 和EN
• 低功耗休眠模式，休眠电流最大值仅为120nA
– nSLEEP 引脚
• 小型封装尺寸
DRV8837 具有一个 PWM (IN/IN) 输入接口；
DRV8838 器件具有一个 PH-EN 输入接口。这两个接
口都与行业标准器件兼容。
还提供了用于过流保护、短路保护、欠压锁定和过热保
护的内部关断功能。
– 带有散热焊盘的8 引脚WSON 封装
– 2.0mm × 2.0mm
• 保护特性
器件信息(1)
封装尺寸（标称值）
器件型号
DRV8837
DRV8838
封装
– VCC 欠压闭锁(UVLO)
– 过流保护(OCP)
– 热关断(TSD)
WSON (8)
2.00mm × 2.00mm
2 应用范围
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
• 摄像头
1.8 V to 7 V
VCC
0 V to 11 V
VM
• 数字单镜头反光(DSLR) 镜头
• 消费类产品
• 玩具
• 机器人技术
• 医疗设备
PWM
or
PH and EN
DRV8837 and
DRV8838
1.8 A
M
nSLEEP
Brushed DC Motor
Driver
DRV883x 简化图
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SLVSBA4
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Table of Contents
7.1 Overview...................................................................10
7.2 Functional Block Diagram.........................................10
7.3 Feature Description...................................................12
7.4 Device Functional Modes..........................................15
8 Power Supply Recommendations................................18
8.1 Bulk Capacitance......................................................18
9 Layout.............................................................................19
9.1 Layout Guidelines..................................................... 19
9.2 Layout Example........................................................ 19
9.3 Power Dissipation..................................................... 19
10 Device and Documentation Support..........................20
10.1 Documentation Support.......................................... 20
10.2 Related Links.......................................................... 20
10.3 Receiving Notification of Documentation Updates..20
10.4 Community Resources............................................20
10.5 Trademarks.............................................................20
1 特性................................................................................... 1
2 应用范围............................................................................ 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................4
Pin Functions.................................................................... 4
5.1 Dapper Pin Functions................................................. 4
6 Specifications.................................................................. 6
6.1 Absolute Maximum Ratings........................................ 6
6.2 ESD Ratings............................................................... 6
6.3 Recommended Operating Conditions.........................6
6.4 Thermal Information....................................................6
6.5 Electrical Characteristics.............................................7
6.6 Timing Requirements..................................................8
6.7 Typical Characteristics................................................9
7 Detailed Description......................................................10
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision E (June 2016) to Revision F (April 2021)
Page
• 更新了整个文档中的表格、图和交叉参考的编号格式.........................................................................................1
• Added in the Independent Half-Bridge Control section.....................................................................................12
Changes from Revision D (December 2015) to Revision E (June 2016)
Page
• Changed the threshold type to the input logic voltage parameters in the Electrical Characteristics table..........7
• Changed the units for the input logic hysteresis parameter from mV to V in the Electrical Characteristics table
............................................................................................................................................................................7
• Added the Receiving Notification of Documentation Updates section .............................................................20
Changes from Revision C (February 2014) to Revision D (December 2015)
Page
• 在说明部分中对每个器件的输入接口进行了说明............................................................................................... 1
• Added CDM and HBM ESD ratings to the ESD Ratings table ...........................................................................6
Changes from Revision B (December 2013) to Revision C (February 2014)
Page
• 添加了DRV8838 器件信息、规格和时序图........................................................................................................1
• 添加了“器件信息”表........................................................................................................................................1
• 添加了PWM 接口图........................................................................................................................................... 1
• Added more information to the Detailed Description and moved information from the Functional Description ...
10
• Added functional block diagram for DRV8838 .................................................................................................10
• Added the Application and Implementation section .........................................................................................16
• Added Power Supply Recommendations, Layout, Device and Documentation Support, and Mechanical,
Packaging, and Orderable Information sections...............................................................................................18
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Changes from Revision A (August 2012) to Revision B (December 2013)
Page
• 更改了“特性”部分........................................................................................................................................... 1
• Changed Recommended Operating Conditions.................................................................................................6
• Changed Electrical Characteristics section........................................................................................................ 7
• Changed Timing Requirements section..............................................................................................................8
• Changed Power Supplies and Input Pins section.............................................................................................15
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5 Pin Configuration and Functions
VM
OUT1
OUT2
GND
1
2
3
4
8
7
6
5
VCC
nSLEEP
IN1
VM
OUT1
OUT2
GND
1
2
3
4
8
7
6
5
VCC
nSLEEP
PH
Thermal
Pad
Thermal
Pad
IN2
EN
图5-1. DSG Package 8-Pin WSON With Thermal
图5-2. DSG Package 8-Pin WSON With Thermal
Pad DRV8837 Top View
Pad DRV8838 Top View
Pin Functions
PIN
NO.
I/O
DESCRIPTION
NAME
DRV8837 DRV8838
POWER AND GROUND
Device ground
This pin must be connected to ground.
GND
VCC
VM
4
8
1
4
8
1
—
Logic power supply
I
I
Bypass this pin to the GND pin with a 0.1-µF ceramic capacitor rated for VCC.
Motor power supply
Bypass this pin to the GND pin with a 0.1-µF ceramic capacitor rated for VM.
CONTROL
EN
5
I
I
ENABLE input
—
IN1 input
IN1
IN2
PH
6
—
See the 节7 section for more information.
IN2 input
5
I
I
—
See the 节7 section for more information.
PHASE input
See the 节7 section for more information.
6
—
Sleep mode input
nSLEEP
7
7
I
When this pin is in logic low, the device enters low-power sleep mode. The device operates
normally when this pin is logic high. Internal pulldown
OUTPUT
OUT1
2
3
2
3
O
O
Motor output
Connect these pins to the motor winding.
OUT2
5.1 Dapper Pin Functions
PIN
I/O
DESCRIPTION
DRV8837 DRV8838
NAME
NO.
NO.
Device ground
This pin must be connected to ground.
GND
VCC
4
4
—
Logic power supply
8
8
I
Bypass this pin to the GND pin with a 0.1-µF ceramic capacitor rated for VCC.
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NAME
PIN
I/O
DESCRIPTION
DRV8837 DRV8838
NO.
NO.
Motor power supply
Bypass this pin to the GND pin with a 0.1-µF ceramic capacitor rated for VM.
VM
EN
IN1
1
1
I
I
I
5
ENABLE input
—
IN1 input
6
—
—
6
See the 节7 section for more information.
IN2 input
IN2
PH
5
I
I
See the 节7 section for more information.
PHASE input
See the 节7 section for more information.
—
Sleep mode input
nSLEEP
7
7
I
When this pin is in logic low, the device enters low-power sleep mode. The device operates
normally when this pin is logic high. Internal pulldown
OUT1
OUT2
2
3
2
3
O
O
Motor output
Connect these pins to the motor winding.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating ambient temperature range (unless otherwise noted)(1) (2)
MIN
–0.3
–0.3
–0.5
MAX
12
7
UNIT
V
Motor power-supply voltage
Logic power-supply voltage
Control pin voltage
VM
VCC
V
IN1, IN2, PH, EN, nSLEEP
OUT1, OUT2
7
V
Peak drive current
Internally limited
A
Operating virtual junction temperature, TJ
Storage temperature, Tstg
150
150
°C
°C
–40
–60
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground pin.
6.2 ESD Ratings
over operating ambient temperature range (unless otherwise noted)
VALUE
±3000
±1500
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Electrostatic
discharge
V(ESD)
V
Charged device model (CDM), per JEDEC specification JESD22-C101(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating ambient temperature range (unless otherwise noted)(1)
MIN
MAX
11
UNIT
VM
Motor power supply voltage
Logic power supply voltage
Motor peak current
0
1.8
0
V
V
VCC
IOUT
fPWM
VLOGIC
TA
7
1.8
250
5.5
85
A
Externally applied PWM frequency
Logic level input voltage
0
kHz
V
0
Operating ambient temperature
°C
–40
(1) Power dissipation and thermal limits must be observed.
6.4 Thermal Information
over operating free-air temperature range (unless otherwise noted)
DRV883x
THERMAL METRIC(1)
DSG (WSON)
8 PINS
60.9
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
71.4
32.2
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
1.6
ψJT
32.8
ψJB
RθJC(bot)
9.8
(1) For more information about traditional and new thermal limits, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics
TA = 25°C, over recommended operating conditions unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
POWER SUPPLIES (VM, VCC)
VM
VM operating voltage
0
11
V
VM = 5 V; VCC = 3 V;
No PWM
40
0.8
30
100
μA
IVM
VM operating supply current
VM = 5 V; VCC = 3 V;
50 kHz PWM
1.5
mA
VM = 5 V; VCC = 3 V;
nSLEEP = 0
IVMQ
VCC
VM sleep mode supply current
VCC operating voltage
95
7
nA
V
1.8
VM = 5 V; VCC = 3 V;
No PWM
300
0.7
5
500
μA
IVCC
VCC operating supply current
VCC sleep mode supply current
VM = 5 V; VCC = 3 V;
50 kHz PWM
1.5
25
mA
nA
VM = 5 V; VCC = 3 V;
nSLEEP = 0
IVCCQ
CONTROL INPUTS (IN1 or PH, IN2 or EN, nSLEEP)
Input logic-low voltage falling
threshold
VIL
0.25 × VCC 0.38 × VCC
0.46 × VCC
V
V
Input logic-high voltage rising
threshold
VIH
0.5 × VCC
VHYS
IIL
Input logic hysteresis
Input logic low current
0.08 × VCC
V
VIN = 0 V
5
–5
μA
μA
μA
kΩ
VIN = 3.3 V
50
IIH
Input logic high current
Pulldown resistance
VIN = 3.3 V, DRV8838 nSLEEP pin
60
100
55
RPD
DRV8838 nSLEEP pin
kΩ
MOTOR DRIVER OUTPUTS (OUT1, OUT2)
VM = 5 V; VCC = 3 V;
IO = 800 mA; TJ = 25°C
rDS(on)
IOFF
HS + LS FET on-resistance
Off-state leakage current
280
330
200
mΩ
VOUT = 0 V
nA
–200
PROTECTION CIRCUITS
VCC falling
VCC rising
1.7
1.8
3.5
V
VUVLO
VCC undervoltage lockout
IOCP
Overcurrent protection trip level
Overcurrent deglitch time
Overcurrent retry time
1.9
A
tDEG
1
μs
ms
°C
tRETRY
TTSD
1
Thermal shutdown temperature
Die temperature TJ
150
160
180
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6.6 Timing Requirements
TA = 25°C, VM = 5 V, VCC = 3 V, RL = 20 Ω
NO.
MIN
MAX
UNIT
ns
1
t1
Delay time, PHASE high to OUT1 low
Delay time, PHASE high to OUT2 high
Delay time, PHASE low to OUT1 high
Delay time, PHASE low to OUT2 low
Delay time, ENBL high to OUTx high
Delay time, ENBL low to OUTx low
Output enable time
160
200
200
160
200
160
300
300
160
160
188
188
30
2
t2
ns
3
t3
ns
See 图6-1.
4
t4
ns
5
t5
ns
6
t6
ns
7
t7
ns
8
t8
Output disable time
ns
9
t9
Delay time, INx high to OUTx high
Delay time, INx low to OUTx low
Output rise time
ns
See 图6-2.
10
11
12
t10
t11
t12
twake
ns
30
30
ns
Output fall time
ns
Wake time, nSLEEP rising edge to part active
μs
EN
PH
t5
t3
OUT1
t1
t6
t2
t6
t4
t5
OUT2
DRV8838
图6-1. Input and Output Timing for DRV8838
IN1
IN2
t7
t10
t8
OUT1
OUT2
Z
Z
t9
Z
Z
DRV8837
80%
80%
OUTx
20%
t11
20%
t12
图6-2. Input and Output Timing for DRV8837
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6.7 Typical Characteristics
0.02
0.018
0.016
0.014
0.012
0.01
6
5
4
3
2
1
0
VCC = 2 V
VCC = 3 V
VCC = 7 V
VM = 2 V
VM = 5 V
VM = 11 V
0.008
0.006
0.004
0.002
0
-40
-20
0
20
40
Ambient Temperature (ºC)
60
80 90
-40
-20
0
20
40
Ambient Temperature (ºC)
60
80 90
D003
D002
图6-4. IVCCQ vs TA
图6-3. IVMQ vs TA
2.5
0.85
0.8
2
1.5
1
VM = 2 V
VM = 5 V
VM = 11 V
VCC = 2 V
VCC = 3 V
VCC = 7 V
0.75
0.7
0.5
0.65
0
-40
-20
0
20
40
Ambient Temperature (ºC)
60
80 90
-40
-20
0
20
40
Ambient Temperature (ºC)
60
80 90
D005
D004
图6-6. IVCC vs TA (50-kHz PWM)
图6-5. IVM vs TA (50-kHz PWM)
700
600
500
400
300
200
VM = 2 V, VCC = 2 V
VM = 5 V, VCC = 3 V
VM = 11 V, VCC = 5V
-40
-20
0
20
40
60
80
90
Ambient Temperature (èC)
D005
图6-7. HS + LS rDS(on) vs TA
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7 Detailed Description
7.1 Overview
The DRV883x family of devices is an H-bridge driver that can drive one dc motor or other devices like solenoids.
The outputs are controlled using either a PWM interface (IN1 and IN2) on the DRV8837 device or a PH-EN
interface on the DRV8838 device.
A low-power sleep mode is included, which can be enabled using the nSLEEP pin.
These devices greatly reduce the component count of motor driver systems by integrating the necessary driver
FETs and FET control circuitry into a single device. In addition, the DRV883x family of devices adds protection
features beyond traditional discrete implementations: undervoltage lockout, overcurrent protection, and thermal
shutdown.
7.2 Functional Block Diagram
0 V to 11 V
VM
VM
VM
OUT1
Gate
Drive
OCP
Charge
Pump
1.8 V to 7 V
VCC
DCM
VM
VCC
Logic
OUT2
Gate
Drive
OCP
IN1
IN2
Over-
Temp
nSLEEP
Osc
GND
图7-1. DRV8837 Functional Block Diagram
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0 V to 11 V
VM
VM
VM
OUT1
Gate
Drive
OCP
Charge
Pump
1.8 V to 7 V
VCC
DCM
VM
VCC
Logic
OUT2
Gate
Drive
OCP
PH
EN
Over-
Temp
nSLEEP
Osc
GND
图7-2. DRV8838 Functional Block Diagram
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7.3 Feature Description
7.3.1 Bridge Control
The DRV8837 device is controlled using a PWM input interface, also called an IN-IN interface. Each output is
controlled by a corresponding input pin.
表7-1 shows the logic for the DRV8837 device.
表7-1. DRV8837 Device Logic
nSLEEP
IN1
IN2
OUT1
OUT2
FUNCTION (DC MOTOR)
0
1
1
1
1
X
X
Z
Z
L
Z
Z
H
L
Coast
Coast
0
0
0
1
Reverse
Forward
Brake
1
0
H
L
1
1
L
The DRV8838 device is controlled using a PHASE/ENABLE interface. This interface uses one pin to control the
H-bridge current direction, and one pin to enable or disable the H-bridge.
表7-2 shows the logic for the DRV8838.
表7-2. DRV8838 Device Logic
nSLEEP
PH
EN
OUT1
OUT2
FUNCTION (DC MOTOR)
0
1
1
1
X
X
Z
L
Z
L
Coast
Brake
X
0
1
1
L
H
L
Reverse
Forward
0
1
H
7.3.2 Independent Half-Bridge Control
Independent half-bridge control is possible with the DRV8837 without adopting more discrete components, as
shown in 节7.3.2. Two inductive loads (M1 and M2), which could be motors or solenoids, are tied between VM
and OUTx, while the corresponding inputs (C1 and C2) are swapped before being fed to INx.
图7-3. Independent Half-Bridge Control Circuit
The control logic for independent half-bridge drive is shown in 表 7-3. Columns INx and OUTx show the original
logic of the DRV8837. Note that although a swap is included in this implementation, it is still valid that Cx = 1
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spins a motor or energizes a solenoid connected at corresponding Mx, while Cx = 0, stops the motor or
discharges the solenoid.
表7-3. Independent Half-Bridge Drive Logic
C1
0
C2
0
IN1
0
IN2 OUT1 OUT2
M1
M2
0
1
0
1
Z
L
Z
H
L
Off: Braking mode 1
On: Driving mode
Off: Braking mode 2
On: Driving mode
Off: Braking mode 1
Off: Braking mode 2
On: Driving mode
On: Driving mode
1
0
0
0
1
1
H
L
1
1
1
L
图 7-4 shows the driving mode and the two current decay paths during current regulation when PWM input
control is used. The driving mode occurs when the corresponding half-bridge Cx signal is HIGH. When the Cx
signal is LOW, the corresponging half bridge can go into either braking mode 1 or braking mode 2. In braking
mode 1, both the high- and low-side MOSFETs of the half-bridge are tri-stated, and the recirculation current
flows through the body diode of the high-side MOSFET as well as the motor itself. This braking mode happens
when both C1 and C2 are LOW. If one of the Cx input is LOW and the other HIGH, the half-bridge
corresponding to the LOW Cx input will go into braking mode 2. In braking mode 2, the low-side FET is OFF
while its high-side counterpart is ON. The recirculation current flows through the high-side MOSFET and the
motor.
图7-4. Normal Driving and Current Decay Modes
When each of the Cx inputs are independently controlled with different PWM frequencies and duty cycle, each
half-bridge will go into a combination of braking mode 1 and braking mode 2. 图 7-5 show a driving and decay
example with independent PWM inputs. If the half-bridge spends more time in braking mode 1, the motor
average speed will be lower since more power is dissipated through the MOSFET body diode. To reduce the
power dissipated during braking mode 1, it is recommended to placed Schottky diodes with forward voltage less
than 0.6V across the motors as shown in 图 7-6. Note that if On/Off control mode (constant HIGH or LOW at
inputs) is used, the two braking modes do not interact with each other and hence have no effect on the average
speed of the two motors.
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图7-5. Driving and Decay Examples with Independent PWM Inputs
图7-6. Improved Application Circuit for Better Motor Performance
7.3.3 Sleep Mode
If the nSLEEP pin is brought to a logic-low state, the DRV883x family of devices enters a low-power sleep mode.
In this state, all unnecessary internal circuitry is powered down.
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7.3.4 Power Supplies and Input Pins
The input pins can be driven within the recommended operating conditions with or without the VCC, VM, or both
power supplies present. No leakage current path will exist to the supply. Each input pin has a weak pulldown
resistor (approximately 100 kΩ) to ground.
The VCC and VM supplies can be applied and removed in any order. When the VCC supply is removed, the
device enters a low-power state and draws very little current from the VM supply. The VCC and VM pins can be
connected together if the supply voltage is between 1.8 and 7 V.
The VM voltage supply does not have any undervoltage-lockout protection (UVLO) so as long as VCC > 1.8 V;
the internal device logic remains active, which means that the VM pin voltage can drop to 0 V. However, the load
cannot be sufficiently driven at low VM voltages.
7.3.5 Protection Circuits
The DRV883x family of devices is fully protected against VCC undervoltage, overcurrent, and overtemperature
events.
7.3.5.1 VCC Undervoltage Lockout
If at any time the voltage on the VCC pin falls below the undervoltage lockout threshold voltage, all FETs in the
H-bridge are disabled. Operation resumes when the VCC pin voltage rises above the UVLO threshold.
7.3.5.2 Overcurrent Protection (OCP)
An analog current-limit circuit on each FET limits the current through the FET by removing the gate drive. If this
analog current limit persists for longer than tDEG, all FETs in the H-bridge are disabled. Operation resumes
automatically after tRETRY has elapsed. Overcurrent conditions are detected on both the high-side and low-side
FETs. A short to the VM pin, GND, or from the OUT1 pin to the OUT2 pin results in an overcurrent condition.
7.3.5.3 Thermal Shutdown (TSD)
If the die temperature exceeds safe limits, all FETs in the H-bridge are disabled. After the die temperature falls to
a safe level, operation automatically resumes.
7.3.5.4
表7-4. Fault Behavior
FAULT
CONDITION
H-BRIDGE
Disabled
Disabled
Disabled
RECOVERY
VCC > 1.8 V
tRETRY elapses
TJ < 150°C
VCC undervoltage (UVLO)
Overcurrent (OCP)
VCC < 1.7 V
IOUT > 1.9 A (MIN)
TJ > 150°C (MIN)
Thermal Shutdown (TSD)
7.4 Device Functional Modes
The DRV883x family of devices is active unless the nSLEEP pin is brought logic low. In sleep mode, the H-
bridge FETs are disabled Hi-Z. The DRV883x is brought out of sleep mode automatically if nSLEEP is brought
logic high.
The H-bridge outputs are disabled during undervoltage lockout, overcurrent, and overtemperature fault
conditions.
表7-5. Operation Modes
MODE
Operating
CONDITION
H-BRIDGE
Operating
Disabled
Disabled
nSLEEP pin = 1
Sleep mode
Fault encountered
nSLEEP pin = 0
Any fault condition met
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Application and Implementation
备注
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
8.1 Application Information
The DRV883x family of devices is device is used to drive one dc motor or other devices like solenoids. The
following design procedure can be used to configure the DRV883x family of devices.
8.2 Typical Application
DRV8837 and
VM
DRV8838
VCC
0.1 µF
0.1 µF
1
2
3
4
8
7
6
5
VM
VCC
nSLEEP
IN1/PH
IN2/EN
OUT1
OUT2
GND
M
图8-1. Schematic of DRV883x Application
8.2.1 Design Requirements
表8-1 lists the required parameters for a typical usage case.
表8-1. System Design Requirements
DESIGN PARAMETER
Motor supply voltage
Logic supply voltage
Target rms current
REFERENCE
EXAMPLE VALUE
VM
VCC
IOUT
9 V
3.3 V
0.8 A
8.2.2 Detailed Design Procedure
8.2.2.1 Motor Voltage
The appropriate motor voltage depends on the ratings of the motor selected and the desired RPM. A higher
voltage spins a brushed dc motor faster with the same PWM duty cycle applied to the power FETs. A higher
voltage also increases the rate of current change through the inductive motor windings.
8.2.2.2 Low-Power Operation
When entering sleep mode, TI recommends setting all inputs as a logic low to minimize system power.
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8.2.3 Application Curves
图8-2. 50% Duty Cycle, Forward Direction
图8-3. 50% Duty Cycle, Reverse Direction
图8-4. 20% Duty Cycle, Forward Direction
图8-5. 20% Duty Cycle, Reverse Direction
备注
DIR_V is an indication of the motor direction. It is not a pin of the DRV883x device.
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8 Power Supply Recommendations
8.1 Bulk Capacitance
Having appropriate local bulk capacitance is an important factor in motor-drive system design. It is generally
beneficial to have more bulk capacitance, while the disadvantages are increased cost and physical size.
The amount of local capacitance needed depends on a variety of factors, including:
• The highest current required by the motor system
• The power-supply capacitance and ability to source current
• The amount of parasitic inductance between the power supply and motor system
• The acceptable voltage ripple
• The type of motor used (brushed dc, brushless dc, stepper)
• The motor braking method
The inductance between the power supply and motor drive system limits the rate at which current can change
from the power supply. If the local bulk capacitance is too small, the system responds to excessive current
demands or dumps from the motor with a change in voltage. When adequate bulk capacitance is used, the
motor voltage remains stable and high current can be quickly supplied.
The data sheet generally provides a recommended value, but system-level testing is required to determine the
appropriate size of bulk capacitor.
Parasitic Wire
Inductance
Motor Drive System
Power Supply
VM
+
Motor
Driver
+
–
GND
Local
Bulk Capacitor
IC Bypass
Capacitor
图8-1. Example Setup of Motor Drive System With External Power Supply
The voltage rating for bulk capacitors should be higher than the operating voltage, to provide margin for cases
when the motor transfers energy to the supply
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9 Layout
9.1 Layout Guidelines
The VM and VCC pins should be bypassed to GND using low-ESR ceramic bypass capacitors with a
recommended value of 0.1 µF rated for VM and VCC . These capacitors should be placed as close to the VM
and VCC pins as possible with a thick trace or ground plane connection to the device GND pin.
9.2 Layout Example
0.1 µF
0.1 µF
VCC
VM
nSLEEP
IN1/PH
IN2/EN
OUT1
OUT2
GND
图9-1. Simplified Layout Example
9.3 Power Dissipation
Power dissipation in the DRV883x family of devices is dominated by the power dissipated in the output FET
resistance, or rDS(on). Use 方程式1 to estimate the average power dissipation when running a stepper motor.
2
PTOT = rDS(on) ´(IOUT(RMS)
)
(1)
where
• PTOT is the total power dissipation
• rDS(on) is the resistance of the HS plus LS FETs
• IOUT(RMS) is the rms or dc output current being supplied to the load
The maximum amount of power that can be dissipated in the device is dependent on ambient temperature and
heatsinking.
备注
The value of rDS(on) increases with temperature, so as the device heats, the power dissipation
increases.
The DRV883x family of devices has thermal shutdown protection. If the die temperature exceeds approximately
150°C, the device is disabled until the temperature drops to a safe level.
Any tendency of the device to enter thermal shutdown is an indication of either excessive power dissipation,
insufficient heatsinking, or too high an ambient temperature.
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10 Device and Documentation Support
10.1 Documentation Support
10.1.1 Related Documentation
For related documentation see the following:
• Calculating Motor Driver Power Dissipation
• DRV8837EVM User’s Guide
• DRV8838EVM User’s Guide
• Independent Half-Bridge Drive with DRV8837
• Understanding Motor Driver Current Ratings
10.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
表10-1. Related Links
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
PARTS
PRODUCT FOLDER
SAMPLE & BUY
DRV8837
DRV8838
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
Click here
10.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
10.4 Community Resources
10.5 Trademarks
所有商标均为其各自所有者的财产。
Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2023 Texas Instruments Incorporated
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重要声明和免责声明
TI 提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，不保证没
有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担保。
这些资源可供使用TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。这些资源如有变更，恕不另行通知。TI 授权您仅可
将这些资源用于研发本资源所述的TI 产品的应用。严禁对这些资源进行其他复制或展示。您无权使用任何其他TI 知识产权或任何第三方知
识产权。您应全额赔偿因在这些资源的使用中对TI 及其代表造成的任何索赔、损害、成本、损失和债务，TI 对此概不负责。
TI 提供的产品受TI 的销售条款(https:www.ti.com/legal/termsofsale.html) 或ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI
提供这些资源并不会扩展或以其他方式更改TI 针对TI 产品发布的适用的担保或担保免责声明。重要声明
邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2021，德州仪器(TI) 公司
PACKAGE OPTION ADDENDUM
www.ti.com
11-Aug-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
DRV8837DSGR
DRV8837DSGT
DRV8838DSGR
DRV8838DSGT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
WSON
WSON
WSON
WSON
DSG
DSG
DSG
DSG
8
8
8
8
3000 RoHS & Green
250 RoHS & Green
3000 RoHS & Green
250 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 85
-40 to 85
-40 to 85
-40 to 85
837
837
838
838
Samples
Samples
Samples
Samples
NIPDAU
NIPDAU
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
11-Aug-2022
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
19-May-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DRV8837DSGR
DRV8837DSGT
DRV8838DSGR
DRV8838DSGT
WSON
WSON
WSON
WSON
DSG
DSG
DSG
DSG
8
8
8
8
3000
250
180.0
180.0
180.0
180.0
8.4
8.4
8.4
8.4
2.3
2.3
2.3
2.3
2.3
2.3
2.3
2.3
1.15
1.15
1.15
1.15
4.0
4.0
4.0
4.0
8.0
8.0
8.0
8.0
Q2
Q2
Q2
Q2
3000
250
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
19-May-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
DRV8837DSGR
DRV8837DSGT
DRV8838DSGR
DRV8838DSGT
WSON
WSON
WSON
WSON
DSG
DSG
DSG
DSG
8
8
8
8
3000
250
210.0
182.0
182.0
182.0
185.0
182.0
182.0
182.0
35.0
20.0
20.0
20.0
3000
250
Pack Materials-Page 2
GENERIC PACKAGE VIEW
DSG 8
2 x 2, 0.5 mm pitch
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224783/A
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PACKAGE OUTLINE
DSG0008A
WSON - 0.8 mm max height
SCALE 5.500
PLASTIC SMALL OUTLINE - NO LEAD
2.1
1.9
B
A
0.32
0.18
PIN 1 INDEX AREA
2.1
1.9
0.4
0.2
ALTERNATIVE TERMINAL SHAPE
TYPICAL
0.8
0.7
C
SEATING PLANE
0.05
0.00
SIDE WALL
0.08 C
METAL THICKNESS
DIM A
OPTION 1
0.1
OPTION 2
0.2
EXPOSED
THERMAL PAD
(DIM A) TYP
0.9 0.1
5
4
6X 0.5
2X
1.5
9
1.6 0.1
8
1
0.32
0.18
PIN 1 ID
(45 X 0.25)
8X
0.4
0.2
8X
0.1
C A B
C
0.05
4218900/E 08/2022
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
DSG0008A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(0.9)
(
0.2) VIA
8X (0.5)
TYP
1
8
8X (0.25)
(0.55)
SYMM
9
(1.6)
6X (0.5)
5
4
SYMM
(1.9)
(R0.05) TYP
LAND PATTERN EXAMPLE
SCALE:20X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4218900/E 08/2022
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
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EXAMPLE STENCIL DESIGN
DSG0008A
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
8X (0.5)
METAL
8
SYMM
1
8X (0.25)
(0.45)
SYMM
9
(0.7)
6X (0.5)
5
4
(R0.05) TYP
(0.9)
(1.9)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 9:
87% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:25X
4218900/E 08/2022
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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重要声明和免责声明
TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，
不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担
保。
这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。
这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。
您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成
本、损失和债务，TI 对此概不负责。
TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改
TI 针对 TI 产品发布的适用的担保或担保免责声明。
TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE
邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2023，德州仪器 (TI) 公司
DRV8838 相关器件
| 型号 | 制造商 | 描述 | 价格 | 文档 |
| DRV8838DSGR | TI | 具有相位/使能控制的 11V、1.8A H 桥电机驱动器 | DSG | 8 | -40 to 85 | 获取价格 |
|
| DRV8838DSGT | TI | 具有相位/使能控制的 11V、1.8A H 桥电机驱动器 | DSG | 8 | -40 to 85 | 获取价格 |
|
| DRV8839 | TI | LOW VOLTAGE DUAL 1/2-H-BRIDGE DRIVER IC | 获取价格 |
|
| DRV8839DSSR | TI | LOW VOLTAGE DUAL 1/2-H-BRIDGE DRIVER IC | 获取价格 |
|
| DRV8839_16 | TI | Low-Voltage Dual H-Bridge Driver IC | 获取价格 |
|
| DRV8840 | TI | DC MOTOR DRIVER IC | 获取价格 |
|
| DRV8840PWP | TI | DC MOTOR DRIVER IC | 获取价格 |
|
| DRV8840PWPR | TI | DC MOTOR DRIVER IC | 获取价格 |
|
| DRV8840_15 | TI | DC Motor Driver IC | 获取价格 |
|
| DRV8841 | TI | DUAL H-BRIDGE DRIVER IC | 获取价格 |
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