SN74AHCT258DBLE
更新时间：2025-01-12 05:22:44
品牌：TI
描述：AHC SERIES, QUAD 2 LINE TO 1 LINE MULTIPLEXER, INVERTED OUTPUT, PDSO16, PLASTIC, SSOP-16
概述
数据手册SN74AHCT258DBLE 概述
AHC SERIES, QUAD 2 LINE TO 1 LINE MULTIPLEXER, INVERTED OUTPUT, PDSO16, PLASTIC, SSOP-16
SN74AHCT258DBLE 数据手册
通过下载SN74AHCT258DBLE数据手册来全面了解它。这个PDF文档包含了所有必要的细节，如产品概述、功能特性、引脚定义、引脚排列图等信息。
PDF下载SN54AHCT258, SN74AHCT258
QUADRUPLE 2-LINE TO 1-LINE DATA SELECTORS/MULTIPLEXERS
WITH 3-STATE OUTPUTS
SCLS344E – MAY 1996 – REVISED OCTOBER 1998
SN54AHCT258 . . . J OR W PACKAGE
SN74AHCT258 . . . D, DB, DGV, N, OR PW PACKAGE
(TOP VIEW)
Inputs Are TTL-Voltage Compatible
EPIC (Enhanced-Performance Implanted
CMOS) Process
A/B
1A
V
CC
1
2
3
4
5
6
7
8
16
15
14
13
Package Options Include Plastic
Small-Outline (D), Shrink Small-Outline
(DB), Thin Very Small-Outline (DGV), Thin
Shrink Small-Outline (PW), and Ceramic
Flat (W) Packages, Ceramic Chip Carriers
(FK), and Standard Plastic (N) and Ceramic
(J) DIPs
OE
4A
4B
1B
1Y
2A
12 4Y
11
10
9
2B
3A
3B
3Y
2Y
GND
description
These quadruple 2-line to 1-line data
selectors/multiplexers are designed for 4.5-V to
SN54AHCT258 . . . FK PACKAGE
(TOP VIEW)
5.5-V V
operation.
CC
The ’AHCT258 devices are designed to multiplex
signals from 4-bit data sources to 4-output data
lines in bus-organized systems. The 3-state
outputs do not load the data lines when the
output-enable (OE) input is at the high logic level.
3
2
1 20 19
18
4A
1B
1Y
NC
2A
2B
4
5
6
7
8
17 4B
16
NC
15
4Y
To ensure the high-impedance state during power
14
3A
up or power down, OE should be tied to V
CC
9 10 11 12 13
through a pullup resistor; the minimum value of
the resistor is determined by the current-sinking
capability of the driver.
NC – No internal connection
The SN54AHCT258 is characterized for
operation over the full military temperature range
of –55°C to 125°C. The SN74AHCT258 is
characterized for operation from –40°C to 85°C.
FUNCTION TABLE
INPUTS
OUTPUT
Y
A/B
A
X
L
B
X
X
X
L
OE
H
L
X
L
Z
H
L
L
L
H
X
X
L
H
H
H
L
L
H
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
Copyright 1998, Texas Instruments Incorporated
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54AHCT258, SN74AHCT258
QUADRUPLE 2-LINE TO 1-LINE DATA SELECTORS/MULTIPLEXERS
WITH 3-STATE OUTPUTS
SCLS344E – MAY 1996 – REVISED OCTOBER 1998
†
logic symbol
15
OE
EN
G1
1
A/B
2
4
7
1A
1B
2A
2B
3A
3B
4A
4B
1
1
MUX
1Y
2Y
3
5
6
11
10
14
13
9
3Y
4Y
12
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the D, DB, DGV, J, N, PW, and W packages.
logic diagram (positive logic)
15
OE
1
A/B
2
1A
4
7
1Y
2Y
3Y
4Y
3
1B
5
2A
6
2B
11
3A
9
10
3B
14
4A
12
13
4B
Pin numbers shown are for the D, DB, DGV, J, N, PW, and W packages.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54AHCT258, SN74AHCT258
QUADRUPLE 2-LINE TO 1-LINE DATA SELECTORS/MULTIPLEXERS
WITH 3-STATE OUTPUTS
SCLS344E – MAY 1996 – REVISED OCTOBER 1998
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
I
Output voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
+ 0.5 V
O
CC
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –20 mA
IK
I
Output clamp current, I
(V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
OK
O O CC
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA
Continuous current through V
Package thermal impedance, θ (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W
O
O
CC
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
JA
DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131°C/W
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51, except for through-hole packages, which use a trace
length of zero.
recommended operating conditions (see Note 3)
SN54AHCT258 SN74AHCT258
UNIT
MIN
4.5
2
MAX
MIN
4.5
2
MAX
V
V
V
V
V
Supply voltage
5.5
5.5
V
V
CC
IH
IL
High-level input voltage
Low-level input voltage
Input voltage
0.8
5.5
0.8
5.5
V
0
0
0
0
V
I
Output voltage
V
CC
–8
V
CC
–8
V
O
I
I
High-level output current
Low-level output current
Input transition rise or fall time
Operating free-air temperature
mA
mA
ns/V
°C
OH
OL
8
8
20
85
∆t/∆v
20
T
A
–55
125
–40
NOTE 3: All unused inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54AHCT258, SN74AHCT258
QUADRUPLE 2-LINE TO 1-LINE DATA SELECTORS/MULTIPLEXERS
WITH 3-STATE OUTPUTS
SCLS344E – MAY 1996 – REVISED OCTOBER 1998
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
T
A
= 25°C
TYP
SN54AHCT258 SN74AHCT258
PARAMETER
TEST CONDITIONS
V
UNIT
CC
MIN
4.4
MAX
MIN
4.4
MAX
MIN
4.4
MAX
I
= –50
A
4.5
OH
V
4.5 V
4.5 V
V
OH
OL
3.94
3.8
3.8
I
= –8 mA
OH
OL
I
= 50
A
0.1
0.36
±0.1
4
0.1
0.44
±1
0.1
0.44
±1
V
V
I
= 8 mA
OL
I
I
V = V
or GND
or GND,
5.5 V
5.5 V
A
A
I
I
CC
CC
V = V
I = 0
O
40
40
CC
I
One input at 3.4 V,
Other inputs at V
†
5.5 V
1.35
1.5
1.5
A
∆I
CC
or GND
CC
or GND
I
V
= V
5.5 V
5 V
±0.25
±2.5
±2.5
A
OZ
O
CC
V = V or GND
CC
C
pF
i
I
†
This is the increase in supply current for each input at one of the specified TTL voltage levels rather than 0 V or V
.
CC
switching characteristics over recommended operating free-air temperature range,
= 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
V
CC
SN54AHCT258
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
PARAMETER
T
A
= 25°C
UNIT
MIN
MAX
MIN
TYP
MAX
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
*
*
*
*
PLH
PHL
PLH
PHL
PZH
A or B
A/B
Y
Y
Y
Y
Y
Y
Y
Y
C
C
C
C
C
C
C
C
= 15 pF
= 15 pF
= 15 pF
= 15 pF
= 50 pF
= 50 pF
= 50 pF
= 50 pF
ns
ns
ns
ns
ns
ns
ns
ns
L
L
L
L
L
L
L
L
*
OE
OE
*
PZL
*
PHZ
*
PLZ
PLH
PHL
PLH
PLH
PZH
PZL
PHZ
PLZ
A or B
A/B
OE
OE
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54AHCT258, SN74AHCT258
QUADRUPLE 2-LINE TO 1-LINE DATA SELECTORS/MULTIPLEXERS
WITH 3-STATE OUTPUTS
SCLS344E – MAY 1996 – REVISED OCTOBER 1998
switching characteristics over recommended operating free-air temperature range,
V
= 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
CC
SN74AHCT258
= 25°C
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
PARAMETER
T
A
UNIT
MIN
MAX
MIN
TYP
MAX
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
PLH
PHL
PLH
PHL
PZH
PZL
PHZ
PLZ
PLH
PHL
PLH
PLH
PZH
PZL
PHZ
PLZ
A or B
Y
Y
Y
Y
Y
Y
Y
Y
C
C
C
C
C
C
C
C
= 15 pF
= 15 pF
= 15 pF
= 15 pF
= 50 pF
= 50 pF
= 50 pF
= 50 pF
ns
ns
ns
ns
ns
ns
ns
ns
L
L
L
L
L
L
L
L
A/B
OE
OE
A or B
A/B
OE
OE
noise characteristics V
= 5 V, C = 50 pF, T = 25°C (see Note 4)
CC
L
A
SN74AHCT258
MIN TYP MAX
PARAMETER
UNIT
V
V
V
V
V
Quiet output, maximum dynamic V
V
V
V
V
V
OL(P)
OL(V)
OH(V)
IH(D)
IL(D)
OL
Quiet output, minimum dynamic V
Quiet output, minimum dynamic V
High-level dynamic input voltage
Low-level dynamic input voltage
OL
OH
NOTE 4: Characteristics are for surface-mount packages only.
operating characteristics, V
= 5 V, T = 25°C
A
CC
PARAMETER
Power dissipation capacitance
TEST CONDITIONS
No load, f = 1 MHz
TYP
UNIT
C
pF
pd
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54AHCT258, SN74AHCT258
QUADRUPLE 2-LINE TO 1-LINE DATA SELECTORS/MULTIPLEXERS
WITH 3-STATE OUTPUTS
SCLS344E – MAY 1996 – REVISED OCTOBER 1998
PARAMETER MEASUREMENT INFORMATION
V
CC
Open
S1
R
= 1 kΩ
L
TEST
S1
From Output
Under Test
Test
Point
From Output
Under Test
GND
t
t
/t
Open
PLH PHL
/t
C
C
L
t
V
CC
L
PLZ PZL
/t
(see Note A)
(see Note A)
GND
PHZ PZH
V
CC
Open Drain
LOAD CIRCUIT FOR
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
3-STATE AND OPEN-DRAIN OUTPUTS
3 V
Timing Input
1.5 V
0 V
t
w
t
h
t
su
3 V
3 V
0 V
1.5 V
1.5 V
Input
Input
1.5 V
1.5 V
Data Input
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
3 V
0 V
3 V
Output
1.5 V
1.5 V
1.5 V
1.5 V
Control
0 V
t
PZL
t
t
t
PHL
PLH
t
PLZ
Output
Waveform 1
V
≈ V
OH
CC
In-Phase
Output
50% V
50% V
CC
50% V
50% V
CC
V
CC
CC
S1 at V
(see Note B)
V
OL
+ 0.3 V
– 0.3 V
CC
V
OL
OL
t
PHZ
t
PHL
PLH
t
PZH
Output
Waveform 2
S1 at GND
V
OH
V
OH
Out-of-Phase
Output
V
OH
50% V
50% V
CC
CC
≈ 0 V
V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. includes probe and jig capacitance.
C
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, Z = 50 Ω, t ≤ 3 ns, t ≤ 3 ns.
O
r
f
D. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1998, Texas Instruments Incorporated
SN74AHCT258DBLE 相关器件
| 型号 | 制造商 | 描述 | 价格 | 文档 |
| SN74AHCT258DBR | TI | AHC SERIES, QUAD 2 LINE TO 1 LINE MULTIPLEXER, INVERTED OUTPUT, PDSO16, PLASTIC, SSOP-16 | 获取价格 |
|
| SN74AHCT258DGV | TI | AHC SERIES, QUAD 2 LINE TO 1 LINE MULTIPLEXER, INVERTED OUTPUT, PDSO16, PLASTIC, TVSOP-16 | 获取价格 |
|
| SN74AHCT258DGVR | TI | AHC SERIES, QUAD 2 LINE TO 1 LINE MULTIPLEXER, INVERTED OUTPUT, PDSO16, PLASTIC, TVSOP-16 | 获取价格 |
|
| SN74AHCT258DR | TI | AHC SERIES, QUAD 2 LINE TO 1 LINE MULTIPLEXER, INVERTED OUTPUT, PDSO16, PLASTIC, SO-16 | 获取价格 |
|
| SN74AHCT258N | TI | AHC SERIES, QUAD 2 LINE TO 1 LINE MULTIPLEXER, INVERTED OUTPUT, PDIP16, PLASTIC, DIP-16 | 获取价格 |
|
| SN74AHCT258PWLE | TI | AHC SERIES, QUAD 2 LINE TO 1 LINE MULTIPLEXER, INVERTED OUTPUT, PDSO16, PLASTIC, TSSOP-16 | 获取价格 |
|
| SN74AHCT258PWR | TI | AHC SERIES, QUAD 2 LINE TO 1 LINE MULTIPLEXER, INVERTED OUTPUT, PDSO16, PLASTIC, TSSOP-16 | 获取价格 |
|
| SN74AHCT273 | TI | OCTAL D-TYPE FLIP-FLOPS WITH CLEAR | 获取价格 |
|
| SN74AHCT273DB | TI | OCTAL D-TYPE FLIP-FLOPS WITH CLEAR | 获取价格 |
|
| SN74AHCT273DBLE | TI | AHCT/VHCT SERIES, OCTAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO20, PLASTIC, SSOP-20 | 获取价格 |
|
SN74AHCT258DBLE 相关文章
中国台湾取消对台积电海外生产2nm芯片限制
- 2025-01-14
- 2
英伟达AI芯片机架过热问题引发关注，微软等客户削减订单
- 2025-01-14
- 2
Arm拟大幅提高芯片设计授权费用300%，并考虑自主开发芯片
- 2025-01-14
- 4
Rapidus计划6月向博通交付2nm芯片，日本半导体产业迈出新步伐
- 2025-01-14
- 2
