UCC2626PWTR

更新时间:2024-12-04 13:11:20
品牌:TI
描述:BRUSHLESS DC MOTOR CONTROLLER, 0.2A, PDSO28, TSSOP-28

UCC2626PWTR 概述

BRUSHLESS DC MOTOR CONTROLLER, 0.2A, PDSO28, TSSOP-28 运动控制电子器件

UCC2626PWTR 规格参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:SSOP
包装说明:TSSOP, TSSOP28,.25针数:28
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.12
模拟集成电路 - 其他类型:BRUSHLESS DC MOTOR CONTROLLERJESD-30 代码:R-PDSO-G28
长度:9.7 mm功能数量:1
端子数量:28最高工作温度:85 °C
最低工作温度:-40 °C最大输出电流:0.2 A
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP28,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH峰值回流温度(摄氏度):NOT SPECIFIED
电源:12 V认证状态:Not Qualified
座面最大高度:1.2 mm子类别:Motion Control Electronics
最大供电电流 (Isup):5 mA最大供电电压 (Vsup):14.5 V
最小供电电压 (Vsup):11 V标称供电电压 (Vsup):12 V
表面贴装:YES技术:BICMOS
温度等级:INDUSTRIAL端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:4.4 mm
Base Number Matches:1

UCC2626PWTR 数据手册

通过下载UCC2626PWTR数据手册来全面了解它。这个PDF文档包含了所有必要的细节,如产品概述、功能特性、引脚定义、引脚排列图等信息。

PDF下载
application  
INFO  
UCC2626  
UCC3626  
available  
PRELIMINARY  
Brushless DC Motor Controller  
FEATURES  
DESCRIPTION  
Two Quadrant and Four Quadrant  
The UCC3626 motor controller IC combines many of the functions re-  
quired to design a high performance, two or four quadrant, 3-phase,  
brushless DC motor controller into one package. Rotor position inputs  
are decoded to provide six outputs that control an external power stage.  
A precision triangle oscillator and latched comparator provide PWM mo-  
tor control in either voltage or current mode configurations. The oscilla-  
tor is easily synchronized to an external master clock source via the  
SYNCH input. Additionally, a QUAD select input configures the chip to  
modulate either the low side switches only, or both upper and lower  
switches, allowing the user to minimize switching losses in less de-  
manding two quadrant applications.  
Operation  
Integrated Absolute Value Current  
Amplifier  
Pulse-by-Pulse and Average Current  
Sensing  
Accurate, Variable Duty Cycle  
Tachometer Output  
Trimmed Precision Reference  
Precision Oscillator  
The chip includes a differential current sense amplifier and absolute  
value circuit which provide an accurate reconstruction of motor current,  
useful for pulse by pulse over current protection as well as closing a  
current control loop. A precision tachometer is also provided for imple-  
menting closed loop speed control. The TACH_OUT signal is a variable  
duty cycle, frequency output which can be used directly for digital con-  
trol or filtered to provide an analog feedback signal. Other features in-  
clude COAST, BRAKE, and DIR_IN commands along with a direction  
output, DIR_OUT.  
Direction Output  
BLOCK DIAGRAM  
28 VDD  
QUAD 20  
5 VOLT  
REFERENCE  
BRAKE 19  
COAST 18  
DIR_IN 21  
HALLA 15  
HALLB 16  
2
VREF  
1.75V  
27 AHI  
25 BHI  
23 CHI  
DIRECTION  
SELECT  
HALL  
DECODER  
HALLC 17  
26  
ALOW  
DIRECTION  
DETECTOR  
DIR_OUT  
8
EDGE  
DETECTOR  
24 BLOW  
22 CLOW  
PWM_NI 14  
PWM_I 13  
PWM COMPARATOR  
OSCILLATOR  
R • C  
SYNCH  
CT  
7
6
S
R
Q
Q
TACH_OUT  
3
OVER-CURRENT  
COMPARATOR  
5
4
C_TACH  
R_TACH  
S
R
Q
Q
OC_REF 12  
IOUT 11  
ONE SHOT  
PWM LOGIC  
SENSE AMPLIFIER  
1
GND  
SNS_NI  
9
SNS_I 10  
X5  
UDG-97173  
04/99  
UCC2626  
UCC3626  
ABSOLUTE MAXIMUM RATINGS  
CONNECTION DIAGRAMS  
Supply Voltage VDD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +15V  
Inputs  
Pins 20, 19, 18, 21, 15, 16, 17, 7, 12, 9, 10 . . . . –0.3V to VDD  
Pins 13, 14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3V to 8.0V  
Output Current  
DIL-28, SOIC-28, TSSOP-28 (Top View)  
N Package, DW Package, PW Package  
Pins 22, 23, 24, 25, 26, 27 . . . . . . . . . . . . . . . . . . . . . 200mA  
Pins 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –20mA  
Pins 3. 8, 11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1mA  
Storage Temperature . . . . . . . . . . . . . . . . . . . –65°C to +150°C  
Junction Temperature. . . . . . . . . . . . . . . . . . . 55°C to +150°C  
Lead Temperature (Soldering 10 Seconds). . . . . . . . . . +300°C  
GND  
VREF  
1
2
3
4
5
6
7
8
9
28 VDD  
27 AHI  
TACH_OUT  
R_TACH  
C_TACH  
CT  
26 ALO  
Note: Unless otherwise indicated, voltages are referenced to  
ground. Currents are positive into, negative out of specified ter-  
minal. Consult packaging section of Databook for thermal limi-  
tations and considerations of package.  
25 BHI  
24 BLOW  
23 CHI  
SYNCH  
DIR_OUT  
SNS_NI  
22 CLOW  
21 DIR_IN  
20 QUAD  
19 BRAKE  
18 COAST  
17 HALLC  
16 HALLB  
15 HALLA  
ORDERING INFORMATION  
UCC 626  
PACKAGE  
TEMPERATURE RANGE  
SNS_I 10  
IOUT 11  
TEMPERATURE RANGE PACKAGE  
UCC2626N  
DIL  
OC_REF 12  
PWM_I 13  
PWM_NI 14  
UCC2626DW  
UCC2626PW  
UCC3626N  
UCC3626DW  
UCC3626PW  
–40°C to +85°C  
0°C to +70°C  
SOIC  
TSSOP  
DIL  
SOIC  
TSSOP  
ELECTRICAL CHARACTERISTICS: Unless otherwise stated, these specifications apply for VCC = 12V; CT = 1nF,  
R
TACH = 250K, CTACH = 100pF, TA = TJ, TA = –40°C to +85°C for the UCC2626, and 0°C to +70°C for the UCC3626.  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
MAX UNITS  
Overall  
Supply Current  
3
10  
mA  
Under-Voltage Lockout  
Start Threshold  
10.5  
0.5  
V
V
UVLO Hysteresis  
5.0 V Reference  
Output Voltage  
I
VREF = –2mA  
4.9  
40  
5
5.1  
10  
30  
V
Line Regulation  
Load Regulation  
Short Circuit Current  
Coast Input Comparator  
Threshold  
11V < VCC < 14.5V  
–1 > IVREF > –5mA  
mV  
mV  
mA  
120  
1.75  
0.1  
V
V
Hysteresis  
Input Bias Current  
0.1  
µA  
2
UCC2626  
UCC3626  
ELECTRICAL CHARACTERISTICS: Unless otherwise stated, these specifications apply for VCC = 12V; CT = 1nF,  
TACH = 250K, CTACH = 100pF, TA = TJ, TA = –40°C to +85°C for the UCC2626, and 0°C to +70°C for the UCC3626.  
R
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
MAX UNITS  
Current Sense Amplifier  
Input Offset Voltage  
Input Bias Current  
Gain  
VCM = 0V  
VCM = 0V  
VCM = 0V  
5
mV  
µA  
V/V  
dB  
dB  
V
10  
5
4.9  
5.1  
CMRR  
–0.3V < VCM < 0.5  
11V < VCC <14.5V  
IIOUT= –100µA  
IIOUT = 100µA  
60  
60  
PSRR  
Output High Voltage  
Output Low Voltage  
Output Source Current  
PWM Comparator  
Input Common Mode Range  
Propogation Delay  
Over-Current Comparator  
Input Common Mode Range  
Propogation Delay  
Logic Inputs  
5
50  
8.0  
5.0  
3.5  
mV  
µA  
VIOUT = 2V  
500  
2.0  
V
75  
nS  
0.0  
1.5  
V
175  
nS  
Logic High  
QUAD, BRAKE, DIR  
QUAD, BRAKE, DIR  
QUAD, BRAKE, DIR  
V
V
Logic Low  
Input Current  
0.1  
µA  
Hall Buffer Inputs  
VIL  
HALLA, HALLB, HALLC  
HALLA, HALLB, HALLC  
0V < VIN < 5V  
1
V
V
VIH  
1.9  
–25  
Input Current  
µA  
Oscillator  
Frequency  
R
TACH = 250k, CT = 1nF  
10  
KHz  
%
V
Frequency Change With Voltage  
CT Peak Voltage  
CT Valley Voltage  
CT Peak-to-Valley Voltage  
SYNCH Pin Minimum Pulse Width  
Tachometer  
12V < VCC < 14.5V  
5
7.5  
2.5  
5.0  
V
V
–500  
ns  
VOH/VREF  
IOUT = –10µA  
IOUT = 10µA  
IOUT = –100µA  
IOUT = 100µA  
99  
0
100  
20  
%
mV  
kΩ  
kΩ  
mV  
V
Vol  
RON High  
1
1
RON Low  
Ramp Threshold, Lo  
Ramp Threshold, Hi  
CTACH Charge Current  
T-on Accuracy  
20  
2.52  
50  
RTACH = 49.9kΩ  
Note 1  
µA  
%
–3  
3
Direction Output  
DIR OUT High Level  
DIR OUT Low Level  
IOUT = –100µA  
IOUT = 100µA  
3.5  
0
5.1  
1
V
V
3
UCC2626  
UCC3626  
ELECTRICAL CHARACTERISTICS: Unless otherwise stated, these specifications apply for VCC = 12V; CT = 1nF,  
R
TACH = 250K, CTACH = 100pF, TA = TJ, TA = –40°C to +85°C for the UCC2626, and 0°C to +70°C for the UCC3626.  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
MAX UNITS  
Output Section  
Maximum Duty Cycle  
Output Low Voltage  
Output High Voltage  
Output Low Voltage  
Output High Voltage  
Rise/Fall Time  
100  
%
V
I
OUT = 10mA  
0.4  
IOUT = –10mA  
IOUT = 1mA  
IOUT = –1mA  
CI = 100pF  
4.0  
4.0  
5.1  
1
V
V
5.1  
V
100  
nS  
Note 1: T(on) is calculated using the formula: T(on) = CTACH Ÿ (VHI –VLO)/ICHARGE. This number is compared to the formula T(on) =  
RTACH Ÿ CTACH  
.
PIN DESCRIPTIONS  
AHI, BHI, CHI: Digital outputs used to control the high DIR_OUT: DIR_OUT represents the actual direction of  
side switches in a three phase inverter. For specific de- the rotor as decoded from the HALLA, B & C inputs. For  
coding information reference Table I.  
any valid combination of HALLA, B &C inputs there are  
two valid transitions, one which translates to a clockwise  
rotation and another which translates to a counterclock-  
wise rotation. The polarity of DIR_OUT is the same as  
DIR_IN while motoring, i.e. sequencing from top to bot-  
tom in Table 1.  
ALOW, BLOW, CLOW: Digital outputs used to control  
the low side switches in a three phase inverter. For spe-  
cific decoding information reference Table I.  
BRAKE: BRAKE is a digital input which causes the de-  
vice to enter brake mode. In brake mode all three high  
side outputs are turned off, AHI, BHI & CHI, while all  
three lowside outputs are turned on, ALOW, BLOW,  
CLOW. During brake mode the tachometer output re-  
GND: GND is the reference ground for all functions of the  
part. Bypass and timing capacitors should be terminated  
as close to this point as possible.  
mains operational. The only conditions which can inhibit HALLA, HALLB, HALLC: These three inputs are de-  
the low side commands during brake are UVLO, ex- signed to accept rotor position information positioned  
ceeding peak current, the output of the PWM compara- 120° apart. For specific decode information reference Ta-  
tor, or the COAST command.  
ble I. These inputs should be externally pulled-up to  
VREF or another appropriate external supply.  
COAST: The COAST input consists of a hysteretic com-  
parator which disables the outputs. The input is useful in IOUT: IOUT represents the output of the current sense  
implementing an overvoltage bus clamp in four quadrant and absolute value amplifiers. The output signal appear-  
applications. The outputs will be disabled when the input ing is a representation of the following expression:  
is above 1.75V.  
IOUT =ABS (ISENS_I ISENS_NI)5  
CT: This pin is used in conjunction with the R_TACH pin  
to set the frequency of the oscillator. A timing capacitor  
This output can be used to close a current control loop as  
well as provide additional filtering of the current sense  
is normally connected between this point and ground  
signal.  
and is alternately charged and discharged between 2.5V  
OC_REF: OC_REF is an analog input which sets the trip  
voltage of the overcurrent comparator. The sense input of  
the comparator is internally connected to the output of the  
current sense amplifier and absolute value circuit.  
and 7.5V.  
C_TACH: A timing capacitor is connected between this  
pin and ground to set the width of the TACH_OUT pulse.  
The capacitor is charged with a current set by the resis-  
tor on pin RT.  
PWM_NI: PWM_NI is the noninverting input to the PWM  
comparator.  
DIR_IN: DIR_IN is a digital input which determines the  
order in which the HALLA,B & C inputs are decoded. For  
specific decode information reference Table I.  
PWM_I: PWM_I is the inverting input to the PWM com-  
parator.  
4
UCC2626  
UCC3626  
PIN DESCRIPTIONS (cont.)  
QUAD: The QUAD input selects between “two” QUAD = TACH_OUT: TACH_OUT is the output of a monostable  
0 and “four” QUAD = 1 quadrant operation. When in triggered by a change in the commutation state, thus pro-  
“two-quadrant” mode only the low side devices are ef- viding a variable duty cycle, frequency output. The  
fected by the output of the PWM comparator. In on-time of the monostable is set by the timing capacitor  
“four-quadrant” mode both high and low side devices are connected to C_TACH. The monostable is capable of be-  
controlled by the PWM comparator.  
ing retriggered if a commutation occurs during it's  
on-time.  
SYNCH: The SYNCH input is used to synchronize the  
PWM oscillator with an external digital clock. When using R_TACH: A resistor connected between R_TACH and  
the SYNCH feature, a resistor equal to RTACH must be ground programs the current for both the oscillator and  
placed in parallel with CT. When not used, ground tachometer.  
SYNCH.  
VDD: VDD is the input supply connection for this device.  
SNS_NI, SNS_I: These inputs are the noninverting and Undervoltage lockout keeps the outputs off for inputs be-  
inverting inputs to the current sense amplifier, respec-  
tively. The integrated amplifier is configured for a gain of  
five. An absolute value function is also incorporated into  
the output in order to provide a representation of actual  
motor current when operating in four quadrant mode.  
low 10.5V. The input should be bypassed with a 0.1µF ce-  
ramic capacitor, minimum.  
VREF: VREF is a 5V, 2% trimmed reference output with  
5mA of maximum available output current. This pin  
should be bypassed to ground with a 0.1µF ceramic ca-  
pacitor, minimum.  
APPLICATION INFORMATION  
Table 1 provides the decode logic for the six outputs, signals are never simultaneously high or low. Motor's  
AHI, BHI, CHI, ALOW, BLOW, and CLOW as a function whose sensors provide 60° encoding can be converted  
of the BRAKE, COAST, DIR_IN, HALLA, HALLB, and to 120° using the circuit shown in Fig. 1.  
HALLC inputs.  
In order to prevent noise from commanding improper  
The UCC3626 is designed to operate with 120° position commutation states, some form of low pass filtering on  
sensor encoding. In this format, the three position sensor HALLA, HALLB, and HALLC is recommended. Passive  
Table 1. Commutation truth table.  
VREF  
1k  
B
R
A
K
E
C
O
A
S
T
D
I
R
_
HALL  
INPUTS  
HIGH SIDE  
OUTPUTS  
LOW SIDE  
OUTPUTS  
499Ω  
HALLB  
HALLA  
A
B
C
A
B
C
A
B
C
IN  
HALLA  
HALLB  
HALLC  
VREF  
1kΩ  
2.2nF  
0
0
0
0
0
0
0
0
0
0
0
0
X
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
X
X
X
X
1
1
1
0
0
0
1
0
0
0
1
1
X
X
1
0
0
0
1
1
1
0
0
0
1
1
1
0
X
X
1
0
1
0
0
0
1
1
1
1
1
0
0
0
X
X
1
0
1
1
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
1
0
0
0
0
0
0
0
1
1
0
1
0
0
0
0
1
0
1
0
0
1
0
0
0
0
1
0
0
0
1
1
0
0
1
0
0
0
1
1
0
0
0
0
1
1
0
0
0
0
1
0
0
1kΩ  
2N2222A  
2.2nF  
VREF  
1kΩ  
499Ω  
HALLC  
2.2nF  
Figure 1. Circuit to convert 60° hall code to 120°  
code.  
5
UCC2626  
UCC3626  
APPLICATION INFORMATION (cont.)  
VREF  
1k  
499Ω  
SYNCH  
HALLA  
HALLB  
HALLC  
HALLA  
2.2nF  
WITHOUT SYNCH  
VREF  
1kΩ  
499Ω  
CT  
WITH SYNCH  
HALLB  
2.2nF  
VREF  
Figure 3. Synchronized and unsynchronized  
oscillator waveforms.  
1kΩ  
499Ω  
HALLC  
2.2nF  
1.E+06  
R_TACH = 25k  
R_TACH = 100k  
1.E+05  
Figure 2. Passive hall filtering technique.  
R_TACH = 250k  
RC networks generally work well and should be located  
as close to the IC as possible. Fig. 2 illustrates these  
techniques.  
1.E+04  
1.E+03  
Configuring the Oscillator  
R_TACH = 500k  
1.E-09  
The UCC3626 oscillator is designed to operate at fre-  
quencies up to 250kHz and provide a triangle waveform  
on CT with a peak to peak amplitude of 5V for improved  
noise immunity. The current used to program CT is de-  
rived off of the R_TACH resistor according to the follow-  
ing equation:  
1.E-10  
1.E-08  
1.E-07  
CT (F)  
Figure 4. PWM oscillator frequency vs. CT and  
R_TACH.  
25  
switching current spikes in the local ground from causing  
jitter in the oscillator.  
IOSC  
=
Amps  
R_TACH  
Synchronizing the Oscillator  
Oscillator frequency is set by R_TACH and CT according  
to the following relationship:  
A common system specification is for all oscillators in a  
design to be synchronized to a master clock. The  
UCC3626 provides a SYNCH input for exactly this pur-  
pose. The SYNCH input is designed to interface with a  
digital clock pulse generated by the master oscillator. A  
positive going edge on this input causes the UCC3626  
2.5  
Frequency =  
Hz  
(R_TACH CT )  
Timing resistor values should be between 25kand  
500kwhile capacitor values should fall between 100pF  
and 1µF. Fig. 4 provides a graph of oscillator frequency oscillator to begin discharging. In order for the slave os-  
for various combinations of timing components. As with cillator to function properly it must be programmed for a  
any high frequency oscillator, timing components should frequency slightly lower than that of the master. Also, a  
be located as close to the IC pins as possible when lay- resistor equal to RTACH must be placed in parallel with  
ing out the printed circuit board. It is also important to ref- CT. Fig. 3 illustrates the waveforms for a slave oscillator  
erence the timing capacitor directly to the ground pin on programmed to 20kHz with a master frequency of 30kHz.  
the UCC3626 rather than daisy chaining it to another The SYNCH pin should be grounded when not used.  
trace or the ground plane. This technique prevents  
6
UCC2626  
UCC3626  
APPLICATION INFORMATION (cont.)  
Programming the Tachometer  
1.E+00  
1.E-01  
1.E-02  
1.E-03  
1.E-04  
1.E-05  
1.E-06  
The UCC3626 tachometer consists of a precision, 5V  
monostable, triggered by either a rising or falling edge on  
any of the three Hall inputs, HALLA, HALLB, HALLC. The  
resulting TACH_OUT waveform is a variable dutycycle  
square wave whose frequency is proportional to motor  
speed, as given by:  
R_TACH = 250k  
R_TACH = 500k  
(V P)  
20  
TACH_OUT =  
Hz  
R_TACH = 100k  
where P is the number of motor pole pairs and V is motor  
velocity in RPM.  
The on-time of the monostable is programmed via timing  
resistor R_TACH and capacitor C_TACH according to the  
following equation:  
R_TACH = 25k  
On Time =R_TACH C_TACH sec  
Fig. 5 provides a graph of On-Time for various combina-  
tions of R_TACH and C_TACH. On-Time is typically set to  
a value less than the minimum TACH-OUT period as  
given by:  
1.E-10  
1.E-09  
1.E-08  
Ctach (F)  
1.E-07  
1.E-06  
Figure 5. Tachometer on-time vs. C_TACH and  
R_TACH.  
20  
T_PeriodMIN  
=
sec  
VMAX P  
The TACH_OUT signal can be used to close a digital  
velocity loop using a microcontroller, as shown in Fig. 6,  
or directly low pass filtered in an analog implementation,  
Fig. 7.  
where P is the number of motor pole pairs and V is motor  
velocity in RPM.  
UCC3626  
4
5
6
R_TACH  
C_TACH  
CT  
MC68HC11  
AD558  
PB0 – PB7  
PC0  
DB0 – DB7  
VCE  
14 PWM_NI  
VCS VOUT  
VOUTSENSE  
VOUTSELECT  
13 PWM_I  
IC1  
3
TACH_OUT  
UDG-97188  
Figure 6. Digital velocity loop implementation using MC68HC11.  
7
UCC2626  
UCC3626  
APPLICATION INFORMATION (cont.)  
Two Quadrant vs Four Quadrant Control  
When configured for two quadrant operation, (QUAD=0),  
the UCC3626 will only modulate the low side devices of  
the output power stage. The current paths within the out-  
put stage during the PWM on and off times are illus-  
trated in Fig. 9. During the 'on' interval, both switches  
are on and current flows through the load down to  
ground. During the 'off' time, the lower switch is shut off  
and the motor current circulates through the upper half  
bridge via the flyback diode. The motor is assumed to be  
operating in either quadrant I or III.  
Fig. 8 illustrates the four possible quadrants of operation  
for a motor. Two quadrant control refers to a system  
whose operation is limited to quadrants I and III where  
torque and velocity are in the same direction. With a two  
quadrant brushless DC amplifier, there are no provisions  
other than friction to decelerate the load, limiting the ap-  
proach to less demanding applications. Four quadrant  
controllers, on the other hand, provide controlled opera-  
tion in all quadrants, including II and IV, where torque and  
rotation are of opposite direction.  
VMOT  
S3  
IPHASE  
S5  
S1  
IOFF  
ION  
UCC3626  
2
4
5
6
VREF  
+ BEMF -  
R_TACH  
C_TACH  
CT  
S4  
S2  
S6  
14 PWM_NI  
13 PWM_I  
+
3
TACH_OUT  
Figure 9. Two quadrant chopping.  
UDG-97189  
VMOT  
Figure 7. Simple analog velocity loop.  
S3  
S5  
S1  
IOFF  
VELOCITY  
CW  
IPHASE  
+ BEMF -  
II  
I
TORQUE  
CW  
CCW  
ION  
S4  
S2  
S6  
III  
IV  
CCW  
Figure 8. Four quadrants of operation.  
Figure 10. Two quadrant reversal.  
8
UCC2626  
UCC3626  
APPLICATION INFORMATION (cont.)  
waveforms for both two and four quadrant operation are  
illustrated in Fig. 12.  
VMOT  
Power Stage Design Considerations  
S3  
IPHASE  
S5  
S1  
The flexible architecture of the UCC3626 requires the  
user to pay close attention to the design of the power  
output stage. Two and Four Quadrant applications that do  
not require the brake function are able to utilize the  
power stage approach illustrated in Fig. 13A. In many  
cases the body diode of the MOSFET can be utilized to  
reduce parts count and cost. If efficiency is a key require-  
ment, Schottky diodes can be used in parallel with the  
switches.  
+ BEMF -  
IOFF  
ION  
S4  
S2  
S6  
If the system requires a braking function, diodes must be  
added in series with the lower power devices and the  
lower flyback diodes returned to ground, as pictured in  
Fig. 13B,C. This requirement prevents brake currents  
from circulating in the lower half bridge and bypassing  
the sense resistor. In addition, the combination of braking  
and four quadrant control necessitates an additional re-  
sistor in the diode path to sense current during the PWM  
'off' time as illustrated in Fig. 13C.  
Figure 11. Four quadrant reversal.  
If one attempts to operate in quadrants II or IV by chang-  
ing the DIR bit and reversing the torque, switches 1 and 4  
are turned off and switches 2 and 3 turned on. Under this  
condition motor current will very quickly decay, reverse  
direction and increase until the control threshold is  
reached. At this point switch 2 will turn off and current will  
once again circulate in the upper half bridge, however, in  
this case the motor's BEMF is in phase with the current,  
i.e. the motor's direction of rotation has not yet changed.  
Fig. 10 illustrates the current paths when operating in this  
mode. Under these conditions there is nothing to limit the  
current other than motor and drive impedance. These  
high circulating currents can result in damage to the  
power devices in addition to high, uncontrolled torque.  
Current Sensing  
The UCC3626 includes a differential current sense am-  
plifier with a fixed gain of five, along with an absolute  
value circuit. The current sense signal should be low  
pass filtered to eliminate leading edge spikes. In order to  
maximize performance, the input impedance of the am-  
plifier should be balanced. If the sense voltage must be  
trimmed for accuracy reasons, a low value input divider  
or a differential divider should be used to maintain im-  
pedance matching, as shown in Fig. 14.  
With four quadrant chopping motor current always flows  
through the sense resistor. However, during the flyback  
period the polarity across the sense resistor is reversed.  
The absolute value amplifier cancels the polarity reversal  
by inverting the negative sense signal during the flyback  
time, see Fig. 15. Therefore, the output of the absolute  
value amplifier is a reconstructed analog of the motor  
current, suitable for protection as well as feedback loop  
closure.  
By pulse width modulating both the upper and lower  
power devices (QUAD=1), motor current will always de-  
cay during the PWM “off” time, eliminating any uncon-  
trolled circulating currents. In addition, current will always  
flow through the current sense resistor, thus providing a  
suitable feedback signal. Fig. 11 illustrates the current  
paths during a four quadrant torque reversal. Motor drive  
9
UCC2626  
UCC3626  
APPLICATION INFORMATION (cont.)  
ROTOR POSITION IN ELECTRICAL DEGREES  
0
60  
120  
180  
240  
300  
360  
420  
480  
540  
600  
660  
720  
H1  
H2  
SENSOR  
INPUTS  
H3  
101  
100  
110  
010  
011  
001  
101  
100  
010  
011  
001  
Code  
110  
AHI  
BHI  
HIGH SIDE  
OUTPUTS  
QUAD=0  
CHI  
ALO  
BLO  
LOW SIDE  
OUTPUTS  
QUAD=0  
CLO  
+
A
B
C
0
-
+
MOTOR  
PHASE  
CURRENTS  
QUAD=0  
0
-
+
0
-
AHI  
BHI  
HIGH SIDE  
OUTPUTS  
QUAD=1  
CHI  
ALO  
BLO  
LOW SIDE  
OUTPUTS  
QUAD=1  
CLO  
+
0
A
B
C
-
+
MOTOR  
PHASE  
CURRENTS  
QUAD=1  
0
-
+
0
-
100% Duty Cycle PWM  
50% Duty Cycle PWM  
UDG-97190  
Figure 12. Motor drive and current waveforms for 2 quadrant (QUAD=0) and 4 quadrant (QUAD=1) operation.  
10  
UCC2626  
UCC3626  
TYPICAL APPLICATIONS  
VMOT  
VMOT  
VMOT  
TO  
MOTOR  
TO  
MOTOR  
TO  
MOTOR  
CURRENT  
SENSE  
CURRENT  
SENSE  
CURRENT  
SENSE  
(a)  
(b)  
(c)  
CURRENT SENSE  
AVERAGE  
TWO  
QUADRANT  
FOUR  
SAFE  
BRAKING  
POWER  
PULSE BY  
QUADRANT  
REVERSAL  
PULSE  
Yes  
Yes  
Yes  
Yes  
Yes  
No  
No  
Yes  
Yes  
In 4-Quad Only  
No  
Yes  
No  
(a)  
(b)  
(c)  
Yes  
Yes  
In 4-Quad Only  
Yes  
Yes  
Figure 13. Power stage topologies.  
Fig. 16 illustrates a simple 175V, 2A two quadrant velocity Four quadrant applications require the control of motor  
controller using the UCC3626. The power stage is de- current. Fig. 17 illustrates a sign/magnitude current con-  
signed to operate with a rectified off-line supply using trol loop within an outer bipolar velocity loop using the  
IR2210s to provide the interface between the low voltage UCC3626. U1 serves as the velocity loop error amplifier  
control signals and the power MOSFETs. The power to- and accepts a +/-5V command signal. Velocity feedback  
pology illustrated in Fig. 13C is implemented in order to is provided by low pass filtering and scaling the  
provide braking capability.  
TACH_OUT signal using U2. The direction output,  
DIR_OUT, switch and U3 set the polarity of the tachom-  
eter gain according to the direction of rotation. The out-  
put of the velocity error amplifier, U1, is then converted  
to sign/magnitude form using U5 and U6. The sign por-  
tion is used to drive the DIR input while the magnitude  
commands the current error amplifier, U8. Current feed-  
back is provided by the internal current sense amplifier  
via the IOUT pin.  
The controller's speed command is set by potentiometer  
R30 while the speed feedback signal is obtained by low  
pass filtering and buffering the TACH-OUT signal using  
R11 and C9. Small signal compensation of the velocity  
control loop is provided by amplifier U5A, whose output is  
used to control the PWM duty cycle. The integrating ca-  
pacitor, C8, places a pole at 0Hz and a zero in conjunc-  
tion with R10. This zero can be used to cancel the low  
frequency motor pole and cross the loop over with a  
–20dB gain response.  
11  
UCC2626  
UCC3626  
TYPICAL APPLICATION (cont.)  
RF  
RF  
SNS_NI  
SNS_I  
SNS_NI  
SNS_I  
RF  
RADJ  
RADJ  
Rs  
CF  
Rs  
CF  
RF  
RF  
RADJ << RF  
(a)  
(b)  
Figure 14. (a) Differential divider and (b) low value divider.  
VMOT  
Ip  
Ip  
Is  
S3  
S5  
S1  
IPHASE  
If  
+ BEMF -  
IOFF  
5*Ip  
ION  
S4  
S2  
S6  
Im  
Is  
X5  
Im  
If  
Figure 15. Current sense amplifier waveform.  
12  
UCC2626  
UCC3626  
TYPICAL APPLICATIONS (cont.)  
UDG-97184  
Figure 16. Two quadrant velocity controller.  
13  
UCC2626  
UCC3626  
TYPICAL APPLICATIONS (cont.)  
SIGN/MAGNITUDE CONVERTER  
10k 10k 10k  
11 IOUT  
10k  
U1  
U5  
VELOCITY  
COMMAND  
+/– 5V  
+
+
U8  
13 PWM_I  
10k  
U6  
+
+
CURRENT  
ERROR  
AMPLIFIER  
CURRENT  
MAGNITUDE  
U7  
21 DIR  
CURRENT SIGN  
BIPOLAR  
TACH GAIN  
10k  
10k  
TACHOMETER  
FILTER  
4.99k  
4.99k  
U3  
U2  
+
3
8
TACH_OUT  
+
2N7002  
DIR_OUT  
UDG-99061  
Figure 17. Four quadrant control loop.  
UNITRODE CORPORATION  
7 CONTINENTAL BLVD. • MERRIMACK, NH 03054  
TEL. (603) 424-2410 • FAX (603) 424-3460  
14  
IMPORTANT NOTICE  
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue  
any product or service without notice, and advise customers to obtain the latest version of relevant information  
to verify, before placing orders, that information being relied on is current and complete. All products are sold  
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those  
pertaining to warranty, patent infringement, and limitation of liability.  
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in  
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent  
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily  
performed, except those mandated by government requirements.  
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF  
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL  
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR  
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER  
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO  
BE FULLY AT THE CUSTOMER’S RISK.  
In order to minimize risks associated with the customer’s applications, adequate design and operating  
safeguards must be provided by the customer to minimize inherent or procedural hazards.  
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent  
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other  
intellectual property right of TI covering or relating to any combination, machine, or process in which such  
semiconductor products or services might be or are used. TI’s publication of information regarding any third  
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.  
Copyright 1999, Texas Instruments Incorporated  

UCC2626PWTR 相关器件

型号 制造商 描述 价格 文档
UCC27200 TI 120-V Boot, 3-A Peak, High Frequency, High-Side/Low-Side Driver 获取价格
UCC27200-Q1 TI 120-V BOOT, 3-A PEAK, HIGH-FREQUENCY HIGH-SIDE/LOW-SIDE DRIVER 获取价格
UCC27200-Q1_16 TI High-Frequency High-Side and Low-Side Driver 获取价格
UCC27200A TI 120-V Boot, 3-A Peak, High Frequency, High-Side/Low-Side Driver 获取价格
UCC27200AD TI 120-V Boot, 3-A Peak, High Frequency, High-Side/Low-Side Driver 获取价格
UCC27200ADDA TI 120-V Boot, 3-A Peak, High Frequency, High-Side/Low-Side Driver 获取价格
UCC27200ADDAR TI 120-V Boot, 3-A Peak, High Frequency, High-Side/Low-Side Driver 获取价格
UCC27200ADPRR TI IC 3 A HALF BRIDGE BASED PRPHL DRVR, PDSO10, WSON-10, Peripheral Driver 获取价格
UCC27200ADPRT TI IC 3 A HALF BRIDGE BASED PRPHL DRVR, PDSO10, WSON-10, Peripheral Driver 获取价格
UCC27200ADR TI 120-V Boot, 3-A Peak, High Frequency, High-Side/Low-Side Driver 获取价格

UCC2626PWTR 相关文章

  • Nidec交付全球首款4U 250kw CDU,助力英伟达GB200 NVL72高效冷却
    2024-12-06
    9
  • 博通推出行业首个3.5D F2F封装技术,将赋能富士通2nm MONAKA处理器
    2024-12-06
    9
  • 东方晶源回应被美国商务部列入实体清单:预计对公司影响可控
    2024-12-06
    9
  • 台积电与英伟达就美国工厂生产AI芯片展开谈判
    2024-12-06
    9