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UCC27221PWPR

更新时间：2025-07-09 13:11:20
品牌：TI
描述：3.3A HALF BRDG BASED MOSFET DRIVER, PDSO14, GREEN, PLASTIC, HTSSOP-14

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UCC27221PWPR 概述

3.3A HALF BRDG BASED MOSFET DRIVER, PDSO14, GREEN, PLASTIC, HTSSOP-14 MOSFET 驱动器

UCC27221PWPR 规格参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：TSSOP
包装说明：HTSSOP,针数：14
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01Factory Lead Time：1 week
风险等级：5.83高边驱动器：YES
接口集成电路类型：HALF BRIDGE BASED MOSFET DRIVERJESD-30 代码：R-PDSO-G14
JESD-609代码：e4长度：5 mm
湿度敏感等级：2功能数量：1
端子数量：14最高工作温度：105 °C
最低工作温度：-40 °C标称输出峰值电流：3.3 A
封装主体材料：PLASTIC/EPOXY封装代码：HTSSOP
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, HEAT SINK/SLUG, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：260认证状态：Not Qualified
座面最大高度：1.2 mm最大供电电压：20 V
最小供电电压：8.5 V标称供电电压：12 V
表面贴装：YES温度等级：INDUSTRIAL
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：GULL WING
端子节距：0.65 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED断开时间：0.11 µs
宽度：4.4 mmBase Number Matches：1

UCC27221PWPR 数据手册

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ꢀꢁ ꢁꢂ ꢃꢂ ꢂꢄ  
ꢀꢁ ꢁꢂ ꢃꢂ ꢂꢂ  
SLUS486B − AUGUST 2001 − REVISED JULY 2003  
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FEATURES  
APPLICATIONS  
ꢀ
Maximizes Efficiency by Minimizing  
Body-Diode Conduction and Reverse  
Recovery Losses  
ꢀ
Non-Isolated Single or Multi-phased  
DC-to-DC Converters for Processor Power,  
General Computer, Telecom and Datacom  
Applications  
ꢀ
Transparent Synchronous Buck Gate Drive  
Operation From the Single Ended PWM Input  
Signal  
DESCRIPTION  
ꢀ
ꢀ
12-V or 5-V Input Operation  
The UCC27221 and UCC27222 are high-speed  
synchronous buck drivers for today’s  
high-efficiency, lower-output voltage designs.  
Using Predictive Gate Driveꢁ (PGD) control  
technology, these drivers reduce diode  
conduction and reverse recovery losses in the  
3.3-V Input Operation With Availability of  
12-V Bus Bias  
ꢀ
ꢀ
On-Board 6.5-V Gate Drive Regulator  
3.3-A TrueDriveGate Drives for High  
Current Delivery at MOSFET Miller  
Thresholds  
synchronous  
rectifier  
MOSFET(s).  
The  
UCC27221 has an inverted PWM input while the  
UCC27222 has a non-inverting PWM input.  
ꢀ
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Automatically Adjusts for Changing  
Operating Conditions  
Predictive Gate Driveꢁ technology uses control  
loops which are stabilized internally and are  
therefore transparent to the user. These loops use  
no external components, so no additional design  
is needed to take advantage of the higher  
efficiency of these drivers.  
Thermally Enhanced 14-Pin PowerPAD  
HTSSOP Package Minimizes Board Area and  
Junction Temperature Rise  
FUNCTIONAL APPLICATION DIAGRAM  
This closed loop feedback system detects  
body-diode conduction, and adjusts deadtime  
delays to minimize the conduction time interval.  
This virtually eliminates body-diode conduction  
while adjusting for temperature, load- dependent  
delays, and for different MOSFETs. Precise gate  
timing at the nanosecond level reduces the  
reverse recovery time of the synchronous rectifier  
MOSFET body-diode, reducing reverse recovery  
losses seen in the main (high-side) MOSFET. The  
lower junction temperature in the low-side  
MOSFET increases product reliability. Since the  
power dissipation is minimized, a higher switching  
frequency can also be used, allowing for smaller  
component sizes.  
V
IN  
UCC27222  
IN VHI  
6,8 GND G1 13  
7
14  
PWM  
IN  
V
OUT  
3
VDD  
SW 11,12  
G2 9,10  
4,5 VLO  
The UCC27221 and UCC27222 are offered in the  
GND  
thermally enhanced 14-pin PowerPADꢁ package  
GND  
OUT  
IN  
Note: 12-V input system shown. For 5-V input only systems, see Figure 6.  
with 2°C/W θ .  
jc  
Predictive Gate Driveꢁ and PowerPADꢁ are trademarks of Texas Instruments Incorporated.  
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Copyright 2002, Texas Instruments Incorporated  
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ꢞ ꢢ ꢟ ꢞꢗ ꢘꢬ ꢚꢙ ꢝ ꢥꢥ ꢣꢝ ꢛ ꢝ ꢜ ꢢ ꢞ ꢢ ꢛ ꢟ ꢧ  
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1
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SLUS486B − AUGUST 2001 − REVISED JULY 2003  
PWP PACKAGE  
(TOP VIEW)  
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
N/C  
N/C  
VDD  
VLO  
PVLO  
AGND  
IN  
VHI  
G1  
SW  
SWS  
G2S  
G2  
8
PGND  
N/C − No internal connection  
AVAILABLE OPTIONS  
PACKAGED DEVICES  
PowerPAD  
HTSSOP−14 (PWP)  
UCC27221PWP  
UCC27222PWP  
PWM INPUT  
(IN)  
T
ꢁ
A
INVERTING  
−40ꢂ C to 105ꢂ C  
NON-INVERTING  
ꢃThe PWP package is available taped and reeled. Add R suffix to device type  
(e.g. UCC27221PWPR) to order quantities of 2,000 devices per reel and 90  
units per tube.  
†}  
absolute maximum ratings over operating free-air temperature (unless otherwise noted)  
Supply voltage range, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 to 20 V  
Input voltage, VHI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 V  
SW, SWS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 V  
Supply current, I  
including gate drive current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100 mA  
DD,  
Sink current (peak) pulsed, G1/G2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.0 A  
Source current (peak) pulsed, G1/G2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −4.0 A  
Analog input, IN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −3.0 V to V  
+ 0.3 V, not to exceed 15 V  
DD  
Power Dissipation at T = 25°C (PWP package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 W  
A
Operating junction temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −55°C to 115°C  
J
Storage temperature range, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C  
stg  
Lead temperature soldering 1.6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . 300°C  
†
‡
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and  
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not  
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.  
All voltages are with respect to AGND and PGND. Currents are positive into, negative out of the specified terminal.  
2
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SLUS486B − AUGUST 2001 − REVISED JULY 2003  
ELECTRICAL CHARACTERISTICS  
V
DD  
= 12-V, 1-µF capacitor from VDD to GND, 1-µF capacitor from VHI to SW, 0.1-µF and 2.2-µF capacitor from PVLO to PGND, PVLO tied to  
VLO, T = −40ꢂ C to 105ꢂ C for the UCC2722x, T = T (unless otherwise noted)  
A
A
J
VLO regulator  
PARAMETER  
TEST CONDITIONS  
MIN  
6.2  
6.2  
6.1  
TYP  
6.5  
6.5  
6.5  
2
MAX  
6.8  
6.8  
6.9  
10  
UNIT  
V
V
V
V
= 12 V,  
I
I
I
= 0 mA  
DD  
VLO  
VLO  
VLO  
= 20 V,  
= 0 mA  
Regulator output voltage  
V
DD  
= 8.5 V,  
= 100 mA  
DD  
Line Regulation  
Load Regulation  
= 12 V to 20 V  
= 0 mA to 100 mA  
= 8.5 V  
DD  
mV  
I
15  
40  
VLO  
(1)  
Short-circuit current  
V
DD  
220  
7.8  
mA  
V
Dropout voltage, (VDD at 5% VLO drop)  
VLO = 6.175 V,  
I
= 100 mA  
7.1  
8.5  
VLO  
undervoltage lockout  
PARAMETER  
TEST CONDITIONS  
Measured at VLO  
MIN  
3.30  
3.15  
0.07  
TYP  
3.82  
3.70  
0.12  
MAX  
4.40  
4.25  
0.20  
UNIT  
Start threshold voltage  
Minimum operating voltage after start  
Hysteresis  
V
bias currents  
PARAMETER  
TEST CONDITIONS  
MIN  
3.6  
5.5  
5.5  
TYP  
4.7  
7.1  
10  
MAX  
5.8  
8.5  
20  
UNIT  
V
V
bias current at VLO (ON), 5 V applications only  
VLO = 4.5 V,  
VDD = 8.5 V  
VDD = no connect  
LO  
mA  
bias current  
DD  
f
IN  
= 500 kHz,  
No load on G1/G2  
input command (IN)  
PARAMETER  
TEST CONDITIONS  
MIN  
3.3  
TYP  
3.6  
MAX  
3.9  
2.8  
1
UNIT  
High-level input voltage  
Low-level input voltage  
Input bias current  
10 V < VDD < 20 V  
10 V < VDD < 20 V  
V
2.2  
2.5  
V
DD  
= 15 V  
µA  
input (SWS)  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
f
= 500 kHz,  
t
t
t
maximum,  
minimum,  
minimum  
IN  
G2S = 0.0 V  
ON, G2  
ON, G2  
ON, G1  
High-level input threshold voltage  
1.4  
2.0  
2.6  
V
f
= 500 kHz,  
IN  
G2S = 0.0 V  
0.7  
1.0  
1.3  
Low-level input threshold voltage  
Input bias current  
f
= 500 kHz,  
−100 −300 −500  
mV  
mA  
IN  
SWS = 0.0 V  
−0.9  
−1.2  
−1.5  
input (G2S)  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
f
= 500 kHz,  
t
maximum,  
minimum,  
IN  
SWS = 0.0 V  
ON, G2  
High-level input voltage  
Low-level input voltage  
1.4  
2.0  
2.6  
V
f
IN  
= 500 kHz,  
t
ON, G2  
0.7  
1.0  
1.3  
SWS = 0.0 V  
Input bias current  
G2S = 0 V  
−370 −470 −570  
µA  
NOTE 1: Ensured by design. Not production tested.  
3
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SLUS486B − AUGUST 2001 − REVISED JULY 2003  
ELECTRICAL CHARACTERISTICS  
V
DD  
= 12-V, 1-µF capacitor from VDD to GND, 1-µF capacitor from VHI to SW, 0.1-µF and 2.2-µF capacitor from PVLO to PGND, PVLO tied to  
VLO, T = −40ꢂ C to 105ꢂ C for the UCC2722x, T = T (unless otherwise noted)  
A
A
J
G1 main output  
PARAMETER  
TEST CONDITIONS  
MIN  
0.3  
10  
−3  
3
TYP  
0.9  
25  
MAX  
1.5  
UNIT  
Sink resistance  
SW = 0 V,  
SW = 0 V,  
SW = 0 V,  
SW = 0 V,  
VHI = 6 V, IN = 0 V,  
G1 = 0.5 V  
Ω
(2)  
Source resistance  
VHI = 6 V, IN = 6.5 V, G1 = 5.5 V  
VHI = 6 V, IN = 6.5 V, G1 = 3.0 V  
45  
(1)(2)  
Source current  
−3.3  
3.3  
17  
A
(1)(2)  
Sink current  
Rise time  
Fall time  
VHI = 6 V, IN = 0 V,  
G1 = 3.0 V  
C = 2.2 nF from G1 to SW,  
C = 2.2 nF from G1 to SW,  
V
= 20 V  
= 20 V  
25  
25  
DD  
DD  
ns  
V
17  
G2 SR output  
PARAMETER  
(2)  
TEST CONDITIONS  
PVLO = 6.5 V, IN = 6.5 V, G1 = 0.25 V  
MIN  
5
TYP  
15  
MAX  
30  
UNIT  
Sink resistance  
Source resistance  
(1)(2)  
Ω
(2)  
PVLO = 6.5 V, IN = 0 V,  
PVLO = 6.5 V, IN = 0 V  
PVLO = 6.5 V, IN = 6.5 V  
G2 = 6.0 V  
G2 = 3.25 V  
G2 = 3.25 V  
10  
−3  
3
20  
35  
Source current  
(1)(2)  
−3.3  
3.3  
17  
A
Sink current  
(2)  
Rise time  
C = 2.2 nF from G2 to PGND V  
C = 2.2 nF from G2 to PGND V  
= 20 V  
= 20 V  
25  
35  
DD  
ns  
Fall time  
20  
DD  
deadtime delay  
PARAMETER  
TEST CONDITIONS  
MIN  
60  
TYP  
80  
MAX  
100  
110  
4.7  
UNIT  
t
t
, IN to G2 falling  
, IN to G1 falling  
OFF, G2  
55  
80  
OFF, G1  
Delay Step Resolution  
3.5  
4.1  
−15  
48  
t
t
t
t
minimum  
maximum  
minimum  
maximum  
ns  
ON, G1  
ON, G1  
ON, G2  
−21  
38  
,
ON G2  
NOTE 1: Ensured by design. Not production tested.  
2: The pullup / pulldown circuits of the drivers are bipolar and MOSFET transistors in parallel. The peak output current rating is the  
combined current from the bipolar and MOSFET transistors. The output resistance is the RDS(ON) of the MOSFET transistor when the  
voltage on the driver output is less than the saturation voltage of the bipolar transistor.  
t
OFF,G1  
3.25 V  
UCC27222  
IN  
t
t
t
ON,G2  
OFF,G2  
ON,G1  
90%  
10%  
G1  
G2  
90%  
10%  
UDG−01042  
Figure 1. Predictive Gate Drive Timing Diagram  
4
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SLUS486B − AUGUST 2001 − REVISED JULY 2003  
TERMINAL FUNCTIONS  
TERMINAL  
NAME NO.  
DESCRIPTION  
I/O  
Analog ground for all internal logic circuitry. AGND and PGND should be tied to the PCB ground plane  
with vias.  
AGND  
6
−
G1  
G2  
13  
9
O
O
High-side gate driver output that swings between SW and VHI.  
Low-side gate driver output that swings between PGND and PVLO.  
Used by the predictive deadtime controller for sensing the SR MOSFET gate voltage to set the  
appropriate deadtime.  
G2S  
IN  
10  
7
I
I
Digital input command pin. A logic high forces on the main switch and forces off the synchronous  
rectifier.  
PGND  
PVLO  
SW  
8
5
−
I
Ground return for the G2 driver. Connect PGND to PCB ground plane with several vias.  
PVLO supplies the G2 driver. Connect PVLO to VLO and bypass on the PCB.  
G1 driver return connection.  
12  
−
Used by the predictive controller to sense SR body-diode conduction. Connect to SR MOSFET drain  
close to the MOSFET package.  
SWS  
VDD  
VHI  
11  
3
I
I
Input to the internal VLO regulator. Nominal VDD range is from 8.5 V to 20 V. Bypass with at least  
0.1 µF of capacitance.  
Floating G1 driver supply pin. VHI is fed by an external Schottky diode during the SR MOSFET on-time.  
Bypass VHI to SW with an external capacitor.  
14  
4
I
Output of the VLO regulator and supply input for the logic and control circuitry. Connect VLO to PVLO and  
bypass on the PCB.  
VLO  
O
SIMPLIFIED BLOCK DIAGRAM  
N/C  
N/C  
1
2
14 VHI  
13 G1  
12 SW  
VLO  
VLO  
REGULATOR  
VDD  
VLO  
3
4
11 SWS  
10 G2S  
PREDICTIVE  
DELAY  
CONTROLLER  
+
3.82 V/ 3.7 V  
PVLO  
UVLO  
PVLO  
AGND  
5
6
PVLO  
UCC27221  
UCC27222  
9
8
G2  
IN  
7
PGND  
UDG−01030  
5
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SLUS486B − AUGUST 2001 − REVISED JULY 2003  
APPLICATION INFORMATION  
predictive gate drive technique  
The Predictive Gate Driveꢁ technology utilizes a digital feedback system to detect body-diode conduction, and  
then adjusts the deadtime delays to minimize it. This system virtually eliminates the body-diode conduction time  
intervals for the synchronous MOSFET, while adjusting for different MOSFETs characteristics, propagation and  
load dependent delays. Maximum power stage efficiency is the end result.  
Two internal feedback loops in the predictive delay controller continuously adjusts the turn on delays for the two  
MOSFET gate drives G1 and G2. As shown in Figure 2, t  
body-diode conduction in the synchronous rectifier MOSFET Q . The turn-off delay for both G1 and G2, t  
and t  
are varied to provide minimum  
ON,G1  
ON,G2  
2
OFF,G1  
and t  
are fixed by propagation delays internal to the device.  
OFF,G2  
The predictive delay controller is implemented using a digital control technique, and the time delays are  
therefore discrete. The turn-on delays, t and t , are changed by a single step (typically 3 ns) every  
ON, G1  
ON, G2  
switching cycle. The minimum and maximum turn-on delays for G1 and G2 are specified in the electrical  
characteristics table.  
UCC27221  
3.25 V  
t
OFF,G1  
IN  
3.25 V  
UCC37222  
t
t
t
ON,G2  
OFF,G2  
ON,G1  
90%  
10%  
G1  
G2  
90%  
10%  
Figure 2. Predictive Gate Drive Timing Diagram  
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A typical application circuit for systems with 8.5-V to 20-V input is shown in Figure 3.  
VIN  
D1  
R1  
UCC27222  
N/C  
N/C  
VHI  
G1  
Q1  
L1  
C1  
SW  
SWS  
G2S  
G2  
VDD  
C
V
IN  
OUT  
VLO  
PVLO  
AGND  
Q2  
C2  
Cout  
PWM  
Input  
PGND  
IN  
GND  
GND  
Figure 3. System Application: 8.5-V to 20-V Input  
selection of VHI series resistor R1 (dV/dt Considerations):  
The series resistor R1 may be needed to slowdown the turn-on of the main forward switch to limit the dV/dt which  
can inadvertently turn on the synchronous rectifier switch. In nominal 12-V input designs, a R1 value of 4-Ω to  
10-Ω can be used depending on the type of MOSFET used and the high-side/low-side MOSFET ratio. In 5-V  
or lower input applications however, R1 is not needed.  
When the drain-source voltage of a MOSFET quickly rises, inadvertent dV/dt induced turn-on of the device is  
possible. This can especially be a problem for input voltages of 12 V or greater. As Q1 rapidly turns on, the  
drain-to-source voltage of Q2 rises sharply, resulting in a dV/dt voltage spike appearing on the gate signal of  
Q2. If the dV/dt induced voltage spike were to exceed the given threshold voltage, the MOSFET may briefly  
turn on when it should otherwise be commanded off. Obviously this undesired event would have a negative  
impact on overall efficiency.  
Minimizing the dV/dt effect on Q2 can be accomplished by proper MOSFET selection and careful layout  
techniques. The details of how to select a MOSFET to minimize dV/dt susceptibility are outlined in SEM−1400,  
Topic 2, Appendix A, Section A5. Secondly, the switch node connecting Q1, Q2 and L1 should be laid out as  
tight as possible, minimizing any parasitic inductance, which might worsen the dV/dt problem.  
If the dV/dt induced voltage spike is still present on the gate Q2, a 4W to 10W value of R1 is recommended to  
minimize the possibility of inadvertently turning on Q2. The addition of R1 slows the turn-on of Q1, limiting the  
dV/dt rate appearing on the drain-to-source of Q2. Slowing down the turn-on of Q1 will result in slightly higher  
switching loss for that device only, but the efficiency gained by preventing dV/dt turn-on of Q2 will far outweigh  
the negligible effect of adding R1.  
When Q2 is optimally selected for dV/dt robustness and careful attention is paid to the PCB layout of the switch  
node, R1 may not be needed at all, and can therefore be replaced with a 0-Ω jumper to maintain high efficiency.  
The goal of the designer should not be to completely eliminate the dV/dt turn-on spike but to assure that the  
maximum amplitude is less than the MOSFET gate-to-source turn-on threshold voltage under all operating  
conditions.  
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APPLICATION INFORMATION  
selection of bypass capacitor C1  
Bypass capacitors should be selected based upon allowable ripple voltage, usually expressed as a percent of  
the regulated power supply rail to be bypassed. In all of the UCC27222 application circuits shown herein, C1  
provides the bypass for the main (high-side) gate driver. Every time Q1 is switched on, a packet of charge is  
removed from C1 to charge Q1’s gate to approximately 6.0 V. The charge delivered to the gate of Q1 can be  
found in the manufacturer’s datasheet curves. An example of a gate charge curve is shown in Figure 4.  
GATE-TO-SOURCE VOLTAGE  
vs  
TOTAL GATE CHARGE  
8
6
4
2
31 nC  
0
0
10  
20  
30  
40  
Q6 − Total Gate Charge − nC  
Figure 4.  
As shown in Figure 4, 31 nC of gate charge is required in order for Q1’s gate to be charged to 6.0 V, relative  
to its source. The minimum bypass capacitor value can be found using the following calculation:  
Q
G
C1  
+
MIN  
k   ǒVHI * VSWǓ  
(1)  
where k is the percent ripple on C1, Q is the total gate charge required to drive the gate of Q1 from zero to  
G
the final value of (VHI−VSW). In this example gate charge curve, the value of the quantity (VHI−VSW) is taken  
to be 6.0 V. This value represents the nominal VLO regulator output voltage minus the forward voltage drop of  
the external Schottky diode, D1. For the MOSFET with the gate charge described in Figure 4, the minimum  
capacitance required to maintain a 3% peak-to-peak ripple voltage can be calculated to be 172 nF, so a 180-nF  
or a 220-nF capacitor could be used. The maximum peak-to-peak C1 ripple must be kept below 0.4 V for proper  
operation.  
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selection of MOSFETs  
The peak current rating of a driver imposes a limit on the maximum gate charge of the external power MOSFET  
driven by it. The limit is based on the amount of time needed to deliver or remove the required charge to achieve  
the desired switching speed during turn-on and turn-off of the external transistor. Hence, there are the families  
of gate driver circuits with different current ratings.  
To demonstrate this, assume a constant time interval for the switching transition and a fixed gate drive  
amplitude. A larger MOSFET with more gate charge will require higher current capability from the driver to  
turn-on or turn-off the device in the same amount of time. Accordingly, there is a practical upper limit on gate  
charge which can be driven by the UCC27222 family of drivers. Considering the current capability of the  
TrueDriveoutput stage and the available dynamic range (delay adjust range) of the Predictive Gate Drive  
circuitry, this limit is approximately 120 nC of gate charge.  
Some higher current applications require several MOSFETs to be connected parallel and driven by the same  
gate drive signal. If their combined gate charge exceeds 120 nC, the rise and fall times of the gate drive signals  
will extend and limit the delay adjust range of the PGD circuit in the UCC27222. This may limit the benefits of  
the PGD technology under certain operating conditions.  
Note that there are additional considerations in the gate drive circuit design which influence the maximum gate  
charge of the external MOSFETs. The most significant of these is the operating frequency which, together with  
the amount of gate charge, will define the power dissipation in the driver. The allowable power dissipation is a  
function of the maximum junction and operating temperatures, thermal and reliability considerations.  
selection of bypass capacitor C2  
C2 supplies the peak current required to turn on the Q2 synchronous rectifier MOSFET, as well as the peak  
current to charge the C1 capacitor through the bootstrap diode. Since the synchronous MOSFET is turned on  
with 0 V across its drain-to-source, there is no Miller, or gate-to-drain charge. Therefore the synchronous  
MOSFET gate can be modeled as a simple linear capacitance. The value of this capacitance can be found from  
the datasheet’s gate charge curve. Referring to Figure 5, the slope of the curve past the Miller plateau indicates  
the equivalent gate capacitance. Because the Y-axis is described in volts, the capacitance is actually the inverse  
of the slope of the curve. For example, the curve in Figure 4 has a slope of approximately 2 V / 12 nC over the  
gate charge range of 10 nC to 40 nC. The equivalent capacitance is 12 nC / 2 V = 6 nF. With the equivalent  
capacitance, the minimum bypass capacitor value can be calculated as:  
C
EQ  
C2  
+
MIN  
k
(2)  
where  
ꢀ
ꢀ
C
is the equivalent gate capacitance,  
EQ  
k is the voltage ripple on C2, expressed as a percentage  
For a peak-to-peak ripple of 3%, the minimum C2 capacitor value is calculated to be 200 nF. A 220-nF capacitor  
would be used in this case.  
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regulator current and power dissipation  
The regulator current can be calculated from the dc or average current required by the two gate drivers. This  
current can be expressed as:  
  ǒC  
GǓ  
I
+ F  
  VLO ) Q  
EQ  
REG  
SW  
(3)  
Assuming all the power dissipation is internal to the device, and the internal bias current is negligible, the power  
dissipated by the device is:  
  ǒC  
Ǔ
P
+ F  
  VLO ) Q   VDD  
DIS  
SW  
EQ G  
(4)  
For a 500-kHz design, using MOSFETs with the gate charge characteristics shown in Figure 4 for both Q1 and  
Q2, the average regulator current would be 35 mA, and, when operated from a 12-V input rail, the resulting  
power dissipation is calculated to be 420 mW.  
systems using 3.3-V or 5-V power input and 12-V gate drive  
Figure 5 shows a schematic for systems where the power bus input is 5 V and 12 V is available for powering  
the gate drives. This system provides the 6.5-V gate drive to both MOSFETs, while the power stage operates  
off the 3.3-V or 5-V bus.  
+3.3 V  
or +5V  
D1  
R1  
UCC27222  
N/C  
N/C  
VHI  
G1  
C
Q1  
IN  
L1  
C1  
+12 V  
VDD  
VLO  
SW  
SWS  
G2S  
G2  
V
OUT  
C3  
PVLO  
Q2  
C2  
AGND  
IN  
Cout  
PWM  
Input  
PGND  
GND  
GND  
Figure 5. System Application: 3.3-V or 5-V Power Input with 12 V Available for Gate Drive  
Note that the series resistor R1 may be needed to slowdown the turn-on of the main forward switch to limit the  
dV/dt which can inadvertently turn on the synchronous rectifier switch. The dV/dt considerations and the  
selection of R1 are discussed in the previous section.  
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systems with 5-V input only  
The circuit pictured in Figure 6 starts up from a 5-V input bus and provides a 6.5-V gate drive to the power  
MOSFETs. This circuit uses a charge pump consisting of D , D and C to effectively double the input voltage  
3
4
3
and apply this to the input of the linear regulator. The regulator then regulates the doubled input voltage to the  
6.5-V nominal for VLO.  
D3  
D4  
+5V  
D1  
C3  
D2  
C2  
UCC27222  
N/C  
N/C  
VHI  
G1  
C
Q1  
IN  
L1  
C1  
VDD  
VLO  
SW  
SWS  
G2S  
G2  
V
OUT  
C4  
PVLO  
AGND  
Q2  
Cout  
PWM  
Input  
IN  
PGND  
GND  
GND  
Figure 6. System Application: 5-V-Only Power Input with 6.5-V Gate Drive Using Charge Pump Circuit  
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selecting D , D , and D  
4
2
3
Selection of suitable diodes is based upon the conducted peak and average currents. D2 simply provides a path  
to charge C2 at converter power-up. Virtually any one of the common BAT54 series of Schottky diodes can be  
used. To select D3 and D4, the peak currents of these two diodes need to be taken into account. First, the  
average current flowing in both D3 and D4 is the same as the regulator current described in equation (3). The  
peak currents in D3 and D4 are described as:  
I
REG  
I
I
+
+
D3PK  
1 * D  
(5)  
(6)  
I
REG  
D4PK  
D
For most UCC27222 applications, the duty cycle is much less than 50%, and the peak current in D3 is quite  
reasonable. However, the peak current in D4 is quite high. This high peak current requires using a diode with  
a higher current rating for D4.  
To maintain a reasonable charge pump efficiency, BAT54-type diodes can be used for applications where the  
peak currents are below approximately 40 mA. For applications where the peak current is greater than 40 mA,  
a 350-mA or 500-mA diode should be used. A typical 350-mA diode is SD103CW, SOD−123 package,  
manufactured by Diodes Inc. A typical 500-mA diode is the ZHCS500, SOT−23 package, available from Zetex  
Inc.  
selection of the flying capacitor C3  
The flying capacitor is subjected to large peak currents, and to keep the peak-to-peak ripple voltage low, this  
capacitor has to be larger than C1 and C2. Selection of C3 should be done based on allowable peak-to-peak  
ripple on C3:  
I
REG  
C3  
+
MIN  
  k   ǒVIN * VFD3Ǔ  
F
SW  
(7)  
where I  
is the regulator output current, F  
is the switching frequency, k is the percent ripple on C3, and  
REG  
SW  
V
is the forward drop of D3.  
FD2  
selection of bypass capacitor C4  
The bypass capacitor C4 needs to be sized to take the peak current from the charge pump diode D4. The  
capacitor is sized based on allowable ripple voltage:  
(
  1 * D)  
I
REG  
C
+
MIN  
  k   ǒ2   VIN * V  
FD4Ǔ  
* V  
F
FD3  
SW  
and V  
(8)  
where V  
are the forward voltages of D3 and D4 and k is the percent ripple allowed on C4.  
FD4  
FD3  
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synchronous rectification and predictive delay  
In a normal buck converter, when the main switch turns off, current is flowing to the load in the inductor. This  
current cannot be stopped immediately without using infinite voltage. For the current path to flow and maintain  
voltage levels at a safe level, a rectifier or catch device is used. This device can be either a conventional diode,  
or it can be a controlled active device if a control signal is available to drive it. The UCC27222 provides a signal  
to drive an N-channel MOSFET as a rectifier. This control signal is carefully coordinated with the drive signal  
for the main switch so that there is minimum delay from the time that the rectifier MOSFET turns off and the main  
switch turns on, and minimum delay from when the main switch turns off and the rectifier MOSFET turns on.  
This scheme, Predictive Gate Driveꢁ delay, uses information from the current switching cycle to adjust the  
delays that are to be used in the next cycle. Figure 7 shows the switch-node voltage waveform for a  
synchronously rectified buck converter. Illustrated are the relative effects of a fixed-delay drive scheme  
(constant, pre-set delays for the turnoff to turn on intervals), an adaptive delay drive scheme (variable delays  
based upon voltages sensed on the current switching cycle) and the predictive delay drive scheme.  
Note that the longer the time spent in body-diode conduction during the rectifier conduction period, the lower  
the efficiency. Also, not described in Figure 7 is the fact that the predictive delay circuit can prevent the body  
diode from becoming forward biased at all while at the same time avoiding cross conduction or shoot through.  
This results in a significant power savings when the main MOSFET turns on, and minimizes reverse recovery  
loss in the body diode of the rectifier MOSFET.  
The power dissipation on the main (forward) MOSFET is reduced as well, although that savings is not as  
significant as the savings in the rectifier MOSFET.  
During reverse recovery the body diode is still forward biased, thus the reverse recovery current goes through  
the forward MOSFET while the drain−source voltage is still high, causing additional switching losses. Without  
PGD during this switching transition, Vds = Vin and Ids = Iload + Irr in the main MOSFET. With PGD however,  
Vds = Vin and Ids = Iload. The reduction in current accounts for additional power savings in the main MOSFET.  
V
IN  
0 V  
V
D
GND  
Channel Conduction  
Body Diode Conduction  
Fixed Delay  
Adaptive Delay  
Predictive Delay  
UDG−02175  
Figure 7. Switch Node Waveforms for Synchronous Buck Converter  
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comparison between predictive and adaptive gate drive techniques  
The first synchronous rectifier controllers had a fixed turn-on delay between the two gate drivers. The advantage  
of this well-known technique is its simplicity. The drawbacks include the need to make the delay times long  
enough to cover the entire application of the device and the temperature and lot-to-lot variation of the time delay.  
Since the body-diode of the synchronous rectifier conducts during this deadtime, the efficiency of this technique  
varies with different MOSFETs, ambient temperature, and with the lot-to-lot variation of the deadtime delay.  
To combat the variability of the internal time delays, second generation controllers used state information from  
the power stage to control the turn-on of the two gate drivers. This technique is usually referred to as adaptive  
gate drive technique and is pictured in FIgure 8.  
V
IN  
+
+
ON ON  
OFF  
V
OUT  
UDG−01031  
Figure 8. Adaptive Gate Drive Technique  
The main advantage of the adaptive technique is the on-the-fly delay adjustment for different MOSFETs and  
temperature-variable time delays. The disadvantages include the body-diode conduction time intervals caused  
by delays in the cross-coupling loops and the inability to compensate for the delay to charge the MOSFET gates  
to the threshold levels. Additionally, it is difficult to determine whether the synchronous MOSFET channel is off  
by solely monitoring the SR MOSFET gate voltage. Some devices actually add a programmable delay between  
the turn-off of the synchronous rectifier and the turn-on of the main MOSFET via an external capacitor. This  
added delay directly affects the power stage efficiency through additional body-diode conduction losses. Since  
these losses are centralized in the synchronous MOSFET, the stress and temperature rise in this component  
becomes a major design headache.  
The third-generation predictive control technique is different from the adaptive technique in that it uses  
information from the previous switching cycle to set the deadtime for the current cycle. The adaptive technique  
on the other hand uses the current state information to set the delay times. The inherent feedback loop  
propagation delays cause body-diode conduction.  
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adaptive vs. predictive waveforms  
Figures 9 through 11 illustrate the adaptive (left) vs. predictive (right) switching waveforms. Key comparison  
regions are denoted with (A), (B), (C), (D), and (E) for the adaptive control waveforms and (A′), (B′), (C′), (D′),  
and (E′) for the predictive control waveforms. Figures 10 and 11 are close-ups of each transition edge.  
At (A), the propagation delay from sensing the synchronous rectifier gate going low to the high-side gate going  
high results in approximately 60 ns of body-diode conduction shown at (B). With the predictive drive, as soon  
as the body-diode conduction of the SR MOSFET (B) is sensed, the high-side turn-on delay is adjusted to  
minimize the body-diode conduction time (B′).  
At (A′), the high side gate-to-source voltage is increasing while the synchronous rectifier gate-to-source voltage  
is decreasing. A natural result of the precise timing of the high-side MOSFET turn-on is shown at (C) and (C′).  
The overshoot and ringing for the predictive drive (C′) has much smaller amplitude than the adaptive drive (C)  
due a reduction in reverse recovery in the SR MOSFET body diode. This reduction in reverse recovery is only  
possible with the extremely precise gate timing used in the predictive drive technique.  
At (D), the propagation delay from the synchronous rectifier drain-to-source voltage falling to the gate-to-source  
voltage rising causes the body diode of the SR MOSFET to conduct for approximately 60 ns (E). When the  
predictive drive is enabled (D′), the inherent delay is eliminated and virtually no body-diode conduction is shown  
at (E′).  
Complementary  
Gate Drive  
Waveforms  
2 V / div  
D
A
A4  
D4  
C
C4  
VDS of SR  
MOSFET  
Switch  
E4  
B4  
E
B
2 V / div  
Predictive Drive  
100 ns / div  
Adaptive Drive  
100 ns / div  
Figure 9. Adaptive vs. Predictive Switching Waveforms  
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A4  
Complementary  
Gate Drive  
A
Waveforms  
2 V / div  
C
C4  
VDS of SR  
MOSFET  
Switch  
B4  
B
2 V / div  
Adaptive Drive  
20 ns / div  
Predictive Drive  
20 ns / div  
Figure 10. Close-Up: Turn-Off of Synchronous Rectifier Switch to Turn-On of Main Switch  
Complementary  
Gate Drive  
Waveforms  
D4  
D
2 V / div  
VDS of SR  
MOSFET  
Switch  
E4  
E
2 V / div  
Adaptive Drive  
20 ns / div  
Predictive Drive  
20 ns / div  
Figure 11. Close-Up: Turn-Off of Main Switch to Turn-On of Synchronous Rectifier Switch  
efficiency comparison  
Figures 12 through 15 show a series of efficiency measurements taken at two output voltages (0.9 V and 1.8  
V) and two switching frequencies (250 kHz and 500 kHz) for both predictive and adaptive delay techniques.  
The efficiency gain using the predictive technique is 1% for a V  
of 250 kHz (Figure 12). Figures 13 and 14 show the efficiency gain approximately doubles when V  
level of 1.8 V and at a switching frequency  
OUT  
is lowered  
OUT  
by a factor of two (to 0.9 V), or when the switching frequency is doubled to 500 kHz. With both doubled frequency  
and one-half of the output voltage, the efficiency gain of predictive technology is about 4% over the adaptive  
technology (Figure 15). Therefore, as the switching frequency increases and output voltages are lowered, the  
efficiency gains are higher. This results in lower operational temperatures for increased reliability as well as  
smaller size designs for increased frequencies.  
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APPLICATION INFORMATION  
EFFICIENCY  
vs  
EFFICIENCY  
vs  
OUTPUT CURRENT  
OUTPUT CURRENT  
96  
94  
92  
90  
88  
86  
84  
82  
80  
0.5  
96  
0.5  
V
V
= 5 V  
= 0.9 V  
= 250 kHz  
IN  
OUT  
94  
92  
90  
88  
86  
84  
82  
80  
PREDICTIVE  
f
SW  
0.4  
0.3  
PREDICTIVE  
0.4  
0.3  
ADAPTIVE  
ADAPTIVE  
0.2  
0.1  
0.0  
0.2  
0.1  
0.0  
DELTA POWER  
DISSIPATION  
78  
76  
78  
76  
DELTA POWER  
DISSIPATION  
V
V
= 5 V  
= 1.8 V  
= 250 kHz  
IN  
OUT  
f
SW  
74  
74  
0
5
10  
15  
20  
0
5
10  
15  
20  
I
− Output Current − A  
I
− Output Current − A  
OUT  
OUT  
Figure 12  
Figure 13  
EFFICIENCY  
vs  
EFFICIENCY  
vs  
OUTPUT CURRENT  
OUTPUT CURRENT  
96  
94  
92  
90  
88  
86  
84  
82  
80  
1.2  
1.0  
96  
94  
92  
90  
88  
86  
84  
82  
80  
1.2  
1.0  
V
V
= 5 V  
IN  
= 0.9 V  
= 500 kHz  
OUT  
PREDICTIVE  
f
SW  
PREDICTIVE  
0.8  
0.6  
0.8  
0.6  
ADAPTIVE  
DELTA POWER  
DISSIPATION  
ADAPTIVE  
0.4  
0.2  
0.4  
0.2  
78  
76  
78  
76  
V
V
= 5 V  
= 1.8 V  
IN  
OUT  
= 500 kHz  
DELTA POWER  
DISSIPATION  
f
SW  
74  
0.0  
20  
74  
0.0  
20  
0
5
10  
15  
0
5
10  
15  
I
− Output Current − A  
OUT  
I
− Output Current − A  
OUT  
Figure 14  
Figure 15  
17  
www.ti.com  
ꢀ ꢁꢁꢂ ꢃ ꢂ ꢂ ꢄ  
ꢀ ꢁꢁꢂ ꢃ ꢂ ꢂ ꢂ  
SLUS486B − AUGUST 2001 − REVISED JULY 2003  
LAYOUT CONSIDERATIONS  
packaging  
The UCC27221/2 are only available in TI’s thermally enhanced 14-pin PowerPadpackage. This package  
offers exceptional thermal impedance with a junction-to-case rating of 2ꢂC/W. Shown as the crosshatched  
region in Figure 16, PowerPadincludes an exposed leadframe die pad located on the bottom side of the  
package. Exposed pad dimensions for the PowerPadꢁ TSSOP 14-pin package are 69 mils x 56 mils (1.8 mm  
x 1.4 mm). However, the exposed pad tolerances can be + 41 / − 2 mils (+ 1.05 /− .05 mm) due to position and  
mold flow variation. Effectively removing the heat from the PowerPADpackage requires a thermal land area,  
shown as the shaded gray region in Figure 16, designed into the PCB directly beneath the package. A minimum  
thermal land area of 5 mm by 3.4 mm is recommended as illustrated in Figure 16. Any tolerance variances of  
the exposed PowerPadfalls well within the thermal land area when the recommended minimum land area  
is included on the printed circuit board. In addition, a 2-by-3 array of 13-mil thermal vias is required within the  
exposed PowerPadarea, as shown in Figure 16. If additional heat sinking capability is required, larger 25-mil  
vias can be added to the thermal land area.  
Required Vias on PowerPad Area  
2 x 3 Array  
3.4mm  
(0.1339”)  
0.65mm  
0.33mm  
(0.0256”)  
(13 mil) dia Vias  
Exposed  
5.0mm  
PowerPad  
1.8mm (0.069”)  
(0.1968”)  
1.05mm  
0.3mm  
(0.0118”)  
(0.0413”)  
Optional Vias on Thermal Land Area  
0.635mm  
Exposed  
PowerPad  
(25 mil) dia Vias  
1.4mm (0.056”)  
Figure 16. TSSOP−14PWP Package Outline and Minimum PowerPADE PCB Thermal Land  
18  
www.ti.com  
ꢀ ꢁꢁ ꢂꢃ ꢂꢂ ꢄ  
ꢀ ꢁꢁ ꢂꢃ ꢂꢂ ꢂ  
SLUS486B − AUGUST 2001 − REVISED JULY 2003  
REFERENCE DESIGN AND EVALUATION MODULE  
A reference design is discussed in, 12 V to 1.8 V, 20-A High Efficiency Synchronous Buck Converter Using the  
UCC27222 with Predictive Gate Driveꢁ, TI Literature Number SLUU140 and accompanying evaluation module  
(EVM) SLUP192. The design highlights UCC27222 and its Predictive Gate Driveꢁ synchronous buck operation  
using a simple single ended PWM controller. The schematic is shown in Figure 17.  
Figure 17. Typical Application Diagram  
19  
www.ti.com  
ꢀ ꢁꢁꢂ ꢃ ꢂ ꢂ ꢄ  
ꢀ ꢁꢁꢂ ꢃ ꢂ ꢂ ꢂ  
SLUS486B − AUGUST 2001 − REVISED JULY 2003  
TYPICAL CHARACTERISTICS  
UVLO THRESHOLD  
vs  
TEMPERATURE  
BIAS CURRENT  
vs  
TEMPERATURE (NO LOAD)  
16  
14  
4.2  
4.1  
4.0  
3.9  
3.8  
3.7  
3.6  
I
: VDD = 12 V, 500 kHz  
DD  
12  
10  
UVLO On  
8
6
4
2
0
I
: VDD = 8.5 V, Static  
UVLO Off  
DD  
I
: VLO = 12 V, Static, 5 V Only Systems  
VLO  
3.5  
3.4  
3.3  
3.2  
−50  
−25  
0
25  
50  
75  
100  
125  
−50  
−25  
0
25  
T − Temperature − °C  
A
50  
75  
100  
125  
T
− Temperature − °C  
A
Figure 18  
Figure 19  
VLO LINE REGULATION  
vs  
VLO LOAD REGULATION  
vs  
TEMPERATURE (NO LOAD, IVLO = 0 mA)  
TEMPERATURE  
6.8  
6.8  
6.7  
6.6  
6.7  
6.6  
V
DD  
= 20 V  
I
= 0 mA  
VLO  
6.5  
6.5  
V
DD  
= 12 V  
I
= 100 mA  
VLO  
6.4  
6.3  
6.4  
6.3  
6.2  
6.2  
−50  
−25  
0
25  
50  
75  
100  
125  
−50  
−25  
0
25  
50  
75  
100  
125  
T
A
− Temperature − °C  
T
A
− Temperature − °C  
Figure 20  
Figure 21  
20  
www.ti.com  
ꢀ ꢁꢁ ꢂꢃ ꢂꢂ ꢄ  
ꢀ ꢁꢁ ꢂꢃ ꢂꢂ ꢂ  
SLUS486B − AUGUST 2001 − REVISED JULY 2003  
TYPICAL CHARACTERISTICS  
DROPOUT VOLTAGE (VDD AT VLO = 6.175 V)  
DROPOUT VOLTAGE (VDD AT VLO = 6.175 V)  
vs  
vs  
OUTPUT CURENT  
TEMPERATURE (I  
= 100 mA)  
VLO  
8.6  
8.4  
8.2  
8.0  
7.8  
7.6  
7.4  
8.6  
8.4  
8.2  
8.0  
7.8  
7.6  
7.4  
7.2  
7.0  
7.2  
7.0  
−50  
−25  
0
25  
50  
75  
100  
125  
0
50  
100  
T
A
− Temperature − °C  
IVLO − VLO Output Current − mA  
Figure 22  
Figure 23  
VLO SHORT CIRCUIT CURRENT  
INPUT THRESHOLD  
vs  
vs  
TEMPERATURE  
TEMPERATURE (VDD = 10 V TO 20 V)  
4.0  
3.5  
3.0  
2.5  
2.0  
1.5  
1.0  
300  
Input Threshold Rising  
290  
280  
270  
260  
Input Threshold Falling  
Input Threshold Hyst.  
250  
240  
230  
220  
210  
200  
0.5  
0.0  
−50  
−25  
0
25  
50  
75  
100  
125  
−50  
−25  
0
25  
50  
75  
100  
125  
T
A
− Temperature − °C  
T
A
− Temperature − °C  
Figure 24  
Figure 25  
21  
www.ti.com  
ꢀ ꢁꢁꢂ ꢃ ꢂ ꢂ ꢄ  
ꢀ ꢁꢁꢂ ꢃ ꢂ ꢂ ꢂ  
SLUS486B − AUGUST 2001 − REVISED JULY 2003  
TYPICAL CHARACTERISTICS  
PREDICTIVE DELAY BIT WEIGHT  
PROPAGATION DELAYS  
vs  
vs  
TEMPERATURE  
TEMPERATURE  
4.7  
4.5  
120  
100  
t
, G2  
OFF  
4.3  
4.1  
80  
60  
t
, G1  
OFF  
3.9  
3.7  
40  
20  
3.5  
0
−50  
−25  
0
25  
50  
75  
100  
125  
−50  
−25  
0
25  
50  
75  
100  
125  
T
A
− Temperature − °C  
T
A
− Temperature − °C  
Figure 26  
Figure 27  
PREDICTIVE DELAY RANGE  
PREDICTIVE DELAY RANGE  
vs  
vs  
TEMPERATURE  
TEMPERATURE  
60  
60  
50  
50  
t
, G1 Max  
ON  
40  
30  
40  
30  
t
, G2 Max  
ON  
20  
10  
20  
10  
0
0
t
, G1 Min  
t
, G2 Min  
ON  
ON  
−10  
−10  
−20  
−30  
−20  
−30  
−50  
−25  
0
25  
50  
75  
100  
125  
−50  
−25  
0
25  
50  
75  
100  
125  
T
A
− Temperature − °C  
T
A
− Temperature − °C  
Figure 28  
Figure 29  
22  
www.ti.com  
ꢀ ꢁꢁ ꢂꢃ ꢂꢂ ꢄ  
ꢀ ꢁꢁ ꢂꢃ ꢂꢂ ꢂ  
SLUS486B − AUGUST 2001 − REVISED JULY 2003  
TYPICAL CHARACTERISTICS  
G1 RISE AND FALL TIMES  
G2 RISE AND FALL TIMES  
vs  
vs  
TEMPERATURE (2.2 nF)  
TEMPERATURE (2.2 nF)  
30  
25  
30  
25  
20  
Fall Time  
20  
Rise Time  
15  
10  
15  
Rise Time  
Fall Time  
10  
5
5
0
0
−50  
−25  
0
25  
50  
75  
100  
125  
−50  
−25  
0
25  
50  
75  
100  
125  
T
A
− Temperature − °C  
T
A
− Temperature − °C  
Figure 30  
Figure 31  
G1 SINK RESISTANCE  
vs  
G1 SOURCE RESISTANCE  
vs  
TEMPERATURE (R  
)
TEMPERATURE  
DS(on)  
40  
35  
30  
25  
20  
15  
10  
5
1.5  
1.4  
1.3  
1.2  
1.1  
1.0  
0.9  
0.8  
0.7  
0.6  
0.5  
0
−50  
−25  
0
25  
50  
75  
100  
125  
−50  
−25  
0
25  
50  
75  
100  
125  
T
A
− Temperature − °C  
T
A
− Temperature − °C  
Figure 32  
Figure 33  
23  
www.ti.com  
ꢀ ꢁꢁꢂ ꢃ ꢂ ꢂ ꢄ  
ꢀ ꢁꢁꢂ ꢃ ꢂ ꢂ ꢂ  
SLUS486B − AUGUST 2001 − REVISED JULY 2003  
TYPICAL CHARACTERISTICS  
G2 SOURCE RESISTANCE  
G2 SINK RESISTANCE  
vs  
vs  
TEMPERATURE  
TEMPERATURE (R  
)
DS(on)  
40  
35  
30  
40  
35  
30  
25  
20  
25  
20  
15  
10  
5
15  
10  
5
0
0
−50  
−25  
0
25  
50  
75  
100  
125  
−50  
−25  
0
25  
50  
75  
100  
125  
T
A
− Ambient Temperature − °C  
T
A
− Temperature − °C  
Figure 34  
Figure 35  
RELATED PRODUCTS  
PART  
NUMBER  
GATE  
DRIVE  
DESCRIPTION  
PACKAGE  
TPS2830/1  
TPS2832/3  
TPS2834/5  
TPS2836/7  
TPS2838/9  
TPS2848/9  
Fast synchronous buck MOSFET drivers with dead-time control  
Fast synchronous buck MOSFET drivers with dead-time control  
Synchronous buck MOSFET drivers with dead-time control  
Synchronous buck MOSFET drivers with dead-time control  
Synchronous buck MOSFET drivers with drive regulator  
Synchronous buck MOSFET drivers with drive regulator  
2.4 A  
2.4 A  
2.4 A  
2.4 A  
4 A  
PowerPADꢁ HTSSOP−14, SOIC−14  
SOIC−8  
PowerPADꢁ HTSSOP−14, SOIC−14  
SOIC−8  
PowerPADꢁ HTSSOP−16  
PowerPADꢁ HTSSOP−14  
PowerPADꢁ MSOP−10  
4 A  
TPS40000/1/2/3 Low input voltage mode synchronous buck controller with predictive  
gate drive  
1 A  
REFERENCES  
1. Power Supply Design Seminar SEM−1400 Topic 2: Design and Application Guide for High Speed MOSFET  
Gate Drive Circuits, by Laszlo Balogh, Texas Instruments Literature Number SLUP169.  
2. Power Supply Design Seminar SEM−1400 Topic 7: Implication of Synchronous Rectifiers in Isolated,  
Single-Ended, Forward Converters, by Christopher Bridge, Texas Instruments Literature Number  
SLUP175.  
3. 12 V to 1.8 V, 20 A High-Efficiency Synchronous Buck Converter Using UCC27222 With Predictive Gate  
Drive] Technology, TI Literature Number SLUU140.  
24  
www.ti.com  
ꢀ ꢁꢁ ꢂꢃ ꢂꢂ ꢄ  
ꢀ ꢁꢁ ꢂꢃ ꢂꢂ ꢂ  
ꢐ
SLUS486B − AUGUST 2001 − REVISED JULY 2003  
PowerPADꢁ PLASTIC SMALL−OUTLINE  
PWP (R−PDSO−G14)  
25  
www.ti.com  
ꢀ ꢁꢁꢂ ꢃ ꢂ ꢂ ꢄ  
ꢀ ꢁꢁꢂ ꢃ ꢂ ꢂ ꢂ  
SLUS486B − AUGUST 2001 − REVISED JULY 2003  
MECHANICAL DATA  
PWP (R-PDSO-G**)  
PowerPADPLASTIC SMALL-OUTLINE  
20 PINS SHOWN  
0,30  
0,19  
0,65  
20  
M
0,10  
11  
Thermal Pad  
(See Note F)  
0,15 NOM  
4,50  
4,30  
6,60  
6,20  
Gage Plane  
1
10  
0,25  
A
0°−ā8°  
0,75  
0,50  
Seating Plane  
0,10  
0,15  
0,05  
1,20 MAX  
PINS **  
14  
16  
20  
24  
28  
DIM  
5,10  
4,90  
5,10  
4,90  
6,60  
6,40  
7,90  
7,70  
9,80  
9,60  
A MAX  
A MIN  
4073225/F 10/98  
NOTES: A. All linear dimensions are in millimeters.  
B. This drawing is subject to change without notice.  
C. Body dimensions do not include mold flash or protrusions.  
D. The package thermal performance may be enhanced by attaching an external heat sink to the thermal pad.  
This pad is electrically and thermally connected to the backside of the die.  
E. Falls within JEDEC MO-153  
F. The PowerPADis not directly connected to any leads of the package. However, it is electrically and thermally connected to the  
substrate which is the ground of the device. The exposed pad dimension is 1.4 mm x 1.8 mm. However, the tolerances can be  
+1.05/−0.05 mm (+ 41 / −2 mils) due to position and mold flow variation.  
G. For additional information on the PowerPADꢁ package and how to take advantage of its heat dissipating abilities, refer to Technical  
Brief, PowerPad Thermally Enhanced Package, Texas Instrument s Literature No. SLMA002 and Application Brief, PowerPad Made  
Easy, Texas Instruments Literature No. SLMA004. Both documents are available at www.ti.com.  
26  
www.ti.com  
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TI warrants performance of its hardware products to the specifications applicable at the time of sale in  
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI  
deems necessary to support this warranty. Except where mandated by government requirements, testing of all  
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amplifier.ti.com  
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dataconverter.ti.com  
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dsp.ti.com  
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www.ti.com/broadband  
www.ti.com/digitalcontrol  
www.ti.com/military  
Interface  
Logic  
interface.ti.com  
logic.ti.com  
Power Mgmt  
Microcontrollers  
power.ti.com  
Optical Networking  
Security  
www.ti.com/opticalnetwork  
www.ti.com/security  
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Wireless  
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Copyright 2003, Texas Instruments Incorporated  

UCC27221PWPR 相关器件

型号 制造商 描述 价格 文档
UCC27221PWPRG4 TI 3.3A HALF BRDG BASED MOSFET DRIVER, PDSO14, GREEN, PLASTIC, HTSSOP-14 获取价格
UCC27222 TI HIGH EFFICIENCY PREDICTIVE SYNCHRONOUS BUCK DRIVER 获取价格
UCC27222PWP TI HIGH EFFICIENCY PREDICTIVE SYNCHRONOUS BUCK DRIVER 获取价格
UCC27222PWPG4 TI 高效 Predictive 技术同步降压驱动器 | PWP | 14 | -40 to 105 获取价格
UCC27222PWPR TI 高效 Predictive 技术同步降压驱动器 | PWP | 14 | -40 to 105 获取价格
UCC27222PWPRG4 TI 3.3A HALF BRDG BASED MOSFET DRIVER, PDSO14, GREEN, PLASTIC, HTSSOP-14 获取价格
UCC27223 TI HIGH-EFFICIENCY PREDICTIVE SYNCHRONOUS BUCK DRIVER WITH ENABLE 获取价格
UCC27223PWP TI HIGH-EFFICIENCY PREDICTIVE SYNCHRONOUS BUCK DRIVER WITH ENABLE 获取价格
UCC27223PWPG4 TI HIGH-EFFICIENCY PREDICTIVE SYNCHRONOUS BUCK DRIVER WITH ENABLE 获取价格
UCC27223PWPR TI HIGH-EFFICIENCY PREDICTIVE SYNCHRONOUS BUCK DRIVER WITH ENABLE 获取价格

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