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UCD7230PWP

更新时间：2025-06-29 05:48:23
品牌：TI
描述：Digital Control Compatible Synchronous Buck 【4-A Drivers with Current Sense Conditioning Amplifier

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UCD7230PWP 概述

Digital Control Compatible Synchronous Buck 【4-A Drivers with Current Sense Conditioning Amplifier 数字控制兼容同步降压【 4 -A具有电流感应调放大器驱动器 MOSFET 驱动器

UCD7230PWP 规格参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：TSSOP包装说明：HTSSOP-20
针数：20Reach Compliance Code：compliant
ECCN代码：EAR99HTS代码：8542.39.00.01
Factory Lead Time：1 week风险等级：5.73
Is Samacsys：N高边驱动器：NO
接口集成电路类型：BUFFER OR INVERTER BASED MOSFET DRIVERJESD-30 代码：R-PDSO-G20
JESD-609代码：e4长度：6.5 mm
湿度敏感等级：2功能数量：1
端子数量：20最高工作温度：105 °C
最低工作温度：-40 °C标称输出峰值电流：4 A
封装主体材料：PLASTIC/EPOXY封装代码：HTSSOP
封装等效代码：TSSOP20,.25封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, HEAT SINK/SLUG, THIN PROFILE, SHRINK PITCH峰值回流温度（摄氏度）：260
电源：12 V认证状态：Not Qualified
座面最大高度：1.2 mm子类别：MOSFET Drivers
最大供电电压：15.5 V最小供电电压：4.5 V
标称供电电压：12 V表面贴装：YES
温度等级：INDUSTRIAL端子面层：NICKEL PALLADIUM GOLD
端子形式：GULL WING端子节距：0.65 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：4.4 mmBase Number Matches：1

UCD7230PWP 数据手册

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UCD7230  
www.ti.com  
SLUS741–NOVEMBER 2006  
Digital Control Compatible Synchronous Buck ±4-A Drivers with Current Sense  
Conditioning Amplifier  
FEATURES  
APPLICATIONS  
•
Digitally-Controlled Synchronous-Buck Power  
Stages for Single and Multi-Phase  
Applications  
•
Input from Digital Controller Sets Operating  
Frequency and Duty Cycle  
•
•
Up to 2-MHz Switching Frequency  
•
•
Especially Suited for Use with UCD91xx or  
UCD95xx Contollers  
High-Current Multi-Phase VRM/EVRD  
Regulators for Desktop, Server, Telecom and  
Notebook Processors  
Dual Current Limit Protection with  
Independently Adjustable Thresholds  
•
Fast Current Sense Circuit with 25-ns  
Propagation Delay and Adjustable Blanking  
Interval Prevents Catastrophic Current Levels  
•
Digitally-Controlled Synchronous-Buck Power  
Supplies Using µCs or the TMS320TM DSP  
Family  
•
•
Digital Output Current Limit Flag  
Low Offset, Gain of 25, Differential Current  
Sense Amplifier  
DESCRIPTION  
•
•
•
3.3-V, 10-mA Internal Regulator  
The UCD7230 is part of the UCD7K family of digital  
control compatible drivers for applications utilizing  
digital control techniques or applications requiring  
fast local peak current limit protection.  
Dual ±4-A TrueDrive™ High-Current Drivers  
10-ns Typical Rise/Fall Times with 2.2-nF  
Loads  
•
•
25-ns Input-to-Output Propagation Delay  
25-ns Current Sense-to-Output Propagation  
Delay  
•
4.5-V to 15.5-V Supply Voltage Range  
VIN  
VOUT  
CS  
VDD  
CS+  
BST  
OUT1  
SW  
PVDD  
OUT2  
PGND  
BIAS  
IO  
+
0.6 V  
+
UVLO  
IDLY  
POS  
NEG  
25x  
DriveandDead-Time  
ControlLogic  
(D;1-D)  
Enable  
3V3  
REG  
3V3  
BIAS  
Blank  
AGND  
AO  
IN  
ILOAD  
PWM  
SRE  
Over  
Current  
ILIM  
CLF  
SRE  
DLY  
IMAX  
Current  
Limit Logic  
ILIM/10  
IDLY  
CLF  
+
UCD7230  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
TrueDrive, PowerPAD are trademarks of Texas Instruments.  
PRODUCT PREVIEW information concerns products in the  
formative or design phase of development. Characteristic data and  
other specifications are design goals. Texas Instruments reserves  
the right to change or discontinue these products without notice.  
Copyright © 2006, Texas Instruments Incorporated  
UCD7230  
www.ti.com  
SLUS741–NOVEMBER 2006  
The UCD7230 is a 4-A MOSFET gate driver specifically designed for synchronous buck applications. It is ideally  
suited to provide the bridge between digital controllers such as the UCD91xx or the UCD95xx and the power  
stage. With 25-ns cycle-by-cycle current limit protection, the UCD7230 device protects the power stage from  
faulty input signals or excessive load currents.  
The UCD7230 includes high-side and low-side 4-A gate drivers which utilize Texas Instrument’s TrueDrive™  
output architecture. This architecture delivers rated current into the gate capacitance of a MOSFET during the  
Miller plateau region of the switching. Furthermore, the UCD7230 offers a low offset differential amplifier with a  
fixed gain of 25. This amplifier greatly simplifies the task of conditioning small current sense signals inherent in  
high efficiency buck converters.  
The UCD7230 includes a 3.3-V, 10-mA linear regulator to provide power to digital controllers such as the  
UCD91xx. The UCD7230 is compatible with standard 3.3-V I/O ports of the UCD91xx, the TMS320TM family  
DSPs, µCs, or ASICs.  
The UCD7230 is offered in PowerPAD™ HTSSOP or space-saving QFN packages. Package pin out has been  
carefully designed for optimal board layout  
SIMPLIFIED APPLICATION DIAGRAMS  
VIN  
UCD7230  
1
2
3
VDD  
SRE  
IN  
CS+ 20  
UCD9112  
2
RB0  
CSBIAS 19  
ADC3  
DPWMA0  
2
18  
SW  
AD33  
AVSS  
VOUT  
4
5
6
17  
3V3  
OUT1  
AGND  
DLY  
16  
BST  
RPOS  
GSENSE  
1
2
PVDD 15  
VD25  
EAP  
14  
13  
DPWMB0  
7
8
9
OUT2  
ILIM  
CLF  
I0  
VOUT  
RB1/TMRI1  
PGND  
1
RNEG  
NEG 12  
POS 11  
EAM  
GSENSE  
ADC2  
10 A0  
RST  
2
COMMUNICATION  
(Programming&  
StatusReporting)  
Figure 1. Single-Phase Synchronous Buck Converter using UCD9112 and one UCD7230  
2
UCD7230  
www.ti.com  
SLUS741–NOVEMBER 2006  
SIMPLIFIED APPLICATION DIAGRAMS (continued)  
VIN  
UCD7230PWP  
RB0  
1
2
3
VDD  
SRE  
IN  
CS+ 20  
UCD9112  
2
RB0  
CSBIAS 19  
ADC3  
2
DPWMA0  
18  
SW  
AD33  
AVSS  
VOUT  
4
5
6
17  
3V3  
OUT1  
RPOS1  
AGND  
DLY  
16  
BST  
GSENSE  
2
PVDD 15  
VD25  
EAP  
1
14  
13  
DPWMB0  
7
8
9
OUT2  
ILIM  
CLF  
I0  
VOUT  
RB1/TMRI1  
PGND  
RNEG1  
1
NEG 12  
POS 11  
EAM  
GSENSE  
ADC2  
10 A0  
RST  
UCD7230PWP  
1
2
3
VDD  
SRE  
IN  
CS+ 20  
CSBIAS 19  
SW 18  
2
RB0  
DPWMA1  
2
COMMUNICATION  
(Programming&  
StatusReporting)  
4
5
6
17  
3V3  
OUT1  
RPOS2  
AGND  
DLY  
16  
BST  
2
PVDD 15  
14  
7
8
9
DPWMB1  
ILIM  
CLF  
I0  
OUT2  
13  
PGND  
RB3/TMRI0  
RNEG2  
1
NEG 12  
POS 11  
10 A0  
ADC5  
2
2
Figure 2. Multi-Phase Synchronous Buck Converter using UCD9112 and two UCD7230  
3
UCD7230  
www.ti.com  
SLUS741–NOVEMBER 2006  
CONNECTION DIAGRAMS  
20  
1
2
3
4
CS+  
VDD  
SRE  
19  
CSBIAS  
18  
SW  
IN  
20  
19  
18  
17  
16  
3V3  
1
2
3
15 SW  
17  
16  
15  
14  
13  
12  
11  
OUT1  
3V3  
UCD7230  
(QFN -  
RGW)  
AGND  
DLY  
14 OUT1  
13 BST  
5
6
UCD7230  
(HTSSOP)  
AGND  
DLY  
BST  
PVDD  
(5x5, 0.65)  
ILIM  
CLF  
4
5
12 PVDD  
11 OUT2  
7
ILIM  
OUT2  
6
7
8
9
10  
8
PGND  
NEG  
CLF  
I0  
9
10  
POS  
A0  
ORDERING INFORMATION(1)(2)  
PACKAGED DEVICES  
PowerPAD™ HTSSOP-20 (PWP)  
UCD7230PWP  
TEMPERATURE RANGE  
QFN-20 (RGW)  
-40°C to + 125°C  
UCD7230RGW  
(1) These products are packaged in Pb-Free and green lead finish of Pd-Ni-Au which is compatible with MSL level 1 at 255-260°C peak  
reflow temperature to be compatible with either lead free or Sn/Pb soldering operations.  
(2) HTSSOP-20 (PWP), and QFN-20 (RGW) packages are available taped and reeled. Add R suffix to device type (e.g. UCD7230PWPR) to  
order quantities of 2,000 devices per reel for the PWP package and 1,000 devices per reel for the RSA and RGW packages.  
4
UCD7230  
www.ti.com  
SLUS741–NOVEMBER 2006  
ABSOLUTE MAXIMUM RATINGS(1)  
over operating free-air temperature range (unless otherwise noted)  
PARAMETER  
CONDITION  
VALUE  
UNIT  
VDD  
IDD  
Supply voltage  
16  
20  
V
Quiescent  
Supply current  
mA  
V V  
Switching, TA = 25°C, TJ =  
125°C, VDD = 12 V  
200  
VO  
OUT1, BST  
-1 V to 36  
-1 V to VDD+0.3  
4.0  
Output gate drive voltage  
Output gate drive current  
OUT2  
IOUT(sink)  
OUT1  
IOUT(source)  
IOUT(sink)  
OUT1  
-2.0  
A
OUT2  
4.0  
IOUT(source)  
OUT2  
-4.0  
SW  
-1 to 20  
-0.3 to 20  
-0.3 to 16  
-0.3 to 5.6  
-0.3 to 3.6  
-0.3 to 3.6  
-0.3 to 3.6  
2.67  
CS+  
Analog inputs  
CSBIAS  
POS, NEG  
V
ILIM, DLY, I0  
Analog output  
Digital I/O’s  
A0  
IN, SRE, CLF  
TA = 25°C (PWP-20 package)  
TA = 25°C (QFN-20 package)  
Power dissipation  
W
TJ  
Junction operating temperature  
Storage temperature  
-55 to 150  
-65 to 150  
2000  
°C  
Tstg  
HBM  
CDM  
Human body model  
ESD rating  
V
Charged device model  
500  
Lead temperature (soldering, 10 sec)  
300  
°C  
(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings  
only and functional operation of the device at these or any other condition beyond those indicated is not implied. Exposure to absolute  
maximum rated conditions for extended periods may affect device reliability. All voltages are with respect to GND. Currents are positive  
into, negative out of the specified terminal. Consult company packaging information for thermal limitations and considerations of  
packages.  
5
UCD7230  
www.ti.com  
SLUS741–NOVEMBER 2006  
ELECTRICAL CHARACTERISTICS  
VDD = PVDD = 12 V, 4.7-µF from VDD to AGND, 1 µF from PVDD to PGND, 0.1 µF from CS+ to AGND, 0.22 µF from BST to SW,  
TA = TJ = -40°C to +125°C, RCS+ = 5 kΩ, RDLY = 50 kΩ over operating free-air temperature range (unless otherwise noted).  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
SUPPLY  
Supply current, off  
Supply current  
VDD = 4.2 V  
400  
4
500  
µA  
Outputs not switching IN = LOW  
TBD  
mA  
LOW-VOLTAGE UNDER-VOLTAGE LOCKOUT  
VDD UVLO ON  
VDD rising  
VDD falling  
4.25  
4.05  
150  
4.5  
4.5  
4.75  
4.75  
350  
V
VDD UVLO OFF  
VDD UVLO hysteresis  
250  
mV  
REFERENCE / EXTERNAL BIAS SUPPLY  
3V3 initial set point  
TA = 25°C  
3.267  
3.234  
3.3  
3.3  
1
3.333  
3.366  
7
V
3V3 over temperature  
3V3 load regulation  
ILOAD = 1 mA to 10 mA, VDD = 5V  
mV  
VDD = 4.75 V to 12 V, ILOAD = 10  
mA  
3V3 line regulation  
1
7
Short circuit current  
3V3 OK threshold, ON  
3V3 OK threshold, OFF  
INPUT SIGNAL (IN)  
VDD = 4.75 V to 12 V  
3.3 V rising  
11  
2.9  
2.7  
17  
3
mA  
V
3.1  
2.8  
3.3 V falling  
2.8  
Positive-going input threshold  
INHigh  
voltage  
1.65  
1.16  
0.6  
2.08  
1.5  
Negative-going input threshold  
voltage  
INLow  
V
INHigh –  
Input voltage hysteresis  
INLow  
0.8  
Input resistance to AGND  
Frequency ceiling  
50  
2
100  
150  
kΩ  
MHz  
CURRENT LIMIT (ILIM)  
ILIM internal voltage setpoint  
ILIM input impedance  
ILIM=OPEN  
0.51  
25  
0.55  
50  
0.58  
75  
V
kΩ  
CLF output high level  
ILOAD = 7 mA  
ILOAD = 7 mA  
2.64  
V
CLF output low level  
0.66  
20  
Propagation delay from IN to reset  
CLF  
2nd IN rising to CLF falling after a  
current limit event  
15  
ns  
CURRENT SENSE COMPARATOR (OUTPUT SENSE)  
ILIM = open  
55  
100  
75  
ILIM = 3.3 V  
ILIM = 0.75 V  
ILIM = 0.25 V  
CS threshold (POS - NEG)  
mV  
ns  
25  
Propagation delay from POS to  
OUT1 falling(1)  
ILIM = open, CS = threshold + 60 mV  
ILIM = open, CS = threshold + 60 mV  
ILIM = open, CS = threshold + 60 mV  
60  
80  
50  
Propagation delay from POS to  
OUT2 rising(1)  
Propagation delay from POS to  
CLF(1)  
(1) As designed and characterized. Not 100% tested in production.  
6
UCD7230  
www.ti.com  
SLUS741–NOVEMBER 2006  
ELECTRICAL CHARACTERISTICS (continued)  
VDD = PVDD = 12 V, 4.7-µF from VDD to AGND, 1 µF from PVDD to PGND, 0.1 µF from CS+ to AGND, 0.22 µF from BST to SW,  
TA = TJ = -40°C to +125°C, RCS+ = 5 kΩ, RDLY = 50 kΩ over operating free-air temperature range (unless otherwise noted).  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
CURRENT SENSE COMPARATOR (INPUT SENSE)  
RDLY = 50 kΩ (CSBIAS-CS+)  
RDLY = 100 kΩ (CSBIAS-CS+)  
120  
60  
CS threshold  
mV  
RDLY = 50 kΩ , IN rising to OUT1, IN  
falling to OUT2  
CS blanking time(2)  
Rdelay range  
125  
50  
ns  
25  
100  
kΩ  
Propagation delay from CS+ to  
OUT1(2)  
60  
Propagation delay from CS+ to  
OUT2(2)  
CS = threshold + 60mV  
60  
50  
ns  
Propagation delay from CS+ to  
CLF(2)  
CURRENT SENSE AMP  
Closed loop dc gain (current sense  
resistor method)  
I0 = FLOAT; VPOS = 1.26 V; VNEG  
1.25 V  
=
23  
-0.3  
3
25  
27  
V/V  
Closed loop dc gain (lossless  
current sense method)  
I0 = FLOAT; VPOS= 1.26 V; VNEG =  
1.25 V; RPOS = 1 kΩ  
24  
50  
Input impedance  
Differential, POS – NEG  
kΩ  
V
VCM  
VIO  
Input Common Mode Voltage Range VCM(max) is limited to (VDD-1.2V)  
5.6  
Input Offset Voltage  
I0 = FLOAT; VPOS = VNEG = 1.25 V  
1
mV  
VPOS = 1.2 V; VNEG = 1.3 V;  
A0_ISINK = 250 µA  
A0_Vol  
Minimum Output Voltage  
0.15  
0.2  
3.3  
V
VPOS =1.3 V; VNEG = 1.2 V; A0_  
ISOURCE = 500 µA  
A0_Voh  
Maximum Output Voltage  
Input Bias Current  
3.1  
I0 = FLOAT; VPOS = VNEG = 5.0 V,  
RPOS = 1 kΩ  
POS  
NEG  
POS  
NEG  
10  
10  
2
I0 = FLOAT; VPOS = VNEG = 5.0 V  
uA  
I0 = FLOAT; VPOS = VNEG = 0.8 V,  
RPOS = 1 kΩ  
I0 = FLOAT; VPOS = VNEG = 0.8 V  
2
ZERO CURRENT REFERENCE (IO)  
Reference voltage  
Measured at I0  
0.54  
45  
7
0.6  
25  
50  
5
0.66  
55  
V
IO open, POS = NEG = open,  
measure AO - IO  
IO output offset voltage  
Input transition voltage  
Input transition current  
mV  
With respect to IO reference  
Initial source current into pin to use  
an external I0 voltage  
uA  
IO  
Output impedance  
IZERO = 0.6 V  
10  
14  
kΩ  
(2) As designed and characterized. Not 100% tested in production.  
7
UCD7230  
www.ti.com  
SLUS741–NOVEMBER 2006  
ELECTRICAL CHARACTERISTICS (continued)  
VDD = PVDD = 12 V, 4.7-µF from VDD to AGND, 1 µF from PVDD to PGND, 0.1 µF from CS+ to AGND, 0.22 µF from BST to SW,  
TA = TJ = -40°C to +125°C, RCS+ = 5 kΩ, RDLY = 50 kΩ over operating free-air temperature range (unless otherwise noted).  
PARAMETER  
LOW-SIDE OUTPUT DRIVER (OUT2)  
Source current(3)  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNIT  
VDD = 12 V, IN = high, OUT2 = 5 V  
VDD = 12 V, IN = low, OUT2 = 5 V  
VDD = 4.75 V, IN = high, OUT2 = 0  
4
4
2
(3)  
Sink current  
Source current(3)  
A
VDD = 4.75 V, IN = low, OUT2 =  
4.75 V  
(3)  
Sink current  
3
Rise time  
CLOAD = 2.2 nF, VDD = 12 V  
CLOAD = 2.2 nF, VDD = 12 V  
VDD = 1.0 V, Isink = 10 mA  
10  
10  
ns  
Fall time  
Output with VDD <UVLO  
0.8  
1.2  
V
CLOAD = 2.2 nF, VDD = 12 V, IN  
falling  
Propagation delay from IN to OUT2  
60  
ns  
HIGH-SIDE OUTPUT DRIVER (OUT1)  
VDD = 12 V, BST = 12 V IN = High,  
OUT1 = 5 V  
Source current(3)  
2
4
VDD = 12 V, BST = 12 V IN = Low,  
OUT1 = 5 V  
(3)  
Sink current  
A
VDD = 4.75 V = BST = 4.75 V, IN =  
High, OUT1 = 0  
(3)  
Source current  
1
VDD = 4.75 V, BST = 4.75 V, IN =  
Low, OUT1 = 4.75 V  
(3)  
Sink current  
3
CLOAD = 2.2 nF OUT1 to SW, VDD  
= 12 V  
Rise time  
Fall time  
20  
10  
40  
CLOAD = 2.2 nF OUT1 to SW, VDD  
12 V  
=
ns  
CLOAD = 2.2 nF, VDD = 12 V, IN  
rising  
Propagation delay from IN to OUT1  
(3) As designed and characterized. Not 100% tested in production.  
8
UCD7230  
www.ti.com  
SLUS741–NOVEMBER 2006  
DEVICE INFORMATION  
TERMINAL FUNCTIONS  
TERMINAL  
UCD7230  
I/O  
DESCRIPTION  
NAME  
HTSSOP-  
QFN-20  
20  
Supply input pin to power the internal circuitry except the driver outputs. The  
UCD7230 accepts an input range of 4.5 V to 15.5 V.  
VDD  
1
18  
-
I
Synchronous Rectifier Enable. The SRE pin is a high impedance digital input  
capable of accepting 3.3-V logic level signals, used to disable the synchronous  
rectifier switch. The synchronous rectifier is disabled when this signal is low. A  
Schmitt trigger input comparator desensitizes this pin from external noise.  
SRE  
IN  
2
3
19  
20  
The IN pin is a high impedance digital input capable of accepting 3.3-V logic  
level signals up to 2 MHz. A Schmitt trigger input comparator desensitizes this  
pin from external noise.  
I
Regulated 3.3-V rail. The onboard linear voltage regulator is capable of  
sourcing up to 10 mA of current. Bypass with 0.22-µF ceramic capacitance  
from this pin to analog ground, AGND.  
3V3  
4
5
1
2
O
-
AGND  
Analog ground return.  
Requires a resistor to AGND for setting the current sense blanking time for  
both the high-side and low-side current sense comparators. The value of this  
resistor in conjunction with the resistor in series with the CS+ pin sets the high  
side current sense threshold.  
Output current limit threshold set pin. The output current threshold is 1/10th of  
the value set on this pin. If left floating the voltage on this pin is 0.55 V. The  
voltage on the ILIM pin can range from 0.25 V to 1V to set the threshold from  
25 mV to 100 mV.  
DLY  
ILIM  
6
7
3
4
I
I
Current Limit Flag. The CLF signal is a 3.3-V digital output which is latched  
high after an over current event, triggered by either of the two current sense  
comparators and reset after two clock pulses received on the IN pin.  
CLF  
IO  
8
9
5
6
7
O
I
Sets the current sense linear amplifier “Zero” output level. The default value is  
0.6 V which allows negative current measurement.  
Current sense linear amplifier output. The output voltage level on this pin  
represents the average output current. Any value below the level on the I0 pin  
represents negative output current.  
AO  
10  
O
Non-inverting input of the output current sense amplifier and current limit  
comparator.  
POS  
11  
12  
13  
14  
8
9
I
I
-
I
Inverting input of the output current sense amplifier and current limit  
comparator.  
NEG  
Power ground return. This pin should be connected close to the source of the  
low-side synchronous rectifier MOSFET.  
PGND  
OUT2  
10  
11  
The low-side high-current TrueDrive™ driver output. Drives the gate of the  
low-side synchronous MOSFET between PVDD and PGND.  
Supply pin provides power for the output drivers. It is not connected internally  
to the VDD supply rail. The bypass capacitor for this pin should be returned to  
PGND.  
PVDD  
15  
12  
-
Floating OUT1 driver supply powered by an external Schottky diode from the  
PVDD pin during the synchronous MOSFET on time.  
BST  
16  
17  
13  
14  
I
I
The high-side high-current TrueDrive™ driver output. Drives the gate of the  
high-side buck MOSFET between SW and BST.  
OUT1  
SW  
18  
19  
15  
16  
I/O  
I
OUT1 gate drive return and square wave input to output inductor.  
Supply pin for the high-side current sense comparator.  
CSBIAS  
Non-inverting Input for the high side current sense comparator. A resistor  
connected between this pin and the high side MOSFET drain, in conjunction  
with the DLY resistor sets the high-side current limit threshold.  
CS+  
20  
17  
I
9
UCD7230  
www.ti.com  
SLUS741–NOVEMBER 2006  
APPLICATION INFORMATION  
Introduction  
The UCD7230 is a synchronous buck driver with peak-current limiting. It is a member of the UCD7K family of  
digital compatible drivers suitable either for applications utilizing digital control techniques or analog applications  
that require local fast peak current limit protection.  
In systems using the UCD7230, the feedback loop is closed externally and the IN signal represents the PWM  
information required to regulate the output voltage. The PWM signal may be implemented by either a digital or  
analog controller.  
The UCD7230 has two over-current protection features, one that limits the peak current in the high-side switch  
and one that limits the output current. Both limits are individually programmable. The internal current sense  
blanking enables ease of design with real-world signals. In addition to over current limit protection, current sense  
signals can be conditioned by the on board amplifier for use by the system controller.  
Supply Requirements  
The UCD7230 operates on a supply range of 4.5 V to 15.5 V. The supply voltage should be applied to three  
pins, PVDD, VDD, and CSBIAS. PVDD is the supply pin for the lower driver, and has the greatest current  
demands. The supply connection to PVDD is also the point where an external Schottky diode provides current to  
the high side flying driver. PVDD should be bypassed to PGND with a low ESR ceramic capacitor. In the same  
fashion, the flying driver should be bypassed between BST and SW.  
VDD and CSBIAS are less demanding supply pins, and should be resistively coupled to the supply voltage for  
isolation from noise generated by high current switching and parasitic board inductance. Use 100 Ω for CSBIAS  
and 1 Ω for VDD. VDD should be bypassed to AGND with a 4.7-µF ceramic capacitor while CSBIAS should be  
bypassed to AGND with 0.1 µF. Although the three supply pins are not internally connected, they must be  
biased to the same voltage. It is important that all bypassing be done with low parasitic inductance techniques to  
good ground planes.  
PGND and AGND are the ground return connections to the chip. Ground plane construction should be used for  
both pins. For a MOSFET driver operating at high frequency, it is critical to minimize the stray inductance to  
minimize overshoot, undershoot, and ringing. The low output impedance of the drivers produces waveforms with  
high di/dt. This induces ringing in the parasitic inductances. It is highly desirable that the UCD7230 and the  
MOSFETs be collocated. PGND and the AGND pins should be connected to the PowerPAD™ of the package  
with two thin traces. It is critical to ensure that the voltage potential between these two pins does not exceed 0.3  
V.  
Although quiescent VDD current is low, total supply current depends on the gate drive output current required for  
the capacitive load and the switching frequency. Total supply current is the sum of quiescent VDD current and  
the average OUT current. Knowing the operating frequency and the MOSFET gate charge (Qg), average OUT  
current can be calculated from (IOUT = Qg x f), where f is the operating frequency.  
10  
UCD7230  
www.ti.com  
SLUS741–NOVEMBER 2006  
APPLICATION INFORMATION (continued)  
Reference / External Bias Supply  
The UCD7230 includes a series pass regulator to provide a regulated 3.3 V at the 3V3 pin that can be used to  
power other circuits such as the UCD91xx, a microcontroller or an ASIC. 3V3 can source 10 mA of current. For  
normal operation, place a 0.22-µF ceramic capacitor between 3V3 and AGND.  
Control Inputs  
IN and SRE are high impedance digital inputs designed for 3.3-V logic-level signals. They both have 100-kΩ  
pull-down resistors. Schmitt Trigger input stage design immunizes the internal circuitry from external noise. IN is  
the command input for the upper driver, OUT1, and can function up to 2 MHz. SRE controls the function of the  
lower driver, OUT2. When SRE is false (low), OUT2 is held low. When SRE is true, OUT2 is inverted from OUT1  
with appropriate delays that preclude cross conduction in the Buck MOSFETs.  
Driver Stages  
The driver outputs utilize Texas Instruments’ TrueDrive™ architecture, which delivers rated current into the gate  
of a MOSFET when it is most needed, during the Miller plateau region of the switching transition. This provides  
best switching speeds and reduces switching losses. TrueDrive™ consists of pull-up/ pull-down circuits using  
bipolar and MOSFET transistors in parallel. This hybrid output stage also allows relatively constant current  
sourcing even at reduced supply voltages.  
The low-side high-current output stage of the UCD7230 device is capable of sourcing and sinking 4-A  
peak-current pulses and swings from PVDD to PGND. The high-side floating output diver is capable of sourcing  
2 A and sinking 4-A peak-current pulses. This ratio of gate currents, common to synchronous buck applications,  
minimizes the possibility of parasitic turn on of the low-side power MOSFET due to dv/dt currents during the  
rising edge switching transition.  
If further limiting of the rise or fall times to the power device is desired, an external resistance can be added  
between the output of the driver and the power MOSFET gate. The external resistor also helps remove power  
dissipation from the driver.  
The driver outputs follows the IN and SRE as previously described provided that VDD and 3V3 are above their  
respective under-voltage lockout thresholds. When the supplies are insufficient, the chip holds both OUT1 and  
OUT2 low.  
It is worth reiterating the need mentioned in the supply section for sound high frequency design techniques in  
the circuit board layout and bypass capacitor selection and placement. Some applications may generate  
excessive ringing at the switch-inductor node. This ringing can drag SW to negative voltages that might cause  
functional irregularities. To prevent this, carefull board layout and appropriate snubbing are essential. In addition,  
it may be appropriate to couple SW to the inductor with a 1-Ω resistor, and then bypass SW to PGND with a low  
impedance Schottky diode.  
Current Sensing and Overload Protection  
Since the UCD7230 is physically collocated with the high-current elements of the power converter, it is logical  
that current be monitored by the chip. An internal instrumentation amplifier conditions current sense signals so  
that they can be used by the control chip generating the pwm signal.  
POS and NEG are inputs to an instrumentation amplifier circuit. This amplifier has a nominal gain of 25 and  
presents its output at AO. This can be used to monitor a parallel RC around the buck inductor shown in  
Figure 3. As long as the RPOS x C time constant is the same as the L/R of the inductor and its parasitic  
equivalent series resistance, then the voltage on C is the same as the IR drop on the parasitic inductor  
resistance. Signals in this method can be very small, so the amp is necessary to condition the signals to useful  
amplitudes. Should more accurate current sensing be required, a sense resistor can be placed between the  
buck inductor and output capacitor. Since that resistor represents inefficiency to the converter, it will also be a  
very small value of resistance with small signals, and, again, the amp conditions the signal to useful size.  
11  
UCD7230  
www.ti.com  
SLUS741–NOVEMBER 2006  
APPLICATION INFORMATION (continued)  
The internal configuration of the instrumentation amplifier is such that AO is 0.6 V when POS – NEG = zero.  
Because of this output offset, the amplifier can accurately pass information for both positive and negative load  
current. The offset is controlled by IO. If IO is left to float, the offset is 0.6 V. 0.6 V is present at IO through an  
internal 10-kΩ resistor and should be bypassed to AGND. If a higher value of offset is desired, a voltage in  
excess of 0.65 V can be externally applied to IO. Once IO is forced above 0.65 V, the internal 10 kΩ is  
disconnected, and then the AO output offset is now equal to the voltage at IO. The transfer function of the  
amplifier is given by:  
AO = 25( POS - NEG )+ IO  
SW  
VOUT  
RPOS  
OUT2 PGND  
POS  
RNEG  
NEG  
UCD7230  
Figure 3. Lossless Average Output Current Sensing Using DC Resistance of the Output Inductor  
12  
 
UCD7230  
www.ti.com  
SLUS741–NOVEMBER 2006  
APPLICATION INFORMATION (continued)  
While the amp faithfully passes the sensed current signal, it should be noted that the amplifier is bandwidth  
limited for normal switching frequencies. Therefore, AO represents a moving average of the sensed current.  
Should noise filtering be desired, a capacitor, not to exceed 220 pF, can be placed from AO to AGND. There is  
a 1-kΩ resistor between the amplifier output and A0 for this cap to work with. Alternately, a capacitor can be  
connected between POS and NEG to filter against the RPOS resisance.  
Note that inferring inductor current by use of a parallel RC has the following caveats. As long as the RPOS x C  
time constant is the same as L/R, then the voltage across C is the same as the IR drop across the equivalent R  
of the inductor. If the time constants don’t match, the average voltage across C is still the same as the average  
voltage across R, but the indication of ripple current amplitude will be off. Tolerance of the value of R in the  
inductor has a direct effect on measurement accuracy, as does the temperature coefficient of R. Copper has a  
temperature coefficient of approximately 3800 ppm/°C. For a 100 °C rise in winding temperature, the dc  
resistance of the inductor increases by 38%. The worst case scenario would be a cracked core or  
under-designed inductor in which cases the core could tend towards saturation. In that scenario, inductor current  
could change slope drastically and is not correctly modeled by the capacitor voltage.  
For impedance matching and best common mode rejection, a resistor, RNEG = RPOS, should be inserted in series  
with NEG as shown in Figure 3. RPOS slightly lowers the amplifier gain, and therefore should be kept ≤ 1 kΩ.  
The amp output can go up to 3.3 V, so reasonable designs limit full scale to 3.0 V. Should attenuation be  
necessary, use a resistive divider between AO and the control chip A/D input as shown in Figure 4.  
1 kW  
To A/D  
AO  
Figure 4. Level Shifting and Filtering the Voltage Representation of the Average Output Current  
13  
 
UCD7230  
www.ti.com  
SLUS741–NOVEMBER 2006  
APPLICATION INFORMATION (continued)  
While the current sense amplifier is useful for accurate current monitoring or controlling overload conditions,  
extreme overload conditions must be handled in timeframes that are generally much shorter than the A/D of a  
control chip can achieve. Therefore, there are two comparators on the UCD7230 to sense extreme overload and  
protect the driven power MOSFETs.  
Extreme current overload is handled in two ways by the UCD7230. One is a comparator that monitors the  
voltage between POS and NEG, or effectively the output current of the converter as shown in Figure 3. The  
other is a comparator that monitors the voltage drop across the high side MOSFET, or effectively the input  
current. Should either condition exceed a preset value, OUT1 is immediately turned off for the remainder of the  
cycle.  
To program the current limit, a value of resistance from DLY to AGND must first be chosen to establish a  
blanking time during which the comparators will be blinded to switching noise. The blanking time starts with the  
rising edge on IN for the input comparator and from both the rising and falling edge of IN for the output  
comparator. Blanking time is given by:  
tBLANK ( ns ) = 2.5RDLY ( kW )  
where RDLY is the resistor from DLY to AGND. RDLY should be limited to a range of 25 kΩ to 100 kΩ.  
Once RDLY has been chosen, the threshold for the input comparator, i.e., the drop allowed across the high-side  
MOSFET, is given by:  
VCS( in ) =1.2·( RCS+ RDLY  
)
Where VCS(in) is the threshold of allowed voltage across the high-side MOSFET and RCS+ is a resistor connected  
from CS+ to the drain of the high-side MOSFET.  
The blanking time for the output comparator is identical to the input comparator. The output comparator  
threshold is given by:  
VCS( out ) = ILIM 10  
Where VCS(out) is the threshold of allowed voltage between the POS and NEG pins and ILIM is the voltage on the  
ILIM pin. Note that the ILIM is internally connected to 0.5 V through a 40-kΩ resistor. Any voltage between 0.25  
V and 1.0 V can be applied to ILIM. For voltages above 1.0 V, the maximum VCS(out) threshold is clamped to 0.1  
V. Possible methods for setting ILIM are shown in Figure 5.  
When using the output comparator to monitor the voltage on the parallel sensing capacitor across the inductor,  
the same caveats apply as described for the current sense amplifier.  
14  
UCD7230  
www.ti.com  
SLUS741–NOVEMBER 2006  
APPLICATION INFORMATION (continued)  
A) GPIO Outputs  
DIGITAL  
CONTROLLER  
UCD7230  
3V3  
VCC  
GND  
AGND  
ILIM  
40 kW  
20 kW  
10 kW  
2.5 kW  
GPIO1  
GPIO2  
GPIO3  
GPIO4  
ILIM SETPOINT  
[Volts]  
0.50  
0.00  
0.14  
0.29  
0.43  
0.57  
0.72  
0.86  
1.00  
GPIO3  
GPIO2  
GPIO1  
GPIO4  
ILIM (open)  
ILIM0  
OPEN  
OPEN  
OPEN  
OPEN  
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
0
0
0
0
0
0
ILIM1  
ILIM2  
ILIM3  
ILIM4  
ILIM5  
ILIM6  
ILIM7  
B) PWM Output  
DIGITAL  
UCD7230  
CONTROLLER  
VCC  
3V3  
GND  
AGND  
ILIM  
Cf  
Rf  
PWM  
Rf and Cf filter the PWM  
output to generate a DC  
input to the ILIM PIN  
C) Resistor Divider  
DIGITAL  
CONTROLLER  
UCD7230  
3V3  
VCC  
GND  
AGND  
ILIM  
R2  
R1  
UCD7230  
3V3  
D) Internal Set Point  
AGND  
ILIM  
Cf  
Figure 5. Setting the ILIM Voltage with: A) GPIO Outputs, B) PWM Output, C) Resistor Divider, D) Internal  
Set Point.  
15  
UCD7230  
www.ti.com  
SLUS741–NOVEMBER 2006  
APPLICATION INFORMATION (continued)  
If either comparator threshold is exceeded, OUT1 is immediately turned off for the remainder of the cycle and  
CLF is asserted true. Upon the rising edge of IN, the switches resume normal operation, but the CLF assertion  
is maintained. If a fault is not detected in this switching cycle, then the next rising edge of IN removes the CLF  
assertion. However, if one of the comparators detects a fault, then CLF assertion continues. It is the privilege of  
the control device to monitor CLF and decide how to handle the fault condition. Meanwhile, the protection  
comparators protect the power MOSFET switches on a cycle-by-cycle basis. Note that when a fault condition  
causes OUT1 to be driven low, and OUT2 behaves as if the input pulse had been terminated normally. In some  
fault conditions, it is advantageous to drive OUT2 low. SRE can be used to cause OUT2 to remain low at the  
discretion of the control chip. This can be used to achieve faster discharge of the inductor and also to fully  
disconnect the converter from the output voltage.  
Startup Handshaking  
The UCD7230 has a built-in handshaking feature to facilitate efficient start-up of the digitally controlled power  
supply. At start-up the CLF flag is held high until all the internal and external supply voltages of the device are  
within their operating range. Once the supply voltages are within acceptable limits, CLF goes low and the device  
will process input commands. The digital controller should monitor CLF at start-up and wait for CLF to go low  
before sending pwm information to the UCD7230.  
Thermal Management  
The usefulness of a driver is greatly affected by the drive power requirements of the load and the thermal  
characteristics of the device package. In order for a power driver to be used over a particular temperature range,  
the package must allow for the efficient removal of the heat while keeping the junction temperature within rated  
limits. The UCD7230 is available in PowerPAD™ HTSSOP and QFN packages to cover a range of application  
requirements. Both have the exposed pads to remove thermal energy from the semiconductor junction.  
As illustrated in Reference [3 & 4], the PowerPAD™ packages offer a lead-frame die pad that is exposed at the  
base of the package. This pad is soldered to the copper on the PC board (PCB) directly underneath the device  
package, reducing the θJA down to 38°C/W. The PC board must be designed with thermal lands and thermal  
vias to complete the heat removal subsystem, as summarized in Reference [3].  
Note that the PowerPAD™ is not directly connected to any leads of the package. However, it is electrically and  
thermally connected to the substrate which is the ground of the device. The PowerPAD™ should be connected  
to the quiet ground of the circuit.  
REFERENCES  
1. Power Supply Seminar SEM-1600 Topic 6: A Practical Introduction to Digital Power Supply Control, by  
Laszlo Balogh, Texas Instruments Literature No. SLUP224  
2. Power Supply Seminar SEM–1400 Topic 2: Design and Application Guide for High Speed MOSFET Gate  
Drive Circuits, by Laszlo Balogh, Texas Instruments Literature No. SLUP133.  
3. Technical Brief, PowerPad Thermally Enhanced Package, Texas Instruments Literature No. SLMA002  
4. Application Brief, PowerPAD™ Made Easy, Texas Instruments Literature No. SLMA004  
RELATED PRODUCTS  
RELATED PRODUCTS  
PRODUCT  
UCD9501  
UCD9111  
UCD9112  
DESCRIPTION  
FEATURES  
Digital power controller for high performance multi-loop applications  
Digital power controller for power supply applications  
Digital power controller for power supply applications  
16  
IMPORTANT NOTICE  
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Copyright 2006, Texas Instruments Incorporated  

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