SI9135_11

更新时间:2024-11-30 10:19:17
品牌:VISHAY
描述:SMBus Multi-Output Power-Supply Controller

SI9135_11 概述

SMBus Multi-Output Power-Supply Controller SMBus的多路输出电源控制器

SI9135_11 数据手册

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Not recommended for new designs, please refer to Si9138  
Si9135  
Vishay Siliconix  
SMBus Multi-Output Power-Supply Controller  
DESCRIPTION  
FEATURES  
The Si9135 is a current-mode PWM and PSM converter  
controller, with two synchronous buck converters (3.3 V and  
5 V) and a flyback (non-isolated buck-boost) converter  
(12 V). Designed for portable devices, it offers a total five  
power outputs (three tightly regulated dc/dc converter  
outputs, a precision 3.3 V reference and a 5 V LDO output).  
It requires minimum external components and is capable of  
achieving conversion efficiencies approaching 95 %.  
Along with the SMBUS interface, the Si9135 provides  
programmable output selection capability.  
Up to 95 % Efficiency  
3 % Total Regulation (Each Controller)  
5.5 V to 30 V Input Voltage Range  
3.3 V, 5 V, and 12 V Outputs  
200 kHz/300 kHz Low-Noise Frequency Operation  
Precision 3.3 V Reference Output  
30 mA Linear Regulator Output  
SMBUS Interface  
High Efficiency Pulse Skipping Mode Operation at  
Light Load  
The Si9135 is available in both standard and lead (Pb)-free  
28-pin SSOP packages and specified to operate over the  
extended commercial (0 °C to 90 °C) temperature range.  
Only Three Inductors Required - No Transformer  
LITTLE FOOT® Optimized Output Drivers  
Internal Soft-Start  
Synchronizable  
Minimal External Control Components  
28-Pin SSOP Package  
FUNCTIONAL BLOCK DIAGRAM  
V
IN  
5 - V  
3.3 - V  
V
REF  
(+ 3.3 V)  
V
L
Linear  
Voltage  
(5.0 V)  
Regulator  
Reference  
3.3-V  
SMPS  
5-V  
SMPS  
+ 3.3 V  
+ 5 V  
+ 12 V  
12-V SMPS  
SMBUS Clock Line  
SMBUS Data Line  
On/Off Control  
Document Number: 70817  
S11-0975-Rev. D, 16-May-11  
www.vishay.com  
1
This document is subject to change without notice.  
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000  
Si9135  
Vishay Siliconix  
ABSOLUTE MAXIMUM RATINGS  
Parameter  
Limit  
- 0.3 to + 36  
2
Unit  
VIN to GND  
P
GND to GND  
V
VL to GND  
- 0.3 to + 6.5  
- 0.3 to + 36  
Continuous  
- 6.5 to 0.3  
- 0.3 V to (VL + 0.3)  
BST3, BST5, BSTFY to GND  
VL Short to GND  
LX3 to BST3; LX5 to BST5; LXFY to BST  
Inputs/Outputs to GND (SYNC, CS3, CS5, CSP, CSN)  
SDA, SCL  
- 0.3 to + 5.5  
V
- 0.3 V to (VL + 0.3)  
DL3, DL5, DLFY to PGND  
DH3 to LX3, DH5 to LX5, DHFY to LXFY  
- 0.3 V to (BSTX + 0.3)  
572  
Continuous Power Dissipation (TA = 90 °C)a  
28-Pin SSOPb  
mW  
°C  
Operating Temperature Range  
Storage Temperature Range  
0 to 90  
- 40 to 125  
300  
Lead Temperature (Soldering, 10 Sec.)  
Notes:  
a. Device Mounted with all leads soldered or welded to PC board.  
b. Derate 9.52 mW/°C above 90 °C.  
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation  
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum  
rating conditions for extended periods may affect device reliability.  
SPECIFICATIONS  
Specific Test Conditions  
Limits  
V
IN = 15 V, IVL = IREF = 0 mA  
Parameter  
Unit  
Min.a  
Typ.b Max.a  
TA = 0 °C to 90 °C, All Converters ON  
3.3 V Buck Controller  
Total Regulation (Line, Load, and Temperature)  
Line Regulation  
VIN = 6 to 30, 0 < VCS3 - VFB3 < 90 mV  
3.23  
3.33  
3.43  
0.5  
V
V
IN = 6 to 30 V  
0 < VCS3 - VFB3 < 90 mV  
CS3 - VFB3  
%
Load Regulation  
0.5  
V
Current Limit  
90  
125  
50  
160  
mV  
kHz  
°
Bandwidth  
L = 10 µH, C = 330 µF  
RSENSE = 20 m  
Phase Margin  
65  
5 V Buck Controller  
Total Regulation (Line, Load, and Temperature)  
Line Regulation  
VIN = 6 to 30, 0 < VCS5 - VFB5 < 90 mV  
4.88  
90  
5.03  
5.18  
0.5  
V
V
IN = 6 to 30 V  
0 < VCS5 - VFB5 < 90 mV  
CS5 - VFB5  
%
Load Regulation  
0.5  
V
Current Limit  
125  
50  
160  
mV  
kHz  
°
Bandwidth  
L = 10 µH, C = 330 µF  
RSENSE = 20 m  
Phase Margin  
60  
12 V Flyback Controller  
Total Regulation (Line, Load, and Temperature)  
Line Regulation  
VIN = 6 to 30, 0 < VCSP - VCSN < 300 mV  
11.4  
330  
12.0  
12.6  
0.5  
V
V
IN = 6 to 30 V  
0 < VCSP - VFBN < 300 mV  
CSP - VCSN  
%
Load Regulation  
0.5  
V
Current Limit  
410  
10  
510  
mV  
kHz  
°
Bandwidth  
L = 10 µH, C = 100 µF  
RSENSE = 100 m, Ccomp = 120 pF  
Phase Margin  
65  
www.vishay.com  
2
Document Number: 70817  
S11-0975-Rev. D, 16-May-11  
This document is subject to change without notice.  
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000  
Si9135  
Vishay Siliconix  
SPECIFICATIONS  
Specific Test Conditions  
Limits  
V
IN = 15 V, IVL = IREF = 0 mA  
Parameter  
Unit  
Min.a  
Typ.b Max.a  
TA = 0 °C to 90 °C, All Converters ON  
Internal Regulator  
VL Output  
All Converters OFF, VIN > 5.5 V, 0 < IL < 30 mA  
4.7  
3.6  
5.5  
V
VL Fault Lockout Voltage  
4.2  
VL Fault Lockout Hysteresis  
VL /FB5 Switchover Voltage  
VL /FB5 Switchover Hysteresis  
75  
75  
mV  
V
4.2  
4.7  
mV  
Reference  
REF Output  
No External Load  
0 to 1 mA  
3.24  
3.30  
30  
3.36  
75  
V
REF Load Regulation  
Supply Current  
Supply Current - Shutdown  
Supply Current - Operation  
Oscillator  
mV  
All Converters OFF, No Load  
35  
60  
µA  
All Converters ON, No Load, FOCS = 200 kHz  
1100 1800  
SYNC tied to REF  
270  
180  
200  
200  
300  
200  
330  
220  
Oscillator Frequency  
kHz  
SYNC tied to GND or VL  
SYNC High-Pulse Width  
SYNC Low-Pulse Width  
SYNC Rise/Fall Range  
SYNC VIL  
nsec  
200  
0.8  
V
kHz  
%
SYNC VIH  
VL - 0.5  
250  
92  
Oscillator SYNC Range  
400  
SYNC tied to GND or VL  
SYNC tied to REF  
95  
92  
Maximum Duty Cycle  
89  
Outputs  
Gate Driver Sink/Source Current (Buck)  
Gate Driver On-Resistance (Buck)  
Gate Driver Sink/Source Current (Flyback)  
Gate Driver On-Resistance (Flyback)  
SCL, SDA  
DL3, DH3, DL5, DH5 Forced to 2 V  
High or Low  
1
2
A
A
7
DHFY, DLFY Forced to 2 V  
High or Low  
0.2  
15  
0.6  
VIL  
V
VIH  
1.4  
Notes:  
a. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum.  
b. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.  
Document Number: 70817  
S11-0975-Rev. D, 16-May-11  
www.vishay.com  
3
This document is subject to change without notice.  
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000  
Si9135  
Vishay Siliconix  
PIN CONFIGURATION  
SSOP-28  
CS  
FB  
3
1
2
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
3
FBFY  
BSTFY  
DHFY  
LXFY  
DLFY  
CSP  
DH  
LX  
3
ORDERING INFORMATION  
3
3
Lead (Pb)-free Temperature  
VOUT  
Part Number  
BST  
4
3
Part Number  
Range  
DL  
V
Si9135LG  
5
3
0 to 90 °C  
3.3 V, 5 V, 12 V  
Si9135LG-T1 Si9135LG-T1-E3  
6
IN  
L
V
7
CSN  
FB  
5
8
GND  
PGND  
9
COMP  
REF  
DL  
5
10  
11  
12  
12  
14  
BST  
5
SYNC  
SCL  
LX  
5
DH  
5
SDA  
CS  
5
Top View  
PIN DESCRIPTION  
Pin Number  
Symbol  
Description  
1
CS3  
Current sense input for 3.3 V buck.  
Feedback for flyback.  
2
FBFY  
BSTFY  
DHFY  
LXFY  
DLFY  
CSP  
CSN  
GND  
COMP  
REF  
SYNC  
SCL  
3
Boost capacitor connection for flyback converter.  
Gate-drive output for flyback high-side MOSFET.  
Inductor connection for flyback converter.  
Gate-drive output for flyback low-side MOSFET.  
Current sense positive input for flyback converter.  
Current sense negative input for flyback converter.  
Analog ground.  
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
Flyback compensation connection, if required.  
3.3 V internal reference.  
Oscillator synchronization inputs.  
SMBUS clock line.  
SDA  
CS5  
SMBUS data line.  
Current sense input for 5 V buck controller.  
Inductor connection for buck 5 V.  
DH5  
LX5  
Gate-drive output for 5 V buck high-side MOSFET.  
Boost capacitor connection for 5 V buck converter.  
Gate-drive output for 5 V buck low-side MOSFET.  
Power ground.  
BST5  
DL5  
PGND  
FB5  
Feedback for 5 V buck.  
VL  
5 V logic supply voltage for internal circuitry.  
Input voltage  
VIN  
DL3  
Gate-drive output for 3.3 V buck low-side MOSFET.  
Boost capacitor connection for 3.3 V buck converter.  
Inductor connection for 3.3 V buck low-side MOSFET.  
Gate-drive output for 3.3 V buck high-side MOSFET.  
Feedback for 3.3 V buck.  
BST3  
LX3  
DH3  
FB3  
www.vishay.com  
4
Document Number: 70817  
S11-0975-Rev. D, 16-May-11  
This document is subject to change without notice.  
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000  
Si9135  
Vishay Siliconix  
TYPICAL CHARACTERISTICS (25 °C unless otherwise noted)  
100  
100  
90  
Frequency = 200 kHz  
= 6 V  
Frequency = 200 kHz  
90  
V
IN  
V
IN  
= 6 V  
15 V  
15 V  
80  
70  
60  
80  
70  
60  
30 V  
30 V  
5 V On, 12 V Off  
3.3 V Off, 12 V Off  
50  
50  
0.001  
0.01  
0.1  
1
10  
0.001  
0.01  
0.1  
Current (A)  
1
10  
Current (A)  
Efficiency vs. 3.3 V Output Current  
Efficiency vs. 5.0 V Output Current  
85  
80  
V
IN  
= 15 V  
Frequency = 200 kHz  
6 V  
75  
70  
65  
30 V  
5 V On, 3.3 V Off  
60  
55  
0.001  
0.01  
Current (A)  
0.1  
1
Efficiency vs. 12 V Output Current  
Document Number: 70817  
S11-0975-Rev. D, 16-May-11  
www.vishay.com  
5
This document is subject to change without notice.  
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000  
Si9135  
Vishay Siliconix  
TYPICAL WAVEFORMS  
Ch1: V  
OUT  
Ch1: V  
OUT  
Ch2: Load  
Current (1 A/div)  
Ch2: Load  
Current (1 A/div)  
PWM Unloading  
PWM Loading  
5 V Converter (VIN = 10 V)  
5 V Converter (VIN = 10 V)  
Ch1: V  
OUT  
Ch1: V  
OUT  
Ch2: Load  
Current (1 A/div)  
Ch2: Load  
Current (1 A/div)  
PWM Õ PSM  
PSM Õ PWM  
5 V Converter (VIN = 10 V)  
5 V Converter (VIN = 10 V)  
Ch2: V  
OUT  
Ch2: V  
OUT  
Ch3: Inductor  
Node  
(L X5)  
Ch3: Inductor  
Node  
(L X5)  
Ch4: Inductor  
Current (1 A/div)  
Ch4: Inductor  
Current (1 A/div)  
PWM Operation  
PSM Operation  
5 V Converter (VIN = 10 V)  
5 V Converter (VIN = 10 V)  
www.vishay.com  
6
Document Number: 70817  
S11-0975-Rev. D, 16-May-11  
This document is subject to change without notice.  
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000  
Si9135  
Vishay Siliconix  
TYPICAL WAVEFORMS  
Ch1: V  
OUT  
UT  
Ch2: Load  
Current (1 A/div)  
ad  
(1 A/div)  
PWM, Unloading  
3 V Converter (VIN = 10 V)  
PWM, Loading  
3 V Converter (VIN = 10 V)  
ad  
(1 A/div)  
ad  
(1 A/div)  
PWM Õ PSM  
PSM Õ PWM  
3 V Converter (VIN = 10 V)  
3 V Converter (VIN = 10 V)  
3.3 V Output  
5 V Output  
Ch1: V  
OUT  
12 V Output  
Inductor Current,  
5 V Converter  
(2 A/div)  
Ch4: Load  
Current  
(100 mA/div)  
250 - mA Transient  
Start-Up  
12 V Converter (VIN = 10 V)  
Document Number: 70817  
S11-0975-Rev. D, 16-May-11  
www.vishay.com  
7
This document is subject to change without notice.  
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000  
Si9135  
Vishay Siliconix  
STANDARD APPLICATION CIRCUIT  
V
IN  
+ 5 V up to 30 mA  
C7  
D1  
33 µF  
CMPD2836  
D2  
CMPD2836  
C5  
4.7 µF  
C4  
V
IN  
V
L
33 µF  
C1  
0.1 µF  
C2  
0.1 µF  
BST  
BST  
5
3
Q2  
Si4416DY  
L1, 10 µH  
R
7
DH5  
LX  
R
cs1  
Q1  
Si4416DY  
0.02 Ω  
+ 5 V  
DH3  
LX  
5
C3  
330 µF  
3
Q4  
Si4812DY  
R
cs2  
0.02 Ω  
1
L2  
10 µH  
R
DL5  
+ 3.3 V  
Q3  
Si4812DY  
DL3  
CS  
FB  
5
C6  
330 µF  
5
D3  
CMPD2836  
C8  
CS  
3
C9  
4.7 µF  
BSTFY  
0.1 µF  
Q5  
DHFY  
LXFY  
Si2304DS  
+ 12 V 0 to  
250 mA  
L3, 10 µH  
D4, D1FS4  
C10  
100 µF  
D5, D1FS4  
FB3  
SCL  
Q6  
Si2304DS  
DLFY  
CSP  
SMBUS Clock Line  
R
6
cs3  
SMBUS Data Line  
OSC SYNC  
SDA  
R
SYNC  
CSN  
FBFY  
+ 3.3 V up  
to 1 mA  
REF  
COMP  
PGND  
GND  
C11  
1 µF  
C12  
120 pF  
Figure 1.  
www.vishay.com  
8
Document Number: 70817  
S11-0975-Rev. D, 16-May-11  
This document is subject to change without notice.  
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000  
Si9135  
Vishay Siliconix  
SMBUS Specification  
SMBus: The System Management Bus is a two-wire  
interface through which simple power related chips can  
communicate with the rest of the system. It uses I2C as its  
backbone. Both SDA and SCL are bidirectional lines,  
connected to a positive voltage via a pull-up resistor. When  
the bus is free, both lines are high. The output stages of  
devices connected to the bus must have an open drain or  
open collector in order to perform the wired AND function.  
Data on the SMBus can be transferred at a clock rate up to  
100 kHz. Si9135 is a slave with SMBus address of 0110000.  
SMBUS TRUTH TABLE  
State  
D7  
0
D6  
0
D5  
0
D4  
X
D3  
X
D2  
X
D1  
X
D0  
X
Shutdown  
Buck3 On  
1
0
0
X
X
X
X
X
Buck5 On  
0
1
0
X
X
X
X
X
Flyback On  
Buck3, Buck5 On  
Buck3, Flyback On  
Buck5, Flyback on  
All On  
0
0
1
X
X
X
X
X
1
1
0
X
X
X
X
X
1
0
1
X
X
X
X
X
0
1
1
X
X
X
X
X
1
1
1
X
X
X
X
X
Notes:  
1. Positive logic level is used.  
2. X: don’t care.  
SMBUS ELECTRICAL SPECIFICATION (Test Conditions: V+ = 5.5 V to 30 V, TA = 0 °C)  
Symbol  
Parameter  
Min  
- 0.5  
1.4  
Max  
0.6  
5.5  
0.4  
1
Units  
VIL  
Data, Clock Input Low Voltage  
Data, Clock Input High Voltage  
Data, Clock Output Low Voltage  
Input Leakage  
VIH  
V
VOL  
ILEAK  
µA  
SMBUS AC SPECIFICATIONS  
Symbol  
Parameter  
SMBus Operation Frequency  
Bus free time between Stop and Start  
Data Hold Time  
Min  
10  
Max  
Units  
kHz  
µs  
FSMB  
TBUF  
THD  
TSU  
100  
4.7  
300  
250  
4.7  
4.0  
ns  
µs  
ns  
Data Setup Time  
TLOW  
THIGH  
TF  
Clock Low Period  
Clock High Period  
50  
Clock/Data Fall Time  
Clock/Data Rise Time  
300  
TR  
1000  
Document Number: 70817  
S11-0975-Rev. D, 16-May-11  
www.vishay.com  
9
This document is subject to change without notice.  
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000  
Si9135  
Vishay Siliconix  
TIMING DIAGRAMS  
V
IN  
5.2 V  
3.8 V  
4 V  
V
L
5 V  
3.8 V  
5 V  
3.6 V  
3.3 V  
V
REF  
UVLO  
OSC  
SCL  
End of SMBus Transmission  
SDA  
SS/Enable  
D
H
BBM  
D
L
Figure 2. Start-Up Timing Sequence  
www.vishay.com  
10  
Document Number: 70817  
S11-0975-Rev. D, 16-May-11  
This document is subject to change without notice.  
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000  
Si9135  
Vishay Siliconix  
DETAILED FUNCTIONAL BLOCK DIAGRAMS  
FB  
5
CS_  
FB_  
+
1X  
R
R
X
Internal voltage  
divider is only  
used on 5 V  
output.  
Error  
Amplifier  
Y
SMBUS Control  
BST_  
PWMCMP  
+
REF  
+
DH  
DH  
Logic  
Control  
Pulse  
Skipping  
Control  
LX_  
SLC  
BBM  
DL  
20 mV  
V
L
Current  
Limit  
DL  
V
Soft-Start  
SYNC  
Rectifier Control  
t
Figure 3. Buck Block Diagram  
FBFY  
R1  
SMBUS Control  
R2  
Error  
Amplifier  
PWM  
Comparator  
BSTY  
+
Logic  
Control  
DH  
REF  
+
LXFY  
COMP  
DHFY  
DLFY  
C/S  
Amplifier  
Pulse  
Skipping  
Control  
DL  
ICSP  
ICSN  
+
+
100 mV  
Current Limit  
V
Soft-Start  
t
Figure 4. PWM Flyback Block Diagram  
Document Number: 70817  
S11-0975-Rev. D, 16-May-11  
www.vishay.com  
11  
This document is subject to change without notice.  
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000  
Si9135  
Vishay Siliconix  
5 V  
Linear  
Regulator  
V
IN  
FB  
5
CS  
5
5 V  
Buck  
BST  
5
Controller  
DH5  
LX  
V
L
4.5 V  
5
4 V  
DL5  
SMBUS  
Interface  
Controller  
FB  
3
3.3 V  
Reference  
CS  
3
3.3 V  
Buck  
Controller  
BST  
3
2.4 V  
DH3  
300 kHz/  
200 kHz  
Oscillator  
LX  
3
DL3  
FYBFY  
ICSP  
12 V  
Flyback  
Controller  
ICSN  
BSTFY  
DHFY  
LXFY  
DLFY  
Figure 5. Complete Si9135 Block Diagram  
DESCRIPTION OF OPERATION  
Start-up Sequence  
currents being drawn from the input during startup. The soft-  
start is controlled by initial default start up sequence or  
incoming SMBus command.  
Si9135 is normally controlled by its SMBus interface after VIN  
is applied. Initially, if there is no incoming SMBus control  
command, it comes up in its default power on sequence, first  
the LDO 5 V will come up within its tolerance, and then the  
precision 3.3 V reference will come up. Immediately  
afterwards, the oscillator will begin and 3.3 V BUCK  
converter will turn on and then 5 V BUCK converter and at  
last 12 V FLYBACK converter. If Si9135 receives any SMBus  
controlling command after LDO 5 V is established, the  
designated converters will be allowed to turn on or off  
independently depending on the command received. In the  
event of all three converters are turned off, the oscillator will  
be turned off, the total system would only draw 35 µA supply  
current.  
Si9135 converters a 5.5 V to 30 V input voltage to five  
outputs, two BUCK (step-down) high current, PWM, switch-  
mode supplies, one at 3.3 V and one at 5 V, one FLYBACK  
12 V PWM switch-mode supply, one precision 3.3 V  
reference and one 5 V Low Drop Out linear regulator output.  
Switch-mode supply output current capabilities depend on  
external components (can exceed 10 A). With typical  
application shown on the application diagram, the two BUCK  
converters deliver 4 A and the FLYBACK converters deliver  
0.25 A. The recommended load current for precision 3.3 V  
reference output is less than 1 mA, the recommended load  
current for 5 V LDO output current is less than 30 mA. In  
order to maximize the power efficiency, when the 5 V BUCK  
converter supply is above 4.5 V, the BUCK converter’s  
output is internal connected to LDO output.  
Each converter can soft-start separately. The integrated  
internal soft-start circuitry for each converter gradually  
increases the inductor maximum peak current during soft-  
start period (approximately 4 msec), preventing excessive  
www.vishay.com  
12  
Document Number: 70817  
S11-0975-Rev. D, 16-May-11  
This document is subject to change without notice.  
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000  
Si9135  
Vishay Siliconix  
DESCRIPTION OF OPERATION (CONT’D)  
Buck Converter Operation  
Current Limit: Buck Converters  
The 3.3 V and 5 V buck converters are both current-mode  
PWM and PSM (during light load operation) regulators using  
high-side bootstrap N-Channel and low-side N-Channel  
MOSFETs. At light load conditions, the converters switch at  
a lower frequency than the clock frequency, seen like some  
clock pulses between the actual switching are skipped, this  
operating condition is defined as pulse-skipping. The  
operation of the converter(s) switching at clock frequency is  
defined as normal operation.  
When the buck converter inductor current is too high, the  
voltage across pin CS3(5) and pin FB3(5) exceeds  
approximately 120 mV, the high-side MOSFET would be  
turned off instantaneously regardless of the input, or output  
condition. The Si9135 features clock cycle by clock cycle  
current limiting capability.  
Flyback Converter Operation  
Designed mainly for PCMCIA or EEPROM programming, the  
Si9135 has a 12 V output non-isolated buck boost converter,  
called for brevity a flyback. It consists of two N-Channel  
MOSFET switches that are turned on and off in phase, and  
two diodes. Similar to the buck converter, during the light  
load conditions, the flyback converter will switch at a  
frequency lower than the internal clock frequency, which can  
be defined as pulse skipping mode (PSM); otherwise, it is  
operating in normal PWM mode.  
Normal Operation: Buck Converters  
In normal operation, the buck converter high-side MOSFET  
is turned on with a delay (known as break-before-make time  
- tBBM), after the rising edge of the clock. After a certain on  
time, the high-side MOSFET is turned off and then after a  
delay (tBBM), the low-side MOSFET is turned on until the next  
rising edge of the clock, or the inductor current reaches zero.  
The tBBM (approximately 25 ns to 60 ns), has been optimized  
to guarantee the efficiency is not adversely affected at the  
high switching frequency and a specified minimum to  
account for variations of possible MOSFET gate  
capacitances.  
Normal Operation: Flyback Converter  
In normal operation mode, the two MOSFETs are turned on  
at the rising edge of the clock, and then turned off. The on  
time is controlled internally to provide excellent load, line,  
and temperature regulation. The flyback converter has load,  
line and temperature regulation well within 0.5 %.  
During the normal operation, the high-side MOSFET switch  
on-time is controlled internally to provide excellent line and  
load regulation over temperature. Both buck converters  
should have load, line, regulation to within 0.5 % tolerance.  
Pulse Skipping: Flyback Converter  
Pulse Skipping: Buck Converters  
Under the light load conditions, similar to the buck converter,  
the flyback converter will enter pulse skipping mode. The  
MOSFETs will be turned on until the inductor current  
increases to such a level that the voltage across the pin CSP  
and pin CSN reaches 100 mV, or the on time reaches the  
maximum duty cycle. After the MOSFETs are turned off, the  
inductor current will conduct through two diodes until it  
reaches zero. At this point, the flyback converter output will  
rise slightly above the regulation level, and the converter will  
stay idle for one or several clock cycle(s) until the output falls  
back slightly below the regulation level. The switching losses  
are reduced by skipping pulses and so the efficiency during  
light load is preserved.  
When the buck converter switching frequency is less than  
the internal clock frequency, its operation mode is defined as  
pulse skipping mode. During this mode, the high-side  
MOSFET is turned on until VCS - VFB reaches 20 mV, or the  
on time reaches its maximum duty ratio. After the high-side  
MOSFET is turned off, the low-side MOSFET is turned on  
after the tBBM delay, which will remain on until the inductor  
current reaches zero. The output voltage will rise slightly  
above the regulation voltage after this sequence, causing the  
controller to stay idle for the next one, or several clock cycles.  
When the output voltage falls slightly below the regulation  
level, the high-side MOSFET will be turned on again at the  
next clock cycle. With the converter remaining idle during  
some clock cycles, the switching losses are reduced in order  
to preserve conversion efficiency during the light output  
current condition.  
Current Limit: Flyback Converter  
Similar to the buck converter; when the voltage across pin  
CSP and pin CSN exceeds 410 mV typical, the two  
MOSFETs will be turned off regardless of the input and  
output conditions.  
Document Number: 70817  
S11-0975-Rev. D, 16-May-11  
www.vishay.com  
13  
This document is subject to change without notice.  
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000  
Si9135  
Vishay Siliconix  
DESCRIPTION OF OPERATION (CONT’D)  
SMBus Commands  
ON/OFF Function  
individually or as a group commanded on or off using a code  
word on the SMBus, as detailed in the SMBus Truth Table.  
The command sequence is:  
Logic-low shuts off the appropriate section by disabling the  
gate drive stage. High-side and low-side gate drivers are  
turned off when ON/OFF pins are logic-low. Logic-high  
enables the DH and DL pins.  
1. Receive a start bit, which is a falling edge on the SDA line  
while the SCL line is high.  
2. Receive a one-byte address, which for Si9135 is  
01100000.  
Stability  
3. Send an acknowledge bit.  
4. Receive a one-byte command.  
5. Send an acknowledge bit.  
Buck Converters:  
In order to simplify designs, the Si9135 requires no specified  
external components except load capacitors for stability  
control. Meanwhile, it achieves excellent regulation and  
efficiency. The converters are current mode control, with a  
bandwidth substantially higher than the LC tank dominant  
pole frequency of the output filter. To ensure stability, the  
minimum capacitance and maximum ESR values are:  
6. Receive a stop bit, which is a rising edge on the SDA line  
while the SCL line is high.  
This is a total of 20 bits, which at the maximum clock  
frequency of 100 kHz translates into 200 µsec before any  
change in the status of Si9135 ban be accomplished.  
If Si9135 receives a command to turn on (respectively, off) a  
converter that is already on (respectively, off) it shall not  
falsely command the converter off (respectively, on).  
VREF  
V
OUT x Rcs  
VREF  
CLOAD  
ESR  
Si9135 must be able to receive a stop command at any time  
during a command sequence. If Si9135 receives a stop  
command during a command sequence, it must not change  
the state of any converter, and must be ready to receive the  
next command sequence.  
2π x VOUT x RCS x BW  
Where VREF = 3.3 V, VOUT is the output voltage (5 V or  
3.3 V), Rcs is the current sensing resistor in ohms and BW =  
50 khz.  
With the components specified in the application circuit  
(L = 10 µH, RCS = 0.02 , COUT = 330 µF, ESR  
approximately 0.1 , the converter should have a bandwidth  
at approximately 50 kHz, with minimum phase margin of 65°,  
and dc gain above 50 dB.  
Grounding  
There are two separate grounds on the Si9135, analog  
signal ground (GND) and power ground (PGND). The  
purpose of two separate grounds is to prevent the high  
currents on the power devices (both external and internal)  
from interfering with the analog signals. The internal  
components of Si9135 have their grounds tied (internally)  
together. These two grounds are then tied together  
(externally) at a single point, to ensure Si9135 noise  
immunity.  
Other Outputs  
The Si9135 also provides a 3.3 V reference which can be  
external loaded up to 1 mA, as well as, a 5 V LDO output  
which can be loaded 30 mA, or even more depending on the  
system application. When the 5 V buck converter is turned  
on, the 5 V LDO output is shorted with the 5 V buck converter  
output, so its loading capability is substantially increased.  
For stability, the 3.3 V reference output requires a 1 µF  
capacitor, and 5 V LDO output requires a 4.7 µF capacitor.  
This separation of grounds should be maintained in the  
external circuitry, with the power ground of all power devices  
being returned directly to the input capacitors, and the small  
signal ground being returned to the GND pin of Si9135.  
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Tech-  
nology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability  
data, see www.vishay.com/ppg?70817.  
www.vishay.com  
14  
Document Number: 70817  
S11-0975-Rev. D, 16-May-11  
This document is subject to change without notice.  
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000  
Package Information  
Vishay Siliconix  
SSOP: 28-LEAD (5.3 MM) (POWER IC ONLY)  
28  
15  
B−  
E
1
E
1
14  
A−  
D
e
GAUGE PLANE  
R
c
A
2
A
1
A
C−  
L
SEATING PLANE  
SEATING PLANE  
0.076  
C
L
1
b
S
M
0.12  
A
B
C
MILLIMETERS  
Dim  
A
A1  
A2  
b
c
D
E
E1  
e
Min  
Nom  
1.88  
Max  
1.99  
0.21  
1.78  
0.38  
0.20  
10.33  
8.00  
5.40  
1.73  
0.05  
1.68  
0.25  
0.09  
10.07  
7.60  
5.20  
0.13  
1.75  
0.30  
0.15  
10.20  
7.80  
5.30  
0.65 BSC  
0.75  
0.63  
0.95  
L
1.25 BSC  
0.15  
L1  
R
0.09  
− − −  
0_  
4_  
8_  
ECN: S-40080—Rev. A, 02-Feb-04  
DWG: 5915  
Document Number: 72810  
28-Jan-04  
www.vishay.com  
1
Legal Disclaimer Notice  
Vishay  
Disclaimer  
ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE  
RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE.  
Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively,  
“Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other  
disclosure relating to any product.  
Vishay makes no warranty, representation or guarantee regarding the suitability of the products for any particular purpose or  
the continuing production of any product. To the maximum extent permitted by applicable law, Vishay disclaims (i) any and all  
liability arising out of the application or use of any product, (ii) any and all liability, including without limitation special,  
consequential or incidental damages, and (iii) any and all implied warranties, including warranties of fitness for particular  
purpose, non-infringement and merchantability.  
Statements regarding the suitability of products for certain types of applications are based on Vishay’s knowledge of typical  
requirements that are often placed on Vishay products in generic applications. Such statements are not binding statements  
about the suitability of products for a particular application. It is the customer’s responsibility to validate that a particular  
product with the properties described in the product specification is suitable for use in a particular application. Parameters  
provided in datasheets and/or specifications may vary in different applications and performance may vary over time. All  
operating parameters, including typical parameters, must be validated for each customer application by the customer’s  
technical experts. Product specifications do not expand or otherwise modify Vishay’s terms and conditions of purchase,  
including but not limited to the warranty expressed therein.  
Except as expressly indicated in writing, Vishay products are not designed for use in medical, life-saving, or life-sustaining  
applications or for any other application in which the failure of the Vishay product could result in personal injury or death.  
Customers using or selling Vishay products not expressly indicated for use in such applications do so at their own risk and agree  
to fully indemnify and hold Vishay and its distributors harmless from and against any and all claims, liabilities, expenses and  
damages arising or resulting in connection with such use or sale, including attorneys fees, even if such claim alleges that Vishay  
or its distributor was negligent regarding the design or manufacture of the part. Please contact authorized Vishay personnel to  
obtain written terms and conditions regarding products designed for such applications.  
No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by  
any conduct of Vishay. Product names and markings noted herein may be trademarks of their respective owners.  
Document Number: 91000  
Revision: 11-Mar-11  
www.vishay.com  
1

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