ADD8608A8A-75BA [ADATA]
Double Data Rate SDRAM; 双倍数据速率SDRAM
| 型号： | ADD8608A8A-75BA |
| 厂家： | 
ADATA Technology Co., Ltd. |
| 描述： | Double Data Rate SDRAM |
| 文件： | 总9页 (文件大小：508K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
A-Data
ADD8608A8A
Revision History
Revision 1 ( Dec. 2001 )
1.Fister release.
Revision 2 ( Apr. 2002 )
1. Changed module current specification.
2. Add Performance range.
3. Changed AC Characteristics.
4. Changed typo size on module PCB in package dimensions.
Rev 2 April, 2002
1
A-Data
ADD8608A8A
8M x 8 Bit x 4 Banks
Double Data Rate SDRAM
General Description
Features
•2.5V for VDDQ power supply
•SSTL_2 interface
The ADD8608A8A are four-bank Double Data
Rate(DDR) Synchronous DRAMs organized as
8,392,608 words x 8 bits x 4 banks,
Synchronous design allows precise cycle control
with the use of system clock I/O transactions are
possible on every clock cycle.
•MRS Cycle with address key programs
-CAS Latency (2, 2.5)
-Burst Length (2,4 &8)
-Burst Type (sequential & Interleave)
•4 banks operation
•Differential clock input (CK, /CK) operation
•Double data rate interface
•Auto & Self refresh
Data outputs occur at both rising edges of CK and
/CK.
Range of operating frequencies, programmable
burst length and programmable latencies allow the
same device to be useful for a variety of high
bandwidth high performance memory system
applications
•8192 refresh cycle
•DQM for masking
•Package:66-pins 400 mil TSOP-Type II
Ordering Information.
Part No.
Frequency
Interface
SSTL_2
Package
ADD8608A8A-75BA
ADD8608A8A-75B
133Mhz(7.5ns/CL=2)
133Mhz(7.5ns/CL=2.5)
400mil 66pin TSOPII
Pin Assignment
VDD
V
S S
6
6
65
4
1
2
3
4
5
6
7
8
9
DQ
0
DDQ
DQ7
V
V
S SQ
6
6
3
6 2
NC
DQ1
NC
DQ6
V
S S Q
V
DDQ
1
6
NC
DQ2
NC
DQ5
60
5 9
5 8
V
DDQ
V
S SQ
NC
DQ3
NC
DQ4
5
1 0
1 1
1 2
1 3
1 4
1 5
1 6
7
5 6
5 5
54
V
S S Q
V
DDQ
NC
NC
V
NC
N C
3
5
5 2
5 1
5 0
4
4
4 7
4 6
4 5
44
DDQ
V
S S Q
NC
NC
DQS
N C
VR E F
VS S
1
7
VDD
1 8
1 9
2 0
9
8
NC1
NC
DM
CK
CK
CKE
NC
A12
A11
A9
21
22
23
24
25
26
27
28
29
3 0
3 1
3 2
3 3
WE
CAS
RAS
CS
NC
43
2
4
BS0
41
40
BS1
A10/AP
A0
A8
39
3 8
3 7
3 6
3 5
A7
A 6
A5
A1
A2
A3
A4
VS S
3
4
VDD
66-pin plastic TSOP II 400 mil
Rev 2 April, 2002
2
A-Data
ADD8608A8A
Pin Description
PIN
NAME
FUNCTION
CK, /CK System Clock
Differential clock input.
CKE
Clock Enable
Masks system clock to freeze operation from the next clock cycle. CKE
should be enabled at least on cycle prior new command. Disable input
buffers for power down in standby
/CS
Chip Select
Address
Disables or Enables device operation by masking or enabling all input
except CK, CKE and DQ
Row / Column address are multiplexed on the same pins.
Row address : A0~A12
A0~A12
Column address : A0~A9
BS0~BS1 Banks Select
DQ0~DQ7 Data
Selects bank to be activated during row address latch time.
Selects bank for read / write during column address latch time.
Data inputs / outputs are multiplexed on the same pins.
Latches row addresses on the positive edge of the CLK with /RAS low
Latches Column addresses on the positive edge of the CLK with /CAS
low
/RAS
/CAS
Row Address Strobe
Column Address Strobe
/WE
Write Enable
Enables write operation and row recharge.
VDD/VSS Power Supply/Ground
Power and Ground for the input buffers and the core logic.
VDDQ/VSSQ Data Output Power/Ground Power supply for output buffers.
VREF
NC
Reference Voltage
No Connection
Reference voltage for inputs for SSTL interface.
This pin is recommended to be left No Connection on the device.
Block Diagram
CK
Clock
Generator
Bank3
Bank2
CKE
Bank1
Address
Address
Buffer
&
Bank0
Mode
Register
Refresh
Counter
Amplifier
DQM
DQS
/CS
Column
Address
Buffer
&
Refresh
Counter
Column Decoder
/RAS
/CAS
Data Control Circuit
DQ0~DQ7
/WE
Rev 2 April, 2002
3
A-Data
ADD8608A8A
Absolute Maximum Ratings
Parameter
Symbol
VIN, Vout
VDD, VDDQ
TSTG
Value
-0.5 ~ 3.6
-1.0 ~ 3.6
-55 ~ +150
1.5
Unit
V
Voltage on any pin relative to Vss
Voltage on VDD supply relative to Vss
Storage temperature
V
℃
W
Power dissipation
PD
Short circuit current
IOUT
50
mA
Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATING are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC Operating Condition
Voltage referenced to Vss = 0V, TA = 0 to 70 ℃
Parameter
Supply voltage
Symbol
VDD
VDDQ
VIH
Min
2.3
Max
2.7
Unit
V
Note
Supply voltage
2.3
2.7
1
2
Input logic high voltage
Input logic low voltage
Differential Clock DC Input voltage
Input Differential CLK&/CLK voltage
Input leakage current
VREF+0.15
-0.3
VDDQ+0.3
VREF-0.15
VDDQ+0.3
VDDQ+0.6-
5
V
V
VIL
VICK
VID
-0.3
V
0.7
V
IIL
-5
uA
uA
V
3
4
Output leakage current
Reference Voltage
IOL
-5
5
VREF
VTT
0.49* VDDQ
VREF-0.04
0.51* VDDQ
VREF+0.04
Termination Voltage
5
Note : 1. VDDQ must not exceed the level of VDDQ.
2.VIL(min)=-0.9V with a pulse width ≦ 5ns .
3.Any input 0V ≦ VIN ≦ 3.6V, all other pins are not under test = 0V.
4.Dout is disabled, 0V ≦ VOUT ≦ 2.7V.
5. VREF is expected to be equal to 0.5* VDDQ of the transmitting device, and to track variations in the DC level of
the same. Peak to peak noise on VREF may not exceed ±2% of the DC value.
Rev 2 April, 2002
4
A-Data
ADD8608A8A
AC Operating Condition
Voltage referenced to Vss = 0V, TA = 0 to 70 ℃
Parameter
Symbol
VIH / VIL
Vtrip
Value
Unit
V
Note
AC input high / low level voltage
VREF+0.31/VREF-0.31
Input timing measurement reference level voltage
Input rise / fall time
1.4
1
V
TR / tF
Voutfef
CL
Ns
V
Output timing measurement reference level
Output load capacitance for access time measurement
1.4
50
pF
2
Note: 1. 3.15V ≦ VDD ≦ 3.6V is applied for VDD8608A4A5.
2. Output load to measure access times is equivalent to two TTL gates and one capacitor (30pF). For details,
refer to AC/DC output load circuit.
Capacitance
TA=25℃, f-=1Mhz
Parameter
Input capacitance
Pin
Symbol
Cl1
Min
2
Max
3.0
Unit
pF
CK, /CK
A0~A12,BS0,BS1,CKE,/CS,/RAS,
/CAS,/WE,DQM
Cl2
2
3.0
pF
Data input / output capacitance DQM
CI/O
4
5
pF
Output load circuit
V
tt=0.5*VDDQ
RT=50Ω
Output
Z0=50Ω
V
REF
=0.5*VDDQ
C
LOAD=30pF
Output Load Circuit (SSTL_2)
Rev 2 April, 2002
5
A-Data
ADD8608A8A
DC Characteristics II
Speed
Parameter
Symbol
IDD1
Test condition
Unit
mA
Note
1
-75BA/-75B
Burst length=2, One bank active
Trc=tRC(min),IOUT=0mA
Operating Current
110
Precharge standby
current in power
down mode
CKE≦VIL(max), tCK=min
IDD2P
3
mA
mA
mA
CKE≧VIH(min), /CS≧VIH(min),
Precharge standby
current in Non power IDD2N tCK= tCK min input signals are
40
30
down mode
changed one time during 2clks.
CKE≦VIL(max), tCK= tCK min
CKE≧VIH(min), /CS≧VIH(min),
Active standby
current in power
down mode
IDD3P
Active standby
current in Non power IDD3N tCK=min input signals are
65
mA
mA
down mode
changed one time during 2clks.
tCK≧tCK(min),IOUT=0 mA
All banks active
Burst mode operating
current
IDD4R
155
1
2
tRRC≧tRRC(min), All banks
active
Auto refresh current IDD5
190
3
mA
mA
CKE≦0.2V
Self refresh current IDD6
Note: 1. IDD1 and IDD4 depend on output loading and cycle rates. Specified values are measured with the output
open.
2. Min. of tRRC is shown at AC characteristics.
Rev 2 April, 2002
6
A-Data
ADD8608A8A
AC Characteristics
-75BA
-75B
Parameter
Symbol
tCK2.5
Unit
ns
Min
7.5
7.5
Max
12
Min
7.5
Max
12
System clock
Cycle time
/CAS Latency = 2.5
/CAS Latency = 2
tCK2
12
10
12
Clock high pulse width
tCHW
tCLW
tAC
0.45
0.45
-0.75
-0.75
0.75
65
0.55
0.45
0.45
0.55
CLK
CLK
ns
Clock low pulse width
0.55
0.55
Access time form CK to /CK
Data strobe edge to clock edge
0.75
-0.75
-0.75
0.75
65
0.75
tDQSCK
0.75
0.75
ns
Clock to first rising edge of DQS delay tDQSS
1.25
1.25
CLK
ns
/RAS cycle time
tRC
-
-
/RAS to /CAS delay
tRCD
tRAS
tRP
20
-
20
-
ns
/RAS active time
45
120K
45
120K
ns
/RAS precharge time
/RAS to /RAS bank active delay
/CAS to /CAS delay
20
-
20
-
ns
tRRD
tCCD
tDS
15
-
15
-
ns
1
-
1
-
CLK
ns
Data-in setup time (to DQS)
Data-in hold time (to DQS)
0.5
0.5
0.2
0.2
0.9
0.9
0.35
0.35
0
-
0.5
0.5
0.2
0.2
0.9
0.9
0.35
0.35
0
-
tDH
-
-
ns
DQS Falling Edge to CLK Setup Time tDSS
DQS Falling Edge Hold Time from CLK tDSH
-
-
CLK
CLK
ns
-
-
-
-
Input setup time
tIS
Input hold time
tIH
-
-
ns
DQS-in high level width
DQS-in low level width
tDSH
tDSL
-
-
CLK
CLK
ns
-
-
Clock to DQS write preamble setup time tWPRES
-
-
Write preamble
tWPST
tDQSQ
tMRD
0.4
06
0.5
0.4
06
0.5
CLK
ns
Data strobe edge to output data edge
Mode register set cycle time
DQS read preamble
15
15
tRPRE
0.9
1.1
0.9
1.1
CLK
Rev 2 April, 2002
7
A-Data
ADD8608A8A
Command Truth-Table
Command
Mode Register Set
No Operation
Bank Active
CKEn-1 CKEn
/CS
L
/RAS
/CAS
/WE
L
DM
X
ADDR A10/AP
BS
L
H
H
H
X
X
X
L
H
L
L
H
H
CA
CA
X
L
H
X
L
H
X
V
V
V
Read
L
H
X
L
H
L
H
X
V
Read with Auto Precharge
Write
H
L
H
H
X
X
L
L
H
L
L
L
L
X
X
V
X
V
X
Write with Auto Precharge
Precharge All Bank
H
H
H
Burst Stop
Auto Refresh
Entry
H
H
H
X
H
L
L
L
H
L
H
L
L
H
H
X
H
X
H
X
X
X
X
X
X
L
L
L
Self Refresh
Exit
X
H
L
X
H
X
H
X
X
H
X
H
X
L
H
L
X
X
H
L
Entry
H
Precharge
X
X
H
Power down
Exit
L
H
X
L
H
H
X
Enable
H
H
X
X
X
X
X
X
X
X
X
X
L
Data write
Disable
H
Rev 2 April, 2002
8
A-Data
ADD8608A8A
Package Information
34
66
1
33
MILLIMETER
NOM.
INCH
NOM.
SYMBOL
MIN.
MAX.
1.20
0.15
1.05
0.32
0.2
MIN.
MAX.
0.047
0.006
0.041
0.013
0.008
A
A1
A2
B
0.05
0.95
0.17
0.09
0.002
0.037
0.007
0.004
1.00
0.24
0.145
0.039
0.009
0.0006
c
D
HE
E
e
L
22.62 BSC
11.76
10.16
0.891 BSC
0.463
0.400
11.74
10.15
0.65 BSC
0.40
11.78
10.17
0.462
0.3996
0.026
0.016
0.464
0.4004
0.50
0.60
0.020
0.024
L1
S
0.80 REF
0.71 REF
0.031 REF
0.028 REF
0 °
-
8 °
0 °
-
8 °
θ
400mil 66pin TSOP II Package
Rev 2 April, 2002
9
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