AD53509JSW [ADI]
High Performance Driver/Comparator Active Load on a Single Chip;
| 型号： | AD53509JSW |
| 厂家： | 
ADI |
| 描述： | High Performance Driver/Comparator Active Load on a Single Chip |
| 文件： | 总12页 (文件大小：352K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
High Performance Driver/Comparator,
Active Load on a Single Chip
AD53509
FUNCTIONAL BLOCK DIAGRAM
FEATURES
250 MHz operation
V
V
V
V
V
V
V
V
CC
34
CC
CC
51
CC
52
EE
39
EE
40
EE EE
41 32
Driver/comparator and active load included
On-chip Schottky diode bridge
52-lead LQFP_EP package
39nF
CHDCPL
V
47
45
H
AD53509
V
T
DATA 37
VHDCPL
38
43
42
DATA
IOD
39nF
CLDCPL
46Ω
APPLICATIONS
DRIVER
V
OUT
IOD
VLDCPL
RLD 49
Automatic test equipment (ATE)
Semiconductor test systems
Board test systems
50
RLD
31
V
L
HCOMP
LEH
Instrumentation and characterization equipment
LEH
QH
GENERAL DESCRIPTION
QH
The AD53509 is a single chip that performs the pin electronics
functions of driver, comparator, and active load in ATE VLSI
and memory testers. In addition, a Schottky diode bridge for
the active load and a VCOM buffer are included internally.
COMPARATOR
QL
QL
LEL
LEL
LCOMP
The driver is a proprietary design that features three active
states: data high mode, data low mode, and term mode as well
as an inhibit state. The output voltage range is −2 V to +7 V to
accommodate a wide variety of test devices. The output leakage
is typically <250 nA over the signal range.
ACTIVE LOAD
VCOMI
IOLC
+1
VCOMS
V/I
IOLRTN
OUT_L
THERM
IOHRTN
The dual comparator, with an input range equal to the driver
output range, features built-in latches and ECL-compatible
outputs. The outputs are capable of driving 50 Ω signal lines
terminated to −2 V. Signal tracking capability is >5 V/ns.
INHL 36
35
INHL
1.0µA/K
14 NC
26 NC
IOHC
V/I
The active load can be set up to 40 mA load current with less
than a 10 μA linearity error through the set range. IOH, IOL, and
the buffered VCOM are independently adjustable. On-board
Schottky diodes provide high speed switching and low
capacitance.
9
33 44 46 48
PWRGND
2
5
8
HQGND2
HQGND
VCCO
NC = NO CONNECT
Figure 1.
Also included on the chip is an on-board temperature sensor
whose purpose is to give an indication of the surface temperature
of the DCL. This information can be used to measure θJC and θJA
or flag an alarm if proper cooling is lost. Output from the sensor
is a current sink that is proportional to absolute temperature.
The gain is trimmed to a nominal value of 1.0 μA/K. For example,
the output current can be sensed by using a 10 kꢀ resistor
connected from 10 V to the THERM pin. A voltage drop across
the resistor then develops that equals
10 K × 1 μA/K = 10 mV/K = 2.98 V (at room temperature)
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2008 Analog Devices, Inc. All rights reserved.
AD53509
TABLE OF CONTENTS
Features .............................................................................................. 1
Active Load Specifications ...........................................................6
Total Function Specifications ......................................................7
Absolute Maximum Ratings ............................................................8
ESD Caution...................................................................................8
Pin Configuration and Function Descriptions..............................9
Outline Dimensions....................................................................... 11
Ordering Guide .......................................................................... 11
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Driver Specifications.................................................................... 3
Comparator Specifications.......................................................... 5
REVISION HISTORY
3/08—Rev. A to Rev. B
Updated Format..................................................................Universal
Changes to Features and General Description ............................. 1
Changes to Table 1............................................................................ 3
Changes to Table 3............................................................................ 6
Changes to Table 9............................................................................ 8
Inserted Table 10............................................................................... 9
Updated Outline Dimensions....................................................... 11
Changes to Ordering Guide .......................................................... 11
12/00—Rev. 0 to Rev. A
Rev. B | Page 2 of 12
AD53509
SPECIFICATIONS
DRIVER SPECIFICATIONS
All specifications are at TJ = 85°C 5°C, VCC = 11 V 3ꢁ, VEE = −6 V = 3ꢁ, unless otherwise noted. All temperature coefficients are
measured at TJ = 75°C to 95°C.
Table 1.
Parameter
Min
Typ
Max
Unit
Test Conditions
DIFFERENTIAL INPUT CHARACTERISTICS,
DATA to DATA, IOD to IOD, RLD to RLD
Input Voltage
−2
+3
V
Differential Input Range
Bias Current
2
V
μA
All digital inputs within a 2 V range
VIN = −2 V, +3 V
−250
−50
+250
REFERENCE INPUTS
Bias Currents
+50
μA
VL, VH, VT = 5 V
OUTPUT CHARACTERISTICS
Logic High Range
Logic Low Range
Amplitude, VH and VL
Absolute Accuracy
VH Offset
−2
−2
0.1
+7
+6
9
V
V
V
Data = H, VH = −2 V to +7 V, VL = −2 V, VT = 0 V
Data = L, VL = −2 V to +6 V, VH = 7 V, VT = 0 V
VL = 0 V, VH = 0.1 V, VT = 0 V
VL = −2 V, VH = 7 V, VT = 0 V
−50
0.3 − 5
−50
+50
0.3 + 5
+50
mV
% of VH + mV
mV
Data = H, VH = 0 V, VL = −2 V, VT = −1 V
Data = H, VH = −1 V to +7 V, VL =−2 V, VT = −2 V
Data = L, VL = 0 V, VH = 5 V, VT = 3 V
VH Gain + Linearity Error
VL Offset
VL Gain + Linearity Error
Offset Temperature Coefficient
−0.3 − 5
+0.3 + 5
% of VL + mV
mV/°C
Data = L, VL = −2 V to +6 V, VH = 7 V, VT = 7 V
VL = −2 V, VH = 0 V, VT = −1 V (VH offset),
VL = 0 V, VH = 5 V, VT = 3 V (VL offset)
0.5
Output Resistance
VH = −2 V
VH = +7 V
VL = −2 V
VL = +6 V
VH = +3 V
Dynamic Current Limit
Static Current Limit
44
44
44
44
46
46
46
46
46
>100
48
48
48
48
Ω
Ω
Ω
Ω
Ω
mA
mA
VL = −2 V, VT = 0 V, IOUT = 0 mA, 1 mA, 30 mA
VL = −1 V, VT = 0 V, IOUT = 0 mA, −1 mA, −30 mA
VH = 6 V, VT = 0 V, IOUT = 0 mA, 1, mA 30 mA
VH = 7 V, VT = 0 V, IOUT = 0 mA, −1 mA, −30 mA
VL = 0 V, VT = 0 V, IOUT = −30 mA (trim point)
CBYP = 39 nF, VH = 6 V, VL = −2 V, VT = 0 V
Output to −2 V, VH = 7 V, VL = −1 V, VT = 0 V,
data = H and output to 7 V, VH = 6 V,
VL = −2 V, VT = 0 V, data = L
−85
+85
VT
Voltage Range
VT Offset
VT Gain + Linearity Error
Offset Temperature Coefficient
Output Resistance
−2
−50
−0.3 + 10
+7
+50
V
mV
Term mode, VT = −2 V to +7 V, VL = 0 V, VH = 3 V
Term mode, VT = 0 V, VL = 0 V, VH = 3 V
Term mode, VT = −2 V to +7 V, VL = 0 V, VH = 3 V
VT = 0 V, VL = 0 V, VH = 3 V
IOUT = 30 mA, 1.0 mA, VT = −2.0 V, VH = 3 V,
VL = 0 V, IOUT = −30 mA, −1.0 mA, VT = 7.0 V,
+0.3 + 10 % of VSET + mV
mV/°C
49
0.5
46
44
Ω
VH = 3 V, VL = 0 V, IOUT
= 30 mA, 1.0 mA,
VT = 0 V, VH = 3 V, VL = 0 V
DYNAMIC PERFORMANCE, VH AND VL
Propagation Delay Time
1.5
2
ns
Measured at 50%, VH = 400 mV,
VL = −400 mV, VT = 0 V
Measured at 50%, VH = 400 mV,
VL = −400 mV, VT = 0 V
Measured at 50%, VH = 400 mV,
VL = −400 mV, VT = 0 V
Propagation Delay Temperature
Coefficient
Delay Matching, Edge to Edge
ps/°C
ps
<100
Rev. B | Page 3 of 12
AD53509
Parameter
Min
Typ
Max
Unit
Test Conditions
Rise and Fall Times
1 V Swing
0.42
0.75
1.65
3.0
ns
ns
ns
ns
Measured 20% to 80%, VL = 0 V,
VH = 1 V, VT = 0 V
Measured 20% to 80%, VL = 0 V,
VH = 3 V, VT = 0 V
Measured 10% to 90%, VL = 0 V,
VH = 5 V, VT = 0 V
Measured 10% to 90%, VL = −2 V,
VH = 7 V, VT = 0 V
3 V Swing
5 V Swing
9 V Swing
Rise/Fall Time Temperature Coefficient
1 V Swing
3 V Swing
1
2
4
ps/°C
ps/°C
ps/°C
Measured 20% to 80%, VL = 0 V, VH = 1 V
Measured 20% to 80%, VL = 0 V, VH = 3 V
Measured 10% to 90%, VL = 0 V, VH = 5 V
5 V Swing
Overshoot and Preshoot
<3 + 50
% of Step + mV VL, VH = −0.1 V, +0.1 V, VL, VH = 0 V, +1.0 V
VL, VH = 0 V, 3.0 V, VL, VH = 0 V, 5.0 V
VL, VH = −2.0 V, +7.0 V
Settling Time
to 15 mV
to 4 mV
Delay Change vs. Pulse Width
<50
<10
50
ns
μs
ps
VL = 0 V, VH = 0.5 V, VT = −2 V
VL = 0 V, VH = 0.5 V, VT = −2 V
VL = 0 V, VH = 2 V, pulse width = 2.5 ns/7.5 ns,
30 ns/90 ns
Minimum Pulse Width
3 V Swing
1.4
2.0
250
ns
VL = 0 V, VH = 3 V, 90% (2.7 V) reached,
measure @ 50%
VL = 0 V, VH = 5 V, 90% (4.5 V) reached,
measure @ 50%
5 V Swing
ns
Toggle Rate
MHz
VL = 0 V, VH = 5 V, VDUT > 3.0 V p-p
DYNAMIC PERFORMANCE, INHIBIT
Delay Time, Active to Inhibit
Delay Time, Inhibit to Active
Delay Time Matching, Z
3.3
2.9
<2
ns
ns
ns
Measured at 50%, VH = 2 V, VL = −2 V, VT = 0 V
Measured at 50%, VH = 2 V, VL = −2 V, VT = 0 V
Z = delay time, active to inhibit − delay time,
inhibit to active (of worst two edges)
Input/Output Spike
Rise/Fall Time, Active to Inhibit
150
1.6
mV p-p
ns
VH = 0 V, VL = 0 V, VT = 0 V
VH = 2 V, VL = −2 V (measured 20%/80% of
1 V output)
Rise/Fall Time, Inhibit to Active
1.4
ns
VH = 2 V, VL = −2 V (measured 20%/80% of
1 V output)
DYNAMIC PERFORMANCE, VT
Delay Time, VH to VT and VL to VT
Delay Time, VT to VH and VT to VL
Overshoot and Preshoot
2.5
2.5
<3.0 + 75
ns
ns
Measured at 50%, VL = −1 V, VH = 1 V, VT = 0 V
Measured at 50%, VL = VH = 0.4 V, VT = −0.4 V
% of Step + mV VH/VL, VT = (0 V, −1 V), (0 V, −2.0 V), (0 V, +6.0 V)
VT Mode Rise Time
VT Mode Fall Time
PSRR, Drive, or Term Mode
2.2
2.2
35
ns
ns
dB
VL = −2 V, VH = 2 V, VT = 0 V, 20% to 80%
VL = −2 V, VH = 2 V, VT = 0 V, 20% to 80%
VS = VS 3%
Rev. B | Page 4 of 12
AD53509
COMPARATOR SPECIFICATIONS
All specifications are at TJ = 85°C 5°C. Outputs terminated in 150 ꢀ to GND, VCC = 11 V 3ꢁ, VEE = 6 V 3ꢁ, VCCO = 3.3 V,
unless otherwise specified. All temperatures coefficients are measured at TJ = 75°C to 95°C.
Table 2.
Parameter
Min
Typ
Max
Unit
Test Conditions
DC INPUT CHARACTERISTICS
Offset Voltage, VOS
−25
+25
mV
CMV = 0 V
Offset Voltage, Drift
HCOMP, LCOMP Bias Current
Voltage Range, VCM
Differential Voltage, VDIFF
Gain and Linearity
50
μV/°C CMV = 0 V
−50
−2
+50
+7.0
9.0
μA
V
VIN = 0 V
V
−0.05
+0.05
% FSR VIN = −2 V to +7 V (9 V FSR)
LATCH ENABLE INPUTS
Logic 1 Current, IIH
250
+3
μA
μA
V
LEA, LEA, LEB, LEB = 3 V
LEA, LEA, LEB, LEB = −2 V
Logic 0 Current, IIL
−250
−2
Logic Input Range
DIGITAL OUTPUTS
Logic 1 Voltage, VOH
Logic 0 Voltage, VOL
Slew Rate
VCCO − 0.98
0
V
Qx or Qx, 16.7 mA load
Qx or Qx, 10 mA load
VCCO − 1.5
8
V
1
V/ns
V
VCCO Range
SWITCHING PERFORMANCE
Propagation Delay
Input to Output
1.8
2
2
ns
ns
ps/°C
VIN = 2 V p-p
HCOMP = 1 V, LCOMP = 1 V
Latch Enable to Output
Propagation Delay Temperature Coefficient
Propagation Delay Change with Respect to
Slew Rate: 0.5 V/ns, 1.0 V/ns, 3.0 V/ns
Slew Rate: 5.0 V/ns
Amplitude: 1.0 V, 3.0 V, 5.0 V
Equivalent Input Rise Time
Pulse Width Linearity
Settling Time
< 100
< 350
< 200
450
< 200
25
ps
ps
ps
ps
ps
ns
VIN = 0 V to 5 V
VIN = 0 V to 5 V
VIN = 1.0 V/ns
VIN = 0 V to 3 V, 3 V/ns
VIN = 0 V to 3 V, 3 V/ns, PW = 3 ns to 8 ns
Settling to 8 mV, VIN = 1 V to 0 V
Latch Timing
Input Pulse Width
Setup Time
Hold Time
Hysteresis
1.68
1.0
1.1
6
ns
ns
ns
mV
Latch inputs programmed for hysteresis
Rev. B | Page 5 of 12
AD53509
ACTIVE LOAD SPECIFICATIONS
All specifications are at TJ = 85°C 5°C, VCC = 11 V 3ꢁ, VEE = −6 V = 3ꢁ, unless otherwise noted. All temperature coefficients are
measured at TJ = 75°C to 95°C.
Table 3.
Parameter
Min
Typ Max
Unit
Test Conditions
INPUT CHARACTERISTICS
INHL, INHL
Input Voltage
Bias Current
−2
−250
+3
+250
V
μA
IOHC = 1 V, IOLC = 1 V, VCOM = 2 V, OUT_L = 0 V
INHL, INHL = −2 V, +3 V
IOHC Current Program Range
IOH = 0 mA to −40 mA
IOLC Current Program Range
IOL = 0 mA to 40 mA
IOHC, IOLC Input Bias Current
IOLRTN, IOHRTN Range
VDUT Range
VDUT Range, IOH = 0 mA to −40 mA
VDUT Range, IOL = 0 mA to 40 mA
VCOMI Input Range
0
4
V
OUT_L = −0.7 V, +7 V
0
4
V
μA
V
V
V
OUT_L = −2 V, +5.7 V
−300
−2
−2
−0.7
−2
−2
+300
+7
+7
+7
+5.7
+7
IOLC = 0 V, 4.0 V and IOHC = 0 V, 4.0 V
IOL = 40 mA, IOH = −40 mA, OUT_L = −2 V, +7 V
IOL = 40 mA, IOH = −40 mA, OUT_L − VCOMI >1.3 V
OUT_L − VCOM > 1.3 V
VCOM − VDUT > 1.3 V
IOL = 40 mA, IOH = −40 mA
V
V
OUTPUT CHARACTERISTICS
Accuracy
Absolute Accuracy Error, Load Current
−0.3 − 100
+0.3 + 100 % ISET + μA IOL, IOH = 25 μA to 40 mA, VCOM = 0 V,
OUT_L = 2 V and IOL = 25 μA to 40 mA,
VCOM = 7 V, OUT_L = 5.7 V and IOH = 25 μA to
40 mA, VCOM = −2 V, OUT_L = −0.7 V
VCOM Buffer
Offset Error
Bias Current
Gain Error
−50
−10
−0.2
+50
+10
+0.2
mV
μA
%
IOL, IOH = 40 mA, VCOMI = 0 V, OUT_L = VCOM
VCOMI = 0 V, OUT_L = VCOM
IOL, IOH = 40 mA, VCOMI = −1 V to +6 V,
VOUT = VCOM
+1
Linearity Error
−10
+10
mV
IOL, IOH = 40 mA, VCOMI = −1 V to +6 V,
VOUT = VCOM
Output Current Temperature Coefficient
DYNAMIC PERFORMANCE
Propagation Delay
< 2
μA/°C
Measured at IOH, IOL = 200 μA
IOUT to Inhibit
Inhibit to IOUT
Propagation Delay Matching
Input/Output Spike
Settling Time to 15 mV
Settling Time to 4 mV
1.9
2.8
<1.8
240
<50
<10
ns
ns
ns
mV
ns
μs
VCOM = 2 V, IOL = 20 mA, IOH = −20 mA
VCOM = 2 V, IOL = 20 mA, IOH = 20 mA
VCOM = 0 V, IOL = 20 mA, IOH = −20 mA
IOL = 20 mA, IOH = −20 mA, 50 Ω load to 15 mV
IOL = 20 mA, IOH = −20 mA, 50 Ω load to 4 mV
Rev. B | Page 6 of 12
AD53509
TOTAL FUNCTION SPECIFICATIONS
All specifications are at TJ = 85°C 5°C, VCC = 11 V 3ꢁ, VEE = −6 V = 3ꢁ unless otherwise noted. All temperature coefficients are
measured at TJ = 75°C to 95°C.
Table 4.
Parameter1
Min
Typ Max
Unit
Test Conditions
OUTPUT CHARACTERISTICS
Output Leakage Current, VOUT = −1 V to +5 V
Output Leakage Current, VOUT = −2 V to +7 V
Output Capacitance
−250
−500
+250 nA
+500 μA
pF
8
Driver and load inhibited
POWER SUPPLIES
Total Supply Range
Positive Supply, VCC
Negative Supply, VEE
17
11
−6
V
V
V
Positive Supply Current
Negative Supply Current
VCCO Current
Total Power Dissipation
Temperature Sensor Gain Factor
280
290
mA
mA
mA
W
Driver = INH, ILOAD program = 40 mA, load = active
Driver = INH, ILOAD program = 40 mA, load = active
VCCO = 3.3 V, comparator output 150 Ω to GND
Driver = INH, ILOAD program = 40 mA, load = active
65
1
4.8
μA/K RLOAD = 10 kΩ, VSOURCE = 11 V
1 Connecting or shorting the decoupling pins to ground results in the destruction of the device.
Table 5. Driver Truth Table
DATA
IOD
RLD
DATA
IOD
1
1
0
0
RLD
X
X
0
1
Output State
0
1
X
X
1
0
X
X
0
0
1
1
X
X
1
0
VL
VH
Inhibit
VT
Table 6. Comparator Truth Table
Output States
LEH
LEL
QH
QH
QL
QL
VOUT
>LCOMP
LEH
LEL
>HCOMP
1
0
1
0
1
0
1
0
>HCOMP
<HCOMP
<HCOMP
X
<LCOMP
>LCOMP
<LCOMP
X
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
0
1
1
0
1
0
1
0
1
QH (t − 1)
QH (t − 1)
QL (t − 1)
QL (t − 1)
Table 7. Active Load Truth Table
Output States (Including Diode Bridge)
INHL
OUT_L
INHL
IOH
IOL
I(OUT_L)
<VCOM
0
1
V(IOHC) × 10 mA
V(IOLC) × 10 mA
IOL
>VCOM
X
0
1
1
0
V(IOHC) × 10 mA
0
V(IOLC) × 10 mA
0
IOH
0
Rev. B | Page 7 of 12
AD53509
ABSOLUTE MAXIMUM RATINGS
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Table 8.
Parameter
Rating
Power Supply Voltage
VCC to GND
VEE to GND
VCC to VEE
VCCO to GND
13 V
−8 V
20 V
10 V
0.4 V
PWRGND, HQGND, HQGND2
Inputs
Table 9. Package Thermal Resistance
DATA, DATA, IOD, IOD, RLD, RLD
DATA to DATA, IOD to IOD, RLD to RLD
LEL, LEL, LEH, LEH
LEL to LEL, LEH to LEH
INHL, INHL
−2 V to +5 V
3 V
Airflow (m/s)
θJA (°C/W)
0
1
2
42.7
37.8
36.4
−2 V to +5 V
3 V
−2 V to +5 V
3 V
For liquid-cooled applications, θJC = 3.0°C/W.
INHL to INHL
VH, VL, VT, VCOMI to GND
VH to VL
(VH − VT) and (VT − VL)
IOHC
−3 V to +8 V
10 V
10 V
ESD CAUTION
6 V
IOLC
6 V
HCOMP
LCOMP
−3 V to +8 V
−3 V to +8 V
10 V
HCOMP, LCOMP to VOUT
Outputs
VOUT Short-Circuit Duration
VOUT Inhibit Mode
VHDCPL
Indefinite1
−3 V to +8 V
Do not connect except
for capacitor to VCC
VLDCPL
Do not connect except
for capacitor to VEE
QH, QH, QL, QL Maximum IOUT
Continuous
50 mA
Surge
100 mA
THERM
IOHRTN, IOLRTN
VCOMS Short-Circuit Duration
Environmental
0 V to 13 V
−3.5 V to +8.5 V
3 sec1
Operating Temperature (Junction)
Storage Temperature Range
Lead Temperature (Soldering, 10 sec)2
175°C
−65°C to +150°C
260°C
1 Output short-circuit protection is guaranteed as long as proper heat sinking
is employed to ensure compliance with the operating temperature limits.
2 To ensure lead coplanarity ( 0.002 inches) and solderability, handling with
bare hands should be avoided and the device should be stored in
environments at 24°C 5°C (75°F 10°F) with relative humidity not to
exceed 65%.
Rev. B | Page 8 of 12
AD53509
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
52 51 50 49 48 47 46 45 44 43 42 41 40
39
38
37
V
1
V
EE
CC
VCCO
QL
PIN 1
IDENTIFIER
DATA
DATA
2
3
4
5
6
36 INHL
QL
VCCO
QH
35
INHL
34
V
AD53509
CC
33
32
31
30
29
28
27
PWRGND
HEAT SINK UP
(Not to Scale)
QH
7
8
V
VCCO
PWRGND
EE
V
L
IOLC
9
10
11
12
13
LEL
LEL
IOHC
HQGND
LEH
LEH
IOHRTN
14 15 16 17 18 19 20 21 22 23 24 25 26
NC = NO CONNECT
Figure 2. Pin Configuration
Table 10. Pin Function Descriptions
Pin No.
Mnemonic
Description
1, 34, 51, 52
VCC
Positive Power Supply.
2, 5, 8
3
VCCO
QL
Comparator Output Power Supply.
Comparator Low Output, Inverting.
Comparator Low Output, Noninverting.
Comparator High Output, Inverting.
Comparator High Output, Noninverting.
Ground.
Latch Enable Low Input, Inverting.
Latch Enable Low Input, Noninverting.
Latch Enable High Input, Inverting.
Latch Enable High Input, Noninverting.
Do not connect.
Temperature Sensor Output.
High Comparator Threshold.
Low Comparator Threshold.
Connect 39 nF compensation capacitor to VEE.
Ground.
4
6
QL
QH
7
QH
PWRGND
LEL
9, 33, 44, 46, 48
10
11
12
13
14, 26
15
16
17
18
19
20
21
22
23
24
25
27
28
29
30
LEL
LEH
LEH
NC
THERM
HCOMP
LCOMP
VHDCPL
HQGND2
VOUT
OUT_L
VLDCPL
IOLRTN
VCOMS
VCOMI
IOHRTN
HQGND
IOHC
IOLC
DUT Connection.
Active Load Output.
Connect 39 nF compensation capacitor to VEE.
Active Load Low Inhibit Control.
VCOM Buffer Sense Output.
VCOM Input Voltage.
Active Load High Inhibit Control.
Ground.
Active Load High Current Control Input.
Active Load Low Current Control Input.
Rev. B | Page 9 of 12
AD53509
Pin No.
Mnemonic
VL
Description
31
Low Driver Level.
32, 39, 40, 41
VEE
Negative Power Supply.
Inhibit Load Input, Inverting.
Inhibit Load Input, Noninverting.
Drive Data Input, Noninverting.
Drive Data Input, Inverting.
IO Data Input, Inverting.
IO Data Input, Noninverting.
Term Driver Level.
35
36
37
38
42
43
45
47
49
50
INHL
INHL
DATA
DATA
IOD
IOD
VT
VH
RLD
RLD
High Driver Level.
VT/Inhibit Selection Input, Noninverting.
VT/Inhibit Selection Input, Inverting.
Rev. B | Page 10 of 12
AD53509
OUTLINE DIMENSIONS
16.20
16.00 SQ
15.80
1.60
MAX
0.75
0.60
0.45
40
52
39
1
1.00 REF
PIN 1
SEATING
PLANE
6.00
BSC SQ
EXPOSED
PAD
14.20
14.00 SQ
13.80
1.45
1.40
1.35
0.20
0.09
TOP VIEW
(PINS DOWN)
7°
3.5°
0°
27
13
0.15
0.05
14
26
0.10
COPLANARITY
VIEW A
0.50
0.42
0.35
1.00
BSC
LEAD PITCH
VIEW A
ROTATED 90° CCW
COMPLIANT TO JEDEC STANDARDS MS-026-BEA-HU
Figure 3. 52-Lead Low Profile Quad Flat Package, Exposed Pad [LQFP_EP]
(SW-52-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model
AD53509JSW
AD53509JSWZ1
Temperature Range
0°C to 70°C
0°C to 70°C
Package Description
52-Lead LQFP_EP
52-Lead LQFP_EP
Package Option
Ordering Quantity
SW-52-1
SW-52-1
90
90
1 Z = RoHS Compliant Part.
Rev. B | Page 11 of 12
AD53509
NOTES
©2008 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D01539-0-3/08(B)
Rev. B | Page 12 of 12
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