AD5532HS [ADI]
32-Channel 14-Bit DAC with High-Speed 3-Wire Serial Interface; 32通道14位DAC，高速3线串行接口
| 型号： | AD5532HS |
| 厂家： | 
ADI |
| 描述： | 32-Channel 14-Bit DAC with High-Speed 3-Wire Serial Interface |
| 文件： | 总12页 (文件大小：180K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
32-Channel 14-Bit DAC with
High-Speed 3-Wire Serial Interface
a
AD5532HS*
GENERAL DESCRIPTION
FEATURES
High Integration: 32-Channel DAC in 12
؋
12 mm2 LFBGA Guaranteed Monotonic
The AD5532HS is a 32-channel voltage-output 14-bit DAC
with a high-speed serial interface. The selected DAC register is
written to via the 3-wire interface. The serial interface operates
at clock rates up to 30 MHz and is compatible with DSP and
microcontroller interface standards. The output voltage range is
0 V to 5 V or –2.5 V to +2.5 V and is determined by the offset
voltage at the OFFS_IN pin. It is restricted to a range from
VSS + 2 V to VDD – 2 V because of the headroom of the out-
put amplifier.
DSP-/Microcontroller-Compatible Serial Interface
Channel Update Rate 1.1 MHz
Output Impedance 0.5 ⍀
Selectable Output Voltage 0 V to 5 V or –2.5 V to +2.5 V
Asynchronous RESET Facility
Temperature Range –40؇C to +85؇C
APPLICATIONS
Optical Networks
Level Setting
The device is operated with AVCC = 5 V 5%, DVCC = 2.7 V
to 5.25 V, VSS = –4.75 V to –12 V and VDD = +4.75 V to +12 V
and requires a stable 2.5 V reference on REF_IN.
Instrumentation
Automatic Test Equipment
Industrial Control Systems
Data Acquisition
Low Cost I/O
PRODUCT HIGHLIGHTS
1. 32 14-bit DACs in one package, guaranteed monotonic.
2. The AD5532HS is available in a 74-ball LFBGA package
with a body size of 12 mm by 12 mm.
FUNCTIONAL BLOCK DIAGRAM
DV
AV
V
V
SS
REF_IN
OFFS_IN
CC
CC
DD
R
R
R
R
AD5532HS
R
V
0
OUT
DAC
DAC
DAC
DAC
RESET
DAC_GND
AGND
R
R
V
1
OUT
DGND
V
30
31
OUT
R
INTERFACE
CONTROL
LOGIC
V
OUT
SYNC
SCLK
D
IN
*Protected by U.S. Patent No. 5,969,657; other patents pending.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
www.analog.com
© Analog Devices, Inc., 2001
AD5532HS–SPECIFICATIONS
(VDD = +4.75 V to +12 V, VSS = –4.75 V to –12 V; AVCC = 4.75 V to 5.25 V; DVCC = 2.7 V to 5.25 V; AGND = DGND = DAC_GND = 0 V; REF_IN =
2.5 V; OFFS_IN = 0 V; All outputs unloaded. All specifications TMIN to TMAX unless otherwise noted.)
A Version2
Typ
Parameter1
Min
Max
Unit
Conditions/Comments
D
AC DC PERFORMANCE
Resolution
14
Bits
Integral Nonlinearity (INL)
Differential Nonlinearity (DNL)
Offset Error
–0.39
–1
–10
–1
0.1
0.5
+15
–0.3
+0.39
+1
+50
+0.5
% of FSR
LSB
mV
See TPC 7
Monotonic
See TPC 8
See TPC 9
Full-Scale Error
% of FSR
VOLTAGE REFERENCE REF_IN
Input Voltage Range3
Input Current
2.375
0
2.5
0.001
2.625
1
V
µA
ANALOG INPUT OFFS_IN
Input Voltage Range3, 4
Input Current
VDD – 1.5
1
V
µA
0.1
ANALOG OUTPUTS (VOUT0–VOUT31)
Output Temperature Coefficient3, 5
DC Output Impedance3
Output Range4
20
0.5
ppm/°C
Ω
OFFS_IN = 0
0 – 2REF_IN
V
OFFS_IN = REF_IN
–REF_IN to +REF_IN
V
Resistive Load3
5
kΩ
pF
mA
dB
dB
µV
Capacitive Load3
100
Short-Circuit Current3
DC Power-Supply Rejection Ratio3
7
–70
–70
120
VDD = +10 V 5%
VSS = –10 V 5%
DC Crosstalk3
DIGITAL INPUTS3
Input Current
Input Low Voltage
5
10
0.8
0.4
µA
V
V
V
V
DVCC = 5 V 5%
DVCC = 3 V 10%
DVCC = 5 V 5%
DVCC = 3 V 10%
Input High Voltage
2.4
2.0
Input Hysteresis (SCLK and SYNC Only)
Input Capacitance
200
mV
pF
10
POWER SUPPLY VOLTAGES
VDD
VSS
AVCC
DVCC
+4.75
–4.75
4.75
2.7
+12
–12
5.25
5.25
V
V
V
V
POWER SUPPLY CURRENTS6
IDD
ISS
AICC
DICC
9
9
6.5
0.1
12
12
10
0.5
mA
mA
mA
mA
All Channels Full Scale
All Channels Full Scale
VIH = DVCC and VIL = DGND
VDD = +5 V, VSS = –5 V
POWER DISSIPATION6
123
mW
NOTES
1See Terminology
2A Version: Industrial temperature range –40°C to +85°C; typical at 25°C.
3Guaranteed by design and characterization, not production tested.
4Output range is restricted from VSS + 2 V to VDD – 2 V.
5AD780 as reference for the AD5532HS.
6Outputs unloaded.
Specifications subject to change without notice.
–2–
REV. 0
AD5532HS
(VDD = +4.75 V to +12 V, VSS = –4.75 V to –12 V; AVCC = 4.75 V to 5.25 V; DVCC = 2.7 V to 5.25 V; AGND =
DGND = DAC_GND = 0 V; REF_IN = 2.5 V; All outputs unloaded. All specifications TMIN to TMAX unless otherwise noted.)
AC CHARACTERISTICS
Parameter1, 2
A Version3
Unit
Conditions/Comments
Output Voltage Settling Time4
Slew Rate
Digital-to-Analog Glitch Impulse
Digital Crosstalk
Analog Crosstalk
10
0.85
1
5
1
µs max
100 pF, 5 kΩ Load; Full-Scale Change
V/µs typ
nV-s typ
nV-s typ
nV-s typ
nV-s typ
nV/√Hz typ
1 LSB Change around Major Carry
Digital Feedthrough
Output Noise Spectral Density @ 1 kHz
0.2
170
NOTES
1See Terminology
2Guaranteed by design and characterization, not production tested
3B Version: Industrial temperature range –40°C to +85°C.
4Timed from the end of a write sequence.
Specifications subject to change without notice.
TIMING CHARACTERISTICS
(VDD = +4.75 V to +12 V, VSS = –4.75 V to –12 V; AVCC = 4.75 V to 5.25 V; DVCC = 2.7 V to 5.25 V;
AGND = DGND = DAC_GND = 0 V; All specifications TMIN to TMAX unless otherwise noted.)
Limit at TMIN, TMAX
(A Version)
Parameter1, 2, 3
Unit
Conditions/Comments
fUPDATE
fCLKIN
t1
t2
t3
t4
t5
t6
t7
1.1
30
13
13
15
50
10
10
5
MHz max
MHz max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
Channel Update Rate
SCLK Frequency
SCLK High Pulsewidth
SCLK Low Pulsewidth
SYNC Falling Edge to SCLK Falling Edge Setup Time
SYNC Low Time
SYNC High Time
DIN Setup Time
DIN Hold Time
t8
t9
280
20
19th SCLK Falling Edge to SYNC Falling Edge for Next Write
RESET Pulsewidth
NOTES
1See Timing Diagrams in Figure 1.
2Guaranteed by design and characterization, not production tested.
3All input signals are specified with tR = tF = 5 ns (10% to 90% of DVCC) and timed from a voltage level of (VIL + VIH)/2.
Specifications subject to change without notice.
t1
1
2
3
4
5
16
17
18
19
SCLK
1
t3
t2
t5
SYNC
t4
t8
t6
t7
D
IN
MSB
LSB
RESET
t9
Figure 1. Serial Interface Timing Diagram
–3–
REV. 0
AD5532HS
ABSOLUTE MAXIMUM RATINGS1, 2
Junction Temperature (TJ max) . . . . . . . . . . . . . . . . . . 150°C
74-Lead LFBGA Package, θJA Thermal Impedance . . . 41°C/W
Reflow Soldering
(TA = 25°C unless otherwise noted)
VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +17 V
VSS to AGND . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –17 V
AVCC to AGND, DAC_GND . . . . . . . . . . . . . –0.3 V to +7 V
DVCC to DGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
Digital Inputs to DGND . . . . . . . . . . –0.3 V to DVCC + 0.3 V
REF_IN to AGND, DAC_GND . . . . . . . . . . . –0.3 V to +7 V
Peak Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
Time at Peak Temperature . . . . . . . . . . . . 10 sec to 40 sec
Max Power Dissipation at TA = 70°C,
Outputs Loaded . . . . . . . . . . . . . . . . . . . . . . . . . . 550 mW3
(for TA > 70°C, derate at 26 mW for each °C over 70°C)
NOTES
V
OUT0–VOUT31 to AGND . . . . . . . VSS – 0.3 V to VDD + 0.3 V
1 Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2 Transient currents of up to 100 mA will not cause SCR latch-up.
3 This limit includes load power and applies only when there is a resistive load on
VOUT outputs.
VOUT0–VOUT31 to VSS . . . . . . . . . . . . . . . . . . –0.3 V to +24 V
OFFS_IN to AGND . . . . . . . . . . . VSS – 0.3 V to VDD + 0.3 V
AGND to DGND . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V
Operating Temperature Range
Industrial . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
ORDERING GUIDE
Output
Voltage Span
Package
Description
Package
Option
Model
Function
AD5532HSABC
32 DACs
5 V
74-Ball LFBGA
BC-74
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD5532HS features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
FULL-SCALE
ERROR
ACTUAL
IDEAL
OFFSET
ERROR
0
DAC CODE
16k
Figure 2. DAC Transfer Function (OFFS_IN = 0)
–4–
REV. 0
AD5532HS
PIN CONFIGURATION
1
2
3
4
5
6
7
8
9
10 11
A
B
C
D
E
F
A
B
C
D
E
F
TOP VIEW
G
H
J
G
H
J
K
L
K
L
1
2
3
4
5
6
7
8
9
10 11
AD5532HS 74-Ball (LFBGA) Configuration
LFBGA
Number
Ball
Name
LFBGA
Number
Ball
Name
LFBGA
Number
Ball
Name
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
C1
C2
C6
N/C
N/C
N/C
N/C
SYNC
DVCC
SCLK
N/C
N/C
RESET
N/C
VO16
N/C
N/C
N/C
N/C
DGND
DIN
DGND
N/C
N/C
C10
C11
D1
AVCC1
N/C
VO20
DAC_GND2
AVCC2
N/C
VO26
VO14
AGND1
OFFS_IN
VO25
VO21
AGND2
VO6
VO24
VO8
VO5
VO3
VO23
N/C
VO4
J10
J11
K1
K2
K3
K4
K5
K6
K7
K8
K9
K10
K11
L1
L2
L3
L4
L5
L6
L7
L8
L9
VO9
VO11
VO17
VO15
VO27
VSS3
VSS1
VSS4
VDD2
VO2
VO10
VO13
VO12
N/C
VO28
VO29
VO30
VDD3
VDD1
VDD4
VO31
VO0
D2
D10
D11
E1
E2
E10
E11
F1
F2
F10
F11
G1
G2
G10
G11
H1
H2
H10
H11
J1
REF_IN
VO18
DAC_GND1
VO7
VO22
VO19
VSS2
L10
L11
VO1
N/C
J2
J6
N/C
REV. 0
–5–
AD5532HS
PIN FUNCTION DESCRIPTIONS
Pin
Function
AGND (1–2)
AVCC (1–2)
Analog GND Pins.
Analog Supply Pins. Voltage range from 4.75 V to 5.25 V.
VDD Supply Pins. Voltage range from 8 V to 12 V.
VSS Supply Pins. Voltage range from –4.75 V to –12 V.
Digital GND Pins.
V
V
DD (1–4)
SS (1–4)
DGND
DVCC
DAC_GND (1–2)
REF_IN
Digital Supply Pins. Voltage range from 2.7 V to 5.25 V.
Reference GND Supply for All the DACs.
Reference Voltage for Channels 0–31.
V
OUT0–VOUT31
Analog Output Voltages from the 32 Channels.
SYNC
Active Low Input. This is the Frame Synchronization signal for the serial interface. While SYNC is low,
data is transferred in on the falling edge of SCLK.
SCLK*
Serial Clock Input. Data is clocked into the shift register on the falling edge of SCLK. This
operates at clock speeds up to 30 MHz.
DIN
*
Serial Data Input. Data must be valid on the falling edge of SCLK.
OFFS_IN
RESET*
Offset Input. The user can connect this to GND or REF_IN to determine the output span.
Active Low Input. This pin can also be used to reset the complete device to its power-on-reset conditions.
*Internal pull-up device on this logic input. Therefore, it can be left floating and will default to a logic high condition.
Output Voltage Settling Time
TERMINOLOGY
The time taken from when the last data bit is clocked into the
DAC until the output has settled to within 0.5 LSB of its
final value.
Integral Nonlinearity (INL)
A measure of the maximum deviation from a straight line pass-
ing through the endpoints of the DAC transfer function. It is
expressed as a percentage of full-scale range.
Digital-to-Analog Glitch Impulse
The area of the glitch injected into the analog output when
the code in the DAC register changes state. It is specified as
the area of the glitch in nV-secs when the digital code is changed
by 1 LSB at the major carry transition (011 . . . 11 to 100 . . . 00
or 100 . . . 00 to 011 . . . 11).
Differential Nonlinearity (DNL)
The difference between the measured change and the ideal 1 LSB
change between any two adjacent codes. A specified DNL of
1 LSB maximum ensures monotonicity.
Offset Error
Digital Crosstalk
A measure of the error present at the device output with all 0s
loaded to the DAC. It includes the offset of the DAC and the
output amplifier. It is expressed in mV.
The glitch impulse transferred to the output of one DAC at
midscale while a full-scale code change (all 1s to all 0s and vice
versa) is being written to another DAC. It is expressed in nV-secs.
Full-Scale Error
Analog Crosstalk
A measure of the output error with all 1s loaded to the DAC.
Ideally the output should be 2 REF_IN if OFFS_IN = 0. It is
expressed as a percentage of full-scale range.
The area of the glitch transferred to the output (VOUT) of one
DAC due to a full-scale change in the output (VOUT) of another
DAC. The area of the glitch is expressed in nV-secs.
DC Power-Supply Rejection Ratio (PSRR)
A measure of the change in analog output for a change in supply
voltage (VDD and VSS). It is expressed in dB. VDD and VSS are
varied 5%.
Digital Feedthrough
A measure of the impulse injected into the analog outputs from the
digital control inputs when the part is not being written to, i.e.,
SYNC is high. It is specified in nV-secs and measured with a
worst-case change on the digital input pins, e.g., from all 0s
to all 1s and vice versa.
DC Crosstalk
The dc change in the output level of one DAC at midscale in
response to a full-scale code change (all 0s to all 1s and vice
versa) and output change of all other DACs. It is expressed in µV.
Output Noise Spectral Density
A measure of internally generated random noise. Random noise is
characterized as a spectral density (voltage per root Hertz). It is
measured by loading all DACs to midscale and measuring
noise at the output. It is measured in nV/√Hz.
Output Temperature Coefficient
A measure of the change in analog output with changes in tem-
perature. It is expressed in ppm/°C.
–6–
REV. 0
Typical Performance Characteristics–AD5532HS
1.0
0.8
1.0
0.5
0.2
5.000
V
= 2.5V
= 0V
= 25؇C
REF_IN
V
= 2.5V
= 0V
REFIN
V
OFFS_IN
V
OFFS_IN
T
A
DAC LOADEDTO FULL SCALE
0.6
0.1
0.4
4.995
DNL MAX
INL MAX
0.2
0.0
0.0
0.0
–0.2
–0.4
–0.6
–0.8
–1.0
4.990
4.985
INL MIN
–0.5
–1.0
–0.1
–0.2
DNL MIN
–40
0
40
80
0
2K 4K 6K 8K 10K 12K 14K16K
DAC CODE
–40
0
40
80
TEMPERATURE – ؇C
TEMPERATURE – ؇C
TPC 1. Typical DNL Plot
TPC 3. VOUT vs. Temperature
TPC 2. INL Error and DNL Error vs.
Temperature
2.535
2.530
6
5
2.520
T
V
V
= 25؇C
A
2.518
2.516
2.514
T = 25؇C
A
= 2.5V
REFIN
V
= 2.5V
REFIN
= 0V
OFFS_IN
V
= 0V
OFFS_IN
DAC LOADEDTO MIDSCALE
4
2.512
2.510
2.508
2.506
2.504
2.502
3
2
2.525
2.520
1
T
V
V
= 25؇C
A
2.500
2.498
2.496
= 2.5V
REFIN
0
= 0V
OFFS_IN
–1
2.494
6
4
2
0
–2
–4
–6
TIME BASE – 200ns/DIV
TIME BASE – 1.25s/DIV
SINK/SOURCE CURRENT – mA
TPC 4. VOUT Source and Sink
Capability
TPC 6. Major Code Transition Glitch
Impulse
TPC 5. Full-Scale Settling Time
15
20
10
0
15
10
5
10
5
0
0
0
0.1
0.2
% FSR
0.3
–1.0
–0.5
0.0
0
10
20
30
mV
% FSR
TPC 7. INL Error Distribution at 25°C
TPC 8. Offset Error Distribution
TPC 9. Full-Scale Error Distribution
at 25°C
at 25°C
REV. 0
–7–
AD5532HS
FUNCTIONAL DESCRIPTION
Reset Function
The AD5532HS consists of 32 DACs in a single package. A
14-bit digital word is loaded into one of the 32 DAC registers
via the serial interface. This is then converted (with gain and
offset) into an analog output voltage (VOUT0–VOUT31).
The reset function on the AD5532HS can be used to reset all
nodes on the device to their power-on-reset condition. All the
DACs are loaded with 0s and all registers are cleared. The reset
function is implemented by taking the RESET pin low.
To update a DAC’s output voltage, the required DAC is
addressed via the serial port. When the 5-bit DAC address
and 14-bit DAC data have been loaded the selected DAC
converts the code.
SERIAL INTERFACE
The serial interface is controlled by three pins as follows:
SYNC: This pin is the Frame Synchronization pin for the serial
interface.
On power-on, all the DACs are loaded with zeros.
SCLK: This pin is the Serial Clock Input. It operates at clock
speeds up to 30 MHz.
Digital-to-Analog Section
The architecture of each DAC channel consists of a resistor-
string DAC followed by an output buffer amplifier. The voltage
at the REF_IN pin provides the reference voltage for the cor-
responding DAC. Since the input coding to the DAC is straight
binary, the ideal DAC output voltage is given by:
DIN: This pin is the Serial Data Input. Data must be valid on
the falling edge of SCLK.
To update a single DAC channel a 19-bit data-word is written
into the AD5532HS. See Table II.
VREF _ IN × D
VDAC
=
214
Table II. Serial Data Format
where D = decimal equivalent of the binary code that is loaded
to the DAC register i.e., 0–16,383.
MSB
A4
LSB
A3
A2
A1
A0
DB13–DB0
Output Buffer Stage—Gain and Offset
A4–A0 Bits
The function of the output buffer stage is to translate the
0 V–2.5 V output of the DAC to a wider range. This is done by
gaining up the DAC output by two and offsetting the voltage
by the voltage on OFFS_IN pin.
Used to address any one of the 32 channels (A4 = MSB of
address, A0 = LSB).
DB13–DB0 Bits
VOUT = (2 ×VDAC ) –VOFFS _ IN
These are used to write a 14-bit word into the addressed
DAC register.
V
DAC is the output of the DAC.
Figure 1 shows the timing diagram for a serial write to the
AD5532HS. The serial interface works with both a continuous and
a noncontinuous serial clock. The first falling edge of SYNC resets
a counter that counts the number of serial clocks to ensure
the correct number of bits are shifted in and out of the serial
shift registers. Any further edges on SYNC are ignored until the
correct number of bits are shifted in or out. Once 19 bits have
been shifted in or out, the SCLK is ignored. In order for another
serial transfer to take place, the counter must be reset by the
falling edge of SYNC. The user must allow 280 ns (min)
between successive writes (refer to Timing Specifications).
VOFFS_IN is the voltage at the OFFS_IN pin.
Table I shows how the output range of VOUT relates to the offset
voltage supplied by the user.
Table I. Sample Output Voltage Ranges
VOFFS_IN
(V)
VDAC
(V)
VOUT
(V)
0
2.5
0 to 2.5
0 to 2.5
0 to 5
–2.5 to +2.5
V
V
OUT is limited only by the headroom of the output amplifiers.
OUT must be within maximum ratings.
–8–
REV. 0
AD5532HS
MICROPROCESSOR INTERFACING
AD5532HS-to-ADSP-21xx Interface
The ADSP-21xx family of DSPs are easily interfaced to the
AD5532HS without the need for extra logic.
AD5532HS-to-PIC16C6x/7x Interface
The PIC16C6x/7x Synchronous Serial Port (SSP) is configured
as an SPI Master with the Clock Polarity bit = 0. This is done
by writing to the Synchronous Serial Port Control Register
(SSPCON). See user PIC16/17 Microcontroller User Manual.
In this example I/O port RA1 is being used to pulse SYNC
and enable the serial port of the AD5532HS. This microcontroller
transfers only eight bits of data during each serial transfer
operation; therefore, three consecutive write operations are
necessary to transmit 19 bits of data. Data is transmitted MSB
first. It is important to left-justify the data in the SPDR register
so that the first 19 bits transmitted contain valid data. RA1
must be pulled low to start a transfer. It is taken high and pulled
low again before any further write cycles can take place. Figure 5
shows the connection diagram.
A data transfer is initiated by writing a word to the Tx register
after the SPORT has been enabled. In a write sequence, data is
clocked out on each rising edge of the DSP’s serial clock and
clocked into the AD5532HS on the falling edge of its SCLK.
The easiest way to provide the 19-bit data-word required by
the AD5532HS, is to transmit two 10-bit data-words from the
ADSP-21xx. Ensure that the data is positioned correctly in the
TX register so that the first 19 bits transmitted contain valid
data. The SPORT control register should be set up as follows:
TFSW = 1, Alternate Framing
INVTFS = 1, Active Low Frame Signal
DTYPE = 00, Right Justify Data
ISCLK = 1, Internal Serial Clock
PIC16C6x/7x*
AD5532HS*
SCLK
SCK/RC3
TFSR
ITFS
= 1, Frame Every Word
= 1, Internal Framing Signal
SDI/RC4
RA1
D
IN
SYNC
SLEN = 1001, 10-Bit Data Word
Figure 3 shows the connection diagram.
*ADDITIONAL PINS OMITTED FOR CLARITY
ADSP-2101/
ADSP-2103*
AD5532HS*
Figure 5. AD5532HS-to-PIC16C6x/7x Interface
SCLK
SCLK
AD5532HS-to-8051 Interface
The AD5532HS requires a clock synchronized to the serial
data. The 8051 serial interface must therefore be operated in
Mode 0. In this mode serial data exits the 8051 through RxD
and a shift clock is output on TxD. The SYNC signal is derived
from a port line (P1.1). Figure 6 shows how the 8051 is connected
to the AD5532HS. Because the AD5532HS shifts data out on
the rising edge of the shift clock and latches data in on the
falling edge, the shift clock must be inverted. Note also that
the AD5532HS requires its data with the MSB first. Since the
8051 outputs the LSB first, the transmit routine must take this
into account.
D
DT
IN
TFS
SYNC
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 3. AD5532HS-to-ADSP-2101/ADSP-2103 Interface
AD5532HS-to-MC68HC11 Interface
The Serial Peripheral Interface (SPI) on the MC68HC11 is
configured for Master Mode (MSTR = 1), Clock Polarity Bit
(CPOL) = 0 and the Clock Phase Bit (CPHA) = 1. The SPI is
configured by writing to the SPI Control Register (SPCR)—see
68HC11 User Manual. SCK of the 68HC11 drives the SCLK of
the AD5532HS and the MOSI output drives the serial data line
(DIN) of the AD5532HS. The SYNC signal is derived from a port
line (PC7). When data is being transmitted to the AD5532HS, the
SYNC line is taken low (PC7). Data appearing on the MOSI
output is valid on the falling edge of SCK. The 68HC11 transfers
only eight bits of data during each serial transfer operation;
therefore, three consecutive write operations are necessary to
transmit 19 bits of data. Data is transmitted MSB first. It is
important to left-justify the data in the SPDR register so that
the first 19 bits transmitted contain valid data. PC7 must be
pulled low to start a transfer. It is taken high and pulled low
again before any further write cycles can take place. See Figure 4.
8051*
AD5532HS*
SCLK
TxD
RxD
P1.1
D
IN
SYNC
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 6. AD5532HS-to-8051 Interface
MC68HC11*
AD5532HS*
SCLK
SCK
D
MOSI
PC7
IN
SYNC
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 4. AD5532HS-to-MC68HC11 Interface
REV. 0
–9–
AD5532HS
APPLICATION CIRCUITS
AD5532HS in an Optical Network Control Loop
PARAMETRIC
MEASUREMENT
UNIT
SYSTEM BUS
DAC
DAC
DAC
The AD5532HS can be used in optical network applications
that require a large number of DACs to perform a control and
measurement function. In the circuit shown in Figure 7, the
0 V–5 V outputs of the AD5532HS are amplified to a range of
0 V–180 V and then used to control actuators that determine
the position of MEMS mirrors in an optical switch. The exact
position of each mirror is measured using sensors. The sensor
readings are muxed using four dual 4-channel matrix switches
(ADG739) and fed back to an 8-channel 14-bit ADC (AD7856).
The control loop is driven by an ADSP-21065L, a 32-bit SHARC®
DSP with an SPI-compatible SPORT interface. It writes data
to the DAC, controls the multiplexor, and reads data from
the ADC via a 3-wire serial interface.
ACTIVE
LOAD
STORED
DATA
DRIVER
AND INHIBIT
PATTERN
DAC
DAC
FORMATTER
DUT
PERIOD
GENERATION
AND
DELAY
TIMING
DAC
DAC
COMPARE
REGISTER
COMPARATOR
DACs
SYSTEM BUS
S
E
N
S
O
R
S
1
8
1
1
ACTUATORS
FOR MEMS
MIRROR
Figure 9. AD5532HS in an ATE System
POWER SUPPLY DECOUPLING
ADG739
0V–180V
AD7856
AD5532HS
؋
4 AMPS
ARRAY
32
32
In any circuit where accuracy is important, careful consideration
of the power supply and ground return layout helps to ensure
the rated performance. The printed circuit board on which the
AD5532HS is mounted should be designed so that the analog
and digital sections are separated, and confined to certain areas
of the board. If the AD5532HS is in a system where multiple
devices require an AGND-to-DGND connection, the connection
should be made at one point only. The star ground point should
be established as close as possible to the device. For supplies
with multiple pins (VSS, VDD, AVCC), it is recommended to
tie those pins together. The AD5532HS should have ample
supply bypassing of 10 µF in parallel with 0.1 µF on each supply
located as close to the package as possible, ideally right up against
the device. The 10 µF capacitors are the tantalum bead type. The
0.1 µF capacitor should have low Effective Series Resistance
(ESR) and Effective Series Inductance (ESI), like the common
ceramic types that provide a low impedance path to ground at
high frequencies, to handle transient currents due to internal
logic switching.
ADSP-21065L
Figure 7. AD5532HS and DSP Control an Optical Switch
Alternatively, the AD5532HS can be driven by an ADMC401
Motor-Controller as shown in the control-loop in Figure 8. The
DAC outputs are fed into eight AD8534 quad transconductance
amps to generate currents for voice-coil actuators that determine
the position of the mirrors. The exact position of each mirror
is measured and the readings are muxed into the on-chip
8-channel ADC of the ADMC401.
S
1
1
8
1
VOICE-COIL
ACTUATORS
FOR
MEMS
MIRROR
ARRAY
E
N
S
O
R
S
ADG704
؋
8 AD5532HS
32
32
AD8534
AD8544
؋
8 ؋
2 3
The power supply lines of the AD5532HS should use as large a
trace as possible to provide low impedance paths and reduce
the effects of glitches on the power supply line. Fast switching
signals such as clocks should be shielded with digital ground to
avoid radiating noise to other parts of the board, and should
never be run near the reference inputs. A ground line routed
between the DIN and SCLK lines will help reduce crosstalk
between them (not required on a multilayer board as there will
be a separate ground plane, but separating the lines will help). It
is essential to minimize noise on REF_IN.
S
P
O
R
T
1
8
8-CH
12-BIT
ADC
3
ADMC401
Figure 8. AD5532HS and ADMC401 Control an Optical
Switch
AD5532HS in a Typical ATE System
The AD5532HS is ideally suited for use in Automatic Test
Equipment. Several DACs are required to control pin drivers,
comparators, active loads, and signal timing. Traditionally,
sample-and-hold devices were used in this application.
Avoid crossover of digital and analog signals. Traces on opposite
sides of the board should run at right angles to each other. This
reduces the effects of feedthrough through the board. A microstrip
technique is by far the best, but not always possible with a double-
sided board. In this technique, the component side of the board
is dedicated to ground plane while signal traces are placed on
the solder side.
The AD5532HS has several advantages: no refreshing is required,
there is no droop, pedestal error is eliminated, and there is no
need for extra filtering to remove glitches. A higher level of
integration is achieved in a smaller area (see Figure 9).
As is the case for all thin packages, care must be taken to avoid
flexing the package and to avoid a point load on the surface of
the package during the assembly process.
SHARC is a registered trademark of Analog Devices, Inc.
–10–
REV. 0
AD5532HS
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
74-Ball LFBGA
(BC-74)
0.394 (10.00) BSC
0.472 (12.00) BSC
A1
11 10
9 8 7 6 5 4 3 2 1
A
B
C
D
E
F
G
H
J
0.472
(12.00)
BSC
0.394
(10.00)
BSC
BOTTOM
VIEW
TOP VIEW
0.039
(1.00)
BSC
K
L
0.039 (1.00) BSC
DETAIL A
DETAIL A
0.067
(1.70)
MAX
0.033
(0.85)
MIN
0.020
(0.50)
MIN
CONTROLLING DIMENSIONS
ARE IN MILLIMETERS
0.024 (0.60)
BSC
SEATING
PLANE
BALL DIAMETER
REV. 0
–11–
–12–
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