AD5671RBCPZ-RL [ADI]
Base station power amplifiers;
| 型号： | AD5671RBCPZ-RL |
| 厂家： | 
ADI |
| 描述： | Base station power amplifiers |
| 文件： | 总32页 (文件大小：841K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Octal, 12-/16-Bit nanoDAC+ with
2 ppm/°C Reference, I2C Interface
AD5671R/AD5675R
Data Sheet
FEATURES
GENERAL DESCRIPTION
The AD5671R/AD5675R are low power, octal, 12-/16-bit
buffered voltage output digital-to-analog converters (DACs).
They include a 2.5 V, 2 ppm/°C internal reference (enabled by
default) and a gain select pin giving a full-scale output of 2.5 V
(gain = 1) or 5 V (gain = 2). The devices operate from a single
2.7 V to 5.5 V supply and are guaranteed monotonic by design.
The AD5671R/AD5675R are available in a 20-lead TSSOP and in
a 20-lead LFCSP and incorporate a power-on reset circuit and a
RSTSEL pin that ensures the DAC outputs power up to zero scale
or midscale and remain there until a valid write. The AD5671R/
AD5675R contain a power-down mode, reducing the current
consumption to 1 μA typical while in power-down mode.
High performance
High relative accuracy (INL): 3 LSB maximum at 16 bits
Total unadjusted error (TUE): 0.14ꢀ of FSR maximum
Offset error: 1.5 mꢁ maximum
Gain error: 0.06ꢀ of FSR maximum
Low drift 2.5 ꢁ reference: 2 ppm/°C typical
Wide operating ranges
−40°C to +125°C temperature range
2.7 ꢁ to 5.5 ꢁ power supply
Easy implementation
User selectable gain of 1 or 2 (GAIN pin/bit)
1.8 ꢁ logic compatibility
400 kHz I2C-compatible serial interface
Robust 2 kꢁ HBM and 1.5 kꢁ FICDM ESD rating
20-lead, RoHS-compliant TSSOP and LFCSP
Table 1. Octal nanoDAC+® Devices
Interface
Reference
16-Bit
12-Bit
SPI
Internal
External
Internal
AD5676R
AD5676
AD5675R
AD5672R
Not applicable
AD5671R
APPLICATIONS
Optical transceivers
I2C
Base station power amplifiers
Process control (PLC input/output cards)
Industrial automation
PRODUCT HIGHLIGHTS
1. High Relative Accuracy (INL)
AD5671R (12-bit): ±1 LSB maximum
AD5675R (16-bit): ±± LSB maximum
2. Low Drift, 2.5 V On-Chip Reference
Data acquisition systems
FUNCTIONAL BLOCK DIAGRAM
V
V
V
REFOUT
LOGIC
DD
AD5671R/AD5675R
2.5V
REF
BUFFER
BUFFER
BUFFER
BUFFER
BUFFER
BUFFER
BUFFER
BUFFER
DAC
STRING
DAC 0
INPUT
V
V
V
V
V
V
V
V
0
1
2
3
4
5
6
7
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
REGISTER
REGISTER
DAC
REGISTER
STRING
DAC 1
INPUT
REGISTER
DAC
REGISTER
STRING
DAC 2
INPUT
REGISTER
SCL
DAC
REGISTER
STRING
DAC 3
INPUT
REGISTER
SDA
A1
DAC
REGISTER
STRING
DAC 4
INPUT
REGISTER
DAC
REGISTER
STRING
DAC 5
INPUT
REGISTER
A0
DAC
REGISTER
STRING
DAC 6
INPUT
REGISTER
LDAC
DAC
REGISTER
STRING
DAC 7
INPUT
REGISTER
RESET
GAIN POWER-DOWN
POWER-ON
RESET
×1/×2
LOGIC
RSTSEL
GAIN
GND
Figure 1.
Rev. B
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Tel: 781.329.4700 ©2014–2015 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
AD5671R/AD5675R
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
I2C Slave Address........................................................................ 24
Serial Operation ......................................................................... 24
Write Operation.......................................................................... 24
Read Operation........................................................................... 25
Multiple DAC Readback Sequence.......................................... 25
Power-Down Operation............................................................ 26
Applications....................................................................................... 1
General Description......................................................................... 1
Product Highlights ........................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
AD5671R Specifications.............................................................. 3
AD5675R Specifications.............................................................. 5
AC Characteristics........................................................................ 7
Timing Characteristics ................................................................ 8
Absolute Maximum Ratings............................................................ 9
Thermal Resistance ...................................................................... 9
ESD Caution.................................................................................. 9
Pin Configurations and Function Descriptions ......................... 10
Typical Performance Characteristics ........................................... 11
Terminology .................................................................................... 20
Theory of Operation ...................................................................... 22
Digital-to-Analog Converter (DAC) ....................................... 22
Transfer Function ....................................................................... 22
DAC Architecture....................................................................... 22
Serial Interface ............................................................................ 23
Write and Update Commands.................................................. 24
LDAC
Load DAC (Hardware
Pin)........................................... 26
Mask Register ................................................................. 27
Hardware Reset ( ) .......................................................... 28
LDAC
RESET
Reset Select Pin (RSTSEL) ........................................................ 28
Internal Reference and Amplifier Gain Selection.................. 28
Solder Heat Reflow..................................................................... 28
Long-Term Temperature Drift ................................................. 28
Thermal Hysteresis .................................................................... 29
Applications Information.............................................................. 30
Power Supply Recommendations............................................. 30
Microprocessor Interfacing....................................................... 30
AD5671R/AD5675R to ADSP-BF531 Interface .................... 30
Layout Guidelines....................................................................... 30
Galvanically Isolated Interface ................................................. 30
Outline Dimensions....................................................................... 31
Ordering Guide .......................................................................... 31
REVISION HISTORY
10/15—Rev. A to Rev. B
Changes to Table 17 ....................................................................... 29
Changes to Galvanically Isolated Interface Section and
Figure 70 .......................................................................................... 30
Updated Outline Dimensions....................................................... 31
Changes to Ordering Guide.......................................................... 31
Added 20-Lead LFCSP.......................................................Universal
Changes to Features Section and Figure 1 .................................... 1
Changes to Reference Temperature Coefficient Parameter,
Table 2 and ILOGIC Parameter, Table 2 ............................................. 3
Changes to Reference Temperature Coefficient Parameter,
Table 3 and ILOGIC parameter, Table 3 ............................................. 5
Changes to Table 6............................................................................ 9
Added Thermal Resistance Section and Table 7; Renumbered
Sequentially ...................................................................................... 9
Added Figure 5; Renumbered Sequentially ................................ 10
Changes to Table 8.......................................................................... 10
Changes to Terminology Section.................................................. 20
Change to Table 9 ........................................................................... 23
Change to Read Operation Section.............................................. 25
2/15—Rev. 0 to Rev. A
Added AD5671R Specifications Section ........................................3
Changes to Table 2.............................................................................3
Added AD5675R Specifications Section and Table 3;
Renumbered Sequentially ................................................................5
Changes to Table 5.............................................................................8
Added Figure 3; Renumbered Sequentially ...................................8
Change to Terminology Section................................................... 20
Change to Transfer Function Section .......................................... 22
LDAC
RESET
Changes to
Mask Register Section and Table 14............ 27
Changes to Hardware Reset (
) Section............................ 28
Changed Internal Reference Setup Section to Internal Reference
and Amplier Gain Selection Section............................................ 28
Changes to Internal Reference and Amplier Gain Selection
(LFCSP Only) Section and Table 16............................................. 28
Changes to Ordering Guide.......................................................... 31
10/14—Revision 0: Initial Version
Rev. B | Page 2 of 32
Data Sheet
AD5671R/AD5675R
SPECIFICATIONS
AD5671R SPECIFICATIONS
VDD = 2.7 V to 5.5 V, 1.8 V ≤ VLOGIC ≤ 5.5 V, RL = 2 kΩ, CL = 200 pF, all specifications TA = −40°C to +125°C, unless otherwise noted.
Table 2.
Parameter
STATIC PERFORMANCE1
Min
Typ
Max
Unit
Test Conditions/Comments
Resolution
12
Bits
Relative Accuracy (INL)
±±.12
±±.12
±±.±1
±±.±1
±.8
±1
±1
±±.1
±±.1
1.6
LSB
LSB
LSB
LSB
mV
mV
mV
% of FSR
% of FSR
% of FSR
% of FSR
% of FSR
% of FSR
μV/°C
mV/V
μV
Gain = 1
Gain = 2
Gain = 1
Gain = 2
Gain = 1 or gain = 2
Gain = 1
Gain = 2
Gain = 1
Gain = 2
Gain = 1
Gain = 2
Gain = 1
Gain = 2
Differential Nonlinearity (DNL)
Zero-Code Error
Offset Error
−±.75
−±.1
±2
±1.5
±±.1ꢀ
±±.±7
±±.12
±±.±6
±±.18
±±.1ꢀ
Full-Scale Error
Gain Error
TUE
−±.±18
−±.±13
+±.±ꢀ
−±.±2
±±.±3
±±.±±6
±1
±.25
±2
±3
±2
Offset Error Drift2
DC Power Supply Rejection Ratio (PSRR)2
DC Crosstalk2
DAC code = midscale, VDD = 5 V ± 1±%
Due to single channel, full-scale output change
Due to load current change
μV/mA
μV
Due to powering down (per channel)
OUTPUT CHARACTERISTICS2
Output Voltage Range
±
±
2.5
5
V
V
Gain = 1
Gain = 2
Output Current Drive
Capacitive Load Stability
15
mA
nF
2
RL = ∞
1±
nF
kΩ
μV/mA
RL = 1 kΩ
Resistive Load3
Load Regulation
1
183
177
VDD = 5 V ± 1±%, DAC code = midscale,
−3± mA ≤ IOUT ≤ +3± mA
VDD = 3 V ± 1±%, DAC code = midscale,
−2± mA ≤ IOUT ≤ +2± mA
μV/mA
Short-Circuit Currentꢀ
Load Impedance at Rails5
Power-Up Time
ꢀ±
25
2.5
mA
Ω
μs
Coming out of power-down mode, VDD = 5 V
See the Terminology section
REFERENCE OUTPUT
Output Voltage6
Reference Temperature Coefficient7, 8
2.ꢀ975
2.5±25
V
2±-Lead TSSOP
2±-Lead LFCSP
Output Impedance2
Output Voltage Noise2
Output Voltage Noise Density2
Load Regulation Sourcing2
Load Regulation Sinking2
Output Current Load Capability2
Line Regulation2
2
5
±.±ꢀ
13
2ꢀ±
29
7ꢀ
±2±
ꢀ3
5
1±
ppm/°C
ppm/°C
Ω
μV p-p
nV/√Hz
μV/mA
μV/mA
mA
±.1 Hz to 1± Hz
At ambient, f = 1± kHz, CL = 1± nF, gain = 1 or 2
At ambient
At ambient
VDD ≥ 3 V
μV/V
At ambient
After 1±±± hours at 125°C
First cycle
Long-Term Stability/Drift2
Thermal Hysteresis2
12
125
25
ppm
ppm
ppm
Additional cycles
Rev. B | Page 3 of 32
AD5671R/AD5675R
Data Sheet
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
LOGIC INPUTS2
Input Current
Input Voltage
Low, VINL
±±
µA
Per pin
0.3 × VLOGIC
V
High, VINH
0.7 × VLOGIC
V
Pin Capacitance
LOGIC OUTPUTS (SDA)2
Output Voltage
Low, VOL
3
4
pF
0.4
V
V
pF
ISINK = 200 μA
ISOURCE = 200 μA
High, VOH
VLOGIC − 0.4
Floating State Output Capacitance
POWER REQUIREMENTS
VLOGIC
±.8
5.5
3
3
3
3
V
ILOGIC
µA
µA
µA
µA
V
Power-on, −40°C + ±05°C
Power-on, −40°C + ±25°C
Power-down, −40°C + ±05°C
Power-down, −40°C + ±25°C
Gain = ±
VDD
2.7
VREF + ±.5
5.5
5.5
V
Gain = 2
IDD
VIH = VDD, VIL = GND, VDD = 2.7 V to 5.5 V
Internal reference off, −40°C to +85°C
Internal reference on, −40°C to +85°C
Internal reference off
Normal Mode9
±.±
±.8
±.±
±.8
±
±
±
±
±
±.26
2.0
±.3
2.±
±.7
±.7
2.5
2.5
5.5
5.5
mA
mA
mA
mA
µA
µA
µA
µA
µA
µA
Internal reference on
All Power-Down Modes±0
Tristate to ± kΩ, −40°C to +85°C
Power down to ± kΩ, −40°Cto +85°C
Tristate, −40°C to +±05°C
Power down to ± kΩ, −40°C to +±05°C
Tristate to ± kΩ, −40°C to +±25°C
Power down to ± kΩ, −40°C to +±25°C
±
± DC specifications tested with the outputs unloaded, unless otherwise noted. Upper dead band = ±0 mV and exists only when VREF = VDD with gain = ±, or when VREF/2 =
V
DD with gain = 2. Linearity calculated using a reduced code range of ±2 to 4080.
2 Guaranteed by design and characterization; not production tested.
3 Together, Channel 0, Channel ±, Channel 2, and Channel 3 can source/sink 40 mA. Similarly, together, Channel 4, Channel 5, Channel 6, and Channel 7 can source/sink
40 mA up to a junction temperature of ±25°C.
4 VDD = 5 V. The devices include current limiting to protect the devices during temporary overload conditions. Junction temperature can be exceeded during current
limit. Operation above the specified maximum operation junction temperature may impair device reliability.
5 When drawing a load current at either rail, the output voltage headroom with respect to that rail is limited by the 25 Ω typical channel resistance of the output
devices. For example, when sinking ± mA, the minimum output voltage = 25 Ω × ± mA = 25 mV.
6 Initial accuracy presolder reflow is ±750 µV; output voltage includes the effects of preconditioning drift. See the Internal Reference and Amplifier Gain Selection
section.
7 Reference is trimmed and tested at two temperatures and is characterized from −40°C to +±25°C.
8 Reference temperature coefficient calculated as per the box method. See the Terminology section for further information.
9 Interface inactive. All DACs active. DAC outputs unloaded.
±0 All DACs powered down.
Rev. B | Page 4 of 32
Data Sheet
AD5671R/AD5675R
AD5675R SPECIFICATIONS
VDD = 2.7 V to 5.5 V, 1.8 V ≤ VLOGIC ≤ 5.5 V, RL = 2 kΩ, CL = 200 pF, all specifications TA = −40°C to +125°C, unless otherwise noted.
Table 3.
A Grade
Typ
B Grade
Typ
Parameter
STATIC PERFORMANCE±
Min
Max
Min
Max
Unit
Test Conditions/Comments
Resolution
Relative Accuracy (INL)
±6
±6
Bits
LSB
LSB
LSB
LSB
mV
mV
mV
±±.8
±±.7
±0.7
±0.5
0.8
±8
±8
±±
±±
4
±±.8
±±.7
±0.7
±0.5
0.8
±3
±3
±±
±±
±.6
±2
±±.5
Gain = ±
Gain = 2
Gain = ±
Gain = 2
Gain = ± or gain = 2
Gain = ±
Gain = 2
Differential Nonlinearity (DNL)
Zero-Code Error
Offset Error
−0.75
−0.±
±6
±4
−0.75
−0.±
Full-Scale Error
Gain Error
TUE
−0.0±8 ±0.28
−0.0±3 ±0.±4
−0.0±8 ±0.±4
−0.0±3 ±0.07
% of FSR Gain = ±
% of FSR Gain = 2
% of FSR Gain = ±
% of FSR Gain = 2
% of FSR Gain = ±
% of FSR Gain = 2
µV/°C
+0.04
−0.02
±0.03
±0.24
±0.±2
±0.3
+0.04
−0.02
±0.03
±0.±2
±0.06
±0.±8
±0.006 ±0.25
±±
0.25
±0.006 ±0.±4
±±
0.25
Offset Error Drift2
DC PSRR2
mV/V
DAC code = midscale,
VDD = 5 V ± ±0%
Due to single channel,
full-scale output change
DC Crosstalk2
±2
±2
µV
±3
±2
±3
±2
µV/mA
µV
Due to load current change
Due to powering
down (per channel)
OUTPUT CHARACTERISTICS2
Output Voltage Range
0
0
2.5
5
0
0
2.5
5
V
V
Gain = ±
Gain = 2
Output Current Drive
Capacitive Load Stability
±5
±5
mA
nF
2
2
RL = ∞
±0
±0
nF
kΩ
µV/mA
RL = ± kΩ
Resistive Load3
Load Regulation
±
±
±83
±77
±83
±77
VDD = 5 V ± ±0%, DAC code =
midscale, −30 mA ≤ IOUT ≤ +30 mA
VDD = 3 V ± ±0%, DAC code =
µV/mA
midscale, −20 mA ≤ IOUT ≤ +20 mA
Short-Circuit Current4
Load Impedance at Rails5
Power-Up Time
40
25
2.5
40
25
2.5
mA
Ω
µs
Coming out of
power-down mode, VDD = 5 V
REFERENCE OUTPUT
Output Voltage6
Reference Temperature Coefficient7, 8
2.4975
2.5025 2.4975
2.5025
V
See the Terminology section
5
20
20
2
5
ppm/°C
ppm/°C
Ω
µV p-p
nV/√Hz
20-Lead TSSOP
20-Lead LFCSP
Output Impedance2
Output Voltage Noise2
Output Voltage Noise Density2
5
2
±0
0.04
±3
240
0.04
±3
240
0.± Hz to ±0 Hz
At ambient, f = ±0 kHz,
CL = ±0 nF, gain = ± or 2
At ambient
At ambient
VDD ≥ 3 V
Load Regulation Sourcing2
Load Regulation Sinking2
Output Current Load Capability2
Line Regulation2
29
74
±20
43
29
74
±20
43
µV/mA
µV/mA
mA
µV/V
At ambient
Rev. B | Page 5 of 32
AD5671R/AD5675R
Data Sheet
A Grade
Typ
±2
±25
25
B Grade
Typ
±2
±25
25
Parameter
Long-Term Stability/Drift2
Thermal Hysteresis2
Min
Max
Min
Max
Unit
ppm
ppm
ppm
Test Conditions/Comments
After ±000 hours at ±25°C
First cycle
Additional cycles
LOGIC INPUTS2
Input Current
Input Voltage
Low, VINL
±±
±±
µA
Per pin
0.3 ×
VLOGIC
0.3 ×
VLOGIC
V
High, VINH
0.7 ×
VLOGIC
0.7 ×
VLOGIC
V
Pin Capacitance
LOGIC OUTPUTS (SDA)2
Output Voltage
Low, VOL
3
4
3
4
pF
0.4
0.4
V
V
ISINK = 200 μA
ISOURCE = 200 μA
High, VOH
VLOGIC
0.4
−
VLOGIC
0.4
−
Floating State Output Capacitance
pF
POWER REQUIREMENTS
VLOGIC
ILOGIC
±.8
5.5
3
3
3
3
±.8
5.5
3
3
3
3
V
µA
µA
µA
µA
V
Power-on, −40°C + ±05°C
Power-on, −40°C + ±25°C
Power-down, −40°C + ±05°C
Power-down, −40°C + ±25°C
Gain = ±
VDD
2.7
VREF
±.5
5.5
5.5
2.7
VREF
±.5
5.5
5.5
+
+
V
Gain = 2
IDD
VIH = VDD, VIL = GND,
VDD = 2.7 V to 5.5 V
Internal reference off,
−40°C to +85°C
Internal reference on,
−40°C to +85°C
Normal Mode9
±.±
±.8
±.26
2.0
±.±
±.8
±.26
2.0
mA
mA
±.±
±.8
±
±.3
2.±
±.7
±.±
±.8
±
±.3
2.±
±.7
mA
mA
µA
Internal reference off
Internal reference on
Tristate to ± kΩ,
−40°C to +85°C
All Power-Down Modes±0
±
±.7
±
±.7
µA
Power down to ± kΩ,
−40°C to +85°C
±
±
2.5
2.5
±
±
2.5
2.5
µA
µA
Tristate, −40°C to +±05°C
Power down to ± kΩ,
−40°C to +±05°C
±
±
5.5
5.5
±
±
5.5
5.5
µA
µA
Tristate to ± kΩ, −40°C to +±25°C
Power down to ± kΩ,
−40°C to +±25°C
± DC specifications tested with the outputs unloaded, unless otherwise noted. Upper dead band = ±0 mV and exists only when VREF = VDD with gain = ±, or when VREF/2 =
VDD with gain = 2. Linearity calculated using a reduced code range of 256 to 65,280.
2 Guaranteed by design and characterization; not production tested.
3 Together, Channel 0, Channel ±, Channel 2, and Channel 3 can source/sink 40 mA. Similarly, together, Channel 4, Channel 5, Channel 6, and Channel 7 can source/sink
40 mA up to a junction temperature of ±25°C.
4 VDD = 5 V. The devices include current limiting to protect the devices during temporary overload conditions. Junction temperature can be exceeded during current
limit. Operation above the specified maximum operation junction temperature may impair device reliability.
5 When drawing a load current at either rail, the output voltage headroom with respect to that rail is limited by the 25 Ω typical channel resistance of the output
devices. For example, when sinking ± mA, the minimum output voltage = 25 Ω × ± mA = 25 mV.
6 Initial accuracy presolder reflow is ±750 µV; output voltage includes the effects of preconditioning drift. See the Internal Reference and Amplifier Gain Selection
section.
7 Reference is trimmed and tested at two temperatures and is characterized from −40°C to +±25°C.
8 Reference temperature coefficient calculated as per the box method. See the Terminology section for further information.
9 Interface inactive. All DACs active. DAC outputs unloaded.
±0 All DACs powered down.
Rev. B | Page 6 of 32
Data Sheet
AD5671R/AD5675R
AC CHARACTERISTICS
VDD = 2.7 V to 5.5 V, RL = 2 kΩ to GND, CL = 200 pF to GND, 1.8 V ≤ VLOGIC ≤ 5.5 V, all specifications TA = −40°C to +125°C, unless
otherwise noted. Guaranteed by design and characterization; not production tested.
Table 4.
Parameter
OUTPUT VOLTAGE SETTLING TIME2
Min Typ
Max
Unit
Test Conditions/Comments1
AD567±R
AD5675R
5
5
8
8
µs
µs
¼ to ¾ scale settling to ±2 LSB
¼ to ¾ scale settling to ±2 LSB
SLEW RATE
DIGITAL-TO-ANALOG GLITCH IMPULSE2
DIGITAL FEEDTHROUGH2
CROSSTALK2
Digital
0.8
±.4
0.±3
V/µs
nV-sec
nV-sec
± LSB change around major carry (internal reference, gain = ±)
0.±
−0.25
nV-sec
nV-sec
nV-sec
nV-sec
dB
Analog
−±.3
−2.0
−80
300
6
Internal reference, gain = 2
Internal reference, gain = 2
DAC-to-DAC
TOTAL HARMONIC DISTORTION (THD)3
OUTPUT NOISE SPECTRAL DENSITY2
OUTPUT NOISE2
At TA, bandwidth = 20 kHz, VDD = 5 V, fOUT = ± kHz
nV/√Hz DAC code = midscale, ±0 kHz; gain = 2
µV p-p
dB
0.± Hz to ±0 Hz, gain = ±
SIGNAL-TO-NOISE RATIO (SNR)
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
90
At TA = 25°C, bandwidth = 20 kHz, VDD = 5 V, fOUT = ± kHz
At TA = 25°C, bandwidth = 20 kHz, VDD = 5 V, fOUT = ± kHz
At TA = 25°C, bandwidth = 20 kHz, VDD = 5 V, fOUT = ± kHz
83
dB
SIGNAL-TO-NOISE-AND-DISTORTION
RATIO (SINAD)
80
dB
± The operating temperature range is −40°C to +±25°C; TA = 25°C.
2 See the Terminology section. Measured using internal reference and gain = ±, unless otherwise noted.
3 Digitally generated sine wave at ± kHz.
Rev. B | Page 7 of 32
AD5671R/AD5675R
Data Sheet
TIMING CHARACTERISTICS
VDD = 2.7 V to 5.5 V, 1.8 V ≤ VLOGIC ≤ 5.5 V, all specifications −40°C to +125°C, unless otherwise noted.
Table 5.
Parameter1, 2
Min
0.92
0.±±
0.44
0.04
40
−0.04
−0.045
0.±95
0.±2
0
Max
Unit
µs
µs
µs
µs
ns
µs
µs
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
pF
Description
t±
t2
t3
t4
t5
SCL cycle time
tHIGH, SCL high time
tLOW, SCL low time
tHD,STA, start/repeated start hold time
tSU,DAT, data setup time
tHD,DAT, data hold time
tSU,STA, repeated start setup time
tSU,STO, stop condition setup time
tBUF, bus free time between a stop condition and a start condition
tR, rise time of SCL and SDA when receiving
tF, fall time of SCL and SDA when transmitting/receiving
3
t6
t7
t8
t9
t±0
t±±
4
4, 5
20 + 0.±CB
20
t±2
t±3
t±4
LDAC
pulse width
0.4
LDAC
rising edge
SCL rising edge to
4.8
RESET
RESET
RESET
RESET
minimum pulse width low, ±.8 V ≤ VLOGIC ≤ 2.7 V
minimum pulse width low, 2.7 V ≤ VLOGIC ≤ 5.5 V
activation time, ±.8 V ≤ VLOGIC ≤ 2.7 V
6.2
t±5
±32
80
activation time, 2.7 V ≤ VLOGIC ≤ 5.5 V
6
tSP
CB
0
Pulse width of suppressed spike
Capacitive load for each bus line
5
400
± See Figure 2.
2 Guaranteed by design and characterization; not production tested.
3 A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the minimum VIH of the SCL signal) to bridge the undefined region of the
SCL falling edge.
4 tR and tF are measured from 0.3 × VDD to 0.7 × VDD
5 CB is the total capacitance of one bus line in pF.
.
6 Input filtering on the SCL and SDA inputs suppresses noise spikes that are less than 50 ns.
Timing Diagrams
START
REPEATED START
CONDITION
STOP
CONDITION
CONDITION
SDA
SCL
t9
t10
t11
t4
t3
t4
t2
t1
t6
t5
t7
t8
t12
1
2
t13
LDAC
LDAC
t12
NOTES
1
ASYNCHRONOUS LDAC UPDATE MODE.
SYNCHRONOUS LDAC UPDATE MODE.
2
Figure 2. 2-Wire Serial Interface Timing Diagram
t14
RESET
t15
V
x
OUT
RESET
Figure 3.
Timing Diagram
Rev. B | Page 8 of 32
Data Sheet
AD5671R/AD5675R
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
THERMAL RESISTANCE
The design of the thermal board requires close attention. Thermal
resistance is highly impacted by the printed circuit board (PCB)
being used, layout, and environmental conditions.
Table 6.
Parameter
Rating
VDD to GND
VLOGIC to GND
VOUTx to GND
VREFOUT to GND
Digital Input Voltage to GND
Operating Temperature Range
Storage Temperature Range
Junction Temperature
Reflow Soldering Peak Temperature,
Pb Free (J-STD-020)
−0.3 V to +7 V
−0.3 V to +7 V
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
−0.3 V to VLOGIC + 0.3 V
−40°C to +±25°C
−65°C to +±50°C
±25°C
Table 7.Thermal Resistance
Package Type
θJA
θJB
θJC
ΨJT
ΨJB
Unit
20-Lead TSSOP
(RU-20)±
98.65 44.39 ±7.58 ±.77 43.9 °C/W
20-Lead LFCSP
(CP-20-8)2
82
±6.67 32.5
0.43 22
°C/W
± Thermal impedance simulated values are based on a JEDEC 2S2P thermal
test board. See JEDEC JESD5±
260°C
2 Thermal impedance simulated values are based on a JEDEC 2S2P thermal
test board with nine thermal vias. See JEDEC JESD5±.
ESD
Human Body Model (HBM)
Field Induced Charged Device Model
(FICDM)
2 kV
±.5 kV
ESD CAUTION
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Rev. B | Page 9 of 32
AD5671R/AD5675R
Data Sheet
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
AD5671R/AD5675R
TOP VIEW
1
20
19
18
17
16
15
14
13
12
11
V
1
V
V
V
2
OUT
OUT
(Not to Scale)
2
V
0
3
OUT
OUT
3
V
DD
REFOUT
AD5671R/
AD5675R
TOP VIEW
(Not to Scale)
4
V
RESET
SDA
LOGIC
SCL
A0
5
15
V
REFOUT
V
1
2
3
4
5
6
LDAC
RSTSEL
GND
DD
14 RESET
13 SDA
V
LOGIC
SCL
7
A1
8
GAIN
A0
A1
12 LDAC
11 GND
9
V
7
6
V
V
4
5
OUT
OUT
OUT
10
V
OUT
NOTES
1. NIC = NO INTERNAL CONNECTION.
2. EXPOSED PAD. THE EXPOSED PAD MUST BE TIED TO GND.
Figure 4. TSSOP Pin Configuration
Figure 5. LFCSP Pin Configuration
Table 8. Pin Function Descriptions
Pin No.
TSSOP LFCSP Mnemonic Description
1
2
N/A1
3
19
20
0
VOUT
VOUT
EPAD
VDD
1
0
Analog Output Voltage from DAC 1. The output amplifier has rail-to-rail operation.
Analog Output Voltage from DAC 0. The output amplifier has rail-to-rail operation.
Exposed Pad. The exposed pad must be tied to GND.
Power Supply Input. These devices operate from 2.7 V to 5.5 V. Decouple the VDD supply with a 10 μF
capacitor in parallel with a 0.1 μF capacitor to GND.
1
4
5
2
3
VLOGIC
SCL
Digital Power Supply. The voltage on this pin ranges from 1.8 V to 5.5 V.
Serial Clock Line. In conjunction with the SDA line, this pin clocks data into or out of the 24-bit input shift
register.
6
7
8
4
5
A0
A1
GAIN
Address Input. Sets the first LSB of the 7-bit slave address.
Address Input. Sets the second LSB of the 7-bit slave address.
Span Set Pin. When this pin is tied to GND, all eight DAC outputs have a span from 0 V to VREF. If this pin is
tied to VLOGIC, all eight DACs output a span of 0 V to 2 × VREF
.
9
6
7
8
9
VOUT
VOUT
VOUT
VOUT
7
6
5
4
Analog Output Voltage from DAC 7. The output amplifier has rail-to-rail operation.
Analog Output Voltage from DAC 6. The output amplifier has rail-to-rail operation.
Analog Output Voltage from DAC 5. The output amplifier has rail-to-rail operation.
Analog Output Voltage from DAC 4. The output amplifier has rail-to-rail operation.
No Internal Connection.
Ground Reference Point for All Circuitry on the Device.
Power-On Reset Pin. Tie this pin to GND to power up all eight DACs to zero scale. Tie this pin to VLOGIC to
power up all eight DACs to midscale.
10
11
12
N/A1
13
14
10, 16 NIC
11
GND
RSTSEL
15
16
17
12
13
14
LDAC
Load DAC. LDAC operates in two modes, asynchronously and synchronously. Pulsing this pin low updates
any or all DAC registers if the input registers have new data, which simultaneously updates all DAC outputs.
This pin can also be tied permanently low.
Serial Data Input. In conjunction with the SCL line, this pin clocks data into or out of the 24-bit input shift
register. SDA is a bidirectional, open-drain data line that must be pulled to the supply with an external
pull-up resistor.
Asynchronous Reset Input. The RESET input is falling edge sensitive. When RESET is low, all LDAC pulses are
ignored. When RESET is activated, the input register and the DAC register are updated with zero scale or
midscale, depending on the state of the RSTSEL pin.
SDA
RESET
18
15
VREFOUT
Reference Output Voltage. When using the internal reference, this is the reference output pin. This pin is
the reference output by default.
19
20
17
18
VOUT
VOUT
3
2
Analog Output Voltage from DAC 3. The output amplifier has rail-to-rail operation.
Analog Output Voltage from DAC 2. The output amplifier has rail-to-rail operation.
1 N/A means not applicable.
Rev. B | Page 10 of 32
Data Sheet
AD5671R/AD5675R
TYPICAL PERFORMANCE CHARACTERISTICS
2.0
1.0
0.8
1.5
0.6
1.0
0.4
0.5
0.2
0
0
–0.2
–0.4
–0.6
–0.8
–1.0
–0.5
–1.0
–1.5
–2.0
0
10000
20000
30000
40000
50000
60000
70000
0
500
1000 1500 2000 2500 3000 3500 4000
CODE
CODE
Figure 6. AD5675R INL Error vs. Code
Figure 9. AD5671R DNL Error vs. Code
2.0
0.04
0.03
0.02
0.01
0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
–0.01
–0.02
0
500
1000 1500 2000 2500 3000 3500 4000
CODE
0
10000
20000
30000
40000
50000
60000
70000
CODE
Figure 7. AD5671R INL Error vs. Code
Figure 10. AD5675R TUE vs. Code
1.0
0.8
0.6
0.4
0.2
0
0.04
0.03
0.02
0.01
0
–0.2
–0.4
–0.6
–0.8
–1.0
–0.01
–0.02
0
500
1000 1500 2000 2500 3000 3500 4000
CODE
0
10000
20000
30000
40000
50000
60000
70000
CODE
Figure 8. AD5675R DNL Error vs. Code
Figure 11. AD5671R TUE vs. Code
Rev. B | Page ±± of 32
AD5671R/AD5675R
Data Sheet
10
10
8
8
6
6
4
4
2
2
0
0
–2
–4
–2
–4
–6
–8
–10
V
T
= 5V
= 25°C
V
T
= 5V
= 25°C
–6
–8
DD
DD
A
A
INTERNAL REFERENCE = 2.5V
INTERNAL REFERENCE = 2.5V
–10
–40
–20
0
20
40
60
80
100
120
–40
–20
0
20
40
60
80
100
120
120
120
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 12. AD5675R INL Error vs. Temperature
Figure 15. AD5671R DNL Error vs. Temperature
10
8
0.10
0.09
0.08
0.07
0.06
0.05
0.04
0.03
0.02
0.01
0
6
4
2
0
V
T
= 5V
= 25°C
DD
–2
–4
–6
–8
–10
A
INTERNAL REFERENCE = 2.5V
V
= 5V
= 25°C
DD
T
A
INTERNAL REFERENCE = 2.5V
–40
–20
0
20
40
60
80
100
2.7
3.2
3.7
4.2
4.7
5.2
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
Figure 16. AD5675R TUE vs. Temperature
Figure 13. AD5671R INL Error vs. Supply Voltage
0.10
0.09
0.08
0.07
0.06
0.05
0.04
0.03
0.02
0.01
0
10
8
6
4
2
0
V
T
= 5V
= 25°C
DD
–2
–4
–6
–8
–10
A
INTERNAL REFERENCE = 2.5V
V
T
= 5V
DD
= 25°C
A
INTERNAL REFERENCE = 2.5V
–40
–20
0
20
40
60
80
100
–40
–20
0
20
40
60
80
100
120
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 17. AD5671R TUE vs. Temperature
Figure 14. AD5675R DNL Error vs. Temperature
Rev. B | Page ±2 of 32
Data Sheet
AD5671R/AD5675R
10
0.10
0.08
0.06
0.04
0.02
0
8
6
4
2
0
–2
–4
–0.02
–0.04
–0.06
–0.08
–0.10
V
= 5V
= 25°C
V
= 5V
DD
–6
–8
DD
T
T = 25°C
A
A
INTERNAL REFERENCE = 2.5V
INTERNAL REFERENCE = 2.5V
–10
2.7
3.2
3.7
4.2
4.7
5.2
2.7
3.2
3.7
4.2
4.7
5.2
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
Figure 18. AD5675R INL Error vs. Supply Voltage
Figure 21. AD5675R TUE vs. Supply Voltage
10
8
0.10
0.08
0.06
0.04
0.02
0
6
4
2
0
–2
–4
–6
–8
–10
–0.02
–0.04
–0.06
–0.08
–0.10
V
= 5V
= 25°C
V
= 5V
DD
DD
T
T = 25°C
A
A
INTERNAL REFERENCE = 2.5V
INTERNAL REFERENCE = 2.5V
2.7
3.2
3.7
4.2
4.7
5.2
2.7
3.2
3.7
4.2
4.7
5.2
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
Figure 19. AD5675R DNL Error vs. Supply Voltage
Figure 22. AD5671R TUE vs. Supply Voltage
10
8
0.10
0.08
0.06
0.04
0.02
0
6
4
2
FULL-SCALE ERROR
GAIN ERROR
0
–2
–4
–6
–8
–10
–0.02
–0.04
–0.06
–0.08
–0.10
V
T
= 5V
= 25°C
DD
V
T
= 5V
= 25°C
DD
A
INTERNAL REFERENCE = 2.5V
A
INTERNAL REFERENCE = 2.5V
2.7
3.2
3.7
4.2
4.7
5.2
–40
–20
0
20
40
60
80
100
120
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
Figure 20. AD5671R DNL Error vs. Supply Voltage
Figure 23. AD5675R Gain Error and Full-Scale Error vs. Temperature
Rev. B | Page ±3 of 32
AD5671R/AD5675R
Data Sheet
0.10
0.08
0.06
0.04
0.02
0
1.8
1.5
1.2
0.9
0.6
0.3
0
V
T
= 5V
= 25°C
DD
A
INTERNAL REFERENCE = 2.5V
ZERO CODE ERROR
OFFSET ERROR
GAIN ERROR
–0.02
–0.04
–0.06
FULL-SCALE ERROR
V
= 5V
DD
–0.3
–0.08
–0.10
T = 25°C
A
INTERNAL REFERENCE = 2.5V
–0.6
–40
–20
0
20
40
60
80
100
120
–40
–20
0
20
40
60
80
100
120
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 27. AD5675R Zero-Code Error and Offset Error vs. Temperature
Figure 24. AD5671R Gain Error and Full-Scale Error vs. Temperature
1.8
0.10
0.08
0.06
0.04
0.02
V
T
= 5V
= 25°C
DD
1.5
1.2
0.9
0.6
0.3
0
A
INTERNAL REFERENCE = 2.5V
ZERO CODE ERROR
GAIN ERROR
OFFSET ERROR
0
–0.02
FULL-SCALE ERROR
–0.04
–0.06
V
= 5V
DD
–0.3
–0.6
–0.08
–0.10
T = 25°C
A
INTERNAL REFERENCE = 2.5V
–40
–20
0
20
40
60
80
100
120
2.7
3.2
3.7
4.2
4.7
5.2
TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
Figure 25. AD5675R Gain Error and Full-Scale Error vs. Supply Voltage
Figure 28. AD5671R Zero-Code Error and Offset Error vs. Temperature
0.10
0.08
0.06
0.04
0.02
1.5
1.0
ZERO CODE ERROR
0.5
OFFSET ERROR
0
–0.02
–0.04
–0.06
–0.08
–0.10
GAIN ERROR
0
FULL-SCALE ERROR
–0.5
–1.0
–1.5
V
= 5V
DD
= 25°C
V
= 5V
= 25°C
DD
T
T
A
A
INTERNAL REFERENCE = 2.5V
INTERNAL REFERENCE = 2.5V
2.7
3.2
3.7
4.2
4.7
5.2
2.7
3.2
3.7
4.2
4.7
5.2
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
Figure 29. AD5675R Zero-Code Error and Offset Error vs. Supply Voltage
Figure 26. AD5671R Gain Error and Full-Scale Error vs. Supply Voltage
Rev. B | Page ±4 of 32
Data Sheet
AD5671R/AD5675R
1.5
1.0
0.5
0
6
5
0xFFFF
0xC000
0x8000
ZERO CODE ERROR
OFFSET ERROR
4
3
2
0x4000
0x0000
1
–0.5
0
–1.0
–1.5
V
= 5V
DD
= 25°C
–1
–2
T
A
INTERNAL REFERENCE = 2.5V
2.7
3.2
3.7
4.2
4.7
5.2
–0.06
–0.04
–0.02
0
0.02
0.04
0.06
SUPPLY VOLTAGE (V)
LOAD CURRENT (A)
Figure 33. Source and Sink Capability at 5 V
Figure 30. AD5671R Zero-Code Error and Offset Error vs. Supply Voltage
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
70
V
= 5V
= 25°C
DD
T
A
60
50
40
30
20
10
0
INTERNAL REFERENCE = 2.5V
0xFFFF
0xC000
0x8000
0x4000
0x0000
–0.5
–1.0
–0.06
–0.04
–0.02
0
0.02
0.04
0.06
LOAD CURRENT (A)
I
FULL SCALE (µA)
DD
Figure 34. Source and Sink Capability at 3 V
Figure 31. Supply Current (IDD) Histogram with Internal Reference
1.6
1.5
1.4
1.3
1.2
1.1
1.0
1.4
DEVICE1
DEVICE2
DEVICE3
1.0
0.6
SINKING, V = –2.7V
DD
SINKING, V = –3.0V
DD
SINKING, V = –5.0V
DD
SOURCING, V = –5.0V
DD
SOURCING, V = –3.0V
DD
SOURCING, V = –2.7V
DD
0.2
–0.2
–0.6
–1.0
–1.4
0
10000
20000
30000
40000
50000
60000
70000
0
0.005
0.010
0.015
0.020
0.025
0.030
CODE
LOAD CURRENT (A)
Figure 35. Supply Current (IDD) vs. Code
Figure 32. Headroom/Footroom vs. Load Current
Rev. B | Page ±5 of 32
AD5671R/AD5675R
Data Sheet
2.0
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
1.8
FULL-SCALE
1.6
1.4
1.2
1.0
0.8
0.6
0.4
DAC 1
DAC 2
DAC 3
DAC 4
DAC 5
DAC 5
DAC 7
DAC 8
ZERO CODE
EXTERNAL REFERENCE, FULL-SCALE
V
= 5.5V
DD
GAIN = +1
INTERNAL REFERENCE = 2.5V
1/4 TO 3/4 SCALE
–40
–20
0
20
40
60
80
100
120
80
100
120
140
160
180
200
TEMPERATURE (°C)
TIME (µs)
Figure 36. Supply Current (IDD) vs. Temperature
Figure 39. Full-Scale Settling Time
6
5
0.006
0.005
0.004
0.003
0.002
0.001
0
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
V
V
(V)
DD
0 (V)
1 (V)
2 (V)
3 (V)
4 (V)
5 (V)
6 (V)
7 (V)
OUT
4
FULL-SCALE
V
OUT
V
V
OUT
3
OUT
V
OUT
ZERO CODE
V
OUT
2
V
V
OUT
OUT
EXTERNAL REFERENCE, FULL-SCALE
1
0
–1
–0.001
10
0
2
4
6
8
2.7
3.2
3.7
4.2
4.7
5.2
TIME (ms)
SUPPLY VOLTAGE (V)
Figure 37. Supply Current (IDD) vs. Supply Voltage
Figure 40. Power-On Reset to 0 V and Midscale
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
3.0
2.5
2.0
1.5
1.0
0.5
0
MIDSCALE, GAIN = 2
FULL-SCALE
ZERO CODE
MIDSCALE, GAIN = 1
EXTERNAL REFERENCE, FULL-SCALE
V
T
= 5V
= 25°C
DD
A
INTERNAL REFERENCE = 2.5V
2.7
3.2
3.7
4.2
4.7
5.2
–5
0
5 10
SUPPLY VOLTAGE (V)
TIME (µs)
Figure 41. Exiting Power-Down to Midscale
Figure 38. Supply Current (IDD) vs. Logic Input Voltage
Rev. B | Page ±6 of 32
Data Sheet
AD5671R/AD5675R
0.004
0.003
0.002
0.001
0
1
–0.001
–0.002
–0.003
–0.004
V
= 5V
DD
GAIN = 1
= 25°C
T
D
REFERENCE = 2.5V
CODE = 7FFF TO 8000
ENERGY = 1.209376nV-s
2
CH1 50.0mV
M1.00s
A
CH1
401mV
15
16
17
18
19
20
21
22
TIME (µs)
Figure 42. Digital-to-Analog Glitch Impulse
Figure 45. 0.1 Hz to 10 Hz Output Noise Plot
0.003
0.002
0.001
0
1200
1000
800
600
400
200
0
V
T
= 5V
= 25°C
DD
A
GAIN = 1
INTERNAL REFERENCE = 2.5V
–0.001
–0.002
–0.003
–0.004
–0.005
–0.006
FULL SCALE
MID SCALE
CHANNEL 1
CHANNEL 2
CHANNEL 3
CHANNEL 4
CHANNEL 5
CHANNEL 6
CHANNEL 7
ZERO SCALE
0
2
4
6
8
10
12
14
16
18
20
10
100
1k
10k
100k
1M
TIME (µs)
FREQUENCY (Hz)
Figure 46. Noise Spectral Density (NSD)
Figure 43. Analog Crosstalk
0
–20
0.012
0.010
0.008
0.006
0.004
0.002
0
V
= 5V
= 25°C
CHANNEL 1
CHANNEL 2
CHANNEL 3
CHANNEL 4
CHANNEL 5
CHANNEL 6
CHANNEL 7
DD
T
A
INTERNAL REFERENCE = 2.5V
–40
–60
–80
–100
–120
–140
–160
–180
–0.002
–0.004
–0.006
–0.008
–0.010
0
2
4
6
8
10
12
14
16
18
20
0
2
4
6
8
10
12
14
16
18
20
FREQUENCY (kHz)
TIME (µs)
Figure 44. DAC-to-DAC Crosstalk
Figure 47. Total Harmonic Distortion (THD) at 1 kHz
Rev. B | Page ±7 of 32
AD5671R/AD5675R
Data Sheet
2.0
1.9
1.8
1600
1400
1200
1000
800
600
400
200
0
V
A
= 5V
DD
T
= 25°C
C
C
C
C
C
= 0nF
= 0.1nF
= 1nF
= 4.7nF
= 10nF
L
L
L
L
L
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
10
100
1k
10k
100k
1M
0.10 0.11 0.12 0.13 0.14 0.15 0.16 0.17 0.18 0.19 0.20
TIME (ms)
FREQUENCY (Hz)
Figure 48. Settling Time vs. Capacitive Load
Figure 51. Internal Reference NSD vs. Frequency
2.0
2.5020
2.5015
2.5010
2.5005
2.5000
2.4995
2.4990
2.4985
2.4980
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
DEVICE1
DEVICE2
DEVICE3
DEVICE4
DEVICE5
DAC 1
DAC 2
DAC 3
DAC 4
DAC 5
DAC 6
DAC 7
DAC 8
–40
–20
0
20
40
60
80
100
120
80
100
120
140
160
180
200
TIME (µs)
TEMPERATURE (°C)
Figure 49. Settling Time, 5.5 V
Figure 52. Internal Reference Voltage (VREF) vs. Temperature (A Grade)
3
2
1
0
0.3
2.5020
DEVICE1
DEVICE2
DEVICE3
DEVICE4
DEVICE5
2.5015
2.5010
2.5005
2.5000
2.4995
2.4990
2.4985
2.4980
0.2
0.1
0
RESET
MIDSCALE, GAIN = 1
ZERO SCALE, GAIN = 1
–20
0
20
40
60
–40
–20
0
20
40
60
80
100
120
TIME (µs)
TEMPERATURE (°C)
Figure 53. Internal Reference Voltage (VREF) vs. Temperature (B Grade)
Figure 50. Hardware Reset
Rev. B | Page ±8 of 32
Data Sheet
AD5671R/AD5675R
2.5035
2.50050
2.50045
2.50040
2.50035
2.50030
2.50025
2.50020
2.50015
2.50010
T = 25°C
A
V
T
= 5V
= 25°C
DD
2.5030
2.5025
2.5020
2.5015
2.5010
2.5005
2.5000
2.4995
A
DEVICE1
DEVICE2
DEVICE3
–0.035 –0.025
–0.015 –0.005
0.005
0.015
0.025
0.035
2.5
3.0
3.5
4.0
4.5
5.0
5.5
LOAD CURRENT (A)
V
(V)
DD
Figure 54. Internal Reference Voltage (VREF) vs. Load Current and Supply
Voltage (VDD
Figure 55. Internal Reference Voltage (VREF) vs. Supply Voltage (VDD
)
)
Rev. B | Page ±9 of 32
AD5671R/AD5675R
Data Sheet
TERMINOLOGY
Relative Accuracy or Integral Nonlinearity (INL)
For the DAC, relative accuracy or integral nonlinearity is a
measurement of the maximum deviation, in LSBs, from a
straight line passing through the endpoints of the DAC transfer
function.
Digital-to-Analog Glitch Impulse
Digital-to-analog glitch impulse is the impulse injected into the
analog output when the input code in the DAC register changes
state. It is normally specified as the area of the glitch in nV-sec,
and is measured when the digital input code is changed by
1 LSB at the major carry transition (0x7FFF to 0x8000).
Differential Nonlinearity (DNL)
Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of 1 LSB maximum
ensures monotonicity. These DACs are guaranteed monotonic
by design.
Digital Feedthrough
Digital feedthrough is a measure of the impulse injected into the
analog output of the DAC from the digital inputs of the DAC,
but is measured when the DAC output is not updated. It is
specified in nV-sec, and measured with a full-scale code change
on the data bus, that is, from all 0s to all 1s and vice versa.
Zero-Code Error
Zero-code error is a measurement of the output error when
zero code (0x0000) is loaded to the DAC register. The ideal
output is 0 V. The zero-code error is always positive because the
output of the DAC cannot go below 0 V due to a combination of
the offset errors in the DAC and the output amplifier. Zero-
code error is expressed in mV.
Noise Spectral Density
Noise spectral density is a measurement of the internally
generated random noise. Random noise is characterized as a
spectral density (nV/√Hz). It is measured by loading the DAC
to midscale and measuring noise at the output. It is measured in
nV/√Hz.
Full-Scale Error
DC Crosstalk
Full-scale error is a measurement of the output error when full-
scale code (0xFFFF) is loaded to the DAC register. The ideal
output is VREF − 1 LSB (Gain = 1) or 2 × VREF (Gain = 2). Full-
scale error is expressed in percent of full-scale range (% of FSR).
DC crosstalk is the dc change in the output level of one DAC in
response to a change in the output of another DAC. It is measured
with a full-scale output change on one DAC (or soft power-down
and power-up) while monitoring another DAC kept at midscale.
It is expressed in μV.
Gain Error
Gain error is a measure of the span error of the DAC. It is the
deviation in slope of the DAC transfer characteristic from the
ideal expressed as % of FSR.
DC crosstalk due to load current change is a measure of the
impact that a change in load current on one DAC has on
another DAC kept at midscale. It is expressed in μV/mA.
Offset Error Drift
Digital Crosstalk
Offset error drift is a measurement of the change in offset error
with a change in temperature. It is expressed in µV/°C.
Digital crosstalk is the glitch impulse transferred to the output
of one DAC at midscale in response to a full-scale code change
(all 0s to all 1s and vice versa) in the input register of another
DAC. It is measured in standalone mode and is expressed in
nV-sec.
Offset Error
Offset error is a measure of the difference between VOUT (actual)
and VOUT (ideal) expressed in mV in the linear region of the
transfer function. Offset error is measured with Code 256
loaded in the DAC register. It can be negative or positive.
Analog Crosstalk
Analog crosstalk is the glitch impulse transferred to the output
of one DAC due to a change in the output of another DAC. It is
measured by first loading one of the input registers with a full-
scale code change (all 0s to all 1s and vice versa). Then, execute
DC Power Supply Rejection Ratio (PSRR)
The dc power supply rejection ratio indicates how the output of
the DAC is affected by changes in the supply voltage. PSRR is
the ratio of the change in VOUT to a change in VDD for full-scale
output of the DAC. It is measured in mV/V. VREF is held at 2 V,
and VDD is varied by 10%.
LDAC
a software
and monitor the output of the DAC whose
digital code was not changed. The area of the glitch is expressed
in nV-sec.
DAC-to-DAC Crosstalk
Output Voltage Settling Time
DAC-to-DAC crosstalk is the glitch impulse transferred to the
output of one DAC due to a digital code change and subsequent
analog output change of another DAC. It is measured by
loading the attack channel with a full-scale code change (all 0s
to all 1s and vice versa), using the write to and update commands
while monitoring the output of the victim channel that is at
midscale. The energy of the glitch is expressed in nV-sec.
The output voltage settling time is the amount of time it takes
for the output of a DAC to settle to a specified level for a ¼ to ¾
full-scale input change.
Rev. B | Page 20 of 32
Data Sheet
AD5671R/AD5675R
Multiplying Bandwidth
Voltage Reference Temperature Coefficient (TC)
The multiplying bandwidth is a measure of the finite bandwidth
of the amplifiers within the DAC. A sine wave on the reference
(with full-scale code loaded to the DAC) appears on the output.
The multiplying bandwidth is the frequency at which the output
amplitude falls to 3 dB below the input.
Voltage reference TC is a measure of the change in the reference
output voltage with a change in temperature. The reference TC
is calculated using the box method, which defines the TC as the
maximum change in the reference output over a given tempera-
ture range expressed in ppm/°C, as follows:
Total Harmonic Distortion (THD)
V
REF(MAX) −VREF(MIN)
TC =
×106
THD is the difference between an ideal sine wave and its
attenuated version using the DAC. The sine wave is used as the
reference for the DAC, and the THD is a measurement of the
harmonics present on the DAC output. It is measured in dB.
V
×TempRange
REF(NOM)
where:
REF (MAX) is the maximum reference output measured over the
total temperature range.
REF (MIN) is the minimum reference output measured over the
total temperature range.
REF (NOM) is the nominal reference output voltage, 2.5 V.
V
V
V
TempRange is the specified temperature range of −40°C to
+125°C.
Rev. B | Page 2± of 32
AD5671R/AD5675R
Data Sheet
THEORY OF OPERATION
V
REF
DIGITAL-TO-ANALOG CONVERTER (DAC)
The AD5671R/AD5675R are octal, 12-/16-bit, serial input, voltage
output DACs with an internal reference. The devices operate from
supply voltages of 2.7 V to 5.5 V. Data is written to the AD5671R/
AD5675R in a 24-bit word format via a 2-wire serial interface.
The AD5671R/AD5675R incorporate a power-on reset circuit
to ensure that the DAC output powers up to a known output
state. The devices also have a software power-down mode that
reduces the typical current consumption to 1 µA.
R
R
R
TO OUTPUT
AMPLIFIER
TRANSFER FUNCTION
The internal reference is on by default.
R
R
Gain is the gain of the output amplifier and is set to 1 by default.
This can be set to ×1 or ×2 using the gain select pin (GAIN). When
this pin is tied to GND, all eight DAC outputs have a span from
0 V to VREF. If this pin is tied to VLOGIC, all eight DACs output a
span of 0 V to 2 × VREF
.
Figure 57. Resistor String Structure
DAC ARCHITECTURE
Internal Reference
The AD5671R/AD5675R on-chip reference is enabled at power-up,
but can be disabled via a write to the control register. See the
Internal Reference and Amplifier Gain Selection section for
details.
The AD5671R/AD5675R implement segmented string DAC
architecture with an internal output buffer. Figure 56 shows the
internal block diagram.
V
REF
2.5V
REF
The AD5671R/AD5675R have a 2.5 V, 2 ppm/°C reference, giving
a full-scale output of 2.5 V or 5 V, depending on the state of the
GAIN pin. The internal reference associated with the device is
available at the VREFOUT pin. This buffered reference is capable of
driving external loads of up to 15 mA.
REF (+)
INPUT
REGISTER
DAC
REGISTER
RESISTOR
STRING
V
X
OUT
REF (–)
GAIN
(GAIN = 1 OR 2)
Output Amplifiers
GND
The output buffer amplifier generates rail-to-rail voltages on its
output, which gives an output range of 0 V to VDD. The actual
range depends on the value of VREF, the GAIN pin, the offset
error, and the gain error. The GAIN pin selects the gain of the
output. If the GAIN pin is tied to GND, all eight outputs have a
gain of 1, and the output range is 0 V to VREF. If the GAIN pin is
tied to VLOGIC, all eight outputs have a gain of 2, and the output
Figure 56. Single DAC Channel Architecture Block Diagram
The resistor string structure is shown in Figure 57. The code
loaded to the DAC register determines the node on the string
where the voltage is tapped off and fed into the output amplifier.
The voltage is tapped off by closing one of the switches and
connecting the string to the amplifier. Because each resistance
in the string has same value, R, the string DAC is guaranteed
monotonic.
range is 0 V to 2 × VREF
.
These amplifiers are capable of driving a load of 1 kΩ in parallel
with 10 nF to GND. The slew rate is 0.8 V/µs with a typical ¼ to
¾ scale settling time of 5 µs.
Rev. B | Page 22 of 32
Data Sheet
AD5671R/AD5675R
Table 9. Command Definitions
Command
SERIAL INTERFACE
The AD5671R/AD5675R use a 2-wire, I2C-compatible serial
interface. These devices can be connected to an I2C bus as a
slave device under the control of the master devices. The
AD5671R/AD5675R support standard (100 kHz) and fast
(400 kHz) data transfer modes. Support is not provided for
10-bit addressing and general call addressing.
C3 C2 C1 C0 Description
0
0
0
0
0
0
0
1
No operation
Write to Input Register n (dependent on
LDAC)
0
0
1
0
Update DAC Register n with contents of
Input Register n
Input Shift Register
0
0
0
0
0
1
1
1
0
1
1
1
1
0
0
0
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
Write to and update DAC Channel n
Power down/power up DAC
Hardware LDAC mask register
Software reset (power-on reset)
Internal reference and gain setup register
Reserved
Reserved
Update all channels of input register
simultaneously with the input data
The input shift register of the AD5671R/AD5675R is 24 bits wide.
Data is loaded MSB first (DB23), and the first four bits are the
command bits, C3 to C0 (see Table 9), followed by the 4-bit
DAC address bits, A3 to A0 (see Table 10), and finally, the bit
data-word.
The data-word comprises 16-bit or 12-bit input code, followed by
zero or four don’t care bits for the AD5675R and AD5671R,
respectively (see Figure 58 and Figure 59). These data bits are
transferred to the input register on the 24 falling edges of SCL.
1
0
1
1
Update all channels of DAC register and
input register simultaneously with the
input data
Commands execute on individual DAC channels, combined DAC
channels, or on all DACs, depending on the address bits selected.
1
1
0
0
Reserved
…
1
…
1
…
1
…
1
Reserved
Table 10. Address Commands
Channel Address[3:0]
A3
0
A2
0
A1
0
A0
0
Selected Channel1
DAC 0
0
0
0
1
DAC 1
0
0
1
0
DAC 2
0
0
1
1
DAC 3
0
1
0
0
DAC 4
0
1
0
1
DAC 5
0
1
1
0
DAC 6
0
1
1
1
DAC 7
1 Any combination of DAC channels can be selected using the address bits.
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
C3 C2 C1 C0 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
COMMAND
DAC ADDRESS
DAC DATA
DAC DATA
COMMAND BYTE
DATA HIGH BYTE
DATA LOW BYTE
Figure 58. AD5675R Input Shift Register Content
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
C3 C2 C1 C0 A3 A2 A1 A0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
X
X
X
X
COMMAND
DAC ADDRESS
DAC DATA
DAC DATA
COMMAND BYTE
DATA HIGH BYTE
DATA LOW BYTE
Figure 59. AD5671R Input Shift Register Content
Rev. B | Page 23 of 32
AD5671R/AD5675R
Data Sheet
WRITE AND UPDATE COMMANDS
Write to Input Register n (Dependent on
SERIAL OPERATION
The 2-wire I2C serial bus protocol operates as follows:
)
LDAC
Command 0001 allows the user to write the dedicated input
LDAC
1. The master initiates a data transfer by establishing a start
condition when a high to low transition on the SDA line
occurs while SCL is high. The following byte is the address
byte, which consists of the 7-bit slave address.
register of each DAC individually. When
register is transparent, if not controlled by the
is low, the input
LDAC
mask register.
Update DAC Register n with Contents of Input Register n
2. The slave device with the transmitted address responds by
pulling SDA low during the ninth clock pulse (this is called
the acknowledge bit, or ACK). At this stage, all other
devices on the bus remain idle while the selected device waits
for data to be written to or read from its input shift register.
3. Data is transmitted over the serial bus in sequences of nine
clock pulses (eight data bits followed by an acknowledge bit).
Transitions on the SDA line must occur during the low period
of SCL; SDA must remain stable during the high period of SCL.
4. After all data bits are read or written, a stop condition is
established. In write mode, the master pulls the SDA line high
during the 10th clock pulse to establish a stop condition. In
read mode, the master issues a no acknowledge (NACK)
for the ninth clock pulse (that is, the SDA line remains
high). The master then brings the SDA line low before the
10th clock pulse, and then high again during the 10th clock
pulse to establish a stop condition.
Command 0010 loads the DAC registers and outputs with the
contents of the input registers selected and updates the DAC
outputs directly.
Write to and Update DAC Channel n (Independent of
)
LDAC
Command 0011 allows the user to write to the DAC registers
and updates the DAC outputs directly.
I2C SLAVE ADDRESS
The AD5671R/AD5675R have a 7-bit I2C slave address. The five
MSBs are 00011, and the two LSBs (A1 and A0) are set by the
state of the A1 and A0 address pins. The ability to make hardwired
changes to A1 and A0 allows the user to incorporate up to four
AD5671R/AD5675R devices on one bus (see Table 11).
Table 11. Device Address Selection
A1 Pin Connection
A0 Pin Connection
A1
0
0
±
±
A0
0
±
0
±
GND
GND
VLOGIC
VLOGIC
GND
VLOGIC
GND
VLOGIC
WRITE OPERATION
When writing to the AD5671R/AD5675R, begin with a start
W
command followed by an address byte (R/ = 0), after which
the DAC acknowledges that it is prepared to receive data by pulling
SDA low. The AD5671R/AD5675R require two bytes of data for the
DAC, and a command byte that controls various DAC functions.
Three bytes of data must therefore be written to the DAC with
the command byte followed by the most significant data byte and
the least significant data byte, as shown in Figure 60. All these data
bytes are acknowledged by the AD5671R/AD5675R. A stop
condition follows.
1
9
1
9
SCL
0
0
0
1
1
A1
A0
R/W
ACK BY
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16
SDA
ACK BY
START BY
MASTER
AD5671R/AD5675R
AD5671R/AD5675R
FRAME 1
SLAVE ADDRESS
FRAME 2
COMMAND BYTE
1
9
1
9
SCL
(CONTINUED)
SDA
(CONTINUED)
DB15 DB14 DB13 DB12 DB11 DB10 DB9
DB7
DB6 DB5 DB4
DB3
DB2
DB1
DB0
DB8
ACK BY
AD5671R/AD5675R
ACK BY
STOP BY
AD5671R/AD5675R MASTER
FRAME 3
MOST SIGNIFICANT
DATA BYTE
FRAME 4
LEAST SIGNIFICANT
DATA BYTE
Figure 60. I2C Write Operation
Rev. B | Page 24 of 32
Data Sheet
AD5671R/AD5675R
READ OPERATION
MULTIPLE DAC READBACK SEQUENCE
When reading data back from the AD5671R/AD5675R, begin
When reading data back from multiple AD5671R/AD5675R
W
W
with a start command followed by an address byte (R/ = 0),
DACs, the user begins with an address byte (R/ = 0), after
after which the DAC acknowledges that it is prepared to receive
data by pulling SDA low. The address byte must be followed by
the command byte, which determines both the read command
that is to follow and the pointer address to read from; the
command byte is also acknowledged by the DAC. The user
configures the channel to read back the contents of one or more
DAC input registers and sets the read back command to active
using the command byte.
which the DAC acknowledges that it is prepared to receive data
by pulling SDA low. The address byte must be followed by the
command byte, which is also acknowledged by the DAC. The
user selects the first channel to read back using the command
byte.
Following this sequence, the master establishes a repeated start
W
condition, and the address is resent with R/ = 1. This byte is
acknowledged by the DAC, indicating that it is prepared to
transmit data. The first two bytes of data are then read from
DAC Input Register n (selected using the command byte), MSB
first, as shown in Figure 61. The next two bytes read back are the
contents of DAC Input Register n + 1, and the next bytes read
back are the contents of DAC Input Register n + 2. Data is read
from the DAC input registers in this autoincremented fashion
until a NACK followed by a stop condition follows. If the contents
of DAC Input Register 7 are read out, the next two bytes of data
read are the contents of DAC Input Register 0.
Then, the master establishes a repeated start condition, and the
W
address is resent with R/ = 1. This byte is acknowledged by the
DAC, indicating that it is prepared to transmit data. Two bytes
of data are then read from the DAC, as shown in Figure 61. A
NACK condition from the master, followed by a stop condition,
completes the read sequence. If more than one DAC is selected,
DAC 0 is read back by default.
1
9
1
9
SCL
SDA
0
0
0
1
1
A1
A0
R/W
ACK BY
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16
ACK BY
START BY
MASTER
AD5671R/AD5675R
AD5671R/AD5675R
FRAME 1
SLAVE ADDRESS
FRAME 2
COMMAND BYTE
1
9
1
9
SCL
SDA
0
0
0
1
1
A1
A0
R/W
ACK BY
DB15 DB14 DB13 DB12 DB11 DB10 DB9
DB8
REPEATED START BY
MASTER
ACK BY
MASTER
AD5671R/AD5675R
FRAME 3
SLAVE ADDRESS
FRAME 4
MOST SIGNIFICANT
DATA BYTE n
1
9
1
9
SCL
(CONTINUED)
SDA
(CONTINUED)
DB15 DB14 DB13 DB12 DB11 DB10 DB9
DB8
DB7 DB6
DB5 DB4
DB3 DB2
DB1
DB0
ACK BY
MASTER
NACK BY
MASTER
STOP BY
MASTER
FRAME 5
LEAST SIGNIFICANT
DATA BYTE n
FRAME 6
MOST SIGNIFICANT
DATA BYTE n + 1
Figure 61. I2C Read Operation
Rev. B | Page 25 of 32
AD5671R/AD5675R
Data Sheet
The bias generator, output amplifier, resistor string, and other
associated linear circuitry are shut down when power-down
mode is activated. However, the contents of the DAC registers
are unaffected in power-down mode, and the DAC registers can
be updated while the device is in power-down mode. The time
required to exit power-down is typically 2.5 µs for VDD = 5 V.
POWER-DOWN OPERATION
The AD5671R/AD5675R contain two separate power-down
modes. Command 0100 is designated for the power-down
function (see Table 9). These power-down modes are software
programmable by setting 16 bits, Bit DB15 to Bit DB0, in the
input shift register. There are two bits associated with each DAC
channel. Table 12 shows how the state of the two bits corresponds
to the mode of operation of the device.
LOAD DAC (HARDWARE LDAC PIN)
The AD5671R/AD5675R DACs have double buffered interfaces
consisting of two banks of registers: input registers and DAC
registers. The user can write to any combination of the input
registers. Updates to the DAC registers are controlled by
Any or all DACs (DAC 0 to DAC 7) power down to the selected
mode by setting the corresponding bits. See Table 13 for the
contents of the input shift register during the power-down/
power-up operation.
LDAC
the
Instantaneous DAC Updating (
For instantaneous updating of the DACs,
pin.
LDAC
Held Low)
Table 12. Modes of Operation
Operating Mode
Normal Operation
Power-Down Modes
± kΩ to GND
PD1
PD0
LDAC
is held low while
0
0
data is clocked into the input register using Command 0001. Both
the addressed input register and the DAC register are updated on
the 24th clock, and the output changes immediately.
0
±
±
±
Tristate
LDAC
Deferred DAC Updating (
is Pulsed Low)
LDAC
When both Bit PD1 and Bit PD0 in the input shift register are set
to 0, the device works normally with its normal power
For deferred updating of the DACs,
is held high while data
is clocked into the input register using Command 0001. All DAC
consumption of typically 1 mA at 5 V. However, for the two
power-down modes, the supply current falls to typically 1 µA.
In addition to this fall, the output stage switches internally from
the amplifier output to a resistor network of known values. This
has the advantage that the output impedance of the devices are
known while the devices are in power-down mode. There are
two different power-down options. The output is connected
internally to GND through either a 1 kΩ resistor, or it is left
open-circuited (tristate). The output stage is shown in Figure 62.
LDAC
outputs are asynchronously updated by pulling
low after the
LDAC
th
24 clock. The update occurs on the falling edge of
.
AMPLIFIER
12-/16-BIT
DAC
V
V
X
OUT
REF
DAC
REGISTER
LDAC
INPUT
REGISTER
AMPLIFIER
V
DAC
OUT
SCL
SDA
INTERFACE
LOGIC
POWER-DOWN
CIRCUITRY
RESISTOR
NETWORK
Figure 63. Simplified Diagram of Input Loading Circuitry for a Single DAC
Figure 62. Output Stage During Power-Down
Table 13. 24-Bit Input Shift Register Contents of Power-Down/Power-Up Operation
DAC 7
[DB15: B14] [DB13: B12] [DB11: B10] [DB9:DB8]
[PD±:PD0] [PD±:PD0] [PD±:PD0] [PD±:PD0]
DAC 6
DAC 5
DAC 4
DAC 3
DAC 2
DAC 1
DAC 0
[DB23:DB20]
DB19
[DB18:DB16]
XXX±
[DB7:DB6]
[PD±:PD0]
[DB5:DB4]
[PD±:PD0]
[DB3:DB2]
[PD±:PD0]
[DB1:DB0]
[PD±:PD0]
0±00
0
± X means don’t care.
Rev. B | Page 26 of 32
Data Sheet
AD5671R/AD5675R
LDAC
The
register gives the user extra flexibility and control
LDAC MASK REGISTER
LDAC
LDAC
pin (see Table 15). Setting the
over the hardware
bits (DB0 to DB7) to 0 for a DAC channel means that this
LDAC
LDAC
Command 0101 is reserved for this software
function.
The address bits are ignored. Writing to the DAC using
LDAC
channel update is controlled by the hardware
pin.
Command 0101 loads the 8-bit
The default for each channel is 0, that is, the
normally. Setting the bits to 1 forces this DAC channel to ignore
LDAC
register (DB7 to DB0).
LDAC
pin works
transitions on the
pin, regardless of the state of the
pin. This flexibility is useful in applications
where the user wants to select which channels respond to
LDAC
hardware
LDAC
the
pin.
LDAC
Table 14.
Overwrite Definition
Load LDAC Register
LDAC Bits (DB7 to DB0)
00000000
LDAC Pin
± or 0
X±
LDAC Operation
Determined by the LDAC pin.
DAC channels update and override the LDAC pin. DAC channels see LDAC as ±.
±±±±±±±±
± X means don’t care.
1
LDAC
Table 15. Write Commands and
Command Description
Pin Truth Table
Hardware LDAC Pin State
Input Register Contents
Data update
Data update
DAC Register Contents
No change (no update)
Data update
000±
Write to Input Register n
(dependent on LDAC)
VLOGIC
GND2
VLOGIC
GND
00±0
Update DAC Register n
with contents of Input
Register n
No change
Updated with input register contents
Updated with input register contents
No change
00±±
Write to and update DAC VLOGIC
Channel n
Data update
Data update
Data update
Data update
GND
±
LDAC
A high to low hardware
pin transition always updates the contents of the contents of the DAC register with the contents of the input register on channels that
LDAC
are not masked (blocked) by the mask register.
is permanently tied low, the LDAC mask bits are ignored.
2
LDAC
When
Rev. B | Page 27 of 32
AD5671R/AD5675R
Data Sheet
HARDWARE RESET (
)
SOLDER HEAT REFLOW
RESET
As with all IC reference voltage circuits, the reference value
experiences a shift induced by the soldering process. Analog
Devices, Inc., performs a reliability test called precondition to
mimic the effect of soldering a device to a board. The output
voltage specification quoted previously includes the effect of
this reliability test.
RESET
The
be cleared to either zero scale or midscale. The clear code value
RESET
pin is an active low reset that allows the outputs to
is user selectable via the RSTSEL pin. Keep
minimum time (see Table 5) to complete the operation. When
RESET
low for a
the
cleared value until a new value is programmed. While
RESET
signal is returned high, the output remains at the
Figure 64 shows the effect of solder heat reflow (SHR) as
measured through the reliability test (precondition).
the
pin is low, the outputs cannot be updated with a new
value. A software executable reset function is also available that
resets the DAC to the power-on reset code. Command 0110 is
designated for this software reset function. Any events
35
POSTSOLDER
HEAT REFLOW
30
LDAC RESET
on
or
during power-on reset are ignored.
PRESOLDER
HEAT REFLOW
25
20
15
10
5
RESET SELECT PIN (RSTSEL)
The AD5671R/AD5675R contain a power-on reset circuit that
controls the output voltage during power-up. By connecting the
RSTSEL pin low, the output powers up to zero scale. Note that
this power-up is outside the linear region of the DAC; by
connecting the RSTSEL pin high, VOUT powers up to midscale.
The output remains powered up at this level until a valid write
sequence is made to the DAC.
0
2.497
2.498
2.499
2.500
(V)
2.501
2.502
INTERNAL REFERENCE AND AMPLIFIER GAIN
SELECTION
V
REF
Figure 64. Solder Heat Reflow Reference Voltage Shift
The on-chip reference is on at power-up by default. To reduce
the supply current, turn off this reference by setting the software
programmable bit, DB0, in the internal reference and gain setup
register.
LONG-TERM TEMPERATURE DRIFT
Figure 65 shows the change in VREF value after 1000 hours in the
life test at 150°C.
70
The state of Bit DB2 in the internal reference and gain setup
register determines the output amplifier gain setting for the
LFCSP package (see Table 16 and Table 17). Ignore Bit DB2 for
the TSSOP package. Command 0111 is reserved for setting up the
internal reference and amplifier gain.
0 HOURS
168 HOURS
500 HOURS
1000 HOURS
60
50
40
30
20
10
0
Table 16. Internal Reference and Gain Setup Register
Bit
Description
DB2
Amplifier gain setting
DB2 = 0; amplifier gain = ± (default)
DB2 = ±; amplifier gain = 2
Reserved; set to 0
DB±
DB0
Internal reference
2.498
2.499
2.500
(V)
2.501
2.502
DB0 = 0; reference is on (default)
DB± = ±; reference is off
V
REF
Figure 65. Reference Drift Through to 1000 Hours
Rev. B | Page 28 of 32
Data Sheet
AD5671R/AD5675R
3
2
1
0
THERMAL HYSTERESIS
FIRST TEMPERATURE SWEEP
SUBSEQUENT TEMPERATURE SWEEPS
Thermal hysteresis is the voltage difference induced on the
reference voltage by sweeping the temperature from ambient to
cold, to hot, and then back to ambient.
Thermal hysteresis data is shown in Figure 66. It is measured by
sweeping the temperature from ambient to −40°C, then to +125°C,
and returning to ambient. The VREF delta is then measured
between the two ambient measurements and shown in blue in
Figure 66. The same temperature sweep and measurements
were immediately repeated, and the results are shown in red in
Figure 66.
–130 –110 –90 –70 –50 –30 –10
10
30
50
70
DISTORTION (ppm)
Figure 66. Thermal Hysteresis
Table 17. 24-Bit Input Shift Register Contents for Internal Reference and Amplifier Gain Setup Command1
DB23 (MSB) DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB1 to DB3 DB2
DB1
DB0 (LSB)
0
±
±
±
X
X
X
X
X
±/0
0
±/0
Command bits (C3 to C0)
Address bits (A3 to A0)
Don’t care
Amplifier
gain
Reserved Reference setup
register
± X means don’t care.
Rev. B | Page 29 of 32
AD5671R/AD5675R
Data Sheet
APPLICATIONS INFORMATION
series inductance (ESI), such as the common ceramic types,
POWER SUPPLY RECOMMENDATIONS
which provide a low impedance path to ground at high
frequencies to handle transient currents due to internal logic
switching.
The AD5671R/AD5675R is typically powered by the following
supplies: VDD = 3.3 V and VLOGIC = 1.8 V.
The ADP7118 can be used to power the VDD pin. The ADP160
can be used to power the VLOGIC pin. This setup is shown in
Figure 67. The ADP7118 can operate from input voltages up to
20 V. The ADP160 can operate from input voltages up to 5.5 V.
In systems where there are many devices on one board, it is
often useful to provide some heat sinking capability to allow
the power to dissipate easily.
The GND plane on the device can be increased (as shown in
Figure 69) to provide a natural heat sinking effect.
5V
INPUT
ADP7118
LDO
3.3V: V
DD
ADP160
LDO
AD5671R/
AD5675R
1.8V: V
LOGIC
Figure 67. Low Noise Power Solution for the AD5671R/AD5675R
MICROPROCESSOR INTERFACING
Microprocessor interfacing to the AD5671R/AD5675R is done
via a serial bus that uses a standard protocol that is compatible
with DSP processors and microcontrollers. The communications
channel requires a 2-wire interface consisting of a clock signal
and a data signal.
GND
PLANE
BOARD
AD5671R/AD5675R TO ADSP-BF531 INTERFACE
Figure 69. Pad Connection to Board
The I2C interface of the AD5671R/AD5675R is designed for
easy connection to industry-standard DSPs and microcontrollers.
Figure 68 shows the AD5671R/AD5675R connected to the Analog
Devices, Inc., Blackfin® processor. The Blackfin processor has
an integrated I2C port that can be connected directly to the I2C
pins of the AD5671R/AD5675R.
GALVANICALLY ISOLATED INTERFACE
In many process control applications, it is necessary to provide
an isolation barrier between the controller and the unit being
controlled to protect and isolate the controlling circuitry from
any hazardous common-mode voltages that may occur. iCoupler®
products from Analog Devices provide voltage isolation in excess
of 2.5 kV. The serial loading structure of the AD5671R/AD5675R
makes the devices ideal for isolated interfaces because the number
of interface lines is kept to a minimum. Figure 70 shows a
2-channel isolated interface to the AD5671R/AD5675R
using an ADuM1251. For further information, visit
AD5671R/
AD5675R
ADSP-BF531
GPIO1
GPIO2
SCL
SDA
www.analog.com/icoupler.
PF9
PF8
LDAC
RESET
ADuM12511
CONTROLLER
TO
DECODE
ENCODE
ENCODE
ENCODE
DECODE
DECODE
Figure 68. AD5671R/AD5675R to ADSP-BF531 Interface
SCL
LAYOUT GUIDELINES
TO
SDA
SDA
SCL
In any circuit where accuracy is important, careful consideration
of the power supply and ground return layout helps to ensure
the rated performance. Design the printed circuit board (PCB) on
which the AD5671R/AD5675R are mounted so that the devices
lie on the analog plane.
1
ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 70. Isolated Interface
The AD5671R/AD5675R must have ample supply bypassing of
10 µF in parallel with 0.1 µF on each supply, located as close to
the package as possible, ideally right up against the device. The
10 µF capacitors are tantalum bead type. The 0.1 µF capacitor
must have low effective series resistance (ESR) and low effective
Rev. B | Page 30 of 32
Data Sheet
AD5671R/AD5675R
OUTLINE DIMENSIONS
6.60
6.50
6.40
20
11
10
4.50
4.40
4.30
6.40 BSC
1
PIN 1
0.65
BSC
1.20 MAX
0.15
0.05
0.20
0.09
0.75
0.60
0.45
8°
0°
0.30
0.19
COPLANARITY
0.10
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-153-AC
Figure 71. 20-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-20)
Dimensions shown in millimeters
4.10
4.00 SQ
3.90
0.30
0.25
0.18
PIN 1
INDICATOR
PIN 1
INDICATOR
16
15
20
0.50
BSC
1
EXPOSED
PAD
2.75
2.60 SQ
2.35
11
5
6
10
0.50
0.40
0.30
0.25 MIN
TOP VIEW
BOTTOM VIEW
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.80
0.75
0.70
0.05 MAX
0.02 NOM
COPLANARITY
0.08
SECTION OF THIS DATA SHEET.
SEATING
PLANE
0.20 REF
COMPLIANT TO JEDEC STANDARDS MO-220-WGGD.
Figure 72. 20-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
4 mm × 4 mm Body, Very Very Thin Quad
(CP-20-8)
Dimensions shown in millimeters
ORDERING GUIDE
Temperature
Resolution Range
Reference Temperature
Coefficient (ppm/°C)
Package
Description
Package
Option
Model1
Accuracy
AD567±RBRUZ
AD567±RBRUZ-REEL7 ±2 Bits
AD567±RBCPZ-REEL7 ±2 Bits
AD567±RBCPZ-RL
AD5675RARUZ
AD5675RARUZ-REEL7 ±6 Bits
AD5675RBRUZ ±6 Bits
AD5675RBRUZ-REEL7 ±6 Bits
AD5675RACPZ-REEL7 ±6 Bits
AD5675RACPZ-RL
AD5675RBCPZ-REEL7 ±6 Bits
EVAL-AD5675RSDZ
±2 Bits
−40°C to +±25°C ±± LSB INL 2 (typical)
−40°C to +±25°C ±± LSB INL 2 (typical)
−40°C to +±25°C ±± LSB INL 2 (typical)
−40°C to +±25°C ±± LSB INL 2 (typical)
−40°C to +±25°C ±8 LSB INL 5 (typical)
−40°C to +±25°C ±8 LSB INL 5 (typical)
−40°C to +±25°C ±3 LSB INL 2 (typical)
−40°C to +±25°C ±3 LSB INL 2 (typical)
−40°C to +±25°C ±8 LSB INL 5 (typical)
−40°C to +±25°C ±8 LSB INL 5 (typical)
−40°C to +±25°C ±3 LSB INL 5 (typical)
20-Lead TSSOP
20-Lead TSSOP
20-Lead LFCSP_WQ
20-Lead LFCSP_WQ
20-Lead TSSOP
20-Lead TSSOP
20-Lead TSSOP
20-Lead TSSOP
20-Lead LFCSP_WQ
20-Lead LFCSP_WQ
20-Lead LFCSP_WQ
AD5675R Evaluation Board
RU-20
RU-20
CP-20-8
CP-20-8
RU-20
RU-20
RU-20
RU-20
±2 Bits
±6 Bits
CP-20-8
CP-20-8
CP-20-8
±6 Bits
± Z = RoHS Compliant Part.
Rev. B | Page 3± of 32
AD5671R/AD5675R
NOTES
Data Sheet
I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).
©2014–2015 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D12664-0-10/15(B)
Rev. B | Page 32 of 32
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