AD5683RBRMZ-3-RL7 [ADI]
Tiny 16-/14-/12-Bit SPI nanoDAC;
| 型号： | AD5683RBRMZ-3-RL7 |
| 厂家： | 
ADI |
| 描述： | Tiny 16-/14-/12-Bit SPI nanoDAC |
| 文件： | 总28页 (文件大小：882K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Tiny 16-/14-/12-Bit SPI nanoDAC+, with
2 (16-Bit) LSB INL and 2 ppm/°C Reference
AD5683R/AD5682R/AD5681R/AD5683
FUNCTIONAL BLOCK DIAGRAM
Data Sheet
FEATURES
V
*
V
V
DD
LOGIC
REF
Ultrasmall package: 2 mm × 2 mm, 8-lead LFCSP
High relative accuracy (INL): 2 LSB maximum at 16 bits
AD5683R/AD5682R/AD5681R
Low drift, 2.5 V reference: 2 ppm/°C typical
Selectable span output: 2.5 V or 5 V
AD5683
POWER-ON
RESET
AD5683R/
AD5682R/
AD5681R
2.5V
REF
LDAC
REF
DAC
REGISTER
OUTPUT
BUFFER
V
16-/14-/12-BIT
DAC
OUT
RESET
External reference only
Selectable span output: VREF or 2 × VREF
Total unadjusted error (TUE): 0.06% of FSR maximum
Offset error: 1.5 mV maximum
Gain error: 0.05% of FSR maximum
Low glitch: 0.1 nV-sec
INPUT
POWER-DOWN
CONTROL LOGIC
RESISTOR
NETWORK
CONTROL LOGIC
*NOT AVAILABLE IN ALL THE MODELS
GND
SYNC SCLK SDI SDO*
High drive capability: 20 mA
Figure 1. AD5683R/AD5682R/AD5681R MSOP
Low power: 1.2 mW at 3.3 V
(For more information, see the Functional Block Diagrams—LFCSP section.)
Independent logic supply: 1.62 V logic compatible
Wide operating temperature range: −40°C to +105°C
Robust 4 kV HBM ESD protection
APPLICATIONS
Process controls
Data acquisition systems
Digital gain and offset adjustment
Programmable voltage sources
GENERAL DESCRIPTION
Table 1. Single-Channel nanoDAC+ Portfolio
The AD5683R/AD5682R/AD5681R/AD5683, members of the
nanoDAC+® family, are low power, single-channel, 16-/14-/12-bit
buffered voltage out digital-to-analog converters (DACs). The
devices, except the AD5683, include an enabled by default internal
2.5 V reference, offering 2 ppm/°C drift. The output span can be
programmed to be 0 V to VREF or 0 V to 2 × VREF. All devices
operate from a single 2.7 V to 5.5 V supply and are guaranteed
monotonic by design. The devices are available in a 2.00 mm ×
2.00 mm, 8-lead LFCSP or a 10-lead MSOP.
Interface
Reference
Internal
External
Internal
External
16-Bit
14-Bit
12-Bit
SPI
AD5683R
AD5683
AD5693R
AD5693
AD5682R
AD5681R
I2C
AD5692R
AD5691R
PRODUCT HIGHLIGHTS
1. High Relative Accuracy (INL).
AD5683R/AD5683 (16-bit): 2 LSB maximum.
2. Low Drift, 2.5 V On-Chip Reference.
2 ppm/°C typical temperature coefficient.
5 ppm/°C maximum temperature coefficient.
3. Two Package Options.
The internal power-on reset circuit ensures that the DAC register
is written to zero scale at power-up while the internal output
buffer is configured in normal mode. The AD5683R/AD5682R
/AD5681R/AD5683 contain a power-down mode that reduces
the current consumption of the device to 2 µA (maximum) at 5 V
and provides software selectable output loads while in power-
down mode.
2.00 mm × 2.00 mm, 8-lead LFCSP.
10-lead MSOP.
The AD5683R/AD5682R/AD5681R/AD5683 use a versatile
3-wire serial interface that operates at clock rates of up to 50 MHz.
RESET
Some devices also include asynchronous
pin options, allowing 1.8 V compatibility.
pin and VLOGIC
Rev. D
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rightsof third parties that may result fromits use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks andregisteredtrademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2013–2016 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
AD5683R/AD5682R/AD5681R/AD5683
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Digital-to-Analog Converter .................................................... 19
Transfer Function....................................................................... 19
DAC Architecture....................................................................... 19
Serial Interface ................................................................................ 21
SPI Serial Data Interface............................................................ 21
Short Write Operation (AD5681R Only)................................ 21
Internal Registers........................................................................ 23
Commands.................................................................................. 23
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Functional Block Diagrams—LFCSP............................................. 3
Specifications..................................................................................... 4
AC Characteristics........................................................................ 6
Timing Characteristics ................................................................ 6
Absolute Maximum Ratings............................................................ 8
Thermal Resistance ...................................................................... 8
ESD Caution.................................................................................. 8
Pin Configurations and Function Descriptions ........................... 9
Typical Performance Characteristics ........................................... 11
Terminology .................................................................................... 17
Theory of Operation ...................................................................... 19
LDAC
Hardware
Hardware
......................................................................... 25
RESET
........................................................................ 25
Thermal Hysteresis .................................................................... 26
Power-Up Sequence ................................................................... 26
Recommended Regulator.......................................................... 26
Layout Guidelines....................................................................... 26
Outline Dimensions ....................................................................... 27
Ordering Guide .......................................................................... 28
REVISION HISTORY
12/2016—Rev. C to Rev. D
10/2014—Rev. A to Rev. B
Changed 1.8 V to 1.62 V, 1.8 V – 10% to 1.62 V, 5 V + 10% to 5.5 V,
and 1.8 V ≤ VLOGIC ≤ 2.7 V to 1.62 V ≤ VLOGIC ≤ 2.7 V.....Throughout
Changes to DC Power Supply Rejection Ratio, PSRR, Test
Conditions/Comments Column, Table 2......................................... 4
Changes to Table 1.............................................................................1
Changes to Figure 14...................................................................... 11
Added Recommended Regulator Section................................... 26
Changes to Ordering Guide.......................................................... 28
3/2016—Rev. B to Rev. C
1/2014—Rev. 0 to Rev. A
Changes to Features Section............................................................ 1
Changes to Specifications Section.................................................. 4
Changes to Table 2............................................................................ 5
Changes to AC Characteristics Section, Timing Characteristics
Section, and Table 4 .......................................................................... 6
Changes to Figure 4.......................................................................... 7
Changes to Table 7............................................................................ 9
Changes to Table 8.......................................................................... 10
Changes to Terminology Section.................................................. 17
Changes to SPI Serial Data Interface Section ............................. 21
Change to Features Section..............................................................1
Removed Endnote 2, Endnote 3, Endnote 5, and Endnote 6,
Table 2; Renumbered Sequentially..................................................5
Removed Endnote 2, Table 3; Renumbered Sequentially ............6
Removed Endnote 1, Table 4; Renumbered Sequentially ............6
Changes to Table 5.............................................................................8
Removed Solder Heat Reflow Section and Figure 53;
Renumbered Sequentially ............................................................. 25
12/2013—Revision 0: Initial Version
Rev. D | Page 2 of 28
Data Sheet
AD5683R/AD5682R/AD5681R/AD5683
FUNCTIONAL BLOCK DIAGRAMS—LFCSP
V
*
V
V
DD
LOGIC
REF
POWER-ON
RESET
AD5683R/
AD5682R/
AD5681R
2.5V
REF
LDAC*
REF
DAC
REGISTER
OUTPUT
BUFFER
V
16-/14-/12-BIT
DAC
OUT
RESET*
INPUT
CONTROL LOGIC
POWER-DOWN
CONTROL LOGIC
RESISTOR
NETWORK
*NOT AVAILABLE IN ALL THE MODELS
GND
SYNC SCLK SDI
Figure 2. AD5683R/AD5682R/AD5681R LFCSP
V
V
DD
REF
POWER-ON
RESET
AD5683
REF
16-BIT
DAC
REGISTER
OUTPUT
BUFFER
V
OUT
LDAC*
DAC
INPUT
CONTROL LOGIC
POWER-DOWN
CONTROL LOGIC
RESISTOR
NETWORK
SYNC SCLK SDI
GND
Figure 3. AD5683 LFCSP
Rev. D | Page 3 of 28
AD5683R/AD5682R/AD5681R/AD5683
SPECIFICATIONS
Data Sheet
VDD = 2.7 V to 5.5 V, RL = 2 kΩ to GND, CL = 200 pF to GND, VREF = 2.5 V, VLOGIC= 1.62 V to 5.5 V, −40°C < TA < +105°C, unless otherwise
noted.
Table 2.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
STATIC PERFORMANCE1
AD5683R
Resolution
Relative Accuracy, INL
A Grade
16
Bits
LSB
LSB
LSB
8
2
3
1
B Grade
Gain = 2
Gain = 1
Differential Nonlinearity, DNL
AD5683
LSB
Guaranteed monotonic by design
Resolution
Relative Accuracy, INL
16
Bits
LSB
LSB
LSB
2
3
1
Gain = 2
Gain =1
Differential Nonlinearity, DNL
AD5682R
Guaranteed monotonic by design
Resolution
14
12
Bits
LSB
LSB
Relative Accuracy, INL
Differential Nonlinearity, DNL
AD5681R
1
1
Guaranteed monotonic by design
Resolution
Bits
LSB
LSB
mV
mV
Relative Accuracy, INL
Differential Nonlinearity, DNL
Zero-Code Error
1
1
1.25
1.5
Guaranteed monotonic by design
All 0s loaded to DAC register
Offset Error
Full-Scale Error
Gain Error
Total Unadjusted Error, TUE
0.075
% of FSR All 1s loaded to DAC register
% of FSR
0.05
0.16
0.14
0.075
0.06
% of FSR Internal reference, gain = 1
% of FSR Internal reference, gain = 2
% of FSR External reference, gain = 1
% of FSR External reference, gain = 2
µV/°C
Zero-Code Error Drift
Offset Error Drift
1
1
µV/°C
Gain Temperature Coefficient
DC Power Supply Rejection Ratio, PSRR
OUTPUT CHARACTERISTICS
Output Voltage Range
1
0.2
ppm/°C
mV/V
DAC code = midscale; VDD = 5 V
0
0
VREF
2 × VREF
V
V
Gain = 1
Gain = 2
Capacitive Load Stability
2
nF
RL = ∞
10
nF
RL = 2 kΩ
Resistive Load
1
kΩ
CL = 0 µF
Load Regulation
10
10
30
20
µV/mA
µV/mA
mA
Ω
5 V, DAC code = midscale; −30 mA ≤ IOUT ≤ +30 mA
3 V, DAC code = midscale; −20 mA ≤ IOUT ≤ +20 mA
Short-Circuit Current
Load Impedance at Rails2
20
50
Rev. D | Page 4 of 28
Data Sheet
AD5683R/AD5682R/AD5681R/AD5683
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
REFERENCE OUTPUT
Output Voltage
Voltage Reference TC3
2.4975
2.5025
V
At ambient
See the Terminology section
A-Grade
B-Grade
5
2
20
5
ppm/°C
ppm/°C
Ω
µV p-p
nV/√Hz
µF
µV/mA
µV/mA
mA
Output Impedance
Output Voltage Noise
Output Voltage Noise Density
Capacitive Load Stability
Load Regulation Sourcing
Load Regulation Sinking
Output Current Load Capability
Line Regulation
0.05
16.5
250
5
50
30
5
80
125
25
0.1 Hz to 10 Hz
At ambient; f = 10 kHz, CL = 10 nF
RL = 2 kΩ
At ambient; VDD ≥ 3 V
At ambient
VDD ≥ 3 V
At ambient
First cycle
Additional cycles
µV/V
ppm
ppm
Thermal Hysteresis
REFERENCE INPUT
Reference Current
26
47
µA
µA
V
VREF = VDD =VLOGIC = 5 V, gain = 1
VREF = VDD =VLOGIC = 5 V, gain = 2
Reference Input Range
1
VDD
Reference Input Impedance
120
60
kΩ
kΩ
Gain = 1
Gain = 2
LOGIC INPUTS
IIN, Input Current
1
µA
V
V
Per pin
VINL, Input Low Voltage4
VINH, Input High Voltage4
CIN, Pin Capacitance
LOGIC OUTPUTS (SDO)5
Output Low Voltage, VOL
Output High Voltage, VOH
Pin Capacitance
0.3 ×VDD
0.7 × VDD
2
pF
0.4
V
V
pF
ISINK = 200 μA
ISOURCE = 200 μA
VDD − 0.4
1.62
4
POWER REQUIREMENTS
5
VLOGIC
ILOGIC
5.5
3
5.5
5.5
V
µA
V
5
0.25
VIH = VLOGIC or VIL = GND
Gain = 1
Gain = 2
VIH = VDD, VIL = GND
Internal reference enabled
Internal reference disabled
VDD
2.7
VREF + 1.5
V
6
IDD
Normal Mode7
350
110
500
180
2
µA
µA
µA
Power-Down Modes8
1 Linearity is calculated using a reduced code range: AD5683R and AD5683 (Code 512 to Code 65,535); AD5682R (Code 128 to Code 16,384); AD5681R (Code 32 to
Code 4096). Output unloaded.
2 When drawing a load current at either rail, the output voltage headroom, with respect to that rail, is limited by the 20 Ω typical channel resistance of the output
devices; for example, when sinking 1 mA, the minimum output voltage = 20 Ω, 1 mA generates 20 mV. See Figure 38 (Headroom/Footroom vs. Load Current).
3 Reference temperature coefficient is calculated as per the box method. See the Terminology section for more information.
4 Substitute VLOGIC for VDD if device includes a VLOGIC pin.
5 The VLOGIC and SDO pins are not available on all models.
6 If the VLOGIC pin is not available, IDD = IDD + ILOGIC
.
7 Interface inactive. DAC active. DAC output unloaded.
8 DAC powered down.
Rev. D | Page 5 of 28
AD5683R/AD5682R/AD5681R/AD5683
Data Sheet
AC CHARACTERISTICS
VDD = 2.7 V to 5.5 V, RL = 2 kΩ to GND, CL = 200 pF to GND, VREF = 2.5 V, VLOGIC= 1.62 V to 5.5 V, −40°C < TA < +105°C, unless otherwise
noted.1
Table 3.
Parameter
Output Voltage Settling Time2, 3
Typ
5
Max
Unit
µs
Test Conditions/Comments
7
Gain = 1
Slew Rate
0.7
0.1
0.1
−83
200
6
V/µs
nV-sec
nV-sec
dB
nV/√Hz
µV p-p
dB
Digital-to-Analog Glitch Impulse2
Digital Feedthrough2
Total Harmonic Distortion2
Output Noise Spectral Density
Output Noise
1 LSB change around major carry, gain = 2
VREF = 2 V 0.1 V p-p, frequency = 10 kHz
DAC code = midscale, 10 kHz
0.1 Hz to 10 Hz; internal reference, DAC = zero scale
At ambient, BW = 20 kHz, VDD = 5 V, fOUT = 1 kHz
At ambient, BW = 20 kHz, VDD = 5 V, fOUT = 1 kHz
At ambient, BW = 20 kHz, VDD = 5 V, fOUT = 1 kHz
SNR
90
SFDR
SINAD
88
82
dB
dB
1 Temperature range = −40°C to +105°C, typical at 25°C.
2 See the Terminology section.
3 AD5683R/AD5683 to 2 LSB, AD5682R to 1 LSB, AD5681R to 0.5 LSB.
TIMING CHARACTERISTICS
VDD = 2.7 V to 5.5 V, VLOGIC= 1.62 V to 5.5 V, −40°C < TA < +105°C, unless otherwise noted.
Table 4.
1.62 V ≤ VLOGIC ≤ 2.7 V 2.7 V ≤ VLOGIC2 ≤ 5.5 V Daisy Chain and Readback
Parameter 1
Symbol
t1
t2
t3
t4
Min
33
16
16
15
5
Typ Max
Min
20
10
10
10
5
Typ
Max
Min
40
20
20
20
5
Typ
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
SCLK Cycle Time
SCLK High Time
SCLK Low Time
SYNC to SCLK Falling Edge Setup Time
Data Setup Time
t5
t6
t7
Data Hold Time
5
5
5
SCLK Falling Edge to SYNC Rising Edge
Minimum SYNC High Time
SYNC Falling Edge to SCLK Fall Ignore
SDO Data Valid from SCLK Rising Edge
SYNC Rising Edge to SCLK Falling Edge
SYNC Rising Edge to SDO Disabled
SYNC Rising Edge to LDAC Falling Edge
LDAC Pulse Width Low
15
20
16
10
40
10
10
20
10
t8
t9
t10
t11
t12
t13
t14
t15
t16
t17
35
60
10
25
25
25
20
15
15
RESET Minimum Pulse Width Low
RESET Pulse Activation Time
75
75
75
150
1.9
150
1.7
150
1.7
SYNC Rising Edge to SYNC Rising Edge
(DAC Updates)
LDAC Falling Edge to SYNC Rising Edge
Reference Power-Up3
Exit Shutdown3
t18
1.8
1.65
1.65
µs
µs
µs
4
tREF_POWER_UP
tSHUTDOWN
600
6
600
600
5
6
6
1 All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.
2 Substitute VDD for VLOGIC on devices that do not include a VLOGIC pin.
3 Not shown in Figure 4.
4 Same timing must be expected when powering up the device after VDD = 2.7 V.
5
SYNC
Time required to exit power-down to normal mode of AD5683R/AD5682R/AD5681R operation;
rising edge to 90% of DAC midscale value, with output unloaded.
Rev. D | Page 6 of 28
Data Sheet
AD5683R/AD5682R/AD5681R/AD5683
Timing and Circuit Diagrams
t4
t7
t1
t9
t2
SCLK
SYNC
t11
t3
t8
t17
t5
t6
SDI
DB23
DB23
DB22
DB22
DB21
DB21
DB20
DB20
DB2
DB1
DB0
t12
t10
DB2
DB1
DB0
SDO
t13
t14
t18
LDAC
t15
RESET
t16
V
OUT
Figure 4. SPI Timing Diagram, Compatible with Mode 1 and Mode 2 (See the AN-1248 Application Note)
200µA
I
OL
TO OUTPUT
PIN
V
(MIN)
OH
C
L
90pF
200µA
I
OH
Figure 5. Load Circuit for Digital Output (SDO) Timing Specifications
Rev. D | Page 7 of 28
AD5683R/AD5682R/AD5681R/AD5683
Data Sheet
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Table 5.
Parameter
VDD to GND
VLOGIC to GND
VOUT to GND
Rating
−0.3 V to +7 V
−0.3 V to +7 V
−0.3 V to VDD + 0.3 V or +7 V
(whichever is less)
VREF to GND
−0.3 V to VDD + 0.3 V or +7 V
(whichever is less)
−0.3 V to VDD + 0.3 V or +7 V
(whichever is less)
THERMAL RESISTANCE
θJA is defined by the JEDEC JESD51 standard, and the value is
dependent on the test board and test environment.
Digital Input Voltage to GND1
Operating Temperature Range
Industrial
Table 6. Thermal Resistance1
Package Type
8-Lead LFCSP
10-Lead MSOP
−40°C to +105°C
−65°C to +150°C
135°C
(TJ max − TA)/θJA
4 kV
θJA
90
135
θJC
25
N/A
Unit
°C/W
°C/W
Storage Temperature Range
Junction Temperature (TJ max)
Power Dissipation
ESD2
1 JEDEC 2S2P test board, still air (0 m/sec airflow).
FICDM3
1.25 kV
ESD CAUTION
1 Substitute VDD with VLOGIC on devices that include a VLOGIC pin.
2 Human body model (HBM) classification.
3 Field-Induced Charged-Device Model classification.
Rev. D | Page 8 of 28
Data Sheet
AD5683R/AD5682R/AD5681R/AD5683
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
V
1
2
3
4
8
7
V
V
DD
OUT
REF
AD5681R/
AD5682R/
AD5683R/
AD5683
LDAC
GND
6 SDI
TOP VIEW
(Not to Scale)
5 SYNC
SCLK
NOTES
1. CONNECT THE EXPOSED PAD TO GND.
LDAC
Figure 6. Pin Configuration, 8-Lead LFCSP,
Option
V
1
2
3
4
8
7
6
5
V
V
DD
OUT
REF
V
LOGIC
GND
AD5683R-1/
AD5681R-1
TOP VIEW
(Not to Scale)
SDI
SYNC
SCLK
NOTES
1. CONNECT THE EXPOSED PAD TO GND.
Figure 7. Pin Configuration, 8-Lead LFCSP, VLOGIC Option
V
1
2
8
7
V
V
DD
OUT
RESET
REF
AD5683R-2
6 SDI
GND 3
TOP VIEW
(Not to Scale)
5 SYNC
SCLK 4
NOTES
1. CONNECT THE EXPOSED PAD TO GND.
RESET
Figure 8. Pin Configuration, 8-Lead LFCSP,
Option
Table 7. Pin Function Descriptions, 8-Lead LFCSP
Pin No.
LDAC
RESET
VLOGIC
1
N/A
Mnemonic Description
1
2
1
N/A
VDD
Power Supply Input. These devices can be operated from 2.7 V to 5.5 V. Decouple the supply to GND.
LDAC
LDAC can be operated in asynchronous mode (see Figure 4). Pulsing this pin low allows the DAC
register to be updated if the input register has new data. This pin can be tied permanently low; in
this case, the DAC is automatically updated when new data is written to the input register.
N/A
N/A
2
N/A
N/A
2
VLOGIC
RESET
Digital Power Supply. Voltage ranges from 1.62 V to 5.5 V.
Asynchronous Reset Input. The RESET input is low level sensitive. When RESET is low, all LDAC pulses
are ignored, the input and DAC registers are at their default values, and the output is connected to
GND. Data written to the AD5683R is ignored. If not used, this pin can be tied to VLOGIC
.
3
4
3
4
3
4
GND
SCLK
Ground Reference Point for All Circuitry on the Device.
Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock
input. Data can be transferred at rates of up to 50 MHz.
5
5
5
SYNC
Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC
goes low, it powers on the SCLK and SDI buffers and enables the input shift register. Data is
transferred in on the falling edges of the next 24 clocks.
6
7
6
7
6
7
SDI
VREF
Serial Data Input. This device has a 24-bit shift register. Data is clocked into the register on the
falling edge of the serial clock input.
AD5683R/AD5682R/AD5681R Reference Output. When using the internal reference, this is the
reference output pin. The default for this pin is as a reference output. It is recommended that this
pin be decoupled to GND with a 10 nF capacitor.
8
0
8
0
8
0
VOUT
EPAD
Analog Output Voltage from the DAC. The output amplifier has rail-to-rail operation.
Exposed Pad. Connect the exposed pad to GND.
Rev. D | Page 9 of 28
AD5683R/AD5682R/AD5681R/AD5683
Data Sheet
V
1
2
3
4
5
10
9
V
V
V
1
2
3
4
5
10
9
V
V
DD
OUT
REF
DD
OUT
RESET
SDO
V
AD5683R-3
AD5683R/
AD5681R
LOGIC
REF
8
SDI
RESET
LDAC
GND
8
SDI
TOP VIEW
(Not to Scale)
TOP VIEW
LDAC
GND
7
SYNC
SCLK
7
SYNC
SCLK
(Not to Scale)
6
6
Figure 10. Pin Configuration, 10-Lead MSOP, SDO Option
Figure 9. Pin Configuration, 10-Lead MSOP, VLOGIC Option
Table 8. Pin Function Descriptions, 10-Lead MSOP
VLOGIC
SDO
Mnemonic Description
1
2
3
1
N/A
2
VDD
VLOGIC
RESET
Power Supply Input. These devices can be operated from 2.7 V to 5.5 V. Decouple this pin to GND.
Digital Power Supply. Voltage ranges from 1.62 V to 5.5 V. Decouple this pin to GND.
Hardware Reset Pin. The RESET input is low level sensitive. When RESET is low, the device is reset and
external pins are ignored. The input and DAC registers are loaded with a zero-scale value, and the write
control register is loaded with default values. If not used, tie this pin to VLOGIC
.
N/A
4
3
4
SDO
LDAC
Serial Data Output. Can be used for daisy chaining or readback commands.
Load DAC. Transfers the content of the input register to the DAC register. It can be operated in
asynchronous mode (see Figure 4). This pin can be tied permanently low; in this case, the DAC register is
automatically updated when new data is written to the input register.
5
6
5
6
GND
SCLK
Ground Reference.
Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock
input. Data can be transferred at rates of up to 50 MHz.
7
7
SYNC
Synchronization Data Input. When SYNC goes low, it enables the SCLK and SDI buffers and the input
shift register.
8
9
8
9
SDI
VREF
Serial Data Input. Data is sampled on the falling edge of SCLK.
Reference Input/Output. When using the internal reference, this is the reference output pin. The default
for this pin is as a reference output. It is recommended that this pin be decoupled to GND with a 10 nF
capacitor.
10
10
VOUT
Analog Output Voltage from the DAC. The output amplifier has rail-to-rail operation.
Rev. D | Page 10 of 28
Data Sheet
AD5683R/AD5682R/AD5681R/AD5683
TYPICAL PERFORMANCE CHARACTERISTICS
2
2
V
= 5V
V
= 5V
DD
DD
T = 25°C
A
T
= 25°C
A
V
= 2.5V
V
= 2.5V
REF
REF
1
1
0
0
–1
–2
–1
–2
0
10000
20000
30000
CODE
40000
50000
60000 65535
0
10000
20000
30000
CODE
40000
50000
60000 65535
Figure 11. AD5683R/AD5683 INL
Figure 14. AD5683R/AD5683 DNL
2
1
1.0
0.8
V
T
= 5V
= 25°C
= 2.5V
V
= 5V
DD
DD
= 25°C
T
A
A
V
V
= 2.5V
REF
REF
0.6
0.4
0.2
0
0
–0.2
–0.4
–0.6
–0.8
–1.0
–1
–2
0
2000 4000 6000 8000 10000 12000 14000
CODE
16383
0
2000 4000 6000 8000 10000 12000 14000
CODE
16383
Figure 12. AD5682R INL
Figure 15. AD5682R DNL
2.0
1.5
1.0
0.8
V
T
V
= 5V
= 25°C
V
= 5V
= 25°C
= 2.5V
DD
DD
T
A
A
= 2.5V
V
REF
REF
0.6
1.0
0.4
0.5
0.2
0
0
–0.2
–0.4
–0.6
–0.8
–1.0
–0.5
–1.0
–1.5
–2.0
0
500
1000 1500 2000 2500 3000 3500 4000
0
500
1000 1500 2000 2500 3000 3500 4000
CODE
CODE
Figure 13. AD5681R INL
Figure 16. AD5681R DNL
Rev. D | Page 11 of 28
AD5683R/AD5682R/AD5681R/AD5683
Data Sheet
1.2
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
V
V
= 5V
U1_DNL
U3_DNL
U2_INL
U2_DNL
U1_INL
U3_INL
V
= 5V
DD
DD
T = 25°C
A
= 2.5V
REF
1.0
0.8
0.6
0.4
0.2
0
U1_DNL_INT
U3_DNL_INT
U2_DNL_EXT
U1_INL_INT
U3_INL_INT
U2_INL_EXT
U2_DNL_INT
U1_DNL_EXT
U3_DNL_EXT
U2_INL_INT
U1_INL_EXT
U3_INL_EXT
–0.2
–0.2
2
3
4
5
–40
–20
0
20
40
60
80
105
V
(V)
TEMPERATURE (°C)
REF
Figure 17. INL and DNL Error vs. Temperature (AD5683R/AD5683)
Figure 20. INL Error and DNL Error vs. VREF (AD5683R/AD5683)
0.02
0.01
0
1.4
U1_DNL_INT
U3_DNL_INT
U2_DNL_EXT
U1_INL_INT
U3_INL_INT
U2_INL_EXT
U2_DNL_INT
U1_DNL_EXT
U3_DNL_EXT
U2_INL_INT
U1_INL_EXT
U3_INL_EXT
T
= 25°C
A
1.2
1.0
0.8
0.6
0.4
0.2
0
–0.01
–0.02
–0.03
–0.04
0
0
0
10000
2000
500
20000
4000
1000
30000
6000
1500
40000
8000
2000
50000
10000
2500
60000 65535 (AD5683/AD5683R)
12000 16383 (AD5682R)
3000 4095 (AD5681R)
CODE
–0.2
2.70
3.30
3.75
4.25
(V)
4.75
5.25
V
DD
Figure 18. INL and DNL Error vs. Supply Voltage
Figure 21. TUE vs. Code
0.06
0.04
0.02
0
0.04
0.03
0.02
0.01
0
T
= 25°C
U1_EXT
U2_EXT
U3_EXT
U1_INT
U2_INT
U3_INT
V
= 5V
A
DD
GAIN = 1
= 2.5V
GAIN = 1
V
= 2.5V
V
REF
REF
–0.02
–0.04
–0.01
–0.02
U1_INT
U2_INT
U3_INT
U1_EXT
U2_EXT
U3_EXT
2.70
3.30
3.75
4.25
(V)
4.75
5.25
–40
0
40
TEMPERATURE (°C)
80
V
DD
Figure 22. TUE vs. Supply
Figure 19. TUE vs. Temperature
Rev. D | Page 12 of 28
Data Sheet
AD5683R/AD5682R/AD5681R/AD5683
0.030
0.03
0.02
0.01
0
T
= 25°C
A
GAIN = 1
V
0.025
0.020
0.015
0.010
0.005
0
= 2.5V
REF
–0.01
–0.005
–0.010
–0.015
–0.020
–0.025
U1_INT
–0.02
–0.03
–0.04
U2_INT
U3_INT
U1_EXT
U2_EXT
U3_EXT
V
= 5V
U1_INT
U2_INT
U3_INT
U1_EXT
U2_EXT
U3_EXT
DD
GAIN = 1
= 2.5V
V
REF
2.70
3.30
3.75
4.25
(V)
4.75
5.25
5.50
–40
0
40
TEMPERATURE (°C)
80
V
DD
Figure 23. Gain Error and Full-Scale Error vs. Temperature
Figure 26. Gain Error and Full-Scale Error vs. Supply
500
400
300
200
100
0
350
300
250
200
150
100
50
V
= 5V
U1_INT
U2_INT
U3_INT
U1_EXT
U2_EXT
U3_EXT
T = 25°C
A
GAIN = 1
DD
GAIN = 1
= 2.5V
V
V
= 2.5V
REF
REF
U1_INT
U2_INT
U3_INT
U1_EXT
U2_EXT
U3_EXT
0
2.70
3.30
3.75
4.25
(V)
4.75
5.25
5.50
–40
–20
0
20
40
60
80
105
V
TEMPERATURE (°C)
DD
Figure 24. Zero Code Error and Offset Error vs. Temperature
Figure 27. Zero Code Error and Offset Error vs. Supply
2.505
2.503
2.501
2.499
2.497
2.495
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
V
= 5V
U1
U2
U3
V
T
= 5V
DD
DD
= 25°C
A
GAIN = 1
–40
10
TEMPERATURE (°C)
60
V
(V)
REF
Figure 25. Internal Reference Voltage vs. Temperature (Grade B)
Figure 28. Reference Output Spread
Rev. D | Page 13 of 28
AD5683R/AD5682R/AD5681R/AD5683
Data Sheet
2.50015
2.5009
2.5008
2.5007
2.5006
2.5005
2.5004
2.5003
5.5V
5.0V
3.0V
2.7V
T
= 25°C
T
= 25°C
A
A
2.50010
2.50005
2.50000
2.49995
2.49990
2.49985
2.49980
D11
D12
D13
2.5
3.5
4.5
5.5
–0.005
–0.003
–0.001
0.001
0.003
0.005
V
(V)
DD
LOAD CURRENT (A)
Figure 29. Internal Reference Voltage vs. Supply Voltage
Figure 32. Internal Reference Voltage vs. Load Current
1800
1600
1400
1200
1000
800
600
400
200
0
V
= 5V
T
DD
= 25°C
T
V
= 25°C
A
T
A
= 5V
DD
1
CH1 10µV
M1.00s
A
CH1
2.00µV
10
100
1k
10k
100k
1M
FREQUENCY (Hz)
Figure 30. Internal Reference Noise, 0.1 Hz to 10 Hz
Figure 33. Internal Reference Noise Spectral Density vs. Frequency
T
T
T
V
= 25°C
T
V
= 25°C
= 5V
A
A
= 5V
DD
DD
1
1
CH1 10µV
M1.00s
A
CH1
2.00µV
CH1 10µV
M1.00s
A
CH1
2.00µV
Figure 34. 0.1 Hz to 10 Hz Output Noise Plot, External Reference
Figure 31. 0.1 Hz to 10 Hz Output Noise Plot, Internal Reference On
Rev. D | Page 14 of 28
Data Sheet
AD5683R/AD5682R/AD5681R/AD5683
1200
1000
800
1.4
V
= 5V
FULL-SCALE
MIDSCALE
ZEROSCALE
DD
= 25°C
SINKING, V = 3V
DD
T = 25°C
A
T
A
SOURCING, V = 5V
DD
GAIN = 1
1.0
0.6
SINKING, V = 5V
DD
SOURCING, V = 3V
DD
0.2
600
–0.2
–0.6
–1.0
–1.4
400
200
0
10
100
1k
10k
100k
1M
0
0.01
0.02
0.03
FREQUENCY (Hz)
LOAD CURRENT (A)
Figure 35. Noise Spectral Density vs. Frequency, Gain = 1
Figure 38. Headroom/Footroom vs. Load Current
6
5
7
V
T
= 5V
V
T
= 5V
0xFFFF
0xC000
0x8000
0x4000
0x0000
0xFFFF
0xC000
0x8000
0x4000
0x0000
DD
= 25°C
DD
= 25°C
A
A
6
5
GAIN = 1
GAIN = 2
4
4
3
3
2
2
1
1
0
0
–1
–1
–2
–50
0
50
–50
0
50
LOAD CURRENT (mA)
LOAD CURRENT (mA)
Figure 36. Source and Sink Capability, Gain = 1
Figure 39. Source and Sink Capability, Gain = 2
0.0015
0.0010
0.0005
0
500
450
400
350
300
250
200
150
100
50
V
= 5V
GAIN = 1
GAIN = 2
DD
V
T
= 5V
DD
= 25°C
A
REFERENCE = 2.5V
CODE = 0x7FFF TO 0x8000
ZS_INT_GAIN = 1
FS_EXT_GAIN = 2
FS_INT_GAIN = 2
ZS_INT_GAIN = 2
FS_INT_GAIN = 1
FS_EXT_GAIN = 1
–0.0005
–0.0010
–0.0015
–0.0020
–0.0025
0
–40
–20
0
20
40
60
80
105
0
1
2
3
4
5
6
7
TEMPERATURE (°C)
TIME (µs)
Figure 37. Supply Current vs. Temperature
Figure 40. Digital-to-Analog Glitch Impulse
Rev. D | Page 15 of 28
AD5683R/AD5682R/AD5681R/AD5683
Data Sheet
2.5
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
0nF
0.2nF
1nF
4.7nF
10nF
0nF
0.2nF
1nF
4.7nF
10nF
2.0
1.5
1.0
V
= 5V
V
= 5V
DD
= 25°C
DD
T = 25°C
A
0.5
0
T
A
GAIN = 1
R
INTERNAL REFERENCE = 2.5V
GAIN = 2
R = 2kΩ
L
INTERNAL REFERENCE = 2.5V
= 2kΩ
L
0
0.01
TIME (ms)
0.02
0
0.01
TIME (ms)
0.02
Figure 41. Capacitive Load vs. Settling Time, Gain = 1
Figure 44. Capacitive Load vs. Settling Time, Gain = 2
0
–10
–20
–30
–40
–50
–60
–70
–80
20
V
= 5V
= 25°C
GAIN = 2
GAIN = 1
DD
T
A
INTERNAL REFERENCE = 2.5V
–30
–80
–130
–180
V
= 5V
= 25°C
DD
T
A
V
= MIDSCALE
EXTERNAL REFERENCE = 2.5V, ±0.1V p-p
OUT
1k
10k
100k
1M
10M
0
5
10
15
20
FREQUENCY (Hz)
FREQUENCY (kHz)
Figure 45. Multiplying Bandwidth, External Reference 2.5 V 0.1 V p-p,
10 kHz to 10 MHz
Figure 42. Total Harmonic Distortion at 1 kHz
6
5
4
3
2
1
0
0.06
0.05
0.04
0.03
0.02
0.01
0
3
V
= 5V
DD
= 25°C
T
A
MIDSCALE, GAIN = 2
2
1
0
V
DD
SYNC
MIDSCALE, GAIN = 1
V
OUT
–1
0
–0.01
1
2
3
4
5
6
7
8
–5
0
5
10
15
TIME (ms)
TIME (µs)
Figure 43. Power-On Reset to 0 V
Figure 46. Exiting Power-Down to Midscale
Rev. D | Page 16 of 28
Data Sheet
AD5683R/AD5682R/AD5681R/AD5683
TERMINOLOGY
Relative Accuracy or Integral Nonlinearity (INL)
For the DAC, relative accuracy or integral nonlinearity is a
measurement of the maximum deviation, in LSBs, from a straight
line passing through the endpoints of the DAC transfer function.
See Figure 11, Figure 12, and Figure 13 for typical INL vs.
code plots.
Output Voltage Settling Time
Output voltage settling time is the amount of time it takes for
the output of a DAC to settle to a specified level for a ¼ to ¾
scale input change.
Digital-to-Analog Glitch Impulse
Digital-to-analog glitch impulse is the impulse injected into the
analog output when the input code in the DAC register changes
state. It is normally specified as the area of the glitch in nV-sec
and is measured when the digital input code is changed by 1 LSB
at the major carry transition (0x7FFF to 0x8000), as shown in
Figure 40.
Differential Nonlinearity (DNL)
Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of 1 LSB maximum
ensures monotonicity. This DAC is guaranteed monotonic by
design. See Figure 14, Figure 15, and Figure 16 for typical DNL
vs. code plots.
Digital Feedthrough
Digital feedthrough is a measure of the impulse injected into
the analog output of the DAC from the digital inputs of the
DAC, but it is measured when the DAC output is not updated.
Digital feedthrough is specified in nV-sec and measured with
a full-scale code change on the data bus, that is, from all 0s to all
1s and vice versa.
Zero Code Error
Zero code error is a measurement of the output error when zero
code (0x0000) is loaded to the DAC register. Ideally, the output
must be 0 V. The zero code error is always positive in the
AD5683R/AD5682R/AD5681R because the output of the DAC
cannot fall below 0 V due to a combination of the offset errors
in the DAC and the output amplifier. Zero code error is expressed
in mV. A plot of zero code error vs. temperature is shown in
Figure 24.
Reference Feedthrough
Reference feedthrough is the ratio of the amplitude of the signal
at the DAC output to the reference input when the DAC output
is not being updated. It is expressed in dB.
Full-Scale Error
Output Noise Spectral Density
Full-scale error is a measurement of the output error when full-
scale code (0xFFFF) is loaded to the DAC register. Ideally, the
output must be VREF – 1 LSB or |2 × VREF| – 1 LSB. Full-scale error is
expressed in percent of full-scale range (% of FSR). See Figure 23
and Figure 26 for plots of full-scale error.
Noise spectral density is a measurement of the internally generated
random noise. Random noise is characterized as a spectral density
(nV/√Hz). It is measured by loading the DAC to midscale and
measuring noise at the output. It is measured in nV/√Hz. See
Figure 31, Figure 34, and Figure 35 for a plot of noise spectral
density. The noise spectral density for the internal reference is
shown in Figure 30 and Figure 33.
Gain Error
Gain error is a measure of the span error of the DAC. It is the
deviation in slope of the DAC transfer characteristic from the
ideal expressed as % of FSR.
Multiplying Bandwidth
The amplifiers within the DAC have a finite bandwidth. The
multiplying bandwidth is a measure of this finite bandwidth.
A sine wave on the reference (with full-scale code loaded to the
DAC) appears on the output. The multiplying bandwidth is the
frequency at which the output amplitude falls to 3 dB below
the input.
Zero-Code Error Drift
Zero-code error drift is a measurement of the change in zero-
code error with a change in temperature. It is expressed in µV/°C.
Gain Temperature Coefficient
Gain temperature coefficient is a measurement of the change in
gain error with changes in temperature. It is expressed in ppm
of FSR/°C.
Total Harmonic Distortion (THD)
THD is the difference between an ideal sine wave and the
attenuated version using the DAC. The sine wave is used as the
reference for the DAC, and the THD is a measurement of the
harmonics present on the DAC output. It is measured in dB.
Offset Error
Offset error is a measure of the difference between VOUT (actual)
and VOUT (ideal) expressed in mV in the linear region of the
transfer function. Offset error is measured on the AD5683R with
Code 512 loaded in the DAC register. It can be negative or positive.
DC Power Supply Rejection Ratio (PSRR)
PSRR indicates how the output of the DAC is affected by changes
in the supply voltage. PSRR is the ratio of the change in VOUT to
a change in VDD for mid-scale output of the DAC. It is measured
in dB. VREF is held at 2 V, and VDD is varied by 10%.
Rev. D | Page 17 of 28
AD5683R/AD5682R/AD5681R/AD5683
Data Sheet
Voltage Reference Temperature Coefficient (TC)
Thermal Hysteresis
Voltage reference TC is a measure of the change in the reference
output voltage with a change in temperature. The reference TC
is calculated using the box method, which defines the TC as the
maximum change in the reference output over a given tempera-
ture range expressed in ppm/°C, as follows:
Thermal hysteresis is the voltage difference induced on the
reference voltage by sweeping the temperature from ambient
to cold, to hot, and then back to ambient.
VREFmax −VREFmin
TC =
×106
V
×TempRange
REFnom
where:
REFmax is the maximum reference output measured over the
total temperature range.
REFmin is the minimum reference output measured over the total
temperature range.
REFnom is the nominal reference output voltage, 2.5 V.
V
V
V
TempRange is the specified temperature range, −40°C to
+105°C.
Rev. D | Page 18 of 28
Data Sheet
AD5683R/AD5682R/AD5681R/AD5683
THEORY OF OPERATION
The simplified segmented resistor string DAC structure is
shown in Figure 48. The code loaded to the DAC register
determines the switch on the string that is connected to the
output buffer.
DIGITAL-TO-ANALOG CONVERTER
The AD5683R/AD5682R/AD5681R are single 16-bit, 14-bit, and
12-bit, serial input, voltage output DACs with a 2.5 V internal
reference. The devices operate from supply voltages of 2.7 V to
5.5 V. Data is written to the AD5683R/AD5682R/AD5681R in
a 24-bit word format via a 3-wire serial interface. The AD5683R/
AD5682R/AD5681R incorporate a power-on reset circuit that
ensures that the DAC output powers up to a zero scale. The devices
also have a software power-down mode that reduces the typical
current consumption to 2 µA maximum.
Because each resistance in the string has same value, R, the
string DAC is guaranteed monotonic.
V
REF
R
R
TRANSFER FUNCTION
The internal reference is on by default. For users that need an
external reference, the AD5683 is available. The input coding to
the DAC is straight binary. The ideal output voltage is given by
the following equations:
TO OUTPUT
BUFFER
R
For the AD5683R,
R
R
D
65,536
V
OUT(D) = Gain × VREF
×
×
×
For the AD5682R,
D
16,384
VOUT(D) = Gain × VREF
Figure 48. Simplified Resistor String Structure
For the AD5681R,
Internal Reference
D
4096
VOUT(D) = Gain × VREF
The AD5683R/AD5682R/AD5681R on-chip reference is on at
power-up but can be disabled via a write to the write control
register.
where:
D is the decimal equivalent of the binary code that is loaded to
The AD5683R/AD5682R/AD5681R each have a 2.5 V, 2 ppm/°C
reference, giving a full-scale output of 2.5 V or 5 V, depending
on the state of the gain bit.
the DAC register.
Gain is the gain of the output amplifier. By default, it is set to
×1. The gain can also be set to ×2 using the gain bit in the write
control register.
The internal reference is available at the VREF pin. It is internally
buffered and capable of driving external loads of up to 50 mA.
DAC ARCHITECTURE
External Reference
The AD5683R/AD5682R/AD5681R/AD5683 implements
segmented string DAC architecture with an internal output
buffer. Figure 47 shows the internal block diagram.
The VREF pin is an input pin in the AD5683. It can also be con-
figured as an input pin on the AD5683R/AD5682R/AD5681R,
allowing the use of an external reference if the application
requires it.
V
REF
2.5V
REF
In the AD5683R/AD5682R/AD5681R, the default condition of
the on-chip reference is on at power-up. Before connecting an
external reference to the pin, disable the internal reference by
writing to the REF bit (Bit DB16) in the write control register.
REF (+)
INPUT
REGISTER
DAC
REGISTER
RESISTOR
STRING
V
OUT
REF (–)
GND
Figure 47. DAC Channel Architecture Block Diagram
Rev. D | Page 19 of 28
AD5683R/AD5682R/AD5681R/AD5683
Data Sheet
Output Buffer
The output buffer can drive a 10 nF capacitance with a 2 kΩ
resistor in parallel, as shown in Figure 41 and Figure 44. If
a higher capacitance load is required, use the snubber method
or a shunt resistor to isolate the load from the output amplifier.
The slew rate is 0.7 V/µs with a ¼ to ¾ scale settling time of 5 µs.
The output buffer is designed as an input/output rail-to-rail,
which gives a maximum output voltage range of up to VDD
The gain bit sets the segmented string DAC gain to ×1 or ×2,
as shown in Table 12.
.
The output buffer voltage is determined by VREF, the gain bit,
and the offset and gain errors.
Rev. D | Page 20 of 28
Data Sheet
AD5683R/AD5682R/AD5681R/AD5683
SERIAL INTERFACE
The AD5683R/AD5682R/AD5681R/AD5683 uses a 3-wire
serial interface that is compatible with some SPI modes, Mode 1
and Mode 2, as well as with completely synchronous interfaces
such as SPORT. See Figure 4 for a timing diagram of a typical
write sequence. See the AN-1248 Application Note for more
information about the SPI interface.
SHORT WRITE OPERATION (AD5681R ONLY)
The AD5681R SPI serial interface allows data to be transferred
using a smaller number of clocks, if required. The last eight bits
are don’t care bits if the input or DAC registers are written as
shown in Table 9. To increase the DAC update rate, the size of
the data-word can be reduced.
SPI SERIAL DATA INTERFACE
SYNC
If
interpreted as a valid write and only the first 16 bits are decoded,
SYNC
is brought high between 16 and 24 clock edges, this is
SYNC
Pulling low
enabled, the data in the SDI pin is sampled into the input shift
SYNC
pin, the internal input shift register is
as shown in Figure 49. If
is brought high before 16 falling
register on the falling edge of SCLK. The
held low until the complete data-word (24-bits) is loaded from
SYNC
pin must be
clock edges, the serial write is ignored and the write sequence is
considered invalid. If the DCEN bit is enabled, this functionality
is not available (see Table 11).
the SDI pin (see Figure 4). When
data-word is decoded, following the instructions in Table 9.
SYNC
returns high, the serial
SDO Pin
Between consecutive data-words,
must be held high for a
SYNC
The serial data output pin (SDO), which is available only in the
AD5683R, serves two purposes: to read back the contents of the
DAC registers and to connect the device in daisy-chain mode.
minimum of 20 ns. Between consecutive DAC updates,
must be held high for more than 20 ns to satisfy the DAC
update condition as shown in Figure 4.
The SDO pin contains a push-pull output that internally includes
a weak pull-down resistor. The data is clocked out of SDO on
the rising edge of SCLK, as shown in Figure 4, and the pin is
active only when the DCEN bit is enabled in the write control
register or automatically enabled during a readback command. In
standby mode, the internal pull-down resistor forces a Logic 0 on
the bus. Due to the high value of the internal pull-down resistor,
other devices can have control over the SDO line if a parallel
connection is made.
SYNC
If
is brought high after 24 falling clock edges, it is interpreted
as a valid write, and the first 24 bits are loaded to the input shift
register.
To minimize power consumption, it is recommended that all
serial interface pins be operated close to the supply rails.
SCLK
SDI
DB15 DB14 DB13 DB12 DB11 DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
X
X
X
X
X
X
X
X
SYNC
Figure 49. Short Write on the AD5681R
Rev. D | Page 21 of 28
AD5683R/AD5682R/AD5681R/AD5683
Data Sheet
Daisy-Chain Connection
By default, the SDO pin is disabled. To enable daisy-chain
operation, the DCEN bit must be set in the write control
register (see Table 10).
Daisy chaining minimizes the number of pins required from the
controlling IC. As shown in Figure 50, the SDO pin of one package
must be tied to the SDI pin of the next package. The clock period
may need to be increased, as shown in Table 4, because of the
propagation delay of the line between subsequent devices.
When the daisy-chain mode is enabled (DCEN = 1), the
AD5683R/AD5682R/AD5681R/AD5683 accept as a valid
frame any data-word larger than 24 bits, decoding the last
24 bits received, as shown in Figure 51.
AD5683R
U1
CONTROLLER
MOSI
SDI
SCLK
SCLK
SYNC
SDO
SS
MISO
SDI
AD5683R
U2
SCLK
SYNC
SDO
Figure 50. Daisy-Chain Connection
SCLK
SYNC
MOSI
24
48
DB23
DB0
DB23
DB0
INPUT WORD FOR DAC 2
INPUT WORD FOR DAC 1
DB23
DB0
SDO_U1
UNDEFINED
INPUT WORD FOR DAC 2
Figure 51. Daisy-Chain Timing Diagram
Rev. D | Page 22 of 28
Data Sheet
AD5683R/AD5682R/AD5681R/AD5683
INTERNAL REGISTERS
COMMANDS
Input Shift Register
Write Input Register
The shift register of the AD5683R/AD5682R/AD5681R/AD5683
is 24 bits wide. Serial data is loaded MSB first (DB23) and the
first four bits are the command bits, C3 to C0, followed by the
data bits.
The input register allows the preloading of a new value for the
DAC register. The transfer from the input register to the DAC
LDAC
register can be triggered by hardware, by the
software using Command 2.
pin, or by
The data bits comprise a 20-bit, 18-bit, or 16-bit input code,
followed by a number of don’t care bits as shown in Table 9.
If new data is loaded into the DAC register directly using
Command 3, the DAC register automatically overwrites the
input register.
SYNC
The command is decoded on the rising edge of
.
Input Register
Update DAC Register
The input register acts as a buffer to preload new data. This
register does not control the voltage in the VOUT pin. There are
two different ways to transfer the contents of the input register
to the DAC register: by software or by hardware.
This command transfers the contents of the input register to the
DAC register and, consequently, the VOUT pin is updated.
LDAC
This operation is equivalent to a software
.
Write DAC Register
DAC Register
The DAC register controls the output voltage in the DAC. This
command updates the DAC register on completion of the write
operation. The input register is refreshed automatically with the
DAC register value.
The DAC register controls the voltage in the VOUT pin. This
register can be updated by issuing a command or by
transferring the contents of the input register to the DAC
register.
Table 9. Command Operation
Command
[DB23:DB20]
Data Bits [DB19:DB0]1
C3 C2 C1 C0 DB19 DB18 DB17 DB16 DB15 DB14 [DB13:DB8] DB7 DB6 DB5
DB4
[DB3:DB0] Operation
0
0
0
0
0
0
0
0
1
0
1
0
X
X
X
X
X
X
X…X
DB10 DB9…DB4
X…X
X
X
X
X
X…X
Do nothing
DB15 DB14 DB13 DB12 DB11
DB32 DB22 DB12, 3 DB02, 3 X…X
Write input register
Update DAC register
X
X
X
X
X
X
X
X
X
X
X…X
LDAC
(software
)
0
0
1
1
DB15 DB14 DB13 DB12 DB11
DB19 DB18 DB17 DB16 DB15
DB10 DB9…DB4
DB14 0…0
DB32 DB22 DB12, 3 DB02, 3 X…X
Write DAC and input
register
0
0
1
1
0
0
0
1
0
0
0
0
0…0
X…X
Write control register
X
X
X
X
X
X
X…X
X
X
X
X
Readback input
register
1 X means don’t care.
2 This bit is a don’t care bit for the AD5681R only.
3 This bit is a don’t care bit for the AD5682R only.
Rev. D | Page 23 of 28
AD5683R/AD5682R/AD5681R/AD5683
Data Sheet
Write Control Register
In power-down mode, the output buffer is internally disabled
and the VOUT pin output impedance can be selected to a well-
known value, as shown in Table 14.
The write control register sets the power-down and gain
functions. It also enables/disables the internal reference and
perform a software reset. See Table 10 for the write control
register functionality.
Table 14. Operation Modes
Operating Mode
PD1
PD0
Table 10. Write Control Register Bits
Normal Mode
0
0
DB19
DB18
DB17
DB16
DB15
DB14
Power-Down Modes
1 kΩ Output Impedance
100 kΩ Output Impedance
Three-State Output Impedance
Reset
PD1
PD0
REF
Gain
DCEN
0
1
1
1
0
1
DCEN Bit
The daisy-chain enable bit (DCEN, Bit DB14) enables the SDO pin,
allowing the device to operate in daisy-chain mode. This bit is
automatically disabled when a readback command is executed.
Enabling this bit disables the write short command feature in the
AD5681R.
In power-down mode, the device disables the output buffer but
does not disable the internal reference. To achieve maximum
power savings, it is recommend to disable the REF bit, if
possible.
Disabling both the internal reference and the output buffer
results in the supply current falling to 2 μA at 5 V.
Table 11. Daisy-Chain Enable Bit (DCEN)
DB0
Mode
The output stage is shown in Figure 52.
0
1
Standalone mode (default)
DCEN mode
DAC
AMPLIFIER
V
OUT
Gain Bit
The gain bit selects the gain of the output amplifier. Table 12
shows how the output voltage range corresponds to the state of
the gain bit.
POWER-DOWN
CIRCUITRY
RESISTOR
NETWORK
Table 12. Gain Bit
Gain
Output Voltage Range
0 V to VREF (default)
0 V to 2 × VREF
Figure 52. Output Stage During Power-Down
0
1
The output amplifier is shut down when the power-down mode
is activated. However, unless the internal reference is powered
down (using Bit DB16 in the write control register), the bias
generator, reference, and resistor string remain on. When in
power-down mode, the weak SDO resistor is also disconnected.
The supply current falls to 2 μA at 5 V. The contents of the DAC
register are unaffected when in power-down mode, and the DAC
register can continue to be updated. The time that is required to
exit power-down is typically 4 ꢀs for VDD = 5 V, or 600 ꢀs if the
reference is disabled.
REF Bit
The on-chip reference is on at power-up by default. This reference
can be turned on or off by setting a software-programmable bit,
DB16, in the write control register. Table 13 shows how the state
of the bit corresponds to the mode of operation.
To reduce the power consumption, it is recommended to
disable the internal reference if the device is placed in power-
down mode.
Reset Bit
The write control register of the AD5683R/AD5682R/AD5681R
contains a software reset function that resets the input and DAC
registers to zero scale and resets the write control register to the
default value. A software reset is initiated by setting the reset bit
(Bit DB19) in the write control register to 1. When the software
reset is complete, the reset bit is cleared to 0 automatically.
Table 13. Reference Bit (REF)
REF
Reference Function
Reference enabled (default)
Reference disabled
0
1
PD0 and PD1 Bits
The AD5683R/AD5682R/AD5681R contain two separate mode of
operation that are accessed by writing to the write control register.
In normal mode, the output buffer is directly connected to the
V
OUT pin.
Rev. D | Page 24 of 28
Data Sheet
AD5683R/AD5682R/AD5681R/AD5683
Readback Input Register
HARDWARE LDAC
The AD5683R allows readback of the contents of the input
register through the SDO pin by using Command 5 (see Table 9),
as shown in Figure 53.
The DACs of the AD5683R/AD5682R/AD5681R/AD5683 have
a double buffered interface consisting of an input register and a
LDAC
DAC register. The
to the DAC register and, consequently, the output is updated.
LDAC
transfers data from the input register
The SDO pin is automatically enabled for the duration of the
read operation, after which it is disabled again, as shown in
Table 15. If the DCEN bit was enabled before the read operation,
the bit is reset after a readback operation. If the AD5683R was
operating in daisy-chain mode, the user must enable the DCEN
bit again.
Hold
high while data is clocked into the input shift
LDAC
register. The DAC output is updated by taking
low after
is taken high. The output DAC is updated on the falling
SYNC
LDAC
edge of
.
LDAC
If
ignored.
is pulsed while the data is being clocked, the pulse is
Table 15. Write and Readback sequence
SDI
SDO
Action
HARDWARE RESET
0x180000 0x000000
0x500000 0x000000
Write 0x8000 to the input register
Prepare data read from the input register
RESET
is an active low signal that sets the input and DAC
registers to zero scale and the control registers to their default
RESET
0x000000 0xX8000X1 Clock out the data
values. It is necessary to keep
low for 75 ns to complete
signal returns high, the output
remains at the zero scale until a new value is programmed.
RESET
1 X mean don’t care.
RESET
the operation. When the
While the
any new command.
RESET
pin is low, the AD5683R/AD5681R ignore
If
is held low at power-up, the internal reference is not
RESET
initialized correctly until the
pin is released.
SCLK
24
24
1
1
SYNC
DB23
DB0
DB23
DB0
DB0
SDI
READBACK COMMAND
NOP CONDITION
DB23
SDO
DATA
Figure 53. Readback Operation
Rev. D | Page 25 of 28
AD5683R/AD5682R/AD5681R/AD5683
Data Sheet
THERMAL HYSTERESIS
LAYOUT GUIDELINES
Thermal hysteresis is the voltage difference induced on the
reference voltage by sweeping the temperature from ambient
to cold, to hot, and then back to ambient.
In any circuit where accuracy is important, careful consideration of
the power supply and ground return layout helps to ensure the
rated performance. The printed circuit board (PCB) on which the
ADCs are mounted must be designed such that the AD5683R/
AD5682R/AD5681R/AD5683 lie on the analog plane.
The thermal hysteresis data is shown in Figure 54. It is measured by
sweeping the temperature from ambient to −40°C, then to +105°C,
and finally returning to ambient. The VREF delta is next measured
between the two ambient measurements; the result is shown in a
solid line in Figure 54. The same temperature sweep and measure-
ments were immediately repeated; the results are shown in a
patterned line in Figure 54.
Ensure that the AD5683R/AD5682R/AD5681R/AD5683 have
ample supply bypassing of 10 µF, in parallel with a 0.1 µF capacitor
on each supply that is located as near to the package as possible
(ideally, right up against the device). The 10 µF capacitors are
of the tantalum bead type. The 0.1 µF capacitor must have
low effective series resistance (ESR) and low effective series
inductance (ESI), such as the common ceramic types, which
provide a low impedance path to ground at high frequencies to
handle transient currents due to internal logic switching.
6
FIRST TEMPERATURE SWEEP
SUBSEQUENT…
5
4
3
2
1
0
In systems where there are many devices on one board, it is
often useful to provide some heat sinking capability to allow
the power to dissipate easily.
The LFCSP packages of the AD5683R/AD5682R/AD5681R/
AD5683 have an exposed pad beneath the device. Connect this
pad to the GND supply of the device. For optimum performance,
use special consideration when designing the motherboard and
mounting the package. For enhanced thermal, electrical, and
board level performance, solder the exposed pad on the bottom
of the package to the corresponding thermal land pad on the
PCB. Design thermal vias into the PCB land pad area to further
improve heat dissipation.
–100
–80
–60
–40
–20
0
20
40
60
DISTORTION (ppm)
Figure 54. Thermal Hysteresis
POWER-UP SEQUENCE
The GND plane on the device can be increased (as shown in
Figure 55) to provide a natural heat sinking effect.
Because there are diodes to limit the voltage compliance at the
digital pins and analog pins, it is important to power GND first
before applying any voltage to VDD, VOUT, and VLOGIC. Otherwise,
the diode is forward-biased such that VDD is powered uninten-
tionally. The ideal power-up sequence is GND, VDD, VLOGIC
REF, followed by the digital inputs.
AD5683R/
AD5682R/
AD5681R/
AD5683
,
V
RECOMMENDED REGULATOR
GND
PLANE
The AD5683R/AD5682R/AD5681R/AD5683 use a 5 V (VDD
supply as well as a digital logic supply (VLOGIC).
)
BOARD
The analog and digital supplies required for the AD5683R/
AD5682R/AD5681R/AD5683 can be generated using Analog
Devices, Inc., low dropout (LDO) regulators such as the ADP7118
and the ADP162, respectively, for analog and digital supplies.
Figure 55. Pad Connection to Board
Rev. D | Page 26 of 28
Data Sheet
AD5683R/AD5682R/AD5681R/AD5683
OUTLINE DIMENSIONS
1.70
1.60
1.50
2.10
2.00 SQ
1.90
0.50 BSC
8
5
0.15 REF
PIN 1 INDEX
EXPOSED
PAD
1.10
1.00
0.90
AREA
0.425
0.350
0.275
4
1
PIN 1
INDICATOR
(R 0.15)
TOP VIEW
BOTTOM VIEW
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.60
0.55
0.50
0.05 MAX
0.02 NOM
SECTION OF THIS DATA SHEET.
SEATING
PLANE
0.30
0.25
0.20
0.20 REF
Figure 56. 8-Lead Lead Frame Chip Scale Package [LFCSP_UD]
2.00 mm × 2.00 mm Body, Ultrathin, Dual Lead
(CP-8-10)
Dimensions shown in millimeters
3.10
3.00
2.90
10
1
6
5
5.15
4.90
4.65
3.10
3.00
2.90
PIN 1
IDENTIFIER
0.50 BSC
0.95
0.85
0.75
15° MAX
1.10 MAX
0.70
0.55
0.40
0.15
0.05
0.23
0.13
6°
0°
0.30
0.15
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-187-BA
Figure 57. 10-Lead Mini Small Outline Package [MSOP]
(RM-10)
Dimensions shown in millimeters
Rev. D | Page 27 of 28
AD5683R/AD5682R/AD5681R/AD5683
Data Sheet
ORDERING GUIDE
Resolution
Package
Description
Package
Option
Model1
(Bits)
16
16
16
16
16
16
16
16
16
16
16
16
Pinout Temperature Range
Performance
A Grade
A Grade
A Grade
A Grade
A Grade
B Grade
B Grade
B Grade
B Grade
B Grade
B Grade
B Grade
Branding
94
AD5683RACPZ-RL7
AD5683RACPZ-1RL7
AD5683RACPZ-2RL7
AD5683RARMZ
AD5683RARMZ-RL7
AD5683RBRMZ
AD5683RBRMZ-RL7
AD5683RBRMZ-3
AD5683RBRMZ-3-RL7
AD5683RBCPZ-RL7
AD5683RBCPZ-1RL7
AD5683BCPZ-RL7
LDAC
VLOGIC
RESET
VLOGIC
VLOGIC
VLOGIC
VLOGIC
SDO
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
8-Lead LFCSP_UD CP-8-10
8-Lead LFCSP_UD CP-8-10
8-Lead LFCSP_UD CP-8-10
95
96
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
8-Lead LFCSP_UD CP-8-10
8-Lead LFCSP_UD CP-8-10
8-Lead LFCSP_UD CP-8-10
8-Lead LFCSP_UD CP-8-10
8-Lead LFCSP_UD CP-8-10
8-Lead LFCSP_UD CP-8-10
RM-10
RM-10
RM-10
RM-10
RM-10
RM-10
DHY
DHY
DHZ
DHZ
DJ0
DJ0
97
SDO
LDAC
VLOGIC
LDAC
DX
9A
AD5682RBCPZ-RL7
14
LDAC
−40°C to +105°C
B Grade
9B
AD5681RBCPZ-RL7
AD5681RBCPZ-1RL7
AD5681RBRMZ
AD5681RBRMZ-RL7
EVAL-AD5683RSDZ
12
12
12
12
LDAC
VLOGIC
VLOGIC
VLOGIC
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
B Grade
B Grade
B Grade
B Grade
98
99
DHX
DHX
10-Lead MSOP
10-Lead MSOP
Evaluation Board
RM-10
RM-10
1 Z = RoHS Compliant Part.
©2013–2016 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D11955-0-12/16(D)
Rev. D | Page 28 of 28
相关型号：
©2020 ICPDF网 联系我们和版权申明