AD5764R_08 [ADI]
Complete Quad, 16-Bit, High Accuracy, Serial Input, Bipolar Voltage Output DAC; 完整的四通道， 16位，高精度，串行输入，双极性电压输出DAC
| 型号： | AD5764R_08 |
| 厂家： | 
ADI |
| 描述： | Complete Quad, 16-Bit, High Accuracy, Serial Input, Bipolar Voltage Output DAC |
| 文件： | 总32页 (文件大小：723K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Complete Quad, 16-Bit, High Accuracy,
Serial Input, Bipolar Voltage Output DAC
AD5764R
FEATURES
GENERAꢁ DESCRIPTION
Complete quad, 16-bit digital-to-analog converter (DAC)
Programmable output range: 10 V, 10.2ꢀ64 V, or 10.ꢀ263 V
1 ꢁSB maximum INꢁ error, 1 ꢁSB maximum DNꢁ error
ꢁow noise: 60 nV/√Hz
Settling time: 10 μs maximum
Integrated reference buffers
The AD5764R is a quad, 16-bit, serial input, bipolar voltage output
DAC that operates from supply voltages of 11ꢀ4 ꢁ to 16ꢀ5
ꢀ
Nominal full-scale output range is 10 ꢀ The AD5764R provides
integrated output amplifiers, reference buffers, and proprietary
power-up/power-down control circuitryꢀ The part also features
a digital I/O port, programmed via the serial interface, and an
analog temperature sensorꢀ The part incorporates digital offset
and gain adjust registers per channelꢀ
Internal reference: 10 ppm/°C maximum
On-chip die temperature sensor
Output control during power-up/brownout
Programmable short-circuit protection
Simultaneous updating via ꢁDAC
Asynchronous CꢁR to zero code
Digital offset and gain adjust
The AD5764R is a high performance converter that provides
guaranteed monotonicity, integral nonlinearity (INL) of 1 LSB,
low noise, and 10 μs settling timeꢀ The AD5764R includes an
on-chip 5 ꢁ reference with a reference temperature coefficient
of 10 ppm/°C maximumꢀ During power-up when the supply
voltages are changing, ꢁOUTx is clamped to 0 ꢁ via a low
impedance pathꢀ
ꢁogic output control pins
DSP-/microcontroller-compatible serial interface
Temperature range: −40°C to +8ꢀ°C
iCMOS process technology
The AD5764R is based on the iCMOS® technology platform, which
is designed for analog systems designers within industrial/instru-
mentation equipment OEMs who need high performance ICs at
higher voltage levelsꢀ iCMOS enables the development of analog
ICs capable of 30 ꢁ and operation at 15 ꢁ supplies, while allowing
reductions in power consumption and package size, coupled with
increased ac and dc performanceꢀ
APPꢁICATIONS
Industrial automation
Open-loop/closed-loop servo control
Process control
Data acquisition systems
Automatic test equipment
Automotive test and measurement
High accuracy instrumentation
The AD5764R uses a serial interface that operates at clock rates
of up to 30 MHz and is compatible with DSP and microcontroller
interface standardsꢀ Double buffering allows the simultaneous
updating of all DACsꢀ The input coding is programmable to either
twos complement or offset binary formatsꢀ The asynchronous clear
function clears all DAC registers to either bipolar zero or zero scale,
depending on the coding usedꢀ The AD5764R is ideal for both
closed-loop servo control and open-loop control applicationsꢀ
The AD5764R is available in a 32-lead TQFP and offers guaranteed
specifications over the −40°C to +85°C industrial temperature
range (see Figure 1 for the functional block diagram)ꢀ
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2008 Analog Devices, Inc. All rights reserved.
AD5764R
TABLE OF CONTENTS
Features ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ 1
Function Register ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ 24
Data Registerꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ 25
Coarse Gain Register ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ 25
Fine Gain Registerꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ 25
Offset Register ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ 26
Offset and Gain Adjustment Worked Exampleꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ 26
Design Featuresꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ 27
Analog Output Control ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ 27
Digital Offset and Gain Controlꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ 27
Programmable Short-Circuit Protection ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ 27
Digital I/O Portꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ 27
Die Temperature Sensorꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ 27
Local Ground Offset Adjustꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ 27
Applications Informationꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ 28
Typical Operating Circuit ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ 28
Layout Guidelinesꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ 30
Galvanically Isolated Interface ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ 30
Microprocessor Interfacingꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ 30
Evaluation Boardꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ 31
Outline Dimensionsꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ 32
Ordering Guide ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ 32
Applicationsꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ 1
General Descriptionꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ 1
Revision History ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ 2
Functional Block Diagram ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ 3
Specificationsꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ 4
AC Performance Characteristicsꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ 6
Timing Characteristics ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ 7
Absolute Maximum Ratingsꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ 10
Thermal Resistance ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ 10
ESD Cautionꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ 10
Pin Configuration and Function Descriptionsꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ 11
Typical Performance Characteristics ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ 13
Terminology ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ 19
Theory of Operation ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ 21
DAC Architectureꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ 21
Reference Buffersꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ 21
Serial Interface ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ 21
LDAC
Simultaneous Updating via
Transfer Functionꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ 23
CLR
ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ 22
Asynchronous Clear (
)ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ 23
Registersꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ 24
REVISION HISTORY
10/08—Revision 0: Initial Version
Rev. 0 | Page 2 of 32
AD5764R
FUNCTIONAL BLOCK DIAGRAM
AV
AV
AV
AV
SS
REFOUT
RSTOUT
RSTIN
PGND
REFGND
REFAB
DD
SS
DD
VOLTAGE
MONITOR
AND
DV
CC
REFERENCE
BUFFERS
5V
AD5764R
REFERENCE
CONTROL
DGND
ISCC
16
16
G1
G1
G1
G1
INPUT
REG A
DAC
REG A
DAC A
DAC B
DAC C
DAC D
SDIN
SCLK
SYNC
SDO
VOUTA
AGNDA
INPUT
SHIFT
G2
REGISTER
AND
GAIN REG A
CONTROL
LOGIC
OFFSET REG A
16
16
16
INPUT
REG B
DAC
REG B
VOUTB
AGNDB
G2
G2
G2
GAIN REG B
OFFSET REG B
D0
D1
INPUT
REG C
DAC
REG C
VOUTC
AGNDC
GAIN REG C
OFFSET REG C
BIN/2sCOMP
INPUT
REG D
DAC
REG D
VOUTD
AGNDD
GAIN REG D
CLR
OFFSET REG D
REFERENCE
BUFFERS
TEMP
SENSOR
LDAC
REFCD
TEMP
Figure 1.
Rev. 0 | Page 3 of 32
AD5764R
SPECIFICATIONS
AꢁDD = 11ꢀ4 ꢁ to 16ꢀ5 ꢁ, AꢁSS = −11ꢀ4 ꢁ to −16ꢀ5 ꢁ, AGND = DGND = REFGND = PGND = 0 ꢁ; REFAB = REFCD = 5 ꢁ external;
DꢁCC = 2ꢀ7 ꢁ to 5ꢀ25 ꢁ, RLOAD = 10 kΩ, CL = 200 pFꢀ All specifications TMIN to TMAX, unless otherwise notedꢀ
Table 1.
Parameter
B Grade1
C Grade1
Unit
Test Conditions/Comments
ACCURACY
Outputs unloaded
Resolution
16
2
1
16
1
1
Bits
Relative Accuracy (INL)
Differential Nonlinearity (DNL)
Bipolar Zero Error
LSB max
LSB max
mV max
Guaranteed monotonic
25°C; error at other temperatures obtained
using bipolar zero tempco
2
2
3
2
2
3
2
2
mV max
ppm FSR/°C max
mV max
Bipolar Zero Tempco2
Zero-Scale Error
25°C; error at other temperatures obtained
using zero-scale tempco
2.5
2
0.02
2
2.5
2
0.02
2
mV max
ppm FSR/°C max
% FSR max
ppm FSR/°C max
LSB max
Zero-Scale Tempco2
Gain Error
Gain Tempco2
DC Crosstalk2
0.5
0.5
REFERENCE INPUT/OUTPUT
Reference Input2
Reference Input Voltage
DC Input Impedance
Input Current
5
1
10
1/7
5
1
10
1/7
V nominal
MΩ min
μA max
1% for specified performance
Typically 100 MΩ
Typically 30 nA
Reference Range
Reference Output
Output Voltage
V min/V max
4.995/5.005
10
1
4.995/5.005 V min/V max
At 25°C, AVDD/AVSS = 13.5 V
Typically 1.7ppm/°C
Reference Tempco2
10
ppm/°C max
MΩ min
2
RLOAD
1
Power Supply Sensitivity2
Output Noise2
Noise Spectral Density2
Output Voltage Drift vs. Time2
300
18
75
40
50
70
30
300
18
75
40
50
70
30
μV/V typ
μV p-p typ
nV/√Hz typ
ppm/500 hr typ
ppm/1000 hr typ
ppm typ
0.1 Hz to 10 Hz
At 10 kHz
Thermal Hysteresis2
First temperature cycle
Subsequent temperature cycles
ppm typ
OUTPUT CHARACTERISTICS2
Output Voltage Range3
10.5263
14
13
10.5263
V min/V max
V min/V max
ppm FSR/500 hr typ
ppm FSR/1000 hr
typ
AVDD/AVSS = 11.4 V, REFIN = 5 V
AVDD/AVSS = 16.5 V, REFIN = 7 V
14
13
15
Output Voltage Drift vs. Time
15
Short-Circuit Current
Load Current
10
1
10
1
mA typ
mA max
RISCC = 6 kΩ, see Figure 31
For specified performance
Capacitive Load Stability
RLOAD = ∞
RLOAD = 10 kΩ
200
1000
0.3
200
1000
0.3
pF max
pF max
Ω max
DC Output Impedance
Rev. 0 | Page 4 of 32
AD5764R
Parameter
DIGITAL INPUTS2
B Grade1
C Grade1
Unit
Test Conditions/Comments
DVCC = 2.7 V to 5.25 V
Input High Voltage, VIH
Input Low Voltage, VIL
Input Current
2.4
0.8
1.2
10
2.4
0.8
1.2
10
V min
V max
μA max
pF max
Per pin
Per pin
Pin Capacitance
DIGITAL OUTPUTS (D0, D1, SDO)2
Output Low Voltage
Output High Voltage
Output Low Voltage
0.4
DVCC − 1
0.4
0.4
DVCC − 1
0.4
V max
V min
V max
DVCC = 5 V 5%, sinking 200 μA
DVCC = 5 V 5%, sourcing 200 μA
DVCC = 2.7 V to 3.6 V,
sinking 200 μA
Output High Voltage
DVCC − 0.5
DVCC − 0.5
V min
DVCC = 2.7 V to 3.6 V,
sourcing 200 μA
High Impedance Leakage Current
High Impedance Output Capacitance
DIE TEMPERATURE SENSOR2
Output Voltage at 25°C
Output Voltage Scale Factor
Output Voltage Range
Output Load Current
Power-On Time
1
5
1
5
μA max
pF typ
SDO only
SDO only
1.47
5
1.175/1.9
200
10
1.47
5
1.175/1.9
200
10
V typ
Die temperature
mV/°C typ
V min/V max
μA max
−40°C to +105°C
Current source only
ms typ
POWER REQUIREMENTS
AVDD/AVSS
11.4/16.5
2.7/5.25
11.4/16.5
2.7/5.25
V min/V max
V min/V max
DVCC
Power Supply Sensitivity2
∆VOUT/∆ΑVDD
AIDD
AISS
DICC
−85
3.55
2.8
−85
3.55
2.8
dB typ
mA/channel max
mA/channel max
mA max
Outputs unloaded
Outputs unloaded
1.2
1.2
VIH = DVCC, VIL = DGND, 750 μA typ
12 V operation output unloaded
Power Dissipation
275
275
mW typ
1 Temperature range: −40°C to +85°C; typical at +25°C. Device functionality is guaranteed to +105°C with degraded performance.
2 Guaranteed by design and characterization; not production tested.
3 Output amplifier headroom requirement is 1.4 V minimum.
Rev. 0 | Page 5 of 32
AD5764R
AC PERFORMANCE CHARACTERISTICS
AꢁDD = 11ꢀ4 ꢁ to 16ꢀ5 ꢁ, AꢁSS = −11ꢀ4 ꢁ to −16ꢀ5 ꢁ, AGND = DGND = REFGND = PGND = 0 ꢁ; REFAB = REFCD = 5 ꢁ external;
DꢁCC = 2ꢀ7 ꢁ to 5ꢀ25 ꢁ, RLOAD = 10 kΩ, CL = 200 pFꢀ All specifications TMIN to TMAX, unless otherwise notedꢀ
Table 2.
Parameter
B Grade
C Grade
Unit
Test Conditions/Comments
Full-scale step to 1 LSB
512 LSB step settling
DYNAMIC PERFORMANCE1
Output Voltage Settling Time
8
10
2
8
10
2
μs typ
μs max
μs typ
Slew Rate
5
5
V/μs typ
Digital-to-Analog Glitch Energy
Glitch Impulse Peak Amplitude
Channel-to-Channel Isolation
DAC-to-DAC Crosstalk
Digital Crosstalk
Digital Feedthrough
Output Noise (0.1 Hz to 10 Hz)
Output Noise (0.1 Hz to 100 kHz)
1/f Corner Frequency
8
8
nV-sec typ
mV max
dB typ
nV-sec typ
nV-sec typ
nV-sec typ
LSB p-p typ
μV rms max
kHz typ
25
80
8
2
2
0.1
45
1
25
80
8
2
2
0.1
45
1
Effect of input bus activity on DAC outputs
Output Noise Spectral Density
Complete System Output Noise Spectral Density2
60
80
60
80
nV/√Hz typ
nV/√Hz typ
Measured at 10 kHz
Measured at 10 kHz
1 Guaranteed by design and characterization; not production tested.
2 Includes noise contributions from integrated reference buffers, a 16-bit DAC, and an output amplifier.
Rev. 0 | Page 6 of 32
AD5764R
TIMING CHARACTERISTICS
AꢁDD = 11ꢀ4 ꢁ to 16ꢀ5 ꢁ, AꢁSS = −11ꢀ4 ꢁ to −16ꢀ5 ꢁ, AGND = DGND = REFGND = PGND = 0 ꢁ; REFAB = REFCD = 5 ꢁ external;
DꢁCC = 2ꢀ7 ꢁ to 5ꢀ25 ꢁ, RLOAD = 10 kΩ, CL = 200 pFꢀ All specifications TMIN to TMAX, unless otherwise notedꢀ
Table 3.
Parameter1, 2, 3
ꢁimit at TMIN, TMAX
Unit
Description
t1
t2
t3
t4
33
13
13
13
13
40
2
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
μs min
ns min
ns min
ns max
μs max
ns min
μs max
ns max
ns min
μs max
ns min
SCLK cycle time
SCLK high time
SCLK low time
SYNC falling edge to SCLK falling edge setup time
24th SCLK falling edge to SYNC rising edge
Minimum SYNC high time
4
t5
t6
t7
t8
t9
Data setup time
Data hold time
SYNC rising edge to LDAC falling edge (all DACs updated)
SYNC rising edge to LDAC falling edge (single DAC updated)
LDAC pulse width low
5
1.7
480
10
500
10
10
2
t10
t11
t12
t13
t14
LDAC falling edge to DAC output response time
DAC output settling time
CLR pulse width low
CLR pulse activation time
5, 6
t15
25
13
2
SCLK rising edge to SDO valid
SYNC rising edge to SCLK falling edge
SYNC rising edge to DAC output response time (LDAC = 0)
LDAC falling edge to SYNC rising edge
t16
t17
t18
170
1 Guaranteed by design and characterization; not production tested.
2 All input signals are specified with tR = tF = 5 ns (10% to 90% of DVCC) and timed from a voltage level of 1.2 V.
3 See Figure 2, Figure 3, and Figure 4.
4 Standalone mode only.
5 Measured with the load circuit of Figure 5.
6 Daisy-chain mode only.
Rev. 0 | Page 7 of 32
AD5764R
Timing Diagrams
t1
SCLK
1
2
24
t3
t2
t6
t4
t5
SYNC
t8
t7
DB23
SDIN
DB0
t10
t10
t9
LDAC
t18
t12
t11
VOUTx
LDAC = 0
t12
t17
VOUTx
CLR
t13
t14
VOUTx
Figure 2. Serial Interface Timing Diagram
t1
SCLK
24
48
t3
t2
t6
t5
t16
t4
SYNC
SDIN
t8
t7
DB23
DB0
DB23
DB0
INPUT WORD FOR DAC N
INPUT WORD FOR DAC N – 1
INPUT WORD FOR DAC N
t15
DB23
DB0
SDO
t9
UNDEFINED
t10
LDAC
Figure 3. Daisy-Chain Timing Diagram
Rev. 0 | Page 8 of 32
AD5764R
SCLK
24
48
SYNC
SDIN
DB23
DB0
DB23
DB0
NOP CONDITION
INPUT WORD SPECIFIES
REGISTER TO BE READ
DB23
DB0
SDO
UNDEFINED
SELECTED REGISTER DATA
CLOCKED OUT
Figure 4. Readback Timing Diagram
200µA
I
OL
V
V
(MIN) OR
(MAX)
TO OUTPUT
PIN
OH
OL
C
L
50pF
200µA
I
OH
Figure 5. Load Circuit for SDO Timing Diagram
Rev. 0 | Page 9 of 32
AD5764R
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise notedꢀ Transient currents of up to
100 mA do not cause SCR latch-upꢀ
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the deviceꢀ This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not impliedꢀ Exposure to absolute
maximum rating conditions for extended periods may affect
device reliabilityꢀ
Table 4.
Parameter
Rating
AVDD to AGND, DGND
AVSS to AGND, DGND
DVCC to DGND
−0.3 V to +17 V
+0.3 V to −17 V
−0.3 V to +7 V
THERMAꢁ RESISTANCE
Digital Inputs to DGND
−0.3 V to (DVCC + 0.3 V) or +7 V,
whichever is less
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packagesꢀ
Digital Outputs to DGND
REFIN to AGND, PGND
REFOUT to AGND
−0.3 V to DVCC + 0.3 V
−0.3 V to AVDD + 0.3 V
AVSS to AVDD
Table 5. Thermal Resistance
Package Type
θJA
θJC
Unit
TEMP
AVSS to AVDD
32-Lead TQFP
65
12
°C/W
VOUTx to AGND
AVSS to AVDD
AGND to DGND
−0.3 V to +0.3 V
Operating Temperature Range
Industrial
Storage Temperature Range
Junction Temperature (TJ max)
Lead Temperature (Soldering)
ESD CAUTION
−40°C to +85°C
−65°C to +150°C
150°C
JEDEC Industry Standard
J-STD-020
Rev. 0 | Page 10 of 32
AD5764R
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
32 31 30 29 28 27 26 25
1
2
3
4
5
6
7
8
24
AGNDA
23 VOUTA
22
SYNC
PIN 1
SCLK
SDIN
SDO
VOUTB
AD5764R
TOP VIEW
(Not to Scale)
21 AGNDB
20 AGNDC
19 VOUTC
18 VOUTD
CLR
LDAC
D0
AGNDD
17
D1
9
10 11 12 13 14 15 16
Figure 6. Pin Configuration
Table 6. Pin Function Descriptions
Pin No. Mnemonic Description
1
SYNC
Active Low Input. This is the frame synchronization signal for the serial interface. While SYNC is low, data is
transferred in on the falling edge of SCLK.
2
SCLK
Serial Clock Input. Data is clocked into the shift register on the falling edge of SCLK. This operates at clock
speeds of up to 30 MHz.
3
4
5
6
SDIN
SDO
CLR
Serial Data Input. Data must be valid on the falling edge of SCLK.
Serial Data Output. This pin is used to clock data from the serial register in daisy-chain or readback mode.
Negative Edge Triggered Input.1 Asserting this pin sets the DAC registers to 0x0000.
LDAC
Load DAC. This logic input is used to update the DAC registers and, consequently, the analog outputs. When
tied permanently low, the addressed DAC register is updated on the rising edge of SYNC. If LDAC is held high
during the write cycle, the DAC input register is updated but the output update is held off until the falling edge
of LDAC. In this mode, all analog outputs can be updated simultaneously on the falling edge of LDAC. The LDAC
pin must not be left unconnected.
7, 8
D0, D1
Digital I/O Port. D0 and D1 form a digital I/O port. The user can set up these pins as inputs or outputs that are
configurable and readable over the serial interface. When configured as inputs, these pins have weak internal
pull-ups to DVCC. When programmed as outputs, D0 and D1 are referenced by DVCC and DGND.
9
RSTOUT
RSTIN
Reset Logic Output. This is the output from the on-chip voltage monitor used in the reset circuit. If desired, it
can be used to control other system components.
Reset Logic Input. This input allows external access to the internal reset logic. Applying a Logic 0 to this input
clamps the DAC outputs to 0 V. In normal operation, RSTIN should be tied to Logic 1. Register values remain
unchanged.
10
11
12
13, 31
14
15, 30
16
DGND
DVCC
AVDD
PGND
AVSS
Digital Ground Pin.
Digital Supply Pin. Voltage ranges from 2.7 V to 5.25 V.
Positive Analog Supply Pins. Voltage ranges from 11.4 V to 16.5 V.
Ground Reference Point for Analog Circuitry.
Negative Analog Supply Pins. Voltage ranges from –11.4 V to –16.5 V.
This pin is used in association with an optional external resistor to AGND to program the short-circuit current of
the output amplifiers. Refer to the Design Features section for more information.
ISCC
17
18
AGNDD
VOUTD
Ground Reference Pin for DAC D Output Amplifier.
Analog Output Voltage of DAC D. Buffered output with a nominal full-scale output range of 10 V. The output
amplifier is capable of directly driving a 10 kΩ, 200 pF load.
19
VOUTC
Analog Output Voltage of DAC C. Buffered output with a nominal full-scale output range of 10 V. The output
amplifier is capable of directly driving a 10 kΩ, 200 pF load.
20
21
AGNDC
AGNDB
Ground Reference Pin for DAC C Output Amplifier.
Ground Reference Pin for DAC B Output Amplifier.
Rev. 0 | Page 11 of 32
AD5764R
Pin No. Mnemonic
Description
22
VOUTB
Analog Output Voltage of DAC B. Buffered output with a nominal full-scale output range of 10 V. The output
amplifier is capable of directly driving a 10 kΩ, 200 pF load.
23
VOUTA
Analog Output Voltage of DAC A. Buffered output with a nominal full-scale output range of 10 V. The output
amplifier is capable of directly driving a 10 kΩ, 200 pF load.
24
25
AGNDA
REFAB
Ground Reference Pin for DAC A Output Amplifier.
External Reference Voltage Input for Channel A and Channel B. The reference input range is 1 V to 7 V, and it
programs the full-scale output voltage. REFIN = 5 V for specified performance.
26
27
REFCD
External Reference Voltage Input for Channel C and Channel D. The reference input range is 1 V to 7 V, and it
programs the full-scale output voltage. REFIN = 5 V for specified performance.
Reference Output. This is the reference output from the internal voltage reference. The internal reference is 5 V
3 mV at 25°C, with a reference temperature coefficient of 10 ppm/°C.
REFOUT
28
29
REFGND
TEMP
Reference Ground Return for the Reference Generator and Buffers.
This pin provides an output voltage proportional to temperature. The output voltage is 1.47 V typical at 25°C die
temperature; variation with temperature is 5 mV/°C.
32
BIN/2sCOMP
This pin determines the DAC coding. This pin should be hardwired to either DVCC or DGND. When hardwired to
DVCC, input coding is offset binary (see Table 7). When hardwired to DGND, input coding is twos complement
(see Table 8).
1 Internal pull-up device on this logic input. Therefore, it can be left floating; and it defaults to a logic high condition.
Rev. 0 | Page 12 of 32
AD5764R
TYPICAL PERFORMANCE CHARACTERISTICS
1.0
1.0
0.8
T
= 25°C
T = 25°C
A
A
V
/V = ±15V
V
/V = ±12V
0.8
DD SS
DD SS
REFIN = 5V
REFIN = 5V
0.6
0.6
0.4
0.4
0.2
0.2
0
0
–0.2
–0.4
–0.6
–0.8
–1.0
–0.2
–0.4
–0.6
–0.8
–1.0
0
0
0
10,000
20,000
30,000
40,000
50,000
60,000
0
10,000
20,000
30,000
40,000
50,000
60,000
DAC CODE
DAC CODE
Figure 7. Integral Nonlinearity Error vs. DAC Code,
VDD/VSS 15 V
Figure 10. Differential Nonlinearity Error vs. DAC Code,
=
V
DD/VSS
=
12 V
1.0
0.8
0.5
0.4
0.3
0.2
0.1
0
T
V
= 25°C
A
T = 25°C
A
/V = ±12V
DD SS
V
/V = ±15V
DD SS
REFIN = 5V
REFIN = 5V
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
–0.1
–0.2
10,000
20,000
30,000
40,000
50,000
60,000
–40
–20
0
20
40
60
80
100
DAC CODE
TEMPERATURE (°C)
Figure 8. Integral Nonlinearity Error vs. DAC Code,
VDD/VSS 12 V
Figure 11. Integral Nonlinearity Error vs. Temperature,
VDD/VSS 15 V
=
=
1.0
0.8
0.5
0.4
0.3
0.2
0.1
0
T
= 25°C
A
T
= 25°C
/V = ±12V
A
V
/V = ±15V
DD SS
V
DD SS
REFIN = 5V
REFIN = 5V
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
–0.1
–40
10,000
20,000
30,000
40,000
50,000
60,000
–20
0
20
40
60
80
100
DAC CODE
TEMPERATURE (°C)
Figure 9. Differential Nonlinearity Error vs. DAC Code,
VDD/VSS 15 V
Figure 12. Integral Nonlinearity Error vs. Temperature,
VDD/VSS 12 V
=
=
Rev. 0 | Page 13 of 32
AD5764R
0.15
0.10
0.05
0
0.15
0.10
T
= 25°C
A
REFIN = 5V
0.05
0
–0.05
–0.10
–0.15
–0.20
–0.05
–0.10
–0.15
–0.20
–0.25
T
V
= 25°C
A
/V = ±15V
DD SS
REFIN = 5V
–0.25
–40
–20
0
20
40
60
80
100
11.4
12.4
13.4
14.4
15.4
16.4
TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
Figure 13. Differential Nonlinearity Error vs. Temperature,
VDD/VSS = 15 V
Figure 16. Differential Nonlinearity Error vs. Supply Voltage
0.15
0.8
T
= 25°C
A
0.6
0.4
0.10
0.05
0.2
0
0
–0.05
–0.10
–0.15
–0.20
–0.25
–0.2
–0.4
–0.6
–0.8
–1.0
T
V
= 25°C
A
/V = ±12V
DD SS
REFIN = 5V
–40
–20
0
20
40
60
80
100
1
2
3
4
5
6
7
TEMPERATURE (°C)
REFERENCE VOLTAGE (V)
Figure 14. Differential Nonlinearity Error vs. Temperature,
VDD/VSS = 12 V
Figure 17. Integral Nonlinearity Error vs. Reference Voltage,
VDD/VSS
= 16.5 V
0.5
0.4
0.3
0.2
0.1
0
0.4
0.3
T
= 25°C
T
= 25°C
A
A
REFIN = 5V
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.1
–0.2
11.4
12.4
13.4
14.4
15.4
16.4
1
2
3
4
5
6
7
SUPPLY VOLTAGE (V)
REFERENCE VOLTAGE (V)
Figure 15. Integral Nonlinearity Error vs. Supply Voltage
Figure 18. Differential Nonlinearity Error vs. Reference Voltage,
VDD/VSS 16.5 V
=
Rev. 0 | Page 14 of 32
AD5764R
0.6
0.4
0.8
0.6
0.4
0.2
0
T
= 25°C
A
REFIN = 5V
V
/V = ±15V
DD SS
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
–1.2
–1.4
–1.6
V
/V = ±12V
DD SS
–0.2
–0.4
1
2
3
4
5
6
7
–40
–20
0
20
40
60
80
100
REFERENCE VOLTAGE (V)
TEMPERATURE (°C)
Figure 19. Total Unadjusted Error vs. Reference Voltage,
Figure 22. Bipolar Zero Error vs. Temperature
VDD/VSS
= 16.5 V
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
14
13
12
11
10
9
REFIN = 5V
T
= 25°C
A
REFIN = 5V
|I
DD
|
V
/V = ±12V
DD SS
V
/V = ±15V
DD SS
|I
SS
|
–0.2
–40
8
11.4
–20
0
20
40
60
80
100
12.4
13.4
V
14.4
/V (V)
15.4
16.4
TEMPERATURE (°C)
DD SS
Figure 23. Gain Error vs. Temperature
Figure 20. IDD/ISS vs. VDD/VSS
0.25
0.20
0.15
0.10
0.05
0
0.0014
0.0013
0.0012
0.0011
0.0010
0.0009
0.0008
0.0007
0.0006
T
= 25°C
REFIN = 5V
V
/V = ±15V
DD SS
A
5V
V
/V = ±12V
DD SS
–0.05
–0.10
–0.15
–0.20
–0.25
3V
–40
–20
0
20
40
60
80
100
0
0.5
1.0
1.5
2.0
2.5
3.0
(V)
3.5
4.0
4.5
5.0
TEMPERATURE (°C)
V
LOGIC
Figure 21. Zero-Scale Error vs. Temperature
Figure 24. DICC vs. Logic Input Voltage
Rev. 0 | Page 15 of 32
AD5764R
7000
–4
–6
T
= 25°C
A
REFIN = 5V
6000
5000
4000
3000
2000
1000
0
V
/V = ±15V
DD SS
–8
–10
–12
–14
–16
–18
–20
–22
–24
–26
V
/V = ±12V
DD SS
V
/V = ±12V,
DD SS
REFIN = 5V,
= 25°C,
T
A
0x8000 TO 0x7FFF,
500ns/DIV
–1000
–10
–5
0
5
10
–2.0–1.5–1.0–0.5
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
TIME (µs)
SOURCE/SINK CURRENT (mA)
Figure 28. Major Code Transition Glitch Energy, VDD/VSS
= 12 V
Figure 25. Source and Sink Capability of Output Amplifier with
Positive Full Scale Loaded
10,000
9000
8000
7000
6000
5000
4000
3000
2000
1000
0
V
/V = ±15V
DD SS
T
= 25°C
A
MIDSCALE LOADED
REFIN = 0V
REFIN = 5V
V
/V = ±15V
DD SS
V
/V = ±12V
DD SS
4
50µV/DIV
CH4
–1000
CH4 50.0µV
M1.00s
26µV
–12
–7
–2
3
8
SOURCE/SINK CURRENT (mA)
Figure 26. Source and Sink Capability of Output Amplifier with
Negative Full Scale Loaded
Figure 29. Peak-to-Peak Noise (100 kHz Bandwidth)
V
/V = ±12V,
DD SS
T
V
/V = ±15V
= 25°C
DD SS
REFIN = 5V, T = 25°C,
RAMP TIME = 100µs,
LOAD = 200pF||10kΩ
A
T
A
REFIN = 5V
1
2
3
1
1µs/DIV
CH1 –120mV
B
CH1 10.0V
CH2 10.0V
M100µs A CH1
29.60%
7.80mV
CH1 3.00V
M1.00µs
W
B
CH3 10.0mV
T
W
Figure 30. VOUTx vs. VDD/VSS on Power-Up
Figure 27. Full-Scale Settling Time
Rev. 0 | Page 16 of 32
AD5764R
10
9
8
7
6
5
4
3
2
1
0
V
/V = ±12V
= 25°C
DD SS
V
/V = ±15V
= 25°C
DD SS
T
A
T
A
REFIN = 5V
1
5µV/DIV
A CH1
M1.00s
18mV
0
20
40
60
(kΩ)
80
100
120
R
ISCC
Figure 31. Short-Circuit Current vs. RISCC
Figure 34. REFOUT Output Noise 0.1 Hz to 10 Hz
6
T
V
/V = ±12V
DD SS
T
V
= 25°C
A
T
= 25°C
A
/V = ±15V
DD SS
5
4
3
2
1
0
1
2
3
B
B
CH1 10.0V
CH3 5.00V
CH2 10.0V
M400µs A CH1
29.60%
7.80mV
W
W
0
20
40
60
80
100 120 140 160 180 200
T
LOAD CURRENT (µA)
Figure 32. REFOUT Turn-On Transient
Figure 35. REFOUT Load Regulation
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
V
/V = ±12V
= 25°C,
DD SS
T
V
= 25°C
A
T
A
/V = ±15V
DD SS
10µF CAPACITOR ON REFOUT
1
50µV/DIV
A CH1
CH1 50.0µV
M1.00s
15µV
–40
–20
0
20
40
60
80
100
TEMPERATURE (°C)
Figure 36. Temperature Output Voltage vs. Temperature
Figure 33. REFOUT Output Noise 100 kHz Bandwidth
Rev. 0 | Page 17 of 32
AD5764R
40
35
30
25
20
15
10
5
5.003
5.002
5.001
5.000
4.999
4.998
20 DEVICES SHOWN
MAX: 10ppm/°C
TYP: 1.7ppm/°C
0
4.997
–40
–20
0
20
40
60
80
100
0.5
1.5
2.5
3.5
4.5
5.5
6.5
7.5
8.5
9.5
TEMPERATURE DRIFT (ppm/°C)
TEMPERATURE (°C)
Figure 37. Reference Output Voltage vs. Temperature
Figure 38. Reference Output Temperature Drift (−40°C to +85°C)
Rev. 0 | Page 18 of 32
AD5764R
TERMINOLOGY
Total Unadjusted Error (TUE)
Relative Accuracy or Integral Nonlinearity (INL)
For the DAC, a measure of the maximum deviation, in LSBs,
from a straight line passing through the endpoints of the DAC
transfer functionꢀ
A measure of the output error, considering all the various
errorsꢀ Figure 19 shows a plot of total unadjusted error vsꢀ
reference voltageꢀ
Zero-Scale Error Temperature Coefficient
Differential Nonlinearity (DNL)
A measure of the change in zero-scale error with a change in
temperatureꢀ It is expressed as parts per million of full-scale
range per degree Celsius (ppm FSR/°C)ꢀ
The difference between the measured change and the ideal 1 LSB
change between any two adjacent codesꢀ A specified differential
nonlinearity of 1 LSB maximum ensures monotonicityꢀ This DAC
is guaranteed monotonicꢀ
Gain Error Temperature Coefficient
A measure of the change in gain error with changes in tempera-
tureꢀ It is expressed as parts per million of full-scale range per
degree Celsius (ppm FSR/°C)ꢀ
Monotonicity
A DAC is monotonic if the output either increases or remains
constant for increasing digital input codeꢀ The AD5744R is
monotonic over its full operating temperature rangeꢀ
Digital-to-Analog Glitch Energy
The impulse injected into the analog output when the input
code in the DAC register changes stateꢀ It is normally specified
as the area of the glitch in nanovolt-seconds (nꢁ-sec) and is
measured when the digital input code is changed by 1 LSB at the
major carry transition (0x7FFF to 0x8000), as shown in Figure 28ꢀ
Bipolar Zero Error
The deviation of the analog output from the ideal half-scale
output of 0 ꢁ when the DAC register is loaded with 0x8000
(offset binary coding) or 0x0000 (twos complement coding)ꢀ
Figure 22 shows a plot of bipolar zero error vsꢀ temperatureꢀ
Digital Feedthrough
Bipolar Zero Temperature Coefficient
A measure of the impulse injected into the analog output of the
DAC from the digital inputs of the DAC, but measured when
the DAC output is not updatedꢀ It is specified in nanovolt-seconds
(nꢁ-sec) and measured with a full-scale code change on the
data bus, that is, from all 0s to all 1s, and vice versaꢀ
The measure of the change in the bipolar zero error with a
change in temperatureꢀ It is expressed as parts per million of
full-scale range per degree Celsius (ppm FSR/°C)ꢀ
Full-Scale Error
The measure of the output error when full-scale code is loaded
to the DAC registerꢀ Ideally, the output voltage should be 2 ×
Power Supply Sensitivity
Indicates how the output of the DAC is affected by changes in
the power supply voltageꢀ
ꢁ
REFIN − 1 LSBꢀ Full-scale error is expressed as a percentage of
full-scale range (% FSR)ꢀ
DC Crosstalk
Negative Full-Scale Error/Zero-Scale Error
The dc change in the output level of one DAC in response to a
change in the output of another DACꢀ It is measured with a full-
scale output change on one DAC while monitoring another
DAC, and is expressed in least significant bits (LSBs)ꢀ
The error in the DAC output voltage when 0x0000 (offset binary
coding) or 0x8000 (twos complement coding) is loaded to the
DAC registerꢀ Ideally, the output voltage should be −2 × ꢁREFINꢀ
Figure 21 shows a plot of zero-scale error vsꢀ temperatureꢀ
DAC-to-DAC Crosstalk
Output Voltage Settling Time
The glitch impulse transferred to the output of one DAC due to
a digital code change and subsequent output change of another
DACꢀ This includes both digital and analog crosstalkꢀ It is
measured by loading one of the DACs with a full-scale code
The amount of time it takes for the output to settle to a specified
level for a full-scale input changeꢀ
Slew Rate
A limitation in the rate of change of the output voltageꢀ The
output slewing speed of a voltage-output DAC is usually limited
by the slew rate of the amplifier used at its outputꢀ Slew rate is
measured from 10% to 90% of the output signal and is given in
volts per microsecond (ꢁ/μs)ꢀ
LDAC
change (from all 0s to all 1s, and vice versa) with
low and
monitoring the output of another DACꢀ The energy of the glitch
is expressed in nanovolt-seconds (nꢁ-sec)ꢀ
Channel-to-Channel Isolation
The ratio of the amplitude of the signal at the output of one DAC
to a sine wave on the reference input of another DACꢀ It is
measured in decibels (dB)ꢀ
Gain Error
A measure of the span error of the DACꢀ It is the deviation in
slope of the DAC transfer characteristic from the ideal, expressed
as a percentage of the full-scale range (% FSR)ꢀ Figure 23 shows
a plot of gain error vsꢀ temperatureꢀ
Reference Temperature Coefficient
A measure of the change in the reference output voltage with
a change in temperatureꢀ It is expressed in parts per million per
degree Celsius (ppm/°C)ꢀ
Rev. 0 | Page 19 of 32
AD5764R
Digital Crosstalk
Thermal Hysteresis
A measure of the impulse injected into the analog output of one
DAC from the digital inputs of another DAC but is measured
when the DAC output is not updatedꢀ It is specified in nanovolt-
seconds (nꢁ-sec) and measured with a full-scale code change
on the data bus; that is, from all 0s to all 1s, and vice versaꢀ
The change of reference output voltage after the device is cycled
through temperatures from −40°C to +85°C and back to −40°Cꢀ
This is a typical value from a sample of parts put through such
a cycleꢀ
Rev. 0 | Page 20 of 32
AD5764R
THEORY OF OPERATION
The AD5764R is a quad, 16-bit, serial input, bipolar voltage output
DAC that operates from supply voltages of 11ꢀ4 ꢁ to 16ꢀ5 ꢁ and
has a buffered output voltage of up to 10ꢀ5263 ꢀ Data is written to
the AD5764R in a 24-bit word format via a 3-wire serial interfaceꢀ
The AD5764R also offers an SDO pin that is available for daisy
chaining or readbackꢀ
SERIAꢁ INTERFACE
The AD5764R is controlled over a versatile 3-wire serial interface
that operates at clock rates of up to 30 MHz and is compatible
with SPI, QSPI™, MICROWIRE™, and DSP standardsꢀ
Input Shift Register
The input shift register is 24 bits wideꢀ Data is loaded into the
device, MSB first, as a 24-bit word under the control of a serial
clock input, SCLKꢀ The input register consists of a read/write bit,
a reserved bit that must be set to 0, three register select bits, three
DAC address bits, and 16 data bits, as shown in Table 9ꢀ The
timing diagram for this operation is shown in Figure 2ꢀ
The AD5764R incorporates a power-on reset circuit that ensures
that the DAC registers are loaded with 0x0000 at power-upꢀ The
AD5764R features a digital I/O port that can be programmed via
the serial interface, an analog die temperature sensor, on-chip
10 ppm/°C voltage reference, on-chip reference buffers, and per
channel digital gain and offset registersꢀ
Upon power-up, the DAC registers are loaded with zero code
(0x0000) and the outputs are clamped to 0 ꢁ via a low impedance
pathꢀ The outputs can be updated with the zero code value by
DAC ARCHITECTURE
The DAC architecture of the AD5764R consists of a 16-bit
current mode segmented R-2R DACꢀ The simplified circuit
diagram for the DAC section is shown in Figure 39ꢀ
LDAC CLR
asserting either
or ꢀ The corresponding output voltage
2sCOMP
2sCOMP
depends on the state of the BIN/ pinꢀ If the BIN/
R
R
R
V
REF
pin is tied to DGND, the data coding is twos complement and
2sCOMP
the outputs update to 0 ꢀ If the BIN/
pin is tied to
2R
2R
2R
2R
2R
2R
2R
DꢁCC, the data coding is offset binary and the outputs update to
negative full scaleꢀ To have the outputs power up with zero code
R/8
E15
E14
E1
S0
S11
S10
CLR
loaded to the outputs, the
power-upꢀ
pin should be held low during
I
OUT
VOUTx
Standalone Operation
AGNDx
The serial interface works with both a continuous and noncon-
tinuous serial clockꢀ A continuous SCLK source can be used only
4 MSBs DECODED INTO
15 EQUAL SEGMENTS
12-BIT, R-2R LADDER
Figure 39. DAC Ladder Structure
SYNC
if
gated clock mode, a burst clock containing the exact number of
SYNC
is held low for the correct number of clock cyclesꢀ In
The four MSBs of the 16-bit data-word are decoded to drive
15 switches, E1 to E15ꢀ Each of these switches connects one
of the 15 matched resistors to either AGNDx or IOUTꢀ The
remaining 12 bits of the data-word drive Switch S0 to Switch S11
of the 12-bit R-2R ladder networkꢀ
clock cycles must be used, and
the final clock to latch the dataꢀ The first falling edge of
starts the write cycleꢀ Exactly 24 falling clock edges must be
must be taken high after
SYNC
SYNC
SYNC
applied to SCLK before
is brought high againꢀ If
is
brought high before the 24th falling SCLK edge, then the data
written is invalidꢀ If more than 24 falling SCLK edges are applied
REFERENCE BUFFERS
The AD5764R can operate with either an external or an internal
referenceꢀ The reference inputs (REFAB and REFCD) have an
input range of up to 7 ꢀ This input voltage is then used to provide
a buffered positive and negative reference for the DAC coresꢀ
The positive reference is given by
SYNC
before
is brought high, the input data is also invalidꢀ The
SYNC
must be brought
input register addressed is updated on the rising edge of
SYNC
ꢀ
For another serial transfer to take place,
low againꢀ After the end of the serial data transfer, data is
automatically transferred from the input shift register to the
addressed registerꢀ
+VREF = 2 × VREFIN
The negative reference to the DAC cores is given by
−VREF = −2 × VREFIN
When the data has been transferred into the chosen register of
the addressed DAC, all DAC registers and outputs can be updated
These positive and negative reference voltages (along with the
gain register values) define the output ranges of the DACsꢀ
LDAC
by taking
lowꢀ
Rev. 0 | Page 21 of 32
AD5764R
SYNC
A continuous SCLK source can be used only if
is held
68HC11*
MOSI
AD5764R*
low for the correct number of clock cyclesꢀ In gated clock mode,
a burst clock containing the exact number of clock cycles must
SDIN
SCK
PC7
PC6
SCLK
SYNC
LDAC
SYNC
be used, and
latch the dataꢀ
must be taken high after the final clock to
Readback Operation
MISO
SDO
Before a readback operation is initiated, the SDO pin must be
enabled by writing to the function register and clearing the SDO
disable bit; this bit is cleared by defaultꢀ Readback mode is invoked
SDIN
AD5764R*
W
by setting the R/ bit to 1 in the serial input register writeꢀ With
W
SCLK
R/ set to 1, Bit A2 to Bit A0, in association with Bit REG2 to
SYNC
LDAC
Bit REG0, select the register to be readꢀ The remaining data bits in
the write sequence are don’t careꢀ During the next SPI write, the
data appearing on the SDO output contains the data from the
previously addressed registerꢀ For a read of a single register, the
NOP command can be used in clocking out the data from the
selected register on SDOꢀ The readback diagram in Figure 4
shows the readback sequenceꢀ For example, to read back the
fine gain register of Channel A, implement the following
sequence:
SDO
SDIN
AD5764R*
SCLK
SYNC
LDAC
1ꢀ Write 0xA0XXXX to the input registerꢀ This write configures
the AD5764R for read mode with the fine gain register of
Channel A selectedꢀ Note that all the data bits, DB15 to DB0,
are don’t careꢀ
SDO
*ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 40. Daisy-Chaining the AD5764R
2ꢀ Follow with a second write: an NOP condition, 0x00XXXXꢀ
During this write, the data from the fine gain register is clocked
out on the SDO line; that is, data clocked out contains the
data from the fine gain register in Bit DB5 to Bit DB0ꢀ
Daisy-Chain Operation
For systems that contain several devices, the SDO pin can be
used to daisy-chain several devices togetherꢀ This daisy-chain
mode can be useful in system diagnostics and in reducing the
SIMUꢁTANEOUS UPDATING VIA ꢁDAC
SYNC
number of serial interface linesꢀ The first falling edge of
starts the write cycleꢀ The SCLK is continuously applied to the
SYNC
SYNC
LDAC
, and after
Depending on the status of both
and
input shift register when
is lowꢀ If more than 24 clock
data has been transferred into the input register of the DACs,
there are two ways to update the DAC registers and DAC outputsꢀ
pulses are applied, the data ripples out of the shift register and
appears on the SDO lineꢀ This data is clocked out on the rising
edge of SCLK and is valid on the falling edgeꢀ By connecting the
SDO of the first device to the SDIN input of the next device in
the chain, a multidevice interface is constructedꢀ Each device in
the system requires 24 clock pulsesꢀ Therefore, the total number
of clock cycles must equal 24n, where n is the total number of
AD5764R devices in the chainꢀ When the serial transfer to all
Individual DAC Updating
LDAC
In individual DAC updating mode,
is being clocked into the input shift registerꢀ The addressed DAC
SYNC
is held low while data
output is updated on the rising edge of
ꢀ
Simultaneous Updating of All DACs
LDAC
In simultaneous updating of all DACs mode,
is held high
SYNC
devices is complete,
is taken highꢀ This latches the input
while data is being clocked into the input shift registerꢀ All DAC
LDAC SYNC
data in each device in the daisy chain and prevents any further
data from being clocked into the input shift registerꢀ The serial
clock can be a continuous or a gated clockꢀ
outputs are updated by taking
has been taken highꢀ The update then occurs on the falling edge
LDAC
low any time after
of
ꢀ
Rev. 0 | Page 22 of 32
AD5764R
See Figure 41 for a simplified block diagram of the DAC load
circuitryꢀ
The output voltage expression for the AD5764R is given by
D
⎡
⎤
VOUT = −2×VREFIN + 4×VREFIN
OUTPUT
I/V AMPLIFIER
⎢
⎥
65,536
⎣
⎦
16-BIT
REFAB, REFCD
VOUTx
where:
D is the decimal equivalent of the code loaded to the DACꢀ
REFIN is the reference voltage applied at the REFAB and
DAC
V
DAC
REGISTER
LDAC
REFCD pinsꢀ
ASYNCHRONOUS CꢁEAR (CꢁR)
INPUT
REGISTER
CLR
is a negative edge triggered clear that allows the outputs to
be cleared to either 0 ꢁ (twos complement coding) or negative
SCLK
SYNC
SDIN
CLR
INTERFACE
LOGIC
full scale (offset binary coding)ꢀ It is necessary to maintain
low for a minimum amount of time for the operation to complete
SDO
Figure 41. Simplified Serial Interface of Input Loading Circuitry
for One DAC Channel
CLR
(see Figure 2)ꢀ When the
remains at the cleared value until a new value is programmedꢀ
CLR
signal is returned high, the output
TRANSFER FUNCTION
If
is at 0 ꢁ at power-on, all DAC outputs are updated with
Table 7 and Table 8 show the ideal input code to output voltage
relationship for offset binary data coding and twos complement
data coding, respectivelyꢀ
the clear valueꢀ A clear can also be initiated through software by
writing the command of 0x04XXXXꢀ
Table 7. Ideal Output Voltage to Input Code Relationship—Offset Binary Data Coding
Digital Input
Analog Output
MSB
1111
1000
1000
0111
0000
ꢁSB VOUT
1111
0000
0000
1111
0000
1111
0000
0000
1111
0000
1111
0001
0000
1111
0000
+2 VREFIN × (32,767/32,768)
+2 VREFIN × (1/32,768)
0 V
−2 VREFIN × (1/32,768)
−2 VREFIN × (32,767/32,768)
Table 8. Ideal Output Voltage to Input Code Relationship—Twos Complement Data Coding
Digital Input
Analog Output
MSB
0111
0000
0000
1111
1000
ꢁSB VOUT
1111
0000
0000
1111
0000
1111
0000
0000
1111
0000
1111
0001
0000
1111
0000
+2 VREFIN × (32,767/32,768)
+2 VREFIN × (1/32,768)
0 V
−2 VREFIN × (1/32,768)
−2 VREFIN × (32,767/32,768)
Rev. 0 | Page 23 of 32
AD5764R
REGISTERS
Table 9. Input Shift Register Format
MSB
LSB
DB23
DB22
DB21
DB20
DB19
DB18
DB17
DB16
DB15 to DB1
Data
DB0
R/W
0
REG2
REG1
REG0
A2
A1
A0
Table 10. Input Shift Register Bit Function Descriptions
Register Bit
Description
R/W
Indicates a read from or a write to the addressed register
REG2, REG1, REG0
Used in association with the address bits, determines if a read or write operation is to the data register, offset register,
gain register, or function register
REG2
REG1
REG0
Function
0
0
0
1
1
0
1
1
0
0
0
0
1
0
1
Function register
Data register
Coarse gain register
Fine gain register
Offset register
A2, A1, A0
Decodes the DAC channels
A2
A1
0
A0
0
Channel Address
DAC A
0
0
0
1
DAC B
0
1
0
DAC C
0
1
1
DAC D
1
0
0
All DACs
Data
Data bits
FUNCTION REGISTER
The function register is addressed by setting the three REG bits to 000. The values written to the address bits and the data bits determine
the function addressed. The functions available via the function register are outlined in Table 11 and Table 12.
Table 11. Function Register Options
REG2 REG1 REG0 A2 A1 A0 DB15 to DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
0
0
0
0
0
0
0
0
1
NOP, data = don’t care
Don’t care
Local ground D1
D1
D0
D0
SDO
offset adjust
direction
value
direction
value
disable
0
0
0
0
0
0
1
1
0
0
0
1
Clear, data = don’t care
Load, data = don’t care
Table 12. Explanation of Function Register Options
Option
Description
NOP
No operation instruction used in readback operations.
Local Ground
Offset Adjust
Set by the user to enable the local ground offset adjust function. Cleared by the user to disable the local ground offset
adjust function (default). See the Design Features section for more information.
D0, D1
Direction
Set by the user to enable the D0 and D1 pins as outputs. Cleared by the user to enable the D0 and D1 pins as inputs (default).
See the Design Features section for more information.
D0, D1 Value
I/O port status bits. Logic values written to these locations determine the logic outputs on the D0 and D1 pins when
configured as outputs. These bits indicate the status of the D0 and D1 pins when the I/O port is active as an input. When
enabled as inputs, these bits are don’t cares during a write operation.
SDO Disable
Clear
Load
Set by the user to disable the SDO output. Cleared by the user to enable the SDO output (default).
Addressing this function resets the DAC outputs to 0 V in twos complement mode and negative full scale in binary mode.
Addressing this function updates the DAC registers and consequently the analog outputs.
Rev. 0 | Page 24 of 32
AD5764R
DATA REGISTER
The data register is addressed by setting the three REG bits to 010ꢀ The DAC address bits select the DAC channel with which the data
transfer takes place (see Table 10)ꢀ The data bits are positioned in DB15 to DB0, as shown in Table 13ꢀ
Table 13. Programming the Data Register
REG2
REG1
REG0
A2
A1
A0
DB1ꢀ to DB0
0
1
0
DAC address
16-bit DAC data
COARSE GAIN REGISTER
The coarse gain register is addressed by setting the three REG bits to 011ꢀ The DAC address bits select the DAC channel with which the
data transfer takes place (see Table 10)ꢀ The coarse gain register is a 2-bit register that allows the user to select the output range of each
DAC, as shown in Table 15ꢀ
Table 14. Programming the Coarse Gain Register
REG2
REG1
REG0
A2
A1
A0
DB1ꢀ to DB2
DB1
DB0
0
1
1
DAC address
Don’t care
CG1
CG0
Table 15. Output Range Selection
Output Range
CG1
CG0
10 V (Default)
10.2564 V
10.5263 V
0
0
1
0
1
0
FINE GAIN REGISTER
The fine gain register is addressed by setting the three REG bits to 100ꢀ The DAC address bits select the DAC channel with which the data
transfer takes place (see Table 10)ꢀ The AD5764R fine gain register is a 6-bit register that allows the user to adjust the gain of each DAC
channel by −32 LSBs to +31 LSBs in 1 LSB steps, as shown in Table 16 and Table 17ꢀ The adjustment is made to both the positive full-scale
points and the negative full-scale points simultaneously, with each point adjusted by one-half of one stepꢀ The fine gain register coding is
twos complementꢀ
Table 16. Programming the Fine Gain Register
REG2
REG1
REG0
A2
A1
A0
DB1ꢀ to DB6
DBꢀ
DB4
DB3
DB2
DB1
DB0
1
0
0
DAC address
Don’t care
FG5
FG4
FG3
FG2
FG1
FG0
Table 17. Fine Gain Register Options
Gain Adjustment
FGꢀ
FG4
1
1
0
0
FG3
1
1
0
0
FG2
1
1
0
0
FG1
FG0
1
0
0
1
+31 LSBs
+30 LSBs
No Adjustment (Default)
−31 LSBs
−32 LSBs
0
0
0
1
1
1
0
0
0
1
0
0
0
0
Rev. 0 | Page 25 of 32
AD5764R
OFFSET REGISTER
The offset register is addressed by setting the three REG bits to 101ꢀ The DAC address bits select the DAC channel with which the data
transfer takes place (see Table 10)ꢀ The AD5764R offset register is an 8-bit register that allows the user to adjust the offset of each channel
by −16 LSBs to +15ꢀ875 LSBs in steps of one-eighth LSB, as shown in Table 18 and Table 19ꢀ The offset register coding is twos complementꢀ
Table 18. Programming the Offset Register
REG2
REG1
REG0
A2
A1
A0
DB1ꢀ to DB8
DB7
DB6
DBꢀ
DB4
DB3
DB2
DB1
DB0
1
0
1
DAC address
Don’t care
OF7
OF6
OF5
OF4
OF3
OF2
OF1
OF0
Table 19. Offset Register Options
Offset Adjustment
+15.875 LSBs
+15.75 LSBs
No Adjustment (Default)
−15.875 LSBs
OF7
OF6
OFꢀ
OF4
OF3
OF2
OF1
OF0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
0
0
1
0
0
1
0
−16 LSBs
The required offset register value can be calculated as follows:
OFFSET AND GAIN ADJUSTMENT WORKED
EXAMPꢁE
1ꢀ Convert the adjustment value to binary: 00010000ꢀ
2ꢀ Convert this binary value to a negative twos complement
number by inverting all bits and adding 1: 11110000ꢀ
3ꢀ Program this value, 11110000, to the offset registerꢀ
Using the information provided in the Offset Register section,
the following worked examples demonstrate how the AD5764R
functions can be used to eliminate both offset and gain errorsꢀ
Because the AD5764R is factory calibrated, offset and gain errors
should be negligibleꢀ However, errors can be introduced by the
system within which the AD5764R is operatingꢀ For example,
a voltage reference value that is not equal to 5 ꢁ introduces
a gain errorꢀ An output range of 10 ꢁ and twos complement
data coding are assumedꢀ
Note that this twos complement conversion is not necessary in
the case of a positive offset adjustmentꢀ The value to be pro-
grammed to the offset register is simply the binary representation
of the adjustment valueꢀ
Removing Gain Error
The AD5764R can eliminate a gain error at negative full-scale
output in the range of −9ꢀ77 mꢁ to +9ꢀ46 mꢁ with a step size of
one-half of a 16-bit LSBꢀ
Removing Offset Error
The AD5764R can eliminate an offset error in the range of
−4ꢀ88 mꢁ to +4ꢀ84 mꢁ with a step size of one-eighth of a
16-bit LSBꢀ
1ꢀ Calculate the step size of the gain adjustment, using the
following equation:
1ꢀ Calculate the step size of the offset adjustment, using the
following equation:
20
Gain Adjust Step Size =
= 152ꢀ59 μꢁ
216 × 2
20
Offset Adjust Step Size =
= 38ꢀ14 μꢁ
216 × 8
2ꢀ Measure the gain error by programming 0x8000 to the
data register and measuring the resulting output voltageꢀ
The gain error is the difference between this value and −10 ꢀ
For this example, the gain error is −1ꢀ2 m ꢀ
3ꢀ Determine how many gain adjustment steps this value
represents, using the following equation:
2ꢀ Measure the offset error by programming 0x0000 to the
data register and measuring the resulting output voltageꢀ
For this example, the measured value is 614 μ ꢀ
3ꢀ Determine how many offset adjustment steps this value
represents, using the following equation:
Measured GainValue
Gain Step Size
1ꢀ2 mꢁ
152ꢀ59 μꢁ
Number of Steps =
= 8 Steps
=
Measured OffsetValue
Offset Step Size
614 μꢁ
Number of Steps =
= 16 Steps
=
38ꢀ14 μꢁ
The gain error measured is negative (in terms of magnitude)ꢀ
Therefore, a positive adjustment of eight steps is requiredꢀ The
gain register is six bits wide, and the coding is twos complementꢀ
The required gain register value can be determined as follows:
The offset error measured is positive; therefore, a negative
adjustment of 16 steps is requiredꢀ The offset register is
eight bits wide, and the coding is twos complementꢀ
1ꢀ Convert the adjustment value to binary: 001000ꢀ
2ꢀ Program this binary number to the gain registerꢀ
Rev. 0 | Page 26 of 32
AD5764R
DESIGN FEATURES
If the ISCC pin is left unconnected, the short circuit current
ANAꢁOG OUTPUT CONTROꢁ
limit defaults to 5 mAꢀ It should be noted that limiting the short
circuit current to a small value can affect the slew rate of the
output when driving into a capacitive loadꢀ Therefore, the value
of the short-circuit current that is programmed should take into
account the size of the capacitive load being drivenꢀ
In many industrial process control applications, it is vital that
the output voltage be controlled during power-up and during
brownout conditionsꢀ When the supply voltages are changing,
the ꢁOUTx pins are clamped to 0 ꢁ via a low impedance pathꢀ
To prevent the output amp from being shorted to 0 ꢁ during
this time, Transmission Gate G1 is also opened (see Figure 42)ꢀ
DIGITAꢁ I/O PORT
The AD5764R contains a 2-bit digital I/O port (D1 and D0)ꢀ These
bits can be configured independently as inputs or outputs and
can be driven or have their values read back via the serial interfaceꢀ
The I/O port signals are referenced to DꢁCC and DGNDꢀ When
configured as outputs, they can be used as control signals to
multiplexers or can be used to control calibration circuitry
elsewhere in the systemꢀ When configured as inputs, the logic
signals from limit switches, for example, can be applied to D0
and D1 and can be read back using the digital interfaceꢀ
RSTOUT
RSTIN
VOLTAGE
MONITOR
AND
CONTROL
G1
VOUTA
AGNDA
G2
DIE TEMPERATURE SENSOR
Figure 42. Analog Output Control Circuitry
The on-chip die temperature sensor provides a voltage output
that is linearly proportional to the Celsius temperature scaleꢀ
Its nominal output voltage is 1ꢀ47 ꢁ at +25°C die temperature,
varying at 5 mꢁ/°C, giving a typical output range of 1ꢀ175 ꢁ to
1ꢀ9 ꢁ over the full temperature rangeꢀ Its low output impedance,
and linear output simplify interfacing to temperature control
circuitry and analog-to-digital converters (ADCs)ꢀ The temper-
ature sensor is provided as more of a convenience than as a precise
feature; it is intended for indicating a die temperature change for
recalibration purposesꢀ
These conditions are maintained until the power supplies stabilize
and a valid word is written to the DAC registerꢀ G2 then opens, and
G1 closesꢀ Both transmission gates are also externally controllable
RSTIN
RSTIN
by using the reset in ( ) control inputꢀ For example, if
RSTIN
is driven from a battery supervisor chip, the
input is driven
low to open G1 and close G2 on power-off or during a brownoutꢀ
RSTOUT
Conversely, the on-chip voltage detector output (
) is
also available to the user to control other parts of the systemꢀ
The basic transmission gate functionality is shown in Figure 42ꢀ
DIGITAꢁ OFFSET AND GAIN CONTROꢁ
ꢁOCAꢁ GROUND OFFSET ADJUST
The AD5764R incorporates a digital offset adjust function with
a 16 LSB adjust range and 0ꢀ125 LSB resolutionꢀ The gain register
allows the user to adjust the AD5764R full-scale output rangeꢀ
The full-scale output can be programmed to achieve full-scale
ranges of 10 ꢁ, 10ꢀ25 ꢁ, and 10ꢀ5 ꢀ A fine gain trim is also
availableꢀ
The AD5764R incorporates a local ground offset adjust feature
that, when enabled in the function register, adjusts the DAC
outputs for voltage differences between the individual DAC ground
pins and the REFGND pin, ensuring that the DAC output voltages
are always referenced to the local DAC ground pinꢀ For example,
if the AGNDA pin is at +5 mꢁ with respect to the REFGND pin,
and ꢁOUTA is measured with respect to AGNDA, a −5 mꢁ error
results, enabling the local ground offset adjust feature to adjust
ꢁOUTA by +5 mꢁ, thereby eliminating the errorꢀ
PROGRAMMABꢁE SHORT-CIRCUIT PROTECTION
The short-circuit current (ISC) of the output amplifiers can be pro-
grammed by inserting an external resistor between the ISCC
pin and the PGND pinꢀ The programmable range for the current
is 500 μA to 10 mA, corresponding to a resistor range of 120 kΩ
to 6 kΩꢀ The resistor value is calculated as follows:
60
ISC
R ≈
Rev. 0 | Page 27 of 32
AD5764R
APPLICATIONS INFORMATION
Initial accuracy error on the output voltage of an external refer-
ence could lead to a full-scale error in the DAC. Therefore, to
minimize these errors, a reference with low initial accuracy
error specification is preferred. Choosing a reference with an
output trim adjustment, such as the ADR425, allows a system
designer to trim system errors out by setting the reference
voltage to a voltage other than the nominal. The trim adjust-
ment can also be used at temperature to trim out any error.
TYPICAL OPERATING CIRCUIT
Figure 43 shows the typical operating circuit for the AD5764R.
The only external components needed for this precision 16-bit
DAC are decoupling capacitors on the supply pins and reference
inputs, and an optional short-circuit current setting resistor.
Because the AD5764R incorporates a voltage reference and
reference buffers, it eliminates the need for an external bipolar
reference and associated buffers, resulting in an overall savings
in both cost and board space.
Long-term drift is a measure of how much the reference output
voltage drifts over time. A reference with a tight long-term drift
specification ensures that the overall solution remains relatively
stable over its entire lifetime.
In Figure 43, AVDD is connected to +15 V, and AVSS is con-
nected to −15 V, but AVDD and AVSS can operate with supplies
from 11.4 V to 16.5 V. In Figure 43, AGNDx is connected to
REFGND.
The temperature coefficient of a reference output voltage affects
INL, DNL, and TUE. A reference with a tight temperature coeffi-
cient specification should be chosen to reduce the dependence
of the DAC output voltage on ambient conditions.
Precision Voltage Reference Selection
To achieve the optimum performance from the AD5764R over
its full operating temperature range, an external voltage reference
must be used. Care must be taken in the selection of a precision
voltage reference. The AD5764R has two reference inputs,
REFAB and REFCD. The voltages applied to the reference inputs
are used to provide a buffered positive and negative reference
for the DAC cores. Therefore, any error in the voltage reference
is reflected in the outputs of the device.
In high accuracy applications, which have a relatively low noise
budget, reference output voltage noise must be considered. It is
important to choose a reference with as low an output noise
voltage as practical for the system resolution that is required.
Precision voltage references, such as the ADR435 (XFET® design),
produce low output noise in the 0.1 Hz to 10 Hz region. However,
as the circuit bandwidth increases, filtering the output of the
reference may be required to minimize the output noise.
There are four possible sources of error to consider when choosing
a voltage reference for high accuracy applications: initial accuracy,
temperature coefficient of the output voltage, long term drift,
and output voltage noise.
Table 20. Some Precision References Recommended for Use with the AD5764R
Initial Accuracy
(mV Maximum)
Long-Term Drift
(ppm Typical)
Temperature Drift
(ppm/°C Maximum)
0.1 Hz to 10 Hz Noise
(μV p-p Typical)
Part No.
ADR435
ADR425
ADR02
ADR395
AD58±
±±
±±
±5
±±
30
50
50
50
15
3
3
3
25
10
3.5
3.4
10
5
±2.5
4
Rev. 0 | Page 28 of 32
AD5764R
+15V –15V
10µF
10µF
100nF
100nF
TEMP
+5V
BIN/2sCOMP
32 31 30 29 28 27 26 25
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
SYNC
SCLK
SDIN
SDO
SYNC
AGNDA
VOUTA
VOUTB
AGNDB
AGNDC
VOUTC
VOUTD
AGNDD
SCLK
SDIN
SDO
CLR
LDAC
D0
VOUTA
VOUTB
AD5764R
LDAC
D0
VOUTC
VOUTD
D1
D1
9
10 11 12 13 14 15 16
RSTOUT
RSTIN
10µF
100nF
10µF
+5V
+15V –15V
Figure 43. Typical Operating Circuit
Rev. 0 | Page 29 of 32
AD5764R
LAYOUT GUIDELINES
In any circuit where accuracy is important, careful considera-
tion of the power supply and ground return layout helps to
ensure the rated performanceꢀ Design the PCB on which the
AD5764R is mounted such that the analog and digital sections
are separated and confined to certain areas of the boardꢀ If the
AD5764R is in a system where multiple devices require an
AGNDx-to-DGND connection, establish the connection at one
point onlyꢀ Establish the star ground point as close as possible to
the deviceꢀ The AD5764R should have ample supply bypassing of
10 μF in parallel with 0ꢀ1 μF on each supply located as close to
the package as possible, ideally right up against the deviceꢀ The
10 μF capacitors are of the tantalum bead typeꢀ The 0ꢀ1 μF
capacitor should have low effective series resistance (ESR) and low
effective series inductance (ESI), such as the common ceramic
types that provide a low impedance path to ground at high
frequencies to handle transient currents due to internal logic
switchingꢀ
angles to each other to reduce the effects of feedthrough on the
boardꢀ A microstrip technique is recommended but not always
possible with a double-sided boardꢀ In this technique, the com-
ponent side of the board is dedicated to the ground plane, and
the signal traces are placed on the solder sideꢀ
GAꢁVANICAꢁꢁY ISOꢁATED INTERFACE
In many process control applications, it is necessary to provide
an isolation barrier between the controller and the unit being
controlled to protect and isolate the controlling circuitry from
any hazardous common-mode voltages that may occurꢀ Iso-
couplers provide voltage isolation in excess of 2ꢀ5 k ꢀ The serial
loading structure of the AD5764R makes it ideal for isolated
interfaces because the number of interface lines is kept to a mini-
mumꢀ Figure 44 shows a 4-channel isolated interface to the
AD5764R using an ADuM1400 iCoupler® productꢀ For more
information on iCoupler products, refer to wwwꢀanalogꢀcomꢀ
MICROPROCESSOR INTERFACING
The power supply lines of the AD5764R should use as large a trace
as possible to provide low impedance paths and reduce the effects
of glitches on the power supply lineꢀ Shield fast-switching signals,
such as clocks, with digital ground to avoid radiating noise to other
parts of the board; they should never be run near the reference
inputsꢀ A ground line routed between the SDIN and SCLK lines
helps reduce cross talk between themꢀ (A ground line is not
required on a multilayer board because it has a separate ground
plane; however, it is helpful to separate the linesꢀ) It is essential to
minimize noise on the reference inputs because it couples
through to the DAC outputꢀ Avoid crossover of digital and
analog signalsꢀ Run traces on opposite sides of the board at right
Microprocessor interfacing to the AD5764R is accomplished via
a serial bus that uses standard protocol that is compatible with
microcontrollers and DSP processorsꢀ The communication
channel is a 3-wire (minimum) interface consisting of a clock
signal, a data signal, and a synchronization signalꢀ The AD5764R
requires a 24-bit data-word with data valid on the falling edge
of SCLKꢀ
For all the interfaces, a DAC output update can be performed
automatically when all the data is clocked in, or it can be done
under the control of LDACꢀ The contents of the DAC register
can be read using the readback functionꢀ
MICROCONTROLLER
SERIAL CLOCK OUT
ADuM1400*
V
V
V
V
V
V
V
V
IA
OA
OB
OC
OD
ENCODE
ENCODE
ENCODE
ENCODE
DECODE
DECODE
DECODE
DECODE
TO SCLK
TO SDIN
TO SYNC
TO LDAC
IB
IC
ID
SERIAL DATA OUT
SYNC OUT
CONTROL OUT
*ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 44. Isolated Interface
Rev. 0 | Page 30 of 32
AD5764R
USB interface of the PCꢀ Software that allows easy program-
EVAꢁUATION BOARD
ming of the AD5764R is available with the evaluation boardꢀ
The software runs on any PC that has Microsoft® Windows®
2000/XP installedꢀ
The AD5764R comes with a full evaluation board to help designers
evaluate the high performance of the part with a minimum of
effortꢀ All that is required to run the evaluation board is a power
supply and a PCꢀ The AD5764R evaluation kit includes a popu-
lated, tested AD5764R PCBꢀ The evaluation board interfaces to the
Rev. 0 | Page 31 of 32
AD5764R
OUTLINE DIMENSIONS
1.20
MAX
0.75
0.60
0.45
9.00 BSC SQ
25
32
1
24
PIN 1
7.00
BSC SQ
TOP VIEW
(PINS DOWN)
0° MIN
1.05
1.00
0.95
0.20
0.09
7°
8
17
3.5°
0°
0.15
0.05
9
16
SEATING
PLANE
0.08 MAX
COPLANARITY
VIEW A
0.80
0.45
0.37
0.30
BSC
LEAD PITCH
VIEW A
ROTATED 90° CCW
COMPLIANT TO JEDEC STANDARDS MS-026-ABA
Figure 45. 32-Lead Thin Plastic Quad Flat Package [TQFP]
(SU-32-2)
Dimensions shown in millimeters
ORDERING GUIDE
Temperature
Range
Internal
Reference
Package
Description
Package
Option
Model
Function
INꢁ
2 LSB Max
2 LSB Max
1 LSB Max
1 LSB Max
AD5764RBSUZ1
AD5764RBSUZ-REEL71
AD5764RCSUZ1
AD5764RCSUZ-REEL71
Quad 16-Bit DAC
Quad 16-Bit DAC
Quad 16-Bit DAC
Quad 16-Bit DAC
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
+5 V
+5 V
+5 V
+5 V
32-Lead TQFP
32-Lead TQFP
32-Lead TQFP
32-Lead TQFP
SU-32-2
SU-32-2
SU-32-2
SU-32-2
1 Z = RoHS Compliant Part.
©2008 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06064-0-10/08(0)
Rev. 0 | Page 32 of 32
相关型号：
AD5765CSUZ-REEL7
QUAD, SERIAL INPUT LOADING, 8us SETTLING TIME, 16-BIT DAC, PQFP32, ROHS COMPLIANT, MS-026ABA, TQFP-32
ADI
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