AD5765 [ADI]
Complete Quad, 16-Bit, High Accuracy, Serial Input, ±5V DACs; 完整的四通道， 16位，高精度，串行输入， ± 5V数模转换器
| 型号： | AD5765 |
| 厂家： | 
ADI |
| 描述： | Complete Quad, 16-Bit, High Accuracy, Serial Input, ±5V DACs |
| 文件： | 总31页 (文件大小：308K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Complete Quad, 16-Bit, High Accuracy,
Serial Input, ± ±5 ꢀACꢁ
Preliminary Technical ꢀata
Aꢀ±76±
FEATURES
GENERAꢀ DESCRIPTION
Complete quad, 16-bit digital-to-analog
converters (DACs)
Programmable output range:
4.096 V, 4.201 V, or 4.311 V
1 ꢀSB maximum INꢀ error, 1 ꢀSB maximum DNꢀ error
ꢀow noise: 60 nV/√Hz
Settling time: 10 µs maximum
The AD5765 is a quad, 16-bit, serial input, bipolar voltage
output digital-to-analog converter that operates from supply
voltages of ±±475 ꢀ up to ±54.5 ꢀ4 Nominal full-scale output
range is ±±4ꢁ06 ꢀ4 The AD5765 provides integrated output
amplifiers, reference buffers and proprietary power-up/power-
down control circuitry4 The part also features a digital I/O port,
which is programmed via the serial interface4 The parts
Integrated reference buffers
On-chip die temperature sensor
incorporate digital offset and gain adjust registers per channel4
Output control during power-up/brownout
Programmable short-circuit protection
The AD5765 is a high performance converter that offers
guaranteed monotonicity, integral nonlinearity (INL) of ±1 LSB,
low noise, and 1ꢁ µs settling time4 During power-up (when the
supply voltages are changing), the outputs are clamped to ꢁ ꢀ
via a low impedance path4
ꢀDAC
Simultaneous updating via
CꢀR
Asynchronous
to zero code
Digital offset and gain adjust
ꢀogic output control pins
The AD5765 uses a serial interface that operates at clock rates of up
to 3ꢁ MHz and is compatible with DSP and microcontroller
interface standards4 Double buffering allows the simultaneous
updating of all DACs4 The input coding is programmable to either
twos complement or offset binary formats4 The asynchronous clear
function clears all DAC registers to either bipolar zero or zero scale
depending on the coding used4 The AD5765 is ideal for both
closed-loop servo control and open-loop control applications4 The
AD5765 is available in a 3.-lead TQFP, and offers guaranteed
specifications over the −±ꢁ°C to +1ꢁ5°C industrial temperature
range4 See Figure 1, the functional block diagram4
DSP-/microcontroller-compatible serial interface
Temperature range: −40°C to +105°C
iCMOS® process technology1
APPꢀICATIONS
Industrial automation
Open-/closed-loop servo control
Process control
Data acquisition systems
Automatic test equipment
Automotive test and measurement
High accuracy instrumentation
Table 1. Related Devices
Part No.
Description
AD5764
Complete quad, 16-bit, high accuracy, serial
input, 1ꢀ0 output DAC
AD5763
Complete dual, 16-bit, high accuracy, serial
input, 50 DAC
1 For analog systems designers within industrial/instrumentation equipment
OEMs who need high performance ICs at higher voltage levels, iCMOS is a
technology platform that enables the development of analog ICs capable of
3ꢀ 0 and operating at 15 0 supplies, allowing dramatic reductions in power
consumption and package size, and increased ac and dc performance.
Rev. PrA
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2007 Analog Devices, Inc. All rights reserved.
Aꢀ±76±
Preliminary Technical ꢀata
TABLE OF CONTENTS
Features 4444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444444 1
Function Register 44444444444444444444444444444444444444444444444444444444444444444444444 .1
Data Register4444444444444444444444444444444444444444444444444444444444444444444444444444444 .1
Coarse Gain Register 44444444444444444444444444444444444444444444444444444444444444444 .1
Fine Gain Register4444444444444444444444444444444444444444444444444444444444444444444444 ..
Offset Register 4444444444444444444444444444444444444444444444444444444444444444444444444444 ..
Offset and Gain Adjustment Worked Example4444444444444444444444 .3
AD5765 Features 4444444444444444444444444444444444444444444444444444444444444444444444444444 .±
Analog Output Control 4444444444444444444444444444444444444444444444444444444444444 .±
Digital Offset and Gain Control44444444444444444444444444444444444444444444444 .±
Programmable Short-Circuit Protection 44444444444444444444444444444444 .±
Digital I/O Port444444444444444444444444444444444444444444444444444444444444444444444444444 .±
Local Ground Offset Adjust444444444444444444444444444444444444444444444444444444 .±
Applications Information44444444444444444444444444444444444444444444444444444444444444 .5
Typical Operating Circuit 444444444444444444444444444444444444444444444444444444444 .5
Layout Guidelines444444444444444444444444444444444444444444444444444444444444444444444444444 .6
Galvanically Isolated Interface 4444444444444444444444444444444444444444444444444 .6
Microprocessor Interfacing4444444444444444444444444444444444444444444444444444444 .6
Evaluation Board444444444444444444444444444444444444444444444444444444444444444444444444 .7
Outline Dimensions44444444444444444444444444444444444444444444444444444444444444444444444 .8
Ordering Guide 44444444444444444444444444444444444444444444444444444444444444444444444444 .8
Applications444444444444444444444444444444444444444444444444444444444444444444444444444444444444444 1
General Description4444444444444444444444444444444444444444444444444444444444444444444444444 1
Revision History 4444444444444444444444444444444444444444444444444444444444444444444444444444444 .
Functional Block Diagram 44444444444444444444444444444444444444444444444444444444444444 3
Specifications4444444444444444444444444444444444444444444444444444444444444444444444444444444444444 ±
AC Performance Characteristics 4444444444444444444444444444444444444444444444444444 6
Timing Characteristics444444444444444444444444444444444444444444444444444444444444444444444 7
Absolute Maximum Ratings4444444444444444444444444444444444444444444444444444444444 1ꢁ
ESD Caution44444444444444444444444444444444444444444444444444444444444444444444444444444444 1ꢁ
Pin Configuration and Function Descriptions444444444444444444444444444 11
Typical Performance Characteristics 4444444444444444444444444444444444444444444 13
Terminology 444444444444444444444444444444444444444444444444444444444444444444444444444444444444 17
Theory of Operation 4444444444444444444444444444444444444444444444444444444444444444444444 18
DAC Architecture44444444444444444444444444444444444444444444444444444444444444444444444 18
Reference Buffers444444444444444444444444444444444444444444444444444444444444444444444444 18
Serial Interface 4444444444444444444444444444444444444444444444444444444444444444444444444444 18
LDAC
Simultaneous Updating via
4444444444444444444444444444444444444444444 10
Transfer Function44444444444444444444444444444444444444444444444444444444444444444444444 .ꢁ
Asynchronous Clear (
)4444444444444444444444444444444444444444444444444444444 .ꢁ
CLR
REVISION HISTORY
Preliminary ꢀersion: PrA December 11, .ꢁꢁ7
Rev. PrA | Page 2 of 31
Preliminary Technical ꢀata
FUNCTIONAL BLOCK ꢀIAGRAM
Aꢀ±76±
AV
AV
AV
AV
SS
RSTOUT
RSTIN
PGND
REFGND
REFAB
DD
SS
DD
VOLTAGE
MONITOR
AND
DV
CC
REFERENCE
BUFFERS
AD5765
CONTROL
DGND
ISCC
16
16
G1
G1
G1
G1
INPUT
REG A
DAC
REG A
DAC A
DAC B
DAC C
DAC D
SDIN
SCLK
SYNC
SDO
VOUTA
AGNDA
INPUT
SHIFT
G2
G2
G2
G2
REGISTER
AND
GAIN REG A
CONTROL
LOGIC
OFFSET REG A
16
16
16
INPUT
REG B
DAC
REG B
VOUTB
AGNDB
GAIN REG B
OFFSET REG B
D0
D1
INPUT
REG C
DAC
REG C
VOUTC
AGNDC
GAIN REG C
OFFSET REG C
BIN/2sCOMP
INPUT
REG D
DAC
REG D
VOUTD
AGNDD
GAIN REG D
CLR
OFFSET REG D
TEMP
SENSOR
REFERENCE
BUFFERS
LDAC
REFCD
TEMP
Figure 1.
Rev. PrA | Page 3 of 31
Aꢀ±76±
Preliminary Technical ꢀata
SPECIFICATIONS
AꢀDD = ±475 ꢀ to 54.5 ꢀ, AꢀSS = −±475 ꢀ to −54.5 ꢀ, AGNDX = DGND = REFGND = PGND = ꢁ ꢀ; REFAB = REFCD = .4ꢁ±8 ꢀ;
DꢀCC = .47 ꢀ to 54.5 ꢀ, RLOAD = 5 kΩ, CLOAD = .ꢁꢁ pF4 All specifications TMIN to TMAX, unless otherwise noted4
Table 2.
Parameter
B Grade1
C Grade1
Unit
Test Conditions/Comments
ACCURACY
Outputs unloaded
Resolution
16
2
1
16
1
1
Bits
Relative Accuracy (INL)
Differential Nonlinearity
Bipolar Zero Error
LSB max
LSB max
m0 max
Guaranteed monotonic
2
2
At 25°C; error at other
temperatures obtained using
bipolar zero TC
Bipolar Zero TC2
Zero-Scale Error
2
2
2
2
ppm FSR/°C max
m0 max
At 25°C; error at other
temperatures obtained using zero
scale TC
Zero-Scale TC2
Gain Error
2
ꢀ.ꢀ2
2
ꢀ.ꢀ2
ppm FSR/°C max
% FSR max
At 25°C; error at other
temperatures obtained using gain
TC
Gain TC2
DC Crosstalk2
2
ꢀ.5
2
ꢀ.5
ppm FSR/°C max
LSB max
REFERENCE INPUT2
Reference Input 0oltage
DC Input Impedance
Input Current
2.ꢀ48
1
1ꢀ
2.ꢀ48
1
1ꢀ
0 nominal
MΩ min
µA max
1% for specified performance
Typically 1ꢀꢀ MΩ
Typically 3ꢀ nA
Reference Range
1 to 2.1
1 to 2.1
0 min to 0 max
OUTPUT CHARACTERISTICS2
Output 0oltage Range3
4.311
4.42
13
15
1ꢀ
4.311
4.42
13
15
1ꢀ
0 min/0 max
0 min/0 max
ppm FSR/5ꢀꢀ hours typ
ppm FSR/1ꢀꢀꢀ hours typ
mA typ
REFIN = 2.ꢀ480
REFIN = 2.10
Output 0oltage Drift vs. Time
Short Circuit Current
Load Current
RISCC = 6 kΩ, see Figure 29
For specified performance
1
1
mA max
Capacitive Load Stability
RL = ∞
RL = 1ꢀ kΩ
DC Output Impedance
DIGITAL INPUTS2
2ꢀꢀ
1ꢀꢀꢀ
ꢀ.3
2ꢀꢀ
1ꢀꢀꢀ
ꢀ.3
pF max
pF max
Ω max
D0CC = 2.7 0 to 5.25 0, JEDEC
compliant
0IH, Input High 0oltage
0IL, Input Low 0oltage
Input Current
2
ꢀ.8
1
2
ꢀ.8
1
0 min
0 max
µA max
pF max
Per pin
Per pin
Pin Capacitance
1ꢀ
1ꢀ
Rev. PrA | Page 4 of 31
Preliminary Technical ꢀata
Aꢀ±76±
Parameter
B Grade1
C Grade1
Unit
Test Conditions/Comments
DIGITAL OUTPUTS (Dꢀ, D1, SDO)2
Output Low 0oltage
Output High 0oltage
Output Low 0oltage
ꢀ.4
D0CC − 1
ꢀ.4
ꢀ.4
D0CC − 1
ꢀ.4
0 max
0 min
0 max
D0CC = 5 0 5%, sinking 2ꢀꢀ µA
D0CC = 5 0 5%, sourcing 2ꢀꢀ µA
D0CC = 2.7 0 to 3.6 0,
sinking 2ꢀꢀ µA
Output High 0oltage
D0CC − ꢀ.5
D0CC − ꢀ.5
0 min
D0CC = 2.7 0 to 3.6 0,
sourcing 2ꢀꢀ µA
High Impedance Leakage Current
High Impedance Output
Capacitance
1
5
1
5
µA max
pF typ
SDO only
SDO only
POWER REQUIREMENTS
A0DD/A0SS
D0CC
Power Supply Sensitivity2
4.75 to 5.25
2.7 to 5.25
4.75 to 5.25
2.7 to 5.25
0 min/0 max
0 min/0 max
∆0OUT/∆Α0DD
AIDD
AISS
DICC
−85
1.75
1.38
1.2
−85
1.75
1.38
1.2
dB typ
mA/channel max
mA/channel max
mA max
Outputs unloaded
Outputs unloaded
0IH = D0CC, 0IL = DGND, 75ꢀ µA typ
5 0 operation output unloaded
Power Dissipation
138
138
mW typ
1 Temperature range: -4ꢀ°C to +1ꢀ5°C; typical at +25°C.
2 Guaranteed by design and characterization; not production tested.
3 Output amplifier headroom requirement is ꢀ.5 0 minimum.
Rev. PrA | Page 5 of 31
Aꢀ±76±
Preliminary Technical ꢀata
AC PERFORMANCE CHARACTERISTICS
AꢀDD = ±475 ꢀ to 54.5 ꢀ, AꢀSS = −±475 ꢀ to −54.5 ꢀ, AGNDX = DGND = REFGND = PGND = ꢁ ꢀ; REFAB = REFCD = .4ꢁ±8 ꢀ;
DꢀCC = .47 ꢀ to 54.5 ꢀ, RLOAD = 5 kΩ, CLOAD = .ꢁꢁ pF4 All specifications TMIN to TMAX, unless otherwise noted4
Table 3.
Parameter
A Grade B Grade C Grade Unit
Test Conditions/Comments
Full-scale step to 1 LSB
512 LSB step settling
DYNAMIC PERFORMANCE1
Output 0oltage Settling Time
8
8
8
µs typ
1ꢀ
2
1ꢀ
2
1ꢀ
2
µs max
µs typ
Slew Rate
5
8
25
8ꢀ
8
5
8
25
8ꢀ
8
5
8
25
8ꢀ
8
0/µs typ
n0-sec typ
m0 max
dB typ
n0-sec typ
n0-sec typ
n0-sec typ
Digital-to-Analog Glitch Energy
Glitch Impulse Peak Amplitude
Channel-to-Channel Isolation
DAC-to-DAC Crosstalk
Digital Crosstalk
2
2
2
2
2
2
Digital Feedthrough
Effect of input bus activity on DAC
outputs
Output Noise (ꢀ.1 Hz to 1ꢀ Hz)
Output Noise (ꢀ.1 Hz to 1ꢀꢀ kHz)
1/f Corner Frequency
ꢀ.1
45
1
ꢀ.1
45
1
ꢀ.1
45
1
LSB p-p typ
µ0 rms max
kHz typ
Output Noise Spectral Density
Complete System Output Noise Spectral
Density2
6ꢀ
8ꢀ
6ꢀ
8ꢀ
6ꢀ
8ꢀ
n0/√Hz typ
n0/√Hz typ
Measured at 1ꢀ kHz
Measured at 1ꢀ kHz
1 Guaranteed by design and characterization; not production tested.
2 Includes noise contributions from integrated reference buffers, 16-bit DAC and output amplifier.
Rev. PrA | Page 6 of 31
Preliminary Technical ꢀata
TIMING CHARACTERISTICS
Aꢀ±76±
AꢀDD = ±475 ꢀ to 54.5 ꢀ, AꢀSS = −±475 ꢀ to −54.5 ꢀ, AGNDX = DGND = REFGND = PGND = ꢁ ꢀ; REFAB = REFCD = .4ꢁ±8 ꢀ;
DꢀCC = .47 ꢀ to 54.5 ꢀ, RLOAD = 5 kΩ, CLOAD = .ꢁꢁ pF4 All specifications TMIN to TMAX, unless otherwise noted4
Table 4.
Parameter1, 2, 3
ꢀimit at TMIN, TMAX
Unit
Description
t1
t2
t3
t4
33
13
13
13
13
4ꢀ
2
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
µs min
ns min
ns min
ns max
µs max
ns min
µs max
ns max
ns min
µs min
ns min
SCLK cycle time
SCLK high time
SCLK low time
SYNC falling edge to SCLK falling edge setup time
24th SCLK falling edge to SYNC rising edge
Minimum SYNC high time
4
t5
t6
t7
t8
t9
Data setup time
Data hold time
SYNC rising edge to LDAC falling edge (all DACs updated)
SYNC rising edge to LDAC falling edge (single DAC updated)
LDAC pulse width low
5
1.4
4ꢀꢀ
1ꢀ
5ꢀꢀ
1ꢀ
1ꢀ
2
t1ꢀ
t11
t12
t13
t14
LDAC falling edge to DAC output response time
DAC output settling time
CLR pulse width low
CLR pulse activation time
5, 6
t15
25
13
2
SCLK rising edge to SDO valid
SYNC rising edge to SCLK falling edge
SYNC rising edge to DAC output response time (LDAC = ꢀ)
LDAC falling edge to SYNC rising edge
t16
t17
t18
17ꢀ
1 Guaranteed by design and characterization; not production tested.
2 All input signals are specified with tR = tF = 5 ns (1ꢀ% to 9ꢀ% of D0CC) and timed from a voltage level of 1.2 0.
3 See Figure 2, Figure 3, and Figure 4.
4 Standalone mode only.
5 Measured with the load circuit of Figure 5.
6 Daisy-chain mode only.
Rev. PrA | Page 7 of 31
Aꢀ±76±
Preliminary Technical ꢀata
t1
SCLK
SYNC
1
2
24
t3
t2
t6
t4
t5
t8
t7
DB23
SDIN
DB0
t10
t10
t9
LDAC
t18
t12
t11
VOUTX
LDAC = 0
t12
t17
VOUTX
CLR
t13
t14
VOUTX
Figure 2. Serial Interface Timing Diagram
t1
SCLK
24
48
t3
t2
t6
t5
t16
t4
SYNC
SDIN
t8
t7
DB23
DB0
DB23
DB0
INPUT WORD FOR DAC N
INPUT WORD FOR DAC N–1
t15
DB23
DB0
SDO
t9
UNDEFINED
INPUT WORD FOR DAC N
t10
LDAC
Figure 3. Daisy-Chain Timing Diagram
Rev. PrA | Page 8 of 31
Preliminary Technical ꢀata
Aꢀ±76±
SCLK
24
48
SYNC
DB23
DB0
DB23
DB0
SDIN
SDO
NOP CONDITION
INPUT WORD SPECIFIES
REGISTER TO BE READ
DB23
DB0
UNDEFINED
SELECTED REGISTER DATA
CLOCKED OUT
Figure 4. Readback Timing Diagram
200µA
I
OL
V
V
(MIN) OR
(MAX)
TO OUTPUT
PIN
OH
OL
C
L
50pF
200µA
I
OH
Figure 5. Load Circuit for SDO Timing Diagram
Rev. PrA | Page 9 of 31
Aꢀ±76±
Preliminary Technical ꢀata
ABSOLUTE MAXIMUM RATINGS
TA = .5°C, unless otherwise noted4 Transient currents of up to
1ꢁꢁ mA do not cause SCR latch-up4
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device4 This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied4 Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability4
Table 5.
Parameter
Rating
A0DD to AGNDX, DGND
A0SS to AGNDX, DGND
D0CC to DGND
−ꢀ.3 0 to +17 0
+ꢀ.3 0 to −17 0
−ꢀ.3 0 to +7 0
Digital Inputs to DGND
−ꢀ.3 0 to D0CC + ꢀ.3 0 or 7 0
(whichever is less)
ESD CAUTION
Digital Outputs to DGND
REFIN to AGNDX, PGND
0OUTA, 0OUTB, 0OUTC, 0OUTD to
AGNDX
−ꢀ.3 0 to D0CC + ꢀ.3 0
−ꢀ.3 0 to A0DD + ꢀ.30
A0SS to A0DD
AGNDX to DGND
−ꢀ.3 0 to +ꢀ.3 0
Operating Temperature Range (TA)
Industrial
Storage Temperature Range
Junction Temperature (TJ max)
Power Dissipation
−4ꢀ°C to +1ꢀ5°C
−65°C to +15ꢀ°C
15ꢀ°C
(TJ max – TA)/ θJA
32-Lead TQFP
θJA Thermal Impedance
θJC Thermal Impedance
Lead Temperature
65°C/W
12°C/W
JEDEC Industry Standard
J-STD-ꢀ2ꢀ
Soldering
Rev. PrA | Page 1ꢀ of 31
Preliminary Technical ꢀata
Aꢀ±76±
PIN CONFIGURATION ANꢀ FUNCTION ꢀESCRIPTIONS
32 31 30 29 28 27 26 25
1
24
AGNDA
23 VOUTA
22
SYNC
PIN 1
2
3
4
5
6
7
8
SCLK
SDIN
SDO
VOUTB
AD5765
TOP VIEW
(Not to Scale)
21 AGNDB
20 AGNDC
19 VOUTC
18 VOUTD
CLR
LDAC
D0
AGNDD
17
D1
9
10 11 12 13 14 15 16
NC = NO CONNECT
Figure 6. Pin Configuration
Table 6. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
SYNC
Active Low Input. This is the frame synchronization signal for the serial interface. While SYNC is low,
data is transferred in on the falling edge of SCLK.
2
SCLK
Serial Clock Input. Data is clocked into the shift register on the falling edge of SCLK. This operates at
clock speeds up to 3ꢀ MHz.
3
4
51
SDIN
SDO
CLR1
LDAC
Serial Data Input. Data must be valid on the falling edge of SCLK.
Serial Data Output. Used to clock data from the serial register in daisy-chain or readback mode.
Negative Edge Triggered Input. Asserting this pin sets the DAC registers to ꢀxꢀꢀꢀꢀ.
6
Load DAC. Logic input. This is used to update the DAC registers and consequently the analog outputs.
When tied permanently low, the addressed DAC register is updated on the rising edge of SYNC. If
LDAC is held high during the write cycle, the DAC input register is updated but the output update is
held off until the falling edge of LDAC. In this mode, all analog outputs can be updated
simultaneously on the falling edge of LDAC. The LDAC pin must not be left unconnected.
7, 8
Dꢀ, D1
Dꢀ and D1 form a digital I/O port. The user can set up these pins as inputs or outputs that are
configurable and readable over the serial interface. When configured as inputs, these pins have weak
internal pull-ups to D0CC. When programmed as outputs, Dꢀ and D1 are referenced by D0CC and DGND.
9
RSTOUT
RSTIN
Reset Logic Output. This is the output from the on-chip voltage monitor used in the reset circuit. If
desired, it can be used to control other system components.
Reset Logic Input. This input allows external access to the internal reset logic. Applying a Logic ꢀ to
this input clamps the DAC outputs to ꢀ 0. In normal operation, RSTIN should be tied to Logic 1.
Register values remain unchanged.
1ꢀ
11
12
13, 31
14
15, 3ꢀ
16
DGND
D0CC
A0DD
PGND
A0SS
Digital Ground Pin.
Digital Supply Pin. 0oltage ranges from 2.7 0 to 5.25 0.
Positive Analog Supply Pins. 0oltage ranges from 4.75 0 to 5.25 0.
Ground Reference Point for Analog Circuitry.
Negative Analog Supply Pins. 0oltage ranges from –4.75 0 to –5.25 0.
This pin is used in association with an optional external resistor to AGND to program the short-circuit
current of the output amplifiers. Refer to the AD5765 Features section on page 25 for further details.
ISCC
17
18
AGNDD
0OUTD
Ground Reference Pin for DAC D Output Amplifier.
Analog Output 0oltage of DAC D. Buffered output with a nominal full-scale output range of 4.ꢀ96 0. The
output amplifier is capable of directly driving a 5 kΩ, 2ꢀꢀ pF load.
19
0OUTC
Analog Output 0oltage of DAC C. Buffered output with a nominal full-scale output range of 4.ꢀ96 0. The
output amplifier is capable of directly driving a 5 kΩ, 2ꢀꢀ pF load.
Rev. PrA | Page 11 of 31
Aꢀ±76±
Preliminary Technical ꢀata
Pin No.
2ꢀ
21
Mnemonic
AGNDC
AGNDB
Description
Ground Reference Pin for DAC C Output Amplifier.
Ground Reference Pin for DAC B Output Amplifier.
22
0OUTB
Analog Output 0oltage of DAC B. Buffered output with a nominal full-scale output range of 4.ꢀ96 0. The
output amplifier is capable of directly driving a 5 kΩ, 2ꢀꢀ pF load.
23
0OUTA
Analog Output 0oltage of DAC A. Buffered output with a nominal full-scale output range of 4.ꢀ96 0. The
output amplifier is capable of directly driving a 5 kΩ, 2ꢀꢀ pF load.
24
25
AGNDA
REFAB
Ground Reference Pin for DAC A Output Amplifier.
External Reference 0oltage Input for Channel A and Channel B. Reference input range is 1 0 to 2.1 0;
programs the full-scale output voltage. REFIN = 2.ꢀ48 0 for specified performance.
26
REFCD
External Reference 0oltage Input for Channel C and Channel D. Reference input range is 1 0 to 2.1 0;
programs the full-scale output voltage. REFIN = 2.ꢀ48 0 for specified performance.
27
28
29
NC
REFGND
TEMP
No Connect.
Reference Ground Return for the Reference Generator and Buffers.
This pin provides an output voltage proportional to temperature. The output voltage is 1.40 typical at
25°C die temperature; variation with temperature is 5m0/°C.
32
BIN/2sCOMP
Determines the DAC Coding. This pin should be hardwired to either D0CC or DGND. When hardwired to
D0CC, input coding is offset binary. When hardwired to DGND, input coding is twos complement
(see Table 7).
1 Internal pull-up device on this logic input. Therefore, it can be left floating and defaults to a logic high condition.
Rev. PrA | Page 12 of 31
Preliminary Technical ꢀata
Aꢀ±76±
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 7. Integral Nonlinearity Error vs. Code
Figure 8. Differential Nonlinearity Error vs. Code
Figure 9. Integral Nonlinearity Error vs. Temperature
Figure 10. Differential Nonlinearity Error vs. Temperature
Figure 11. Integral Nonlinearity Error vs. Supply voltage
Figure 12. Differential Nonlinearity Error vs. Supply Voltage
Rev. PrA | Page 13 of 31
Aꢀ±76±
Preliminary Technical ꢀata
Figure 13.Integral Nonlinearity Error vs. Reference voltage
Figure 16. AIDD/AISS vs. AVDD/AVSS
Figure 17. Zero-Scale Error vs. Temperature
Figure 18. Bipolar Zero Error vs. Temperature
Figure 14. Differential Nonlinearity Error vs Reference Voltage
Figure 15. Total Unadjusted Error vs. Reference Voltage
Rev. PrA | Page 14 of 31
Preliminary Technical ꢀata
Aꢀ±76±
Figure 19. Gain Error vs. Temperature
Figure 22. Source and Sink Capability of Output Amplifier with Negative
Full-Scale Loaded
Figure 20.DICC vs. Logic Input Voltage
Figure 23. Positive Full-Scale Step
Figure 21. Source and Sink Capability of Output Amplifier with Positive Full-
Scale Loaded
Figure 24. Negative Full-Scale Step
Rev. PrA | Page 15 of 31
Aꢀ±76±
Preliminary Technical ꢀata
Figure 25. Settling Time vs. Load Capacitance
Figure 28. VOUT vs. AVDD/AVSS on Power-up
Figure 26. Major Code Transition Glitch Energy
Figure 29. Short-Circuit Current vs. RISCC
Figure 27. Peak-to-Peak Noise (100 kHz Bandwidth)
Figure 30. TEMP Output Voltage vs. Temperature
Rev. PrA | Page 16 of 31
Preliminary Technical ꢀata
TERMINOLOGY
Aꢀ±76±
Total Unadjusted Error
Relative Accuracy or Integral Nonlinearity (INL)
Total unadjusted error (TUE) is a measure of the output error
considering all the various errors4 A plot of total unadjusted
error vs4 reference can be seen in Figure 154
For the DAC, relative accuracy or integral nonlinearity (INL) is
a measure of the maximum deviation, in LSBs, from a straight
line passing through the endpoints of the DAC transfer
function4 A typical INL vs4 code plot can be seen in Figure 74
Zero-Scale Error TC
Zero-scale error TC is a measure of the change in zero-scale
error with a change in temperature4 Zero-scale error TC is
expressed in ppm FSR/°C4
Differential Nonlinearity (DNL)
Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes4 A specified differential nonlinearity of ±1 LSB maximum
ensures monotonicity4 This DAC is guaranteed monotonic4 A
typical DNL vs4 code plot can be seen in Figure 84
Gain Error TC
Gain error TC is a measure of the change in gain error with
changes in temperature4 Gain Error TC is expressed in
(ppm of FSR)/°C4
Monotonicity
A DAC is monotonic if the output either increases or remains
constant for increasing digital input code4 The AD5765 is
monotonic over its full operating temperature range4
Digital-to-Analog Glitch Energy
Digital-to-analog glitch impulse is the impulse injected into the
analog output when the input code in the DAC register changes
state4 It is normally specified as the area of the glitch in nꢀ-secs
and is measured when the digital input code is changed by 1 LSB at
the major carry transition (ꢁx7FFF to ꢁx8ꢁꢁꢁ) (see Figure .6)4
Bipolar Zero Error
Bipolar zero error is the deviation of the analog output from the
ideal half-scale output of ꢁ ꢀ when the DAC register is loaded
with ꢁx8ꢁꢁꢁ (offset binary coding) or ꢁxꢁꢁꢁꢁ (twos complement
coding)4 A plot of bipolar zero error vs4 temperature can be seen
in Figure 184
Digital Feedthrough
Digital feedthrough is a measure of the impulse injected into
the analog output of the DAC from the digital inputs of the
DAC but is measured when the DAC output is not updated4 It is
specified in nꢀ-secs and measured with a full-scale code change
on the data bus, that is, from all ꢁs to all 1s, and vice versa4
Bipolar Zero Temperature Coefficient
Bipolar zero TC is the measure of the change in the bipolar zero
error with a change in temperature4 It is expressed in ppm FSR/°C4
Power Supply Sensitivity
Power supply sensitivity indicates how the output of the DAC is
affected by changes in the power supply voltage4
Full-Scale Error
Full-scale error is a measure of the output error when full-scale
code is loaded to the DAC register4 Ideally the output voltage
should be . × ꢀREF − 1 LSB4 Full-scale error is expressed in
percentage of full-scale range4
DC Crosstalk
DC crosstalk is the dc change in the output level of one DAC in
response to a change in the output of another DAC4 It is
measured with a full-scale output change on one DAC while
monitoring another DAC, and is expressed in LSBs4
Negative Full-Scale Error/Zero Scale Error
Negative full-scale error is the error in the DAC output voltage
when ꢁxꢁꢁꢁꢁ (offset binary coding) or ꢁx8ꢁꢁꢁ (twos
complement coding) is loaded to the DAC register4 Ideally, the
output voltage should be −. × ꢀREF4 A plot of zero-scale error vs4
temperature can be seen in Figure 174
DAC-to-DAC Crosstalk
DAC-to-DAC crosstalk is the glitch impulse transferred to the
output of one DAC due to a digital code change and subsequent
output change of another DAC4 This includes both digital and
analog crosstalk4 It is measured by loading one of the DACs
with a full-scale code change (all ꢁs to all 1s and vice versa) with
Output Voltage Settling Time
Output voltage settling time is the amount of time it takes for the
output to settle to a specified level for a full-scale input change4
LDAC
low and monitoring the output of another DAC4 The
Slew Rate
energy of the glitch is expressed in nꢀ-sec4
The slew rate of a device is a limitation in the rate of change of
the output voltage4 The output slewing speed of a voltage-
output D/A converter is usually limited by the slew rate of the
amplifier used at its output4 Slew rate is measured from 1ꢁ% to
0ꢁ% of the output signal and is given in ꢀ/µs4
Channel-to-Channel Isolation
Channel-to-channel isolation is the ratio of the amplitude of the
signal at the output of one DAC to a sine wave on the reference
input of another DAC4 It is measured in dB4
Digital Crosstalk
Gain Error
Digital crosstalk is a measure of the impulse injected into the
analog output of one DAC from the digital inputs of another
DAC but is measured when the DAC output is not updated4 It is
specified in nꢀ-secs and measured with a full-scale code change
on the data bus, that is, from all ꢁs to all 1s, and vice versa4
Gain error is a measure of the span error of the DAC4 It is the
deviation in slope of the DAC transfer characteristic from the
ideal, expressed as a percentage of the full-scale range4 A plot of
gain error vs4 temperature can be seen in Figure 104
Rev. PrA | Page 17 of 31
Aꢀ±76±
Preliminary Technical ꢀata
THEORY OF OPERATION
The AD5765 is a quad, 16-bit, serial input, bipolar voltage output
DAC and operates from supply voltages of ±±475 ꢀ to ±54.5 ꢀ and
has a buffered output voltage of up to ±±4311 ꢀ4 Data is written to
the AD5765 in a .±-bit word format, via a 3-wire serial interface4
The device also offers an SDO pin, which is available for daisy-
chaining or readback4
SERIAꢀ INTERFACE
The AD5765 is controlled over a versatile 3-wire serial interface
that operates at clock rates of up to 3ꢁ MHz and is compatible
with SPI®, QSPI™, MICROWIRE™, and DSP standards4
Input Shift Register
The input shift register is .± bits wide4 Data is loaded into the
device MSB first as a .±-bit word under the control of a serial
clock input, SCLK4 The input register consists of a read/write
bit, three register select bits, three DAC address bits and 16 data
bits as shown in Table 84 The timing diagram for this operation
is shown in Figure .4
The AD5765 incorporates a power-on reset circuit, which
ensures that the DAC registers power up loaded with ꢁxꢁꢁꢁꢁ4
The AD5765 features a digital I/O port that can be programmed
via the serial interface, on-chip reference buffers and per
channel digital gain, and offset registers4
DAC ARCHITECTURE
Upon power-up, the DAC registers are loaded with zero code
(ꢁxꢁꢁꢁꢁ) and the outputs are clamped to ꢁ ꢀ via a low impedance
path4 The outputs can be updated with the zero code value at this
The DAC architecture of the AD5765 consists of a 16-bit
current mode segmented R-.R DAC4 The simplified circuit
diagram for the DAC section is shown in Figure 314
LDAC CLR
time by asserting either
or 4 The corresponding output
The four MSBs of the 16-bit data word are decoded to drive 15
switches, E1 to E154 Each of these switches connects one of the
15 matched resistors to either AGNDX or IOUT4 The remaining
1. bits of the data-word drive switches Sꢁ to S11 of the 1.-bit
R-.R ladder network4
.sCOMP
voltage depends on the state of the BIN/
.sCOMP
BIN/
pin4 If the
pin is tied to DGND, then the data coding is twos
.sCOMP
complement and the outputs update to ꢁ ꢀ4 If the BIN/
pin is tied to DꢀCC, then the data coding is offset binary and the
outputs update to negative full-scale4 To have the outputs power-up
CLR
R
R
R
V
with zero code loaded to the outputs, the
low during power-up4
pin should be held
REF
2R
2R
2R
2R
2R
2R
2R
Standalone Operation
R/8
The serial interface works with both a continuous and noncon-
tinuous serial clock4 A continuous SCLK source can only be
E15
E14
E1
S0
S11
S10
IOUT
SYNC
used if
In gated clock mode, a burst clock containing the exact number
SYNC
is held low for the correct number of clock cycles4
VOUTX
AGNDX
of clock cycles must be used and
the final clock to latch the data4 The first falling edge of
starts the write cycle4 Exactly .± falling clock edges must be
must be taken high after
4 MSBs DECODED INTO
15 EQUAL SEGMENTS
12-BIT, R-2R LADDER
SYNC
Figure 31. DAC Ladder Structure
REFERENCE BUFFERS
SYNC
applied to SCLK before
SYNC
is brought back high again4 If
th
is brought high before the .± falling SCLK edge, then
The AD5765 operates with an external reference4 The reference
inputs (REFAB and REFCD) have an input range up to .41 ꢀ4
This input voltage is then used to provide a buffered positive
and negative reference for the DAC cores4 The positive
reference is given by
the data written is invalid4 If more than .± falling SCLK edges
SYNC
are applied before
also invalid4 The input register addressed is updated on the
SYNC
is brought high, then the input data is
rising edge of
4 In order for another serial transfer to take
must be brought low again4 After the end of the
SYNC
place,
+ꢀREF = .ꢀREF
serial data transfer, data is automatically transferred from the
input shift register to the addressed register4
The negative reference to the DAC cores is given by
−ꢀREF = −.ꢀREF
When the data has been transferred into the chosen register of
the addressed DAC, all DAC registers and outputs can be
These positive and negative reference voltages (along with the
gain register values) define the output ranges of the DACs4
LDAC
updated by taking
low4
Rev. PrA | Page 18 of 31
Preliminary Technical ꢀata
Aꢀ±76±
SDO DISABLE bit; this bit is cleared by default4 Readback mode
1
AD57651
68HC11
W
is invoked by setting the R/ bit = 1 in the serial input register
MOSI
SCK
PC7
SDIN
W
write4 With R/ = 1, Bit A. to Bit Aꢁ, in association with Bit
SCLK
SYNC
LDAC
REG., Bit REG1, and Bit REGꢁ, select the register to be read4
The remaining data bits in the write sequence are don’t care4
During the next SPI write, the data appearing on the SDO
output contain the data from the previously addressed register4
For a read of a single register, the NOP command can be used
in clocking out the data from the selected register on SDO4 The
readback diagram in Figure ± shows the readback sequence4 For
example, to read back the fine gain register of Channel A on the
AD5765, the following sequence should be implemented:
PC6
MISO
SDO
SDIN
AD57651
SCLK
SYNC
LDAC
14 Write ꢁxAꢁXXXX to the AD5765 input register4 This
configures the AD5765 for read mode with the fine gain
register of Channel A selected4 Note that all the data bits,
DB15 to DBꢁ, are don’t cares4
SDO
SDIN
.4 Follow this with a second write, an NOP condition,
ꢁxꢁꢁXXXX4 During this write, the data from the fine gain
register is clocked out on the SDO line, that is, data clocked
out contain the data from the fine gain register in Bit DB5 to
Bit DBꢁ4
AD57651
SCLK
SYNC
LDAC
SDO
SIMUꢀTANEOUS UPDATING VIA ꢀDAC
SYNC
LDAC
, and after
Depending on the status of both
and
1
ADDITIONAL PINS OMITTED FOR CLARITY
data has been transferred into the input register of the DACs,
there are two ways in which the DAC registers and DAC
outputs can be updated4
Figure 32. Daisy-Chaining the AD5765
Daisy-Chain Operation
For systems that contain several devices, the SDO pin can be
used to daisy-chain several devices together4 This daisy-chain
mode can be useful in system diagnostics and in reducing the
Individual DAC Updating
LDAC
In this mode,
the input shift register4 The addressed DAC output is updated
SYNC
is held low while data is being clocked into
SYNC
number of serial interface lines4 The first falling edge of
starts the write cycle4 The SCLK is continuously applied to the
SYNC
on the rising edge of
Simultaneous Updating of All DACs
LDAC
4
input shift register when
is low4 If more than .± clock
pulses are applied, the data ripples out of the shift register and
appears on the SDO line4 This data is clocked out on the rising
edge of SCLK and is valid on the falling edge4 By connecting the
SDO of the first device to the SDIN input of the next device in
the chain, a multidevice interface is constructed4 Each device in
the system requires .± clock pulses4 Therefore, the total number
of clock cycles must equal .±N, where N is the total number of
AD5765 devices in the chain4 When the serial transfer to all
In this mode,
into the input shift register4 All DAC outputs are updated by
LDAC SYNC
is held high while data is being clocked
taking
low any time after
has been taken high4
LDAC
The update now occurs on the falling edge of
4
OUTPUT
I/V AMPLIFIER
16-BIT
DAC
V
REFIN
V
OUT
SYNC
devices is complete,
is taken high4 This latches the input
DAC
data in each device in the daisy chain and prevents any further
data from being clocked into the input shift register4 The serial
clock can be a continuous or a gated clock4
LDAC
REGISTER
INPUT
REGISTER
SYNC
A continuous SCLK source can only be used if
is held
low for the correct number of clock cycles4 In gated clock mode,
a burst clock containing the exact number of clock cycles must
SCLK
SYNC
SDIN
INTERFACE
LOGIC
SDO
SYNC
be used and
latch the data4
must be taken high after the final clock to
Figure 33. Simplified Serial Interface of Input Loading Circuitry
for One DAC Channel
Readback Operation
Before a readback operation is initiated, the SDO pin must be
enabled by writing to the function register and clearing the
Rev. PrA | Page 19 of 31
Aꢀ±76±
Preliminary Technical ꢀata
TRANSFER FUNCTION
The output voltage expression for the AD5765 is given by
Table 7 shows the ideal input code to output voltage
relationship for the AD5765 for both offset binary and twos
complement data coding4
D
⎡
⎣
⎤
⎦
VOUT = −2×VREFIN + 4×VREFIN
⎢
⎥
65536
where:
D is the decimal equivalent of the code loaded to the DAC4
REFIN is the reference voltage applied at the REFAB/REFCD pins4
Table 7. Ideal Output Voltage to Input Code Relationship
Digital Input
Analog Output
V
Offset Binary Data Coding
MSB
ꢀSB VOUTX
ASYNCHRONOUS CꢀEAR (
)
CꢀR
1111 1111
1ꢀꢀꢀ ꢀꢀꢀꢀ
1ꢀꢀꢀ ꢀꢀꢀꢀ
ꢀ111 1111
ꢀꢀꢀꢀ ꢀꢀꢀꢀ
1111
ꢀꢀꢀꢀ
ꢀꢀꢀꢀ
1111
ꢀꢀꢀꢀ
1111
ꢀꢀꢀ1
ꢀꢀꢀꢀ
1111
ꢀꢀꢀꢀ
20REF × (32767/32768)
20REF × (1/32768)
ꢀ 0
is a negative edge triggered clear that allows the outputs to
CLR
be cleared to either ꢁ ꢀ (twos complement coding) or negative
full scale (offset binary coding)4 It is necessary to maintain
low for a minimum amount of time (see Figure .) for the
CLR
−.0REF × (1/32768)
−.0REF × (32767/32768)
operation to complete4 When the
signal is returned high,
CLR
the output remains at the cleared value until a new value is
programmed4 If at power-on, is at ꢁ ꢀ, then all DAC
Twos Complement Data Coding
MSB
ꢀSB VOUTX
CLR
ꢀ111 1111
ꢀꢀꢀꢀ ꢀꢀꢀꢀ
ꢀꢀꢀꢀ ꢀꢀꢀꢀ
1111 1111
1ꢀꢀꢀ ꢀꢀꢀꢀ
1111
ꢀꢀꢀꢀ
ꢀꢀꢀꢀ
1111
ꢀꢀꢀꢀ
1111
ꢀꢀꢀ1
ꢀꢀꢀꢀ
1111
ꢀꢀꢀꢀ
20REF × (32767/32768)
20REF × (1/32768)
ꢀ 0
outputs are updated with the clear value4 A clear can also be
initiated through software by writing the command ꢁxꢁ±XXXX
to the AD57654
−.0REF × (1/32768)
−.0REF × (32767/32768)
Table 8. AD5765 Input Register Format
MSB
LSB
DB23
DB22
ꢀ
DB21
REG2
DB2ꢀ
REG1
DB19
REGꢀ
DB18
A2
DB17
A1
DB16
Aꢀ
DB15
DB14
DB13
DB12
DB11
DB1ꢀ
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DBꢀ
W
R/
DATA
Table 9. Input Register Bit Functions
Bit
Description
R/W
Indicates a read from or a write to the addressed register.
REG2, REG1, REGꢀ
Used in association with the address bits to determine if a read or write operation is to the data register, offset
register, gain register, or function register.
REG2
REG1
REG0
Function
ꢀ
ꢀ
ꢀ
1
1
ꢀ
1
1
ꢀ
ꢀ
ꢀ
ꢀ
1
ꢀ
1
Function Register
Data Register
Coarse Gain Register
Fine Gain Register
Offset Register
A2, A1, Aꢀ
These bits are used to decode the DAC channels.
A2
A1
ꢀ
A0
ꢀ
Channel Address
DAC A
ꢀ
ꢀ
ꢀ
1
DAC B
ꢀ
1
ꢀ
DAC C
ꢀ
1
1
DAC D
1
ꢀ
ꢀ
ALL DACs
D15:Dꢀ
Data Bits.
Rev. PrA | Page 2ꢀ of 31
Preliminary Technical ꢀata
Aꢀ±76±
FUNCTION REGISTER
The function register is addressed by setting the three REG bits to ꢁꢁꢁ4 The values written to the address bits and the data bits determine
the function addressed4 The functions available via the function register are outlined in Table 1ꢁ and Table 114
Table 10. Function Register Options
REG2 REG1 REG0 A2 A1 A0
DB15:DB6
DB5
DB4
DB3
DB2
DB1
DB0
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
1
NOP, Data = Don’t Care
Don’t Care
Local-
Ground-
Offset Adjust
D1
Direction
D1
0alue
Dꢀ
Direction
Dꢀ
0alue
SDO
Disable
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
1
1
ꢀ
ꢀ
ꢀ
1
CLR, Data = Don’t Care
LOAD, Data = Don’t Care
Table 11. Explanation of Function Register Options
Option
Description
NOP
No operation instruction used in readback operations.
Local-Ground-
Offset Adjust
Set by the user to enable local-ground-offset adjust function. Cleared by the user to disable local-ground-offset adjust
function (default). Refer to Features section for further details.
Dꢀ/D1 Direction
Set by the user to enable Dꢀ/D1 as outputs. Cleared by the user to enable Dꢀ/D1 as inputs (default). Refer to the
Features section for further details.
Dꢀ/D1 0alue
I/O Port Status Bits. Logic values written to these locations determine the logic outputs on the Dꢀ and D1 pins when
configured as outputs. These bits indicate the status of the Dꢀ and D1 pins when the I/O port is active as an input.
When enabled as inputs, these bits are don’t cares during a write operation.
SDO Disable
CLR
LOAD
Set by the user to disable the SDO output. Cleared by the user to enable the SDO output (default).
Addressing this function resets the DAC outputs to ꢀ 0 in twos complement mode and negative full scale in binary mode.
Addressing this function updates the DAC registers and consequently the analog outputs.
DATA REGISTER
The data register is addressed by setting the three REG bits to ꢁ1ꢁ4 The DAC address bits select with which DAC channel the data transfer
is to take place (see Table 0)4 The data bits are in positions DB15 to DBꢁ as shown in Table 1.4
Table 12. Programming the AD5765 Data Register
REG2
REG1
REG0
A2
A1
A0
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
ꢀ
1
ꢀ
DAC Address
16-Bit DAC Data
COARSE GAIN REGISTER
The coarse gain register is addressed by setting the three REG bits to ꢁ114 The DAC address bits select with which DAC channel the data
transfer is to take place (see Table 0)4 The coarse gain register is a .-bit register and allows the user to select the output range of each DAC
as shown in Table 13 and Table 1±4
Table 13. Programming the AD5765 Coarse Gain Register
REG2
REG1
REG0
A2
A1
A0
DB15 …. DB2
DB1
DB0
ꢀ
1
1
DAC Address
Don’t Care
CG1
CGꢀ
Table 14. Output Range Selection
Output Range
4.ꢀ96 0 (default)
4.2ꢀ1 0
CG1
CG0
ꢀ
ꢀ
1
ꢀ
1
ꢀ
4.331 0
Rev. PrA | Page 21 of 31
Aꢀ±76±
Preliminary Technical ꢀata
FINE GAIN REGISTER
The fine gain register is addressed by setting the three REG bits to 1ꢁꢁ4 The DAC address bits select with which DAC channel the data
transfer is to take place (see Table 0)4 The fine gain register is a 6-bit register and allows the user to adjust the gain of each DAC channel
by −3. LSBs to +31 LSBs in 1 LSB increments as shown in Table 15 and Table 164 The adjustment is made to both the positive full-scale
and negative full-scale points simultaneously, each point being adjusted by ½ of one step4 The fine gain register coding is twos
complement4
Table 15. Programming AD5765 Fine Gain Register
REG2
REG1
REG0
A2
A1
A0
DB15:DB6
DB5
DB4
DB3
DB2
DB1
DB0
1
ꢀ
ꢀ
DAC Address
Don’t Care
FG5
FG4
FG3
FG2
FG1
FGꢀ
Table 16. AD5765 Fine Gain Register Options
Gain Adjustment
FG5
FG4
FG3
FG2
FG1
FG0
+31 LSBs
+3ꢀ LSBs
ꢀ
ꢀ
-
1
1
-
1
1
-
1
1
-
1
1
-
1
ꢀ
-
No Adjustment (default)
ꢀ
-
ꢀ
-
ꢀ
-
ꢀ
-
ꢀ
-
ꢀ
-
−31 LSBs
−32 LSBs
1
1
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
1
ꢀ
OFFSET REGISTER
The offset register is addressed by setting the three REG bits to 1ꢁ14 The DAC address bits select with which DAC channel the data
transfer is to take place (see Table 0)4 The AD5765 offset register is an 8-bit register and allows the user to adjust the offset of each channel
by −16 LSBs to +154875 LSBs in increments of ⅛ LSB as shown in Table 17 and Table 184 The offset register coding is twos complement4
Table 17. Programming the AD5765 Offset Register
REG2
REG1
REG0
A2
A1
A0
DB15:DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
1
ꢀ
1
DAC Address
Don’t Care
OF7
OF6
OF5
OF4
OF3
OF2
OF1
OFꢀ
Table 18. AD5765 Offset Register options
Offset Adjustment
OF7
OF6
OF5
OF4
OF3
OF2
OF1
OF0
+15.875 LSBs
+15.75 LSBs
ꢀ
ꢀ
-
1
1
-
1
1
-
1
1
-
1
1
-
1
1
-
1
1
-
1
ꢀ
-
No Adjustment (default)
ꢀ
-
ꢀ
-
ꢀ
-
ꢀ
-
ꢀ
-
ꢀ
-
ꢀ
-
ꢀ
-
−15.875 LSBs
−16 LSBs
1
1
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
1
ꢀ
Rev. PrA | Page 22 of 31
Preliminary Technical ꢀata
Aꢀ±76±
Convert this to a negative twos complement number by
inverting all bits and adding 1: 11ꢁ11ꢁꢁꢁ4
OFFSET AND GAIN ADJUSTMENT WORKED
EXAMPꢀE
11ꢁ11ꢁꢁꢁ is the value that should be programmed to the offset
register4
Using the information provided in the previous section, the
following worked example demonstrates how the AD5765
functions can be used to eliminate both offset and gain errors4
As the AD5765 is factory calibrated, offset and gain errors
should be negligible4 However, errors can be introduced by the
system that the AD5765 is operating within, for example, a
voltage reference value that is not equal to .4ꢁ±8 ꢀ introduces a
gain error4 An output range of ±±4ꢁ06 ꢀ and twos complement
data coding is assumed4
Note that this twos complement conversion is not necessary in
the case of a positive offset adjustment4 The value to be
programmed to the offset register is simply the binary
representation of the adjustment value4
Removing Gain Error
The AD5765 can eliminate a gain error at negative full-scale
output in the range of −. mꢀ to +140± mꢀ with a step size of ½
of a 16-bit LSB4
Removing Offset Error
The AD5765 can eliminate an offset error in the range of −. mꢀ to
+1408 mꢀ with a step size of ⅛ of a 16-bit LSB4
Calculate the step size of the gain adjustment4
8.192
Gain Adjust Step Size =
= 62.5 µV
216 × 2
Calculate the step size of the offset adjustment4
8.192
Measure the gain error by programming ꢁx8ꢁꢁꢁ to the data
register and measuring the resulting output voltage4 The gain
error is the difference between this value and −±4ꢁ06 ꢀ; for this
example, the gain error is −ꢁ48 mꢀ4
Offset Adjust Step Size =
= 15.625 µV
216 × 8
Measure the offset error by programming ꢁxꢁꢁꢁꢁ to the data
register and measuring the resulting output voltage, for this
example the measured value is 61± µꢀ4
Calculate how many gain adjustment steps this value represents4
Calculate the number of offset adjustment steps that this value
represents4
Measured Gain Value 0.8 mV
Number of Steps =
=
=13 Steps
Gain Step Size
62.5 µV
Measured Offset Value
Offset Step Size
614 µV
15.625 µV
The gain error measured is negative (in terms of magnitude);
therefore, a positive adjustment of 13 steps is required4 The gain
register is 6 bits wide and the coding is twos complement, the
required gain register value can be determined as follows:
Convert adjustment value to binary: ꢁꢁ11ꢁ14
The value to be programmed to the gain register is simply this
binary number4
Numberof Steps =
=
= 40 Steps
The offset error measured is positive, therefore, a negative
adjustment of ±ꢁ steps is required4 The offset register is 8 bits
wide and the coding is twos complement4 The required offset
register value can be calculated as follows:
Convert adjustment value to binary: ꢁꢁ1ꢁ1ꢁꢁꢁ4
Rev. PrA | Page 23 of 31
Aꢀ±76±
Aꢀ±76± FEATURES
If the ISCC pin is left unconnected, the short-circuit current
ANAꢀOG OUTPUT CONTROꢀ
limit defaults to 5 mA4 It should be noted that limiting the short
circuit current to a small value can affect the slew rate of the
output when driving into a capacitive load, therefore, the value
of short-circuit current programmed should take into account
the size of the capacitive load being driven4
In many industrial process control applications, it is vital that
the output voltage be controlled during power-up and during
brownout conditions4 When the supply voltages are changing,
the output pins are clamped to ꢁ ꢀ via a low impedance path4
To prevent the output amp being shorted to ꢁ ꢀ during this
time, transmission gate G1 is also opened (see Figure 3±)4 These
conditions are maintained until the power supplies stabilize and
a valid word is written to the DAC register4 At this time, G.
opens and G1 closes4 Both transmission gates are also externally
DIGITAꢀ I/O PORT
The AD5765 contains a .-bit digital I/O port (D1 and Dꢁ)4
These bits can be configured as inputs or outputs independently,
and can be driven or have their values read back via the serial
interface4 The I/O port signals are referenced to DꢀCC and
DGND4 When configured as outputs, they can be used as
control signals to multiplexers or can be used to control
calibration circuitry elsewhere in the system4 When configured
as inputs, the logic signals from limit switches, for example, can
be applied to Dꢁ and D1 and can be read back via the digital
interface4
RSTIN
controllable via the reset logic (
) control input4 For
is driven from a battery supervisor chip, the
input is driven low to open G1 and close G. on power-
down or during a brownout4 Conversely, the on-chip voltage
RSTOUT
RSTIN
instance, if
RSTIN
detector output (
) is also available to the user to
control other parts of the system4 The basic transmission gate
functionality is shown in Figure 3±4
RSTOUT
RSTIN
DIE TEMPERATURE SENSOR
The on-chip die temperature sensor provides a voltage output
that is linearly proportional to the centigrade temperature scale4
Its nominal output voltage is 14± ꢀ at +.5°C die temperature,
varying at 5 mꢀ/°C, giving a typical output range of 14175 ꢀ to
140 ꢀ over the full temperature range4 Its low output impedance,
and linear output simplify interfacing to temperature control
circuitry and A/D converters4 The temperature sensor is
provided as more of a convenience rather than a precise feature;
it is intended for indicating a die temperature change for
recalibration purposes4
VOLTAGE
MONITOR
AND
CONTROL
G1
VOUTA
AGNDA
G2
Figure 34. Analog Output Control Circuitry
DIGITAꢀ OFFSET AND GAIN CONTROꢀ
ꢀOCAꢀ GROUND OFFSET ADJUST
The AD5765 incorporates a digital offset adjust function with a
±16 LSB adjust range and ꢁ41.5 LSB resolution4 The gain
register allows the user to adjust the AD5765 full-scale output
range4 The full-scale output can be programmed to achieve full-
scale ranges of ±±4ꢁ06 ꢀ, ±±4.ꢁ1 ꢀ, and ±±4311 ꢀ4 A fine gain
trim is also provided4
The AD5765 incorporates a local-ground-offset adjust feature
which, when enabled in the function register, adjusts the DAC
outputs for voltage differences between the individual DAC
ground pins and the REFGND pin ensuring that the DAC
output voltages are always with respect to the local DAC ground
pin4 For instance, if pin AGNDA is at +5 mꢀ with respect to the
REFGND pin and ꢀOUTA is measured with respect to
AGNDA, then a −5 mꢀ error results, enabling the local-
ground-offset adjust feature adjusts ꢀOUTA by +5 mꢀ,
eliminating the error4
PROGRAMMABꢀE SHORT-CIRCUIT PROTECTION
The short-circuit current of the output amplifiers can be pro-
grammed by inserting an external resistor between the ISCC
pin and PGND4 The programmable range for the current is
5ꢁꢁ µA to 1ꢁ mA, corresponding to a resistor range of 1.ꢁ kΩ
to 6 kΩ4 The resistor value is calculated as follows:
60
R ≈
ISC
Rev. PrA | Page 24 of 31
Preliminary Technical ꢀata
Aꢀ±76±
APPLICATIONS INFORMATION
Precision Voltage Reference Selection
TYPICAꢀ OPERATING CIRCUIT
To achieve the optimum performance from the AD5765 over its
full operating temperature range, a precision voltage reference
must be used4 Thought should be given to the selection of a
precision voltage reference4 The AD5765 has two reference
inputs, REFAB and REFCD4 The voltages applied to the
reference inputs are used to provide a buffered positive and
negative reference for the DAC cores4 Therefore, any error in
the voltage reference is reflected in the outputs of the device4
Figure 35 shows the typical operating circuit for the AD57654
The only external components needed for this precision 16-bit
DAC are a reference voltage source, decoupling capacitors on
the supply pins and reference inputs, and an optional short-
circuit current setting resistor4 Because the device incorporates
reference buffers, it eliminates the need for an external bipolar
reference and associated buffers4 This leads to an overall savings
in both cost and board space4
There are four possible sources of error to consider when
choosing a voltage reference for high accuracy applications:
initial accuracy, temperature coefficient of the output voltage,
long term drift, and output voltage noise4
In Figure 35, AꢀDD is connected to +5 ꢀ and AꢀSS is connected
to −5 ꢀ4 In Figure 35, AGNDA is connected to REFGND4
+5V
10µF
ADR420
100nF
2
6
VIN
VOUT
GND
4
Initial accuracy error on the output voltage of an external refer-
ence could lead to a full-scale error in the DAC4 Therefore, to
minimize these errors, a reference with low initial accuracy
error specification is preferred4 Choosing a reference with an
output trim adjustment, such as the ADR±3ꢁ, allows a system
designer to trim system errors out by setting the reference
voltage to a voltage other than the nominal4 The trim adjust-
ment can also be used at temperature to trim out any error4
+5V –5V
10µF
10µF
100nF
100nF
100nF
BIN/2sCOMP
32 31 30 29 28 27 26 25
+5V
Long-term drift is a measure of how much the reference output
voltage drifts over time4 A reference with a tight long-term drift
specification ensures that the overall solution remains relatively
stable over its entire lifetime4
SYNC
SCLK
SDIN
SDO
1
2
24
23
22
21
20
19
18
17
SYNC
AGNDA
VOUTA
VOUTB
AGNDB
AGNDC
VOUTC
VOUTD
AGNDD
SCLK
SDIN
SDO
CLR
LDAC
D0
VOUTA
VOUTB
3
4
5
6
7
8
AD5765
LDAC
D0
VOUTC
VOUTD
The temperature coefficient of a reference output voltage affects
INL, DNL, and TUE4 A reference with a tight temperature
coefficient specification should be chosen to reduce the
dependence of the DAC output voltage on ambient conditions4
D1
D1
9
10 11 12 13 14 15 16
RSTOUT
RSTIN
In high accuracy applications, which have a relatively low noise
budget, reference output voltage noise needs to be considered4
Choosing a reference with as low an output noise voltage as
practical for the system resolution required is important4
Precision voltage references such as the ADR±.ꢁ (XFET® design)
produce low output noise in the ꢁ41 Hz to 1ꢁ Hz region4
However, as the circuit bandwidth increases, filtering the output
of the reference may be required to minimize the output noise4
10µF
100nF
NC = NO CONNECT
10µF
+5V
+5V –5V
Figure 35. Typical Operating Circuit
Table 19. Some Precision References Recommended for Use with the AD5765
Part No. Initial Accuracy (mV Max) ꢀong-Term Drift (ppm Typ) Temp Drift (ppm/°C Max) 0.1 Hz to 10 Hz Noise (µV p-p Typ)
ADR43ꢀ
ADR42ꢀ
ADR39ꢀ
1
1
4
4ꢀ
5ꢀ
5ꢀ
3
3
9
3.5
1.75
5
Rev. PrA | Page 25 of 31
Aꢀ±76±
Preliminary Technical ꢀata
LAYOUT GUIꢀELINES
1
In any circuit where accuracy is important, careful consideration
of the power supply and ground return layout helps to ensure the
rated performance4 The printed circuit board on which the
AD5765 is mounted should be designed so that the analog and
digital sections are separated and confined to certain areas of the
board4 If the AD5765 is in a system where multiple devices
require an AGND-to-DGND connection, the connection should
be made at one point only4 The star ground point should be
established as close as possible to the device4 The AD5765 should
have ample supply bypassing of 1ꢁ µF in parallel with ꢁ41 µF on
each supply located as close to the package as possible, ideally
right up against the device4 The 1ꢁ µF capacitors are the tantalum
bead type4 The ꢁ41 µF capacitor should have low effective series
resistance (ESR) and low effective series inductance (ESI) such as
the common ceramic types, which provide a low impedance path
to ground at high frequencies to handle transient currents due to
internal logic switching4
µCONTROLLER
ADuM1400
V
V
V
V
V
V
V
V
IA
IB
IC
ID
OA
OB
OC
OD
ENCODE
ENCODE
ENCODE
ENCODE
DECODE
DECODE
DECODE
DECODE
SERIAL CLOCK OUT
TO SCLK
TO SDIN
TO SYNC
TO LDAC
SERIAL DATA OUT
SYNC OUT
CONTROL OUT
1
ADDITIONAL PINS OMITTED FOR CLARITY
Figure 36. Isolated Interface
MICROPROCESSOR INTERFACING
Microprocessor interfacing to the AD5765 is via a serial bus
that uses a standard protocol that is compatible with micro-
controllers and DSP processors4 The communications channel
is a 3-wire (minimum) interface consisting of a clock signal, a
data signal, and a synchronization signal4 The AD5765 requires
a .±-bit data-word with data valid on the falling edge of SCLK4
The power supply lines of the AD5765 should use as large a
trace as possible to provide low impedance paths and reduce
the effects of glitches on the power supply line4 Fast switching
signals, such as clocks, should be shielded with digital ground
to avoid radiating noise to other parts of the board, and should
never be run near the reference inputs4 A ground line routed
between the SDIN and SCLK lines helps reduce crosstalk
between them (not required on a multilayer board, which has a
separate ground plane, however, it is helpful to separate the
lines)4 It is essential to minimize noise on the reference inputs,
because it couples through to the DAC output4 Avoid crossover
of digital and analog signals4 Traces on opposite sides of the
board should run at right angles to each other4 This reduces the
effects of feedthrough on the board4 A microstrip technique is
recommended, but not always possible with a double-sided
board4 In this technique, the component side of the board is
dedicated to ground plane, and signal traces are placed on the
solder side4
For all the interfaces, the DAC output update can be done
automatically when all the data is clocked in, or it can be done
under the control of
LDAC
4 The contents of the DAC register
can be read using the readback function4
AD5765 to MC68HC11 Interface
Figure 37 shows an example of a serial interface between the
AD5765 and the MC68HC11 microcontroller4 The serial
peripheral interface (SPI) on the MC68HC11 is configured for
master mode (MSTR = 1), clock polarity bit (CPOL = ꢁ), and the
clock phase bit (CPHA = 1)4 The SPI is configured by writing to the
SPI control register (SPCR) (see the MC68HC11 User Manual)4
SCK of the MC68HC11 drives the SCLK of theAD5765, the MOSI
output drives the serial data line (DIN) of the AD57±±/AD5765,
SYNC
and the MISO input is driven from SDO4 The
one of the port lines, in this case, PC74
is driven from
SYNC
When data is being transmitted to the AD5765, the
(PC7) is taken low and data is transmitted MSB first4 Data
line
GAꢀVANICAꢀꢀY ISOꢀATED INTERFACE
appearing on the MOSI output is valid on the falling edge of
SCK4 Eight falling clock edges occur in the transmit cycle, so, in
order to load the required .±-bit word, PC7 is not brought high
until the third 8-bit word has been transferred to the DAC
input shift register4
In many process control applications, it is necessary to provide
an isolation barrier between the controller and the unit being
controlled to protect and isolate the controlling circuitry from
any hazardous common-mode voltages that might occur4
Isocouplers provide voltage isolation in excess of .45 kꢀ4 The
serial loading structure of the AD5765 makes it ideal for
isolated interfaces because the number of interface lines is kept
to a minimum4 Figure 36 shows a ±-channel isolated interface
to the AD5765 using an ADuM1±ꢁꢁ4 For more information, go
to www4analog4com4
1
MC68HC111
AD5765
MISO
MOSI
SCK
PC7
SDO
SDIN
SCLK
SYNC
1
ADDITIONAL PINS OMITTED FOR CLARITY
Figure 37. AD5765 to MC68HC11 Interface
Rev. PrA | Page 26 of 31
Preliminary Technical ꢀata
Aꢀ±76±
LDAC
LDAC
pin via the DSP4 Alternatively,
is controlled by the PC6 port output4 The DAC can be
output is updated using the
LDAC
input can be tied permanently low, and then the
LDAC
updated after each 3-byte transfer by bringing
low4 This
the
example does not show other serial lines for the DAC4 For
CLR
update takes place automatically when TFS is taken high4
example, if
output PC54
were used, it could be controlled by port
AD57651
ADSP2101/
ADSP21031
AD5765 to 8XC51 Interface
DR
DT
SDO
The AD5765 requires a clock synchronized to the serial data4
For this reason, the 8XC51 must be operated in Mode ꢁ4 In this
mode, serial data enters and exits through RxD, and a shift
clock is output on TxD4
SDIN
SCLK
SCLK
TFS
SYNC
LDAC
RFS
FO
P343 and P34± are bit programmable pins on the serial port and
SYNC
LDAC
are used to drive
and
, respectively4 The 8CX51
provides the LSB of its SBUF register as the first bit in the data
stream4 The user must ensure that the data in the SBUF register
is arranged correctly, because the DAC expects the MSB first4
When data is to be transmitted to the DAC, P343 is taken low4
Data on RxD is clocked out of the microcontroller on the rising
edge of TxD and is valid on the falling edge4 As a result, no glue
logic is required between this DAC and the microcontroller
interface4
1
ADDITIONAL PINS OMITTED FOR CLARITY
Figure 39. AD5765 to ADSP2101/ADSP2103 Interface
AD5765 to PIC16C6x/7x Interface
The PIC16C6x/7x synchronous serial port (SSP) is configured
as an SPI master with the clock polarity bit set to ꢁ4 This is done
by writing to the synchronous serial port control register
(SSPCON)4 See the PIC16/17 Microcontroller User Manual4 In
AD57651
8XC511
SYNC
this example, I/O port RA1 is being used to pulse
and
enable the serial port of the AD57654 This microcontroller
transfers only eight bits of data during each serial transfer
operation; therefore, three consecutive write operations are
needed4 Figure ±ꢁ shows the connection diagram4
RxD
SDIN
TxD
P3.3
P3.4
SCLK
SYNC
LDAC
AD57651
PIC16C6x/7x1
SDI/RC4
SDO/RC5
SCLK/RC3
RA1
SDO
SDIN
SCLK
SYNC
1
ADDITIONAL PINS OMITTED FOR CLARITY
Figure 38. AD5765 to 8XC51 Interface
The 8XC51 transmits data in 8-bit bytes with only eight falling
clock edges occurring in the transmit cycle4 Because the DAC
SYNC
expects a .±-bit word,
(P343) must be left low after the
first eight bits are transferred4 After the third byte has been
transferred, the P343 line is taken high4 The DAC can be
1
ADDITIONAL PINS OMITTED FOR CLARITY
Figure 40. AD5765 to PIC16C6x/7x Interface
LDAC
updated using
via P34± of the 8XC514
EVAꢀUATION BOARD
AD5765 to ADSP2101/ADSP2103 Interface
The AD5765 comes with a full evaluation board to aid
An interface between the AD5765 and the ADSP.1ꢁ1/
ADSP.1ꢁ3 is shown in Figure 304 The ADSP.1ꢁ1/ADSP.1ꢁ3
should be set up to operate in the SPORT transmit alternate
framing mode4 The ADSP.1ꢁ1/ADSP.1ꢁ3 are programmed
through the SPORT control register and should be configured
as follows: internal clock operation, active low framing, and
.±-bit word length4
designers in evaluating the high performance of the part with a
minimum of effort4 All that is required with the evaluation
board is a power supply and a PC4 The AD5765 evaluation kit
includes a populated, tested AD5765 printed circuit board4 The
evaluation board interfaces to the USB port of the PC4 Software
is available with the evaluation board, which allows the user to
easily program the AD57654 The software runs on any PC that
has Microsoft® Windows® .ꢁꢁꢁ/NT/XP installed4
Transmission is initiated by writing a word to the Tx register after
the SPORT has been enabled4 As the data is clocked out of the
DSP on the rising edge of SCLK, no glue logic is required to
interface the DSP to the DAC4 In the interface shown, the DAC
The EꢀAL-AD5765EBZ data sheet is available, which gives full
details on operating the evaluation board4
Rev. PrA | Page 27 of 31
Aꢀ±76±
Preliminary Technical ꢀata
OUTLINE ꢀIMENSIONS
1.20
MAX
0.75
0.60
0.45
9.00 BSC SQ
25
32
1
24
PIN 1
7.00
BSC SQ
TOP VIEW
(PINS DOWN)
0° MIN
1.05
1.00
0.95
0.20
0.09
7°
8
17
3.5°
0°
0.15
0.05
9
16
SEATING
PLANE
0.08 MAX
COPLANARITY
VIEW A
0.80
0.45
0.37
0.30
BSC
LEAD PITCH
VIEW A
ROTATED 90° CCW
COMPLIANT TO JEDEC STANDARDS MS-026ABA
Figure 41. 32-Lead Thin Plastic Quad Flat Package [TQFP]
(SU-32-2)
Dimensions shown in millimeters
ORDERING GUIDE
Model
AD5765BSUZ
AD5765CSUZ
INꢀ
2 LSB
1 LSB
Temperature Range
−4ꢀ°C to +1ꢀ5°C
−4ꢀ°C to +1ꢀ5°C
Package Description
32-lead TQFP
32-lead TQFP
Package Option
SU-32-2
SU-32-2
Rev. PrA | Page 28 of 31
Preliminary Technical ꢀata
NOTES
Aꢀ±76±
Rev. PrA | Page 29 of 31
Aꢀ±76±
NOTES
Rev. PrA | Page 3ꢀ of 31
Preliminary Technical ꢀata
NOTES
Aꢀ±76±
©2007 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
PR07249-0-12/07(PrA)
Rev. PrA | Page 31 of 31
相关型号：
AD5765CSUZ-REEL7
QUAD, SERIAL INPUT LOADING, 8us SETTLING TIME, 16-BIT DAC, PQFP32, ROHS COMPLIANT, MS-026ABA, TQFP-32
ADI
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