AD7484BST_技术文档

PRELIMINARY TECHNICAL DATA

3MSPS,

a

PreliminaryTechnicalData

14-BitSARADC

AD7484

FEATURES

FUNC TIO NAL BLO C K D IAGRAM

Fast Throughput Rate: 3Msps

Wide Input Bandw idth: 50MHz

AV

AGND

C

DV

DGND

DD

BIAS DD

VREF1

VREF2

No Pipeline Delays w ith SAR ADC

Excellent DC Accuracy Perform ance

Tw o Parallel Interface Modes

VREF3

BUF

2.5V

REFERENCE

Low Pow er:

90m W (Full-Pow er) and 5m W (NAP Mode)

Standby Mode: 1µA m ax

14-Bit Error

Single +5V Supply Operation

Internal +2.5V Reference

Correcting SAR

VIN

T/H

Full-Scale Overrange Mode (using 15th bit)

System Offset Rem oval via User Access Offset Register

Nom inal 0 to +2.5V Input w ith Shifted Range Capability

Pin Com patible Upgrade of 12-Bit AD7482

AD7484

MODE1

MODE2

CLIP

D14

D13

D12

D11

D10

D9

CONTROL

LOGIC AND I/O

REGISTERS

NAP

STBY

RESET

CONVST

G E NE R AL D E S C R IP T IO N

D8

V

D7

DRIVE

T he AD7484 is a 14-bit, high speed, low power, succes-

sive-approximation ADC. T he part features a parallel

interface with throughput rates up to 3Msps. T he part

contains a low-noise, wide bandwidth track/hold amplifier

which can handle input frequencies in excess of 50MHz.

T he conversion process is a proprietary algorithmic suc-

cessive-approximation technique which results in no

pipeline delays. T he input signal is sampled and a conver-

sion is initiated on the falling edge of the CONVST

signal. T he conversion process is controlled via an inter-

nally trimmed oscillator. Interfacing is via standard

parallel signal lines making the part directly compatible

with microcontrollers and D SPs.

T he AD7484 features an on-board +2.5V reference but

the part can also accomodate an externally-provided

+2.5V reference source. T he nominal analog input range

is 0 to +2.5V but an offset shift capability allows this

nominal range to be offset by +/-200mV. T his allows the

user considerable flexibility in setting the bottom end

reference point of the signal range, a useful feature when

using single-supply op-amps.

T he AD7484 provides excellent ac and dc performance

specifications. Factory trimming ensures high dc accuracy

resulting in very low INL, offset and gain errors.

T he AD7484 also provides the user with an 8% overrange

capability via a 15th bit. T hus, if the analog input range

strays outside the nominal by up to 8%, the user can still

accurately resolve the signal by using the 15th bit.

T he part uses advanced design techniques to achieve very

low power dissipation at high throughput rates. Power

consumption in normal mode of operation is 90mW.

T here are two power-saving modes: a NAP mode, which

keeps the reference circuitry alive for a quick power up

while consuming 5mW and a ST ANDBY mode which

reduces power consumption to a mere 5µW.

T he AD7484 is powered from a +4.75V to +5.25V sup-

ply. T he part also provides a V_DRIVEpin which allows the

user to set the voltage levels for the digital interface lines.

T he range for this V_DRIVEpin is from +2.7V to +5.25V.

T he part is housed in a 48-pin LQFP package and is

specified over a -40°C to +85°C temperature range.

REV. PrC 7/13/01

Inform ation furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assum ed by Analog Devices for its

use, nor for any infringem ents of patents or other rights of third parties

which m ay result from its use. No license is granted by im plication or

otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norw ood, MA 02062-9106, U.S.A.

Tel: 781/ 329-4700

Fax: 781/ 326-8703

World Wide Web Site: http:/ / w w w .analog.com

PRELIMINARY TECHNICAL DATA

(T = 25؇C, V = 4.75 V to 5.25 V, V_DRIVE= 2.7 V to 5.25 V,

A

DD

f_SAMPLE= 3MSPS)

AD7484–SPECIFICATIONS

P ar am eter

Specification

Units

Test Conditions/Com m ents

D YN AM IC PERF O RM AN C E

Signal to Noise + Distortion (SINAD)²

Signal to Noise Ratio (SNR)²

T otal H armonic D istortion (T H D )²

Peak H armonic or Spurious Noise (SFDR)²

Intermodulation D istortion (IM D )²

Second Order T erms

F_IN= 100kHz Sine Wave

78

-90

T BD

dB min

dB max

T BD

10

dB typ

ns typ

T hird Order T erms

Aperture D elay

Aperture Jitter

10

ps typ

Full Power Bandwidth

50

T BD

MH z typ

M H z typ

@ 3 dB

@0.1 dB

D C AC C U RAC Y

Resolution

14

T BD

± 1

T BD

± 1

± 1.5

Bits

LSB max

LSB typ

Integral N onlinearity²

D ifferential N onlinearity²

LSB max Guaranteed No Missed Codes to 14 bits

LSB typ

LSB max

Offset Error²

Gain Error²

AN ALO G IN PU T

Input Voltage

-200

+ 2.7

T BD

10

mV min

Volts max

µA max

pF typ

D C Leakage Current

Input Capacitance

REF EREN C E IN P U T /O U T P U T

V_REFInput Voltage

V_REFInput DC Leakage Current

V_REFInput Capacitance

V_REFOutput Voltage

V_REFError @ 25°C

V_REFError T_MINto T_MAX

V_REFOutput Impedance

+ 2.5

± 1

Volts

±1% for specified performance

µA max

pF max

V nom

mV max

k⍀ typ

T BD

+ 2.5

T BD

LO G IC IN PU T S

Input High Voltage, V_INH

Input Low Voltage, V_INL

Input Current, I_IN

T BD

0.4

T BD

V min

V max

µA max

pF max

2

Input Capacitance, C_IN

LO G IC O U T P U T S

Output High Voltage, V_OH

Output Low Voltage, V_OL

Floating-State Leakage C urrent

Floating-State Output Capacitance^2,3

Output Coding

V_DRIVE- 0.2

0.4

T BD

V min

V max

µA max

pF max

T BD

Straight (Natural) Binary

C O N VERSIO N RAT E

C onversion T ime

T rack/H old Acquisition T ime

T BD

3

ns max

M SPS max

Sine Wave Input

Full-Scale Step Input

T hroughput Rate

P O WER REQ U IREM EN T S

V_DD

+ 5

Volts

± 5 %

V_DRIVE

+ 2.7

+ 5.25

T BD

18

1

V min

V max

mA typ

µA max

I_DDNormal Mode (Static)

Normal Mode (Operational)

NAP Mode

Standby Mode

–2 –

REV. PrC 7/13/01

PRELIMINARY TECHNICAL DATA

AD7484

P ar am eter

Specification

Units

Test Conditions/Com m ents

P O WER REQ U IREM EN T S

(continued)

Power D issipation

N ormal M ode (Operational)

N AP M ode

90

5

mW max

µW max

Standby Mode

NOTES

¹T emperature ranges as follows: –40°C to +85°C.

²See T erminology

³Sample tested @ +25°C to ensure compliance

Specifications subject to change without notice.

(V = 5 V ±5%, AGND = DGND = 0 V, V_REF= Internal;

All specifications T_MINto T_MAXand valid for V_DRIVE= 2.7 V to 5.25 V unless otherwise noted)

DD

TIMING CHARACTERISTICS ^1,2

P ar am eter

Sym bol

Min

Typ

M a x

Units

D ata Read

Acquisition T ime

C onversion T ime

t_ACQ

t_CONV

t_QUIET

t_{QUIET 2}

t₁

t₂

t₃

t₄

t₅

t₆

t₇

t₈

T BD

ns

T BD

Quiet T ime before Conversion start

Quiet T ime during Conversion

CONVST Pulse Width

CONVST falling edge to BUSY falling edge

CS falling edge to RD falling edge

Bus Access T ime

CONVST falling edge to new Data valid

BUSY rising edge to new Data valid

Bus Relinquish T ime

T BD

RD rising edge to CS rising edge

T BD

D ata Wr ite

WRIT E Pulse Width

Data Setup time

Data Hold time

CS falling edge to WRIT E rising edge

WRIT E falling edge to CS rising edge

t₉

T BD

ns

t₁₀

t₁₁

t₁₂

t₁₃

REV. PrC 7/13/01

–3 –

PRELIMINARY TECHNICAL DATA

AD7484

AB SO LUT E M AXIM UM RAT ING S¹

P IN C O NF IG U R AT IO N

(T _A= +25°C unless otherwise noted)

V_DDto GND . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +7 V

V_DRIVEto GND . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +7 V

Analog Input Voltage to GND . . -0.3 V to AV_DD+ 0.3 V

Digital Input Voltage to GND . . -0.3 V to DV_DD+ 0.3 V

REF IN to GND . . . . . . . . . . . . . -0.3 V to AV_DD+ 0.3 V

Input Current to Any Pin Except Supplies . . . . . . . ± 10m A

Operating T emperature Range

C om m ercial . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C

Storage T emperature Range . . . . . . . –65°C to +150°C

Junction T emperature . . . . . . . . . . . . . . . . . . . . . . . + 150°C

48-Pin LQFP Package, Power D issipation . . . . . . . . T BD

PIN 1 IDENTIFIER

AVDD

CBIAS

AGND

AVDD

AGND

VIN

1

2

36 D10

35

34

33

D9

D8

D7

3

4

5

32 VDRIVE

AD7484

TOP VIEW

(Not to Scale)

6

31

30

29

28

27

26

25

DGND

DVDD

D6

7

␪

T hermal Impedance . . . . . . . . . . . . . . . . . . . . 50°C /W

JA

VREF2

VREF1

VREF3

8

␪

T hermal Impedance . . . . . . . . . . . . . . . . . . .

10°C/W

JC

9

Lead T emperature, Soldering

10

D5

Vapor Phase (60 secs) . . . . . . . . . . . . . . . . . . . + 215°C

Infared (15 secs) . . . . . . . . . . . . . . . . . . . . . . . + 220°C

E S D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T BD

AGND 11

AGND 12

D4

D3

NOTES

¹Stressesabove those listed under “Absolute Maximum Ratings” maycause permanent

damage to the device. Thisisa stressratingonlyand functionaloperation ofthe device

at these or any other conditions above those listed in the operational sections of this

specification is not implied. Exposure to absolute maximum rating conditions for

extended periods mayaffect device reliability.

O R D E R ING G U ID E

Tem perature

Range

P ackage

Description

Model

Option

AD 7484BST

-40°C to +85°C

Low-profile Quad Flat Pack

Evaluation Board

C ontroller Board

ST -48

EVAL-AD 7484C B¹

EVAL-C O N T RO L BRD 2²

NOTES

¹T his can be used as a stand-alone evaluation board or in conjunction with the EVAL-CONT ROL BOARD for evaluation/demonstration purposes.

²T his board is a complete unit allowing a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators.

CAUT ION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily

accumulate on the human body and test equipment and can discharge without detection. Although

the AD7484 features proprietary ESD protection circuitry, permanent damage may occur on devices

subjected to high-energyelectrostatic discharges. T herefore, proper ESD precautions are recommended

to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

–4 –

REV. PrC 7/13/01

PRELIMINARY TECHNICAL DATA

AD7484

P IN F U NC T IO N D E SC R IP T IO N

P in

Mnem onic

Description

Positive power supply for analog circuitry.

AVD D

C_BIAS

Decoupling pin for internal bias voltage. A 100nF capacitor should be placed between this pin and

AG N D .

AG N D

VIN

Power supply ground for analog circuitry.

Analog input. Single-ended analog input channel.

VRE F 1

Reference Output. VREF1 connects to the output of the internal 2.5V reference. A 1µF capacitor must

be placed between this pin and AGND.

VRE F 2

VRE F 3

ST BY

N AP

Reference Input. A 1µF capacitor must be placed between this pin and AGND. When using an external

voltage reference source, the reference voltage should be applied to this pin.

Reference decoupling pin. When using the internal reference, a 100nF must be connected from this pin

to AGND. When using an external reference source, this pin should be connected directly to AGND.

Standby logic input. When this pin is logic high, the device will be placed in Standby mode. See Power

Saving Section for further details.

Nap logic input. When this pin is logic high, the device will be placed in a very low power mode. See

Power Saving Section for further details.

D VD D

D G N D

V_DRIVE

Positive power supply for digital circuitry.

Ground reference for digital circuitry.

Logic Power Supply Input. T he voltage supplied at this pin will determine at what voltage

the interface logic of the AD7484 will operate.

CONVST

RESET

Convert Start Logic Input. A conversion is initiated on the falling edge of CONVST signal. T he input

track/hold amplifier goes from track mode to hold mode and the conversion process commences.

Reset Logic Input. A logic 0 on this pin resets the internal state machine and terminates a conversion

that may be in progress. Holding this pin low keeps the part in a reset state.

M O D E 2

M O D E 1

C LIP

Operating Mode Logic Input. See T able 3 for details.

Logic input. A logic high on this pin enables output clipping. In this mode, any input voltage that is

greater than positive full scale or less than negative full scale will be clipped to all 1’s or all 0’s

respectively. Further details are given in the Offset / Overrange setion.

C S

Chip Select Logic Input. T his pin is used in conjunction with RD to access the conversion result. T he

data bus is brought out of tri-state and the current contents of the output register driven onto the data

lines following the falling edge of both CS and RD. CS is also used in conjunction with WRIT E to

perform a write to the Offset Register. CS can be hardwired permanently low.

RD

Read Logic Input. Used in conjunction with CS to access the conversion result.

WRIT E

Write Logic Input. Used in conjunction with CS to write data to the Offset Register. When the desired

offset word has been placed on the data bus, the WRIT E line should be pulsed high. It is the falling

edge of this pulse which latches in the word into the Offset Register.

BUSY

Busy Logic Output. T his pin indicates the status of the conversion process. T he BUSY signal goes low

after the falling edge of CONVST and stays low for the duration of the conversion. In Parallel Mode 2,

the BUSY signal returns high when the conversion result has been clocked into the output register. In

Parallel Mode 1, the BUSY signal returns high as soon as the conversion has been completed but the

conversion result does not get clocked into the output register until the falling edge of the next

CONVST pulse.

D0 - D13

D 14

Data I/O Bits (D13 is MSB). T hese are tri-state pins that are controlled by CS, RD and WRIT E.

T he operating voltage level for these pins is determined by the V_DRIVEinput.

Data Output Bit for overranging. If the over range feature is not used, this pin should be pulled to

DGND via a 100k⍀ resistor.

REV. PrC 7/13/01

–5 –

PRELIMINARY TECHNICAL DATA

AD7484

T E R M I N O L O G Y

In t egr a l Non lin ea r it y

T ota l H a r m on ic D istor tion

T otal harmonic distortion (T HD) is the ratio of the rms

sum of harmonics to the fundamental. For the AD7484 it

is defined as:

T his is the maximum deviation from a straight line pass-

ing through the endpoints of the ADC transfer function.

T he endpoints of the transfer function are zero scale, a

point 1/2 LSB below the first code transition, and full

scale, a point 1/2 LSB above the last code transition.

2

4

2

V₂

V

+

6

+

3

5

THD (d B ) 20 lo g

=

V₁

D iffer en t ia l Non lin ea r it y

This is the difference between the measured and the ideal 1

LSB change between any two adjacent codes in the ADC.

where V₁is the rms amplitude of the fundamental and V₂,

V₃, V₄, V₅and V₆are the rms amplitudes of the second

through the sixth harmonics.

O ffset E r r or

T his is the deviation of the first code transition (00 . . .

000) to (00 . . . 001) from the ideal, i.e AGND + 0.5

L S B

P eak H ar m onic or Spur ious Noise

Peak harmonic or spurious noise is defined as the ratio of

the rms value of the next largest component in the ADC

output spectrum (up to f_S/2 and excluding dc) to the rms

value of the fundamental. Normally, the value of this

specification is determined by the largest harmonic in the

spectrum, but for ADCs where the harmonics are buried

in the noise floor, it will be a noise peak.

Gain Er r or

T his is the deviation of the last code transition (111 . . .

110) to (111 . . . 111) from the ideal (i.e., V_REF– 1.5

LSB) after the offset error has been adjusted out.

In t er m od u la t ion D ist or t ion

With inputs consisting of sine waves at two frequencies, fa

and fb, any active device with nonlinearities will create

distortion products at sum and difference frequencies of

mfa ± nfb where m, n = 0, 1, 2, 3, etc. Intermodulation

distortion terms are those for which neither m nor n are

equal to zero. For example, the second order terms in-

clude (fa + fb) and (fa – fb), while the third order terms

include (2fa + fb), (2fa – fb), (fa + 2fb) and (fa – 2fb).

T r ack/H old Acqu isition T im e

T rack/Hold acquisition time is the time required for the

output of the track/hold amplifier to reach its final value,

within ±1/2 LSB, after the end of conversion (the point

at which the track/hold returns to track mode).

Signal to (Noise + D istor tion) Ratio

T his is the measured ratio of signal to (noise + distor-

tion) at the output of the A/D converter. T he signal is

the rms amplitude of the fundamental. Noise is the sum

of all nonfundamental signals up to half the sampling

frequency (f_S/2), excluding dc. T he ratio is dependent on

the number of quantization levels in the digitization

process; the more levels, the smaller the quantization

noise. T he theoretical signal to (noise + distortion) ratio

for an ideal N-bit converter with a sine wave input is

given by:

T he AD7484 is tested using the CCIF standard where two

input frequencies near the top end of the input bandwidth

are used. In this case, the second order terms are usually

distanced in frequency from the original sine waves while

the third order terms are usually at a frequency close to

the input frequencies. As a result, the second and third

order terms are specified separately. T he calculation of the

intermodulation distortion is as per the T H D specification

where it is the ratio of the rms sum of the individual dis-

tortion products to the rms amplitude of the sum of the

fundamentals expressed in dBs.

Signal to (Noise + Distortion) = (6.02 N + 1.76) dB

T hus for a 14-bit converter, this is 86.04 dB.

–6 –

REV. PrC 7/13/01

PRELIMINARY TECHNICAL DATA

AD7484

C IR C U IT D E S C R IP T IO N

C O NVE R T E R O P E R AT IO N

At the end of conversion, the track/hold returns to track-

ing mode and the acquisition time begins. The track/hold

acquisition time is TBD nS. Figure 3 shows the ADC

during its acquistition phase. SW2 is closed and SW1 is

in position A. T he comparator is held in a balanced con-

dition and the sampling capacitor acquires the signal on

The AD7484 is a 14-bit error correcting successive ap-

proximation analog-to-digital converter based around a

capacitive DAC. It provides the user with track/hold, refer-

ence, A/D converter and versatile interface logic functions

on a single chip. The normal analog input signal range that

the AD7484 can convert is 0 to 2.5 Volts. By using the

offset and overrange features on the ADC, the AD7484 can

convert analog input signals from -200mV to +2.7V while

operating from a single +5V supply. The part requires a

+2.5V reference which can be provided from the part’s own

internal reference or an external reference source. Figure 1

shows a very simplified schematic of the ADC. The Control

Logic, SAR and the Capacitive DAC are used to add and

subtract fixed amounts of charge from the sampling capaci-

tor to bring the comparator back to a balanced condition.

V_IN

.

CAPACITIVE

DAC

A

V

+

IN

SW1

CONTROL LOGIC

B

-

SW2

COMPARATOR

AGND

COMPARATOR

Figure 3. ADC Acquisition Phase

AD C T RANSF E R F U NC T IO N

CAPACITIVE

DAC

The output coding of the AD7484 is straight binary. The

designed code transitions occur midway between successive

integer LSB values (i.e., 1/2 LSB, 3/2 LSBs, etc.). The

LSB size is V_REF/ 16384. The nominal transfer characteris-

tic for the AD7484 in shown in figure 4 below. This

transfer characteristic may be shifted as detailed in the Off-

set/Overrange section.

V

IN

SWITCHES

V

REF

SAR

CONTROL

INPUTS

CONTROL LOGIC

OUTPUT DATA

14-BIT PARALLEL

111...111

111...110

Figure 1. Sim plified Block Diagram of AD7484

Conversion is initiated on the AD7484 by pulsing the

CONVST input. On the falling edge of CONVST, the

track/hold goes from track to hold mode and the conversion

sequence is started. Conversion time for the part is TBD

nS. Figure 2 shows the ADC during conversion. When

conversion starts, SW2 will open and SW1 will move to

position B causing the comparator to become unbalanced.

The ADC then runs through its successive approximation

routine and brings the comparator back into a balanced

condition. When the comparator is rebalanced, the conver-

sion result is available in the SAR register.

111...000

1LSB = V

/16384

REF

011...111

000...010

000...001

000...000

0.5LSB

+V

-1.5LSB

REF

0V

ANALOG INPUT

Figure 4. AD7484 Transfer Characteristic

CAPACITIVE

DAC

A

V

+

IN

SW1

CONTROL LOGIC

B

-

SW2

COMPARATOR

AGND

Figure 2. ADC Conversion Phase

REV. PrC 7/13/01

–7 –

PRELIMINARY TECHNICAL DATA

AD7484

P O WE R SAVING

400nS

600nS

The AD7484 uses advanced design techniques to achieve

very low power dissipation at high throughput rates. In addi-

tion to this the AD7484 features two power saving modes,

Nap Mode and Standby Mode. These modes are selected by

bringing either the NAP or STBY pin to a logic high respec-

tively.

100nS

When operating the AD7484 in normal, fully powered

mode, the current consumption is 18mA during conver-

sion and the quiescent current is 5mA. Operating at a

throughput rate of 1MSPS, the conversion time of 300nS

contributes 27mW to the overall power dissipation.

1 µS

Figure 6. NAP Mode Power Dissipation

Figures 7 and 8 show a typical graphical representation of

Power vs. Throughput for the AD7484 when in Normal and

Nap modes respectively.

(300nS / 1µS) x (5V x 18mA) = 27mW

For the remaining 700nS of the cycle, the AD7484 dissipates

17.5mW of power.

60

55

50

45

40

35

30

25

20

(700nS / 1µS) x (5V x 5mA) = 17.5mW

Thus the power dissipated during each cycle is:

27mW + 17.5mW = 44.5mW

Figure 5 below shows the AD7484 conversion sequence

operating in normal mode.

1 µS

0

500

1000

1500

2000

2500

3000

300 nS

700 nS

THROUGHPUT - KSPS

Figure 7. Norm al Mode - Power vs. Throughput

Figure 5. Norm al Mode Power Dissipation

50

45

40

35

30

25

20

15

10

5

In NAP mode, all the internal circuitry except for the

internal reference is powered down. In this mode, the

power dissipation of the AD7484 is reduced to 5mW.

When exiting NAP mode a minimum of 100nS must be

waited before initiating a conversion. T his is necessary to

allow the internal circuitry to settle after power-up and for

the track/hold to properly acquire the analog input signal.

If the AD7484 is put into NAP mode after each conversion,

the average power dissipation will be reduced but the

throughput rate will be limited by the power-up time. Using

the AD7484 with a throughput rate of 1MSPS while placing

the part in NAP mode after each conversion would result in

average power dissipation as follows: The power-up and

conversion phase will contribute 36mW to the overall power

dissipation.

0

250

500

750

1000

1250

1500

1750

2000

THROUGHPUT - KSPS

Figure 8. Nap Mode - Power vs. Throughput

(400nS / 1µS) x (5V x 18mA) = 36mW

In STANDBY mode, all the internal circuitry is powered

down and the power consumption of the AD7484 is re-

duced to 5µW. T he power-up time necessary before a

conversion can be initiated is longer because the internal

reference has been powered down. If using the internal

reference of the AD7484, the ADC must be brought out

of ST ANDBY mode 200µS before a conversion is initi-

ated. Initiating a conversion before the required power-up

time has elapsed will result in incorrect conversion data.

If an external reference source is used and kept powered

up while the AD7484 is in ST ANDBY mode, the power-

up time required will be reduced.

While in NAP mode for the rest of the cycle, the AD7484

dissipates only 3mW of power.

(600nS / 1µS) x (5V x 1mA) = 3mW

Thus the power dissipated during each cycle is:

36mW + 3mW = 39mW

Figure 6 shows the AD7484 conversion sequence if putting

the part into NAP mode after each conversion.

–8 –

REV. PrC 7/13/01

PRELIMINARY TECHNICAL DATA

AD7484

O F F SE T / O VE RRANG E

The AD7484 provides a ±8% overrange capability as well as

a programmable Offset Register. T he overrange capability is

achieved by the use of a 15th bit (D14) and the CLIP input.

If the CLIP input is at logic high and the contents of the

offset register are zero, then the AD7484 operates as a nor-

mal 14-bit ADC. If the input voltage is greater than the

full-scale voltage, the data output from the ADC will be all

1’s. Similarly, if the input voltage is lower than the zero-

scale voltage, the data output from the ADC will be all 0’s.

In this case D14 acts as an overrange indicator. It is set to a

1 if the analog input voltage is outside the nominal 0 to

+2.5V range.

111...111

111...110

1LSB = V

/16384

REF

111...000

011...111

000...010

000...001

000...000

0.5LSB

-OFFSET

+V

-1.5LSB

REF

0V

-OFFSET

ANALOG INPUT

Figure 10. Transfer Characteristic With NegativeOffset

If the Offset Register contains any value other than zero,

the contents of the register are added to the SAR result at

the end of conversion. This has the effect of shifting the

transfer function of the ADC as shown in Figure 9 and Fig-

ure 10. However, it should be noted that with the CLIP

input set to logic high, the maximum and minimum codes

that the AD7484 will ouput will be 0x3FFF and 0x0000

respectively. Further details are given in Table 1 and Table

2.

T able 1 below shows the expected ADC result for a given

analog input voltage with different offset values and with

CLIP tied to logic high. T he combined advantages of the

offset and overrange features of the AD7484 are shown

clearly in T able 2. It shows the same range of analog in-

put and offset values as T able 1 but with the clipping

feature disabled.

Figure 9 shows the effect of writing a positive value to the

Offset Register. If, for example, the contents of the Offset

Register contained the value 1024, then the value of the ana-

log input voltage for which the ADC would transition from

reading all 0’s to 000...001 (the bottom reference point)

would be:

OFFSET

VIN

-200mV

-156.3mV

0V

+78.2mV

+2.3435V

+2.5V

+2.5779V

+2.7V

-512

0

+1024

ADC DATA, D[0:13]

D14

1

0

1

0

1024

1536

16383

0

512

0.5LSB - (1024 LSBs) = -156.326mV

14847

15871

16383

15359

16383

The analog input voltage for which the ADC would read

full-scale (0x3FFF) in this example would be:

2.5V -1.5LSBs - (1024 LSBs) = 2.34352V

Table 1. Clipping Enabled (CLIP = 1)

111...111

111...110

OFFSET

VIN

-200mV

-156.3mV

0V

+78.2mV

+2.3435V

+2.5V

+2.5779V

+2.7V

-512

0

+1024

ADC DATA, D[0:14]

-1822

-1536

-512

111...000

1LSB = V

/16384

REF

-1310

-1024

0

-286

0

011...111

+V -1.5LSB

REF

-OFFSET

1024

1536

16383

17407

17919

18718

000...010

000...001

000...000

0

512

ANALOG INPUT

14847

15871

16383

17182

15359

16383

16895

17694

0V

Figure 9. Transfer Characteristic With Positive Offset

The effect of writing a negative value to the Offset Register is

shown in Figure 10. If a value of -512 was written to the

Offset Register, the bottom end reference point would now

occur at:

Table 2. Clipping Disabled (CLIP = 0)

Values from -1310 to +1310 may be written to the Offset

Register. These values correspond to an offset of ±200mV. A

write to the Offset Register is performed by writing a 15-bit

word to the part as detailed in the Interfacing sections. The

12 LSBs of the 15-bit word contain the offset value, the 3

MSBs must be set to zero. Failure to write zeros to the 3

MSBs may result in the incorrect operation of the device.

0.5LSB - (-512 LSBs)= +78.20mV

Following from this, the analog input voltage needed to

produce a full-scale (0x3FFF) result from the ADC would

now be:

2.5V - 1.5LSBs - (-512 LSBs) = 2.5779V

REV. PrC 7/13/01

–9 –

7/13/01 5 PM

PRELIMINARY TECHNICAL DATA

AD7484

P ARALLE L INT E RF AC E

T o write to the offset register a 15-bit word is written to

the AD7484 with the 12 LSBs containing the offset value

in 2’s complement format. T he 3 MSBs must be set to

zero. T he offset value must be within the range -1310 to

+1310, corresponding to an offset from -200mV to

+200mV. T he value written to the offset register is stored

and used until power is removed from the device. T he

value stored may be updated at any time between conver-

sions by another write to the device. T able 4 shows some

examples of offset register values and their effective offset

voltage. Figure 14 shows a timing diagram for writing to

the AD 7484.

T he AD7484 features two parallel interfacing modes.

T hese modes are selected by the Mode pins as detailed in

T able 3.

Mode 2

Mode 1

Not Used

0

1

0

1

0

1

Parallel Mode 1

Parallel Mode 2

Not Used

Code (Dec) D14-D12 D11-D0 (2's Comp) Offset (mV)

Table 3. AD7484 Operating Modes

-1310

-512

+256

+1310

000

101011100010

111000000000

000100000000

010100011110

-200

-78.12

+39.06

+200

In Parallel Mode 1, the data in the output register is up-

dated and available for reading when BUSY returns high

at the end of a conversion. T his mode should be used if

the conversion data is required immediately after the con-

version has completed. An example where this may be of

use is if the AD7484 were operating at much lower

throughput rates in conjunction with Nap Mode (for

power-saving reasons) and the input signal being com-

pared with set limits. If the limits were exceeded, the

ADC would then be woken up and commence sampling at

full speed. Figure 12 shows a timing diagram for the

AD7484 operating in Parallel Mode 1.

Table 4. Offset Register Exam ples

Typical Connection

Figure 11 shows a typical connection diagram for the

AD7484 operating in Parallel Mode 1. Conversion is

initiated by a falling edge on CONVST. Once CONVST

goes low, the BUSY signal goes low and at the end of

conversion, the rising edge of BUSY is used to activate an

Interrupt Service Routine. T he CS and RD lines are then

activated to read the 14 data bits (15 bits if using the

overrange feature).

In Parallel Mode 2, the data in the output register is not

updated until the next falling edge of CONVST. T his

mode could be used where a single sample delay is not

vital to the system operation. T his may occur, for ex-

ample, in a system where a large amount of samples are

taken at high speed before a Fast Fourier T ransform is

performed for frequency analysis of the input signal. Fig-

ure 13 shows a timing diagram for the AD7484 operating

in Parallel Mode 2.

In Figure 11 the V_DRIVEpin is tied to DV_DD, which results

in logic output levels being either 0 V or DV_DD. T he volt-

age applied to V_DRIVEcontrols the voltage value of the

output logic signals. For example, if DV_DDis supplied by

a 5 V supply and V_DRIVEby a 3 V supply, the logic output

levels would be either 0 V or 3 V. T his feature allows the

AD7484 to interface to 3 V devices while still enabling the

ADC to process signals at 5 V supply.

Reading D ata fr om the AD 7484

Data is read from the part via a 15-bit parallel data bus

with the standard CS and RD signals. T he CS and RD

signals are internally gated to enable the conversion result

onto the data bus. T he data lines D0 to D14 leave their

high impedance state when both CS and RD are logic low.

T herefore, CS may be permanently tied logic low if re-

quired and the RD signal used to access the conversion

result. Figures 12 and 13 show timing specifications

called t_QUIETand t_{QUIET 2}. T he quiet time, t_QUIET, is the

amount of time that should be left after any data bus activ-

ity before the next conversion is initiated. T he second

quiet time, t_{QUIET 2}, is the period during a conversion where

activity on the data bus should be avoided. Reading a re-

sult from the AD7484 while the latter half of the

conversion is in progress will result in the degradation of

performance by about T BD dB.

ANALOG

SUPPLY

4.75V - 5.25V

1nF

10µF

47µF

0.1µF

AV_DD

DV_DDV_DRIVE

V_BIAS

REF3

REF2

REF1

RESET

MODE1

MODE2

WRITE

CLIP

0.1µF

0.47µF

C/ P

µ

NAP

STBY

AD7484

PARALLEL

INTERFACE

D0-D14

CS

0V to

+2.5V

V

Wr iting to the AD 7484

I

N

CONVST

RD

T he AD7484 features a user accessible offset register.

T his allows the bottom of the transfer function to be

shifted by ±200mV. T his feature is explained in more

detail in the Offset / Overrange section.

BUSY

Figure 11. AD7484 Typical Connection Diagram

–1 0 –

REV. PrC 7/13/01

PRELIMINARY TECHNICAL DATA

AD7484

t_CONV

t_QUIET

t

t_{QUIET 2}

1

t

t_ACQ

2

t

3

t

8

t

6

4

7

Figure 12. Parallel Mode 1 Read Cycle

t_CONV

t_QUIET

t

t_{QUIET 2}

1

t

t_ACQ

2

t

3

t

5

4

Data N

Data N+1

Figure 13. Parallel Mode 2 Read Cycle

t

13

12

t

9

t

11

10

Figure 14. Parallel Mode Write Cycle

REV. PrC 7/13/01

–1 1 –

PRELIMINARY TECHNICAL DATA

AD7484

O UTLINE D IME NSIO NS

D imensions shown in inches and (mm).

48-P in LQ FP P ackage (ST-48)

0.063 (1.60)

MAX

0.354 (9.00) BSC SQ

0.030 (0.75)

37

36

48

0.018 (0.45)

1

0.276

(7.00)

BSC

SQ

TOP VIEW

(PINS DOWN)

COPLANARITY

0.003 (0.08)

12

25

0؇

MIN

13

24

0.019 (0.5) 0.011 (0.27)

0.008 (0.2)

0.004 (0.09)

BSC

0.006 (0.17)

0.057 (1.45)

0.053 (1.35)

7؇

0؇

0.006 (0.15)

SEATING

0.002 (0.05)PLANE

–1 2 –

REV. PrC 7/13/01


型号：	AD7484BST
厂家：	ADI
描述：	3MSPS, 14-Bit SAR ADC 3MSPS ， 14位SAR ADC 转换器模数转换器
文件：	总12页 (文件大小：153K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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