AD7885AN [ADI]
LC2MOS 16-Bit, High Speed Sampling ADCs; LC2MOS 16位高速采样ADC
| 型号： | AD7885AN |
| 厂家： | 
ADI |
| 描述： | LC2MOS 16-Bit, High Speed Sampling ADCs |
| 文件： | 总16页 (文件大小：321K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
2
LC MOS
a
16-Bit, High Speed Sampling ADCs
AD7884/AD7885
FEATURES
FUNCTIO NAL BLO CK D IAGRAMS
Monolithic Construction
Fast Conversion: 5.3 s
High Throughput: 166 kSPS
Low Pow er: 250 m W
V
V
SS
±3V
IN
F
±3V
S
AV
SS
AV
DD
AGNDS AGNDF
DD
IN
R3
3kΩ
AD7884
R2
3kΩ
C1
A1
±5V
±5V
S
F
IN
APPLICATIONS
R1
SW1
IN
5kΩ
Autom atic Test Equipm ent
Medical Instrum entation
Industrial Control
D
O
R4 4kΩ
R
I
DB15
DB0
9-BIT
ADC
U
T
P
U
T
9
9
SW2
LATCH
V
E
R
S
R5
4kΩ
R6
2kΩ
Data Acquisition System s
Robotics
+
16
16
ALU
V
REF–
A2
SW3
16-BIT
9
ACCURATE
DAC
CS
RD
TIMER
CONTROL
R7
2kΩ
GENERAL D ESCRIP TIO N
T he AD7884/AD7885 is a 16-bit monolithic analog-to-digital
converter with internal sample-and-hold and a conversion time
of 5.3 µs. T he maximum throughput rate is 166 kSPS. It uses a
two pass flash architecture to achieve this speed. T wo input
ranges are available: ±5 V and ±3 V. Conversion is initiated by
the CONVST signal. T he result can be read into a microproces-
sor using the CS and RD inputs on the device. T he AD7884 has
a 16-bit parallel reading structure while the AD7885 has a byte
reading structure. T he conversion result is in 2s complement
code.
R8
2kΩ
V
V
V
F
V
S
INV
REF–
GND
DGND
V
REF+
REF+
CONVST BUSY
±3V
AGNDS AGNDF
IN
V
DD
AV
AV
SS
SS
DD
R3 3kΩ
R2
AD7885
3kΩ
C1
A1
±5V
±5V
S
F
IN
IN
R1
5kΩ
SW1
D
O
T he AD7884/AD7885 has its own internal oscillator which con-
trols conversion. It runs from ±5 V supplies and needs a VREF+
of +3 V.
R4 4kΩ
R
I
DB7
DB0
U
T
P
U
T
9-BIT
ADC
9
9
SW2
LATCH
V
E
R
S
R5
4kΩ
R6
2kΩ
+
8
16
ALU
V
REF–
T he AD7884 is available in a 40-pin plastic DIP package and in
a 44-pin PLCC package.
A2
SW3
16-BIT
9
T he AD7885 is available in a 28-pin plastic DIP package and
the AD7885A is available in a 44-pin PLCC package.
ACCURATE
DAC
CS
RD
CONTROL
TIMER
HBEN
R7
2kΩ
R8
2kΩ
V
F
V
S
V
INV
V
REF–
DGND
GND
REF+
REF+
CONVST BUSY
REV. C
Inform ation furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assum ed by Analog Devices for its
use, nor for any infringem ents of patents or other rights of third parties
which m ay result from its use. No license is granted by im plication or
otherwise under any patent or patent rights of Analog Devices.
© Analog Devices, Inc., 1995
One Technology Way, P.O. Box 9106, Norw ood, MA 02062-9106, U.S.A.
Tel: 617/ 329-4700 Fax: 617/ 326-8703
AD7884/AD7885/AD7885A–SPECIFICATIONS (V = +5 V ؎ 5%, V = –5 V ؎ 5%, V +S
DD
SS
REF
= +3 V; AGND = DGND = GND = 0 V; fSAMPLE = 166 kHz. All specifications TMIN to T , unless otherwise noted.)
MAX
A
B
P aram eter
Version1, 2, 3 Versions1, 2, 3 Units
Test Conditions/Com m ents
DC ACCURACY
Resolution
16
16
Bits
Minimum Resolution for Which
No Missing Codes Are Guaranteed
Integral Nonlinearity
Positive Gain Error
Positive Gain Error
Gain T C4
Bipolar Zero Error
Bipolar Zero Error
Bipolar Zero T C4
Negative Gain Error
Negative Gain Error
Offset T C4
16
16
Bits
% FSR max
% FSR typ
% FSR max
ppm FSR/°C typ
% FSR typ
% FSR max
ppm FSR/°C typ
% FSR typ
±0.0075
±0.03
±0.05
±2
±0.05
±0.15
±8
±0.03
±0.05
±2
T ypically 0.003% FSR
AD7885AN/BN: 0.1% typ
AD7885BN: 0.2% max
±0.03
±2
±0.05
±8
±0.03
AD7885AN/BN: 0.1% typ
AD7885BN: 0.2% max
% FSR max
ppm FSR/°C typ
µV rms typ
±2
120
Noise
120
78 µV rms typical in ±3 V Input Range
DYNAMIC PERFORMANCE
Signal to (Noise + Distortion) Ratio
84
82
–88
–84
–88
84
82
–88
–84
–88
dB min
dB typ
dB max
dB typ
dB max
Input Signal: ±5 V, 1 kHz Sine Wave, Typically 86 dB
Input Signal: ±5 V, 12 kHz Sine Wave
Input Signal: ±5 V, 1 kHz Sine Wave
Input Signal: ±5 V, 12 kHz Sine Wave
Input Signal: ±5 V, 1 kHz Sine Wave
T otal Harmonic Distortion
Peak Harmonic or Spurious Noise
Intermodulation Distortion (IMD)
2nd Order T erms
–84
–84
–84
–84
dB typ
dB typ
fA = 11.5 kHz, fB = 12 kHz, fSAMPLE = 166 kHz
fA = 11.5 kHz, fB = 12 kHz, fSAMPLE = 166 kHz
3rd Order T erms
CONVERSION T IME
Conversion T ime
Acquisition T ime
T hroughput Rate
5.3
2.5
166
5.3
2.5
166
µs max
µs max
kSPS max
T here is an overlap between conversion and acquisition.
ANALOG INPUT
Voltage Range
±5
±3
±4
±5
±3
±4
Volts
Volts
mA max
Input Current
REFERENCE INPUT
Reference Input Current
±5
±5
mA max
VREF + S = +3 V
LOGIC INPUT S
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IIN
2.4
0.8
±10
10
2.4
0.8
±10
10
V min
VDD = 5 V ± 5%
VDD = 5 V ± 5%
Input Level = 0 V to VDD
V max
µA max
pF max
4
Input Capacitance, CIN
LOGIC OUT PUT S
Output High Voltage, VOH
Output Low Voltage, VOL
DB15–DB0
4.0
0.4
4.0
0.4
V min
V max
ISOURCE = 40 µA
ISINK = 1.6 mA
Floating-State Leakage Current
10
10
15
µA max
pF max
Floating-State Output Capacitance4 15
POWER REQUIREMENT S
VDD
VSS
IDD
ISS
+5
–5
35
30
+5
–5
35
30
V nom
V nom
mA max
mA max
±5% for Specified Performance
±5% for Specified Performance
T ypically 25 mA
T ypically 25 mA
Power Supply Rejection Ratio
∆Gain/∆VDD
86
86
dB typ
∆Gain/∆VSS
86
86
dB typ
Power Dissipation
325
325
mW max
T ypically 250 mW
NOT ES
1T emperature ranges are as follows: A, B Versions: –40 °C to +85°C.
2VIN = ±5 V.
3T he AD7885AAP has the same specs as the AD7884AP. T he AD7885ABP has the same specs as the AD7884BP.
4Sample tested to ensure compliance.
Specifications subject to change without notice.
–2–
REV. C
AD7884/AD7885
1, 2
(V = +5 V ؎ 5%, V = –5 V ؎ 5%, AGND = DGND = GND = 0 V. See Figures 2, 3, 4 and 5.)
TIMING CHARACTERISTICS
DD
SS
Lim it at +25؇C
Lim it at TMIN, TMAX
(A, B Versions)
P aram eter
(All Versions)
Units
Conditions/Com m ents
t1
t2
t3
t4
t5
50
100
0
60
0
50
100
0
60
0
ns min
ns max
ns min
ns min
ns min
ns max
ns min
ns max
ns min
ns min
ns min
ns min
ns min
ns max
ns max
CONVST Pulse Width
CONVST to BUSY Low Delay
CS to RD Setup T ime
RD Pulse Width
CS to RD Hold T ime
2
t63
57
5
57
5
Data Access T ime after RD
Bus Relinquish T ime after RD
t7
50
40
10
25
60
60
55
55
50
40
80
25
60
60
70
70
t8
t9
New Data Valid before Rising Edge of BUSY
HBEN to RD Setup T ime
HBEN to RD Hold T ime
HBEN Low Pulse Duration
HBEN High Pulse Duration
t10
t11
t12
t13
t14
Propagation Delay from HBEN Falling to Data Valid
Propagation Delay from HBEN Rising to Data Valid
NOT ES
1T iming specifications in bold print are 100% production tested. All other times are sample tested at +5 °C to ensure compliance. All input signals are specified
with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
2t6 is measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V.
3t7 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. T he measured number is then extrap-
olated back to remove the effects of charging or discharging the 100 pF capacitor. T his means that the time, t 7, quoted in the T iming Characteristics is the true
bus relinquish time of the part and as such is independent of external bus loading capacitances.
Specifications subject to change without notice.
O RD ERING GUID E
Linearity
Tem perature
Range
1.6mA
I
OL
Error
(% FSR)
SNR
(dB)
P ackage
O ption2
Model1
AD7884AN –40°C to +85°C
AD7884BN –40°C to +85°C ±0.0075
AD7884AP –40°C to +85°C
AD7884BP –40°C to +85°C ±0.0075
AD7885AN –40°C to +85°C
AD7885BN –40°C to +85°C ±0.0075
AD7885AAP –40°C to +85°C
84
84
84
84
84
84
84
84
N-40A
N-40A
P-44A
P-44A
N-28A
N-28A
P-44A
P-44A
TO OUTPUT PIN
+2.1V
C
L
100pF
AD7885ABP –40°C to +85°C ±0.0075
200µA
I
OH
NOT ES
1Analog Devices reserves the right to ship cerdip (Q) packages in lieu of plastic
DIP (N) packages.
2N = Plastic DIP; P = Plastic Leaded Chip Carrier (PLCC).
Figure 1. Load Circuit for Access Tim e and Bus Relinquish
Tim e
REV. C
–3–
AD7884/AD7885
t
1
t1
CONVST
CONVST
CS
t
2
t5
t3
t
CONVERT
t 4
RD
BUSY
DATA
t2
t
8
tCONVERT
BUSY
OLD DATA VALID
NEW DATA VALID
t7
Hi-Z
t6
Hi-Z
DATA
VALID
DATA
Figure 3. AD7884 Tim ing Diagram , with CS and RD
Perm anently Low
Figure 2. AD7884 Tim ing Diagram , Using CS and RD
t1
CONVST
t9
t10
HBEN
CS
RD
t3
t5
t 4
t2
tCONVERT
BUSY
DATA
t7
t6
Hi-Z
Hi-Z
Hi-Z
DATA
VALID
DATA
VALID
DB0–DB7
DB8–DB15
Figure 4. AD7885 Tim ing Diagram , Using CS and RD
t1
CONVST
HBEN
t12
t11
t2
t CONVERT
BUSY
DATA
t8
t14
t13
NEW DATA VALID
(DB0 – DB7)
OLD DATA VALID
(DB8 – DB15)
NEW DATA VALID
(DB8 – DB15)
NEW DATA VALID
(DB0 – DB7)
NEW DATA VALID
(DB8 – DB15)
Figure 5. AD7885 Tim ing Diagram , with CS and RD Perm anently Low
–4–
REV. C
AD7884/AD7885
ABSO LUTE MAXIMUM RATINGS 1
Operating T emperature Range
VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
AVDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
VSS to AGND . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –7 V
AVSS to AGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to –7 V
AGND Pins to DGND . . . . . . . . . . . . –0.3 V to VDD + 0.3 V
Commercial Plastic (A, B Versions) . . . . . –40°C to +85°C
Industrial Cerdip (A, B Versions) . . . . . . . . –40°C to +85°C
Extended Cerdip (T Versions) . . . . . . . . –55°C to +125°C
Storage T emperature Range . . . . . . . . . . . –65°C to +150°C
Lead T emperature (Soldering, 10 secs) . . . . . . . . . . . +300°C
Power Dissipation (Any Package) to +75°C . . . . . . . 1000 mW
Derates above +75°C by . . . . . . . . . . . . . . . . . . . . 10 mW/°C
1Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. T his is a stress rating only and functional
operation of the device at these or any other conditions above those listed in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
2If the AD7884/AD7885 is being powered from separate analog and digital supplies,
AVSS should always come up before VSS. See Figure 12 for a recommended
protection circuit using Schottky diodes.
2
AVDD to VD2D . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
AVSS to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –7 V
GND to DGND . . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V
VINS, VINF to AGND . . . . . . . . . . VSS –0.3 V to VDD + 0.3 V
VREF+ to AGND . . . . . . . . . . . . . . . VSS –0.3 V to VDD + 0.3 V
VREF– to AGND . . . . . . . . . . . . . . . VSS –0.3 V to VDD + 0.3 V
VINV to AGND . . . . . . . . . . . . . . . VSS –0.3 V to VDD + 0.3 V
Digital Inputs to DGND . . . . . . . . . . . –0.3 V to VDD + 0.3 V
Digital Outputs to DGND . . . . . . . . . . –0.3 V to VDD + 0.3 V
CAUTIO N
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although these devices feature proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. T herefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
P IN CO NFIGURATIO NS
D IP
P LCC
V
INV
1
V
V
V
1
28
27
26
25
24
23
22
40
39
V
S
F
REF–
INV
REF+
6
5
4
3
2
1
44 43 42 41 40
V
V
2
3
2
3
REF–
±3V
S
F
REF+
IN
S
REF+
7
8
39 DB12
DB11
±5V
F
±3V
±3V
±5V
±5V
S
F
S
F
±5V
38
37
V
REF+
DB15
DB14
IN
IN
IN
IN
IN
38
AGNDS
AGNDF
DB7
DB6
DB5
DB4
4
5
±5V
F
4
5
37 DB10
36 DB9
9
AV
DD
10
36 DB13
35 DB12
AGNDS
AGNDF
IN
IN
AV
35
DB8
34 NC
SS 11
AD7884
TOP VIEW
6
6
12
13
14
15
16
17
NC
(Not to Scale)
AGNDS
AGNDF
7
34
DB11
7
AD7885
TOP VIEW
(Not to Scale)
AV
DD
GND
DGND
33
32
31
30
V
AD7884
TOP VIEW
(Not to Scale)
GND
DD
8
33 DB10
8
21 DGND
20
AV
SS
DB7
DB6
V
SS
AV
DD
9
32
GND
9
DB9
DB3
V
SS
10
V
AV
SS
10
11
12
13
14
V
31 DB8
19 DB2
18 DB1
29 DB5
SS
DD
V
11
12
13
14
15
16
17
18
19
30 DGND
GND
GND
18 19 20 21 22 23 24 25 26 27 28
DD
V
29
CONVST
CS
17 DB0
16
DD
NC = NO CONNECT
V
28 DB7
27 DB6
BUSY
SS
V
15 HBEN
RD
SS
DB5
V
26
DD
6
5
4
3
2
1
44 43 42 41 40
25 DB4
CONVST
CS
DB3
DB2
DB1
24
23
22
±5V
F
DB7
DB6
NC
7
8
39
38
37
36
35
34
33
IN
AGNDS
AGNDF
RD
9
V
SS
AV
DD
DB5
DB4
NC
10
11
12
13
14
15
AV
SS
AD7885A
TOP VIEW
20
21 DB0
BUSY
NC
GND
GND
(Not to Scale)
DGND
32
V
DD
V
31 DB3
30 DB2
29 DB1
SS
V
SS 16
DD 17
V
18 19 20 21 22 23 24 25 26 27 28
NC = NO CONNECT
REV. C
–5–
AD7884/AD7885
P IN FUNCTIO N D ESCRIP TIO N
D escription
AD 7884
AD 7885
AD 7885A
VINV
VINV
VINV
T his pin is connected to the inverting terminal of an op amp, as in Figure 6, and allows
the inversion of the supplied +3 V reference.
VREF–
VREF–
VREF–
T his is the negative reference input, and it can be obtained by using an external amplifier
to invert the positive reference input. In this case, the amplifier output is connected to
VREF–. See Figure 6.
±3 VIN
S
_
_
±3 VIN
±3 VIN
S
F
T his is the analog input sense pin for the ±3 volt analog input range on the AD7884 and
AD7885A.
±3 VINF
T his is the analog input force pin for the ±3 volt analog input range on the AD7884 and
AD7885A. When using this input range, the ±5 VINF and ±5 VINS pins should be tied to
AGND.
–
±3 VIN
–
T his is the analog input pin for the ±3 volt analog input range on the AD7885. When us-
ing this input range, the ±5 VINF and ±5 VINS pins should be tied to AGND.
±5 VINS
±5 VINF
±5 VIN
±5 VIN
S
F
±5 VIN
±5 VIN
S
F
T his is the analog input sense pin for the ±5 volt analog input range on both the AD7884,
AD7885 and AD7885A.
T his is the analog input force pin for the ±5 volt analog input range on both the AD7884,
AD7885 and AD7885A. When using this input range, the ±3 VINF and ±3 VINS pins
should be tied to AGND.
AGNDS
AGNDF
AVDD
AVSS
AGNDS
AGNDF
AVDD
AVSS
AGNDS
AGNDF
AVDD
AVSS
T his is the ground return sense pin for the 9-bit ADC and the on-chip residue amplifier.
T his is the ground return force pin for the 9-bit ADC and the on-chip residue amplifier.
Positive analog power rail for the sample-and-hold amplifier and the residue amplifier.
Negative analog power rail for the sample-and-hold amplifier and the residue amplifier.
T his is the ground return for sample-and-hold section.
GND
VSS
GND
VSS
GND
VSS
Negative supply for the 9-bit ADC.
VDD
VDD
VDD
Positive supply for the 9-bit ADC and all device logic.
CONVST
CS
CONVST
CS
CONVST
CS
T his asynchronous control input starts conversion.
Chip Select control input.
RD
RD
RD
Read control input. T his is used in conjunction with CS to read the conversion result
from the device output latch.
–
HBEN
BUSY
–
HBEN
BUSY
–
High Byte Enable. Active high control input for the AD7885. It selects either the high or
the low byte of the conversion for reading.
BUSY
Busy output. T he Busy output goes low when conversion begins and stays low until it is
completed, at which time it goes high.
DB0–DB15
–
Sixteen-bit parallel data word output on the AD7884.
Eight-bit parallel data byte output on the AD7885.
Ground return for all device logic.
DB0–DB7 DB0–DB7
DGND DGND
DGND
V
REF+F
VREF+
VREF+
F
S
VREF+
VREF+
F
S
Reference force input.
VREF+
S
Reference sense input. T he device operates from a +3 V reference.
–6–
REV. C
AD7884/AD7885
TERMINO LO GY
Integr al Nonlinear ity
T his is the maximum deviation from a straight line passing
through the endpoints of the ADC transfer function.
T he AD7884/AD7885 is tested using the CCIFF standard
where two input frequencies near the top end of the input band-
width are used. In this case, the second and third order terms
are of different significance. T he second order terms are usually
distanced in frequency from the original sine waves while the
third order terms are usually at a frequency close to the input
frequencies. As a result, the second and third order terms are
specified separately. T he calculation of the intermodulation dis-
tortion is as per the T HD specification where it is the ratio of
the rms sum of the individual distortion products to the rms am-
plitude of the fundamental expressed in dBs.
D iffer ential Nonlinear ity
T his is the difference between the measured and the ideal 1 LSB
change between any two adjacent codes in the ADC.
Bipolar Zer o Er r or
T his is the deviation of the midscale transition (all 0s to all 1s)
from the ideal (AGND).
P ower Supply Rejection Ratio
P ositive Gain Er r or
T his is the ratio, in dBs, of the change in positive gain error to
the change in VDD or VSS. It is a dc measurement.
T his is the deviation of the last code transition (01 . . . 110 to
01 . . . 111) from the ideal (+VREF+S – 1 LSB), after Bipolar
Zero Error has been adjusted out.
O P ERATIO NAL D IAGRAM
Negative Gain Er r or
An operational diagram for the AD7884/AD7885 is shown in
Figure 6. It is set up for an analog input range of ±5 V. If a
±3 V input range is required, A1 should drive ±3 VINS and
±3 VINF with ±5 VINS, ±5 VINF being tied to system AGND.
T his is the deviation of the first code transition (10 . . . 000 to
10 . . . 001) from the ideal (–VREF+S + 1 LSB), after Bipolar
Zero Error has been adjusted out.
Signal to (Noise + D istor tion) Ratio
+5V
–5V
T his is the measured ratio of signal to (noise + distortion) at the
output of the A/D converter. T he signal is the rms amplitude of
the fundamental. Noise is the rms sum of all nonfundamental
signals up to half the sampling frequency (fS/2), excluding dc.
T he ratio is dependent upon the number of quantization levels
in the digitization process; the more levels, the smaller the quan-
tization noise. T he theoretical signal to (noise + distortion) ratio
for an ideal N-bit converter with a sine wave input is given by:
AV
V
AV
DD SS
V
DD
SS
±5V
S
IN
A1
AD817
AD711
±5V
F
IN
V
IN
±3V
±3V
S
F
IN
AD7884
AD7885
DATA
OUTPUTS
IN
Signal to (Noise + Distortion) = (6.02N + 1.76) dB
AGNDS
AGNDF
T hus for an ideal 16-bit converter, this is 98 dB.
AD817
Total H ar m onic D istor tion
A2
T otal harmonic distortion (T HD) is the ratio of the rms sum of
harmonics to the fundamental. For the AD7884/AD7885, it is
defined as:
CONTROL
INPUTS
V
= +5V
2
DD
V
V
S
REF+
AD845, AD817 OR
EQUIVALENT
A3
V22 +V32 +V42 +V52 +V62
6
F
REF+
INV
THD (dB) = 20 log
AD780
4
10µF
V1
V
8
AD845, AD817 OR
EQUIVALENT
A4
where V1 is the rms amplitude of the fundamental and V2, V3,
V4, V5 and V6 are the rms amplitudes of the second through the
sixth harmonics.
V
REF–
GND DGND
P eak H ar m onic or Spur ious Noise
Peak harmonic or spurious noise is defined as the ratio of the
rms value of the next largest component in the ADC output
spectrum (up to fS/2 and excluding dc) to the rms value of the
fundamental. Normally, the value of this specification is deter-
mined by the largest harmonic in the spectrum, but for parts
where the harmonics are buried in the noise floor, it will be a
noise peak.
NOTE: POWER SUPPLY DECOUPLING NOT SHOWN
Figure 6. AD7884/AD7885 Operational Diagram
T he chosen input buffer amplifier (A1) should have low noise
and distortion and fast settling time for high bandwidth applica-
tions. Both the AD711 and the AD845 are suitable amplifiers.
A2 is the force, sense amplifier for AGND. T he AGNDS pin
should be at zero potential. T herefore, the amplifier must have a
low input offset voltage and good noise performance. It must
also have the ability to deal with fast current transients on the
AGNDS pin. T he AD817 has the required performance and is
the recommended amplifier.
Inter m odulation D istor tion
With inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities will create distortion
products at sum and difference frequencies of mfa ± nfb where
m, n = 0, 1, 2, 3, etc. Intermodulation terms are those for which
neither m or n are equal to zero. For example, the second order
terms include (fa + fb) and (fa – fb), while the third order terms
include (2fa + fb), (2fa – fb), (fa + 2fb) and (fa – 2fb).
If AGNDS and AGNDF are simply tied together to Star
Ground instead of buffering, the SNR and T HD are not signifi-
cantly degraded. However, dc specifications like INL, Bipolar
Zero and Gain Error will be degraded.
REV. C
–7–
AD7884/AD7885
T he required +3 V reference is derived from the AD780 and
buffered by the high-speed amplifier A3 (AD845, AD817 or
equivalent). A4 is a unity gain inverter which provides the –3 V
negative reference. T he gain setting resistors are on-chip and
are factory trimmed to ensure precise tracking of VREF+. Figure
6 shows A3 and A4 as AD845s or AD817s. These have the ability
to respond to the rapidly changing reference input impedance.
A/D Conver ter Section
T he AD7884/AD7885 uses a two-pass flash technique in order
to achieve the required speed and resolution. When the CONVST
control input goes from low to high, the sample-and-hold ampli-
fier goes into the hold mode and a 0 V to –3 V signal is pre-
sented to the input of the 9-bit ADC. T he first phase of
conversion generates the 9 MSBs of the 16-bit result and trans-
fers these to the latch and ALU combination. T hey are also fed
back to the 9 MSBs of the 16-bit DAC. T he 7 LSBs of the
DAC are permanently loaded with 0s. T he DAC output is sub-
tracted from the analog input with the result being amplified
and offset in the Residue Amplifier Section. T he signal at the
output of A2 is proportional to the error between the first phase
result and the actual analog input signal and is digitized in the
second conversion phase. T his second phase begins when the
16-bit DAC and the Residue Error Amplifier have both settled.
First, SW2 is turned off and SW3 is turned on. T hen, the SHA
section of the Residue Amplifier goes into hold mode. Next
SW2 is turned off and SW3 is turned on. T he 9-bit result is
transferred to the output latch and ALU. An error correction al-
gorithm now compensates for the offset inserted in the Residue
Amplifier Section and errors introduced in the first pass conver-
sion and combines both results to give the 16-bit answer.
CIRCUIT D ESCRIP TIO N
Analog Input Section
T he analog input section of the AD7884/AD7885 is shown in
Figure 7. It contains both the input signal conditioning and
sample-and-hold amplifier. Note that the analog input is truly
benign. When SW1a goes open circuit to put the SHA into the
hold mode, SW1b is closed. T his means that the input resis-
tors, R1 and R2 are always connected to either virtual ground
or true ground.
R3 3kΩ
C1
±3V
F
R1 3kΩ
R2 5kΩ
IN
TO
R4 4kΩ
9-BIT
ADC
A1
SW1a
±3V
±5V
±5V
S
F
S
IN
IN
IN
R5 4kΩ
±3V SIGNAL
FROM INPUT
SHA
R4
4kΩ
0 TO –3V
SW2
9-BIT
ADC
R6 2kΩ
9
9
LATCH
+
ALU
R5
4kΩ
SW1b
R6
2kΩ
16
V
REF–
TO RESIDUE
AMPLIFIER A2
V
REF–
SW3
A2
Figure 7. AD7884/AD7885 Analog Input Section
RESIDUE AMP
+ SHA
When the ±3 VINS and ±3 VINF inputs are tied to 0 V, the in-
put section has a gain of –0.6 and transforms an input signal
of ±5 volts to the required ±3 volts. When the ±5 VINS and
±5 VINF inputs are grounded, the input section has a gain of
–1 and so the analog input range is now ±3 volts. Resistors R4
and R5, at the amplifier output, further condition the ±3 volts
signal to be 0 to –3 volts. T his is the required input for the 9-bit
A/D converter section.
16-BIT
9
ACCURATE
DAC
+3V
–3V
R7
2kΩ
R8
2kΩ
With SW1a closed, the output of A1 follows the input (the
sample-and-hold is in the track mode). On the rising edge of
the CONVST pulse, SW1a goes open circuit, and capacitor C1
holds the voltage on the output of A1. T he sample-and-
hold is now in the hold mode. T he aperture delay time for the
sample-and-hold is nominally 50 ns.
V
F
V
S
V
REF–
V
REF+
REF+
INV
Figure 8. A/D Converter Section
–8–
REV. C
AD7884/AD7885
Tim ing and Contr ol Section
±5V
S
IN
Figure 9 shows the timing and control sequence for the
AD7884/AD7885. When the part receives a CONVST pulse,
the conversion begins. T he input sample-and-hold goes into the
hold mode 50 ns after the rising edge of CONVST and BUSY
goes low. T his is the first phase of conversion and takes 3.35 µs
to complete. T he second phase of conversion begins when SW2
is turned off and SW3 turned on. T he Residue Amplifier and
SHA section (A2 in Figure 8) goes into hold mode at this point
and allows the input sample-and-hold to go back into sample
mode. T hus, while the second phase of conversion is ongoing,
the input sample-and-hold is also acquiring the input signal for
the next conversion. T his overlap between conversion and ac-
quisition allows throughput rates of 166 kSPS to be achieved.
±5V
F
A1
IN
V
INV
±3V
±3V
S
F
IN
IN
Figure 10. ±5 V Input Range Connection
±5V
±5V
S
F
IN
IN
CONVST
SECOND
PHASE
FIRST PHASE
±3V
±3V
S
F
3.5µs
IN
IN
1.8µs
BUSY
TACQ
2.5µs
INPUT HOLD
A1
V
SHA
SAMPLE
INV
FIRST PHASE OF CONVERSION
1ST 9-BIT CONVERSION
DAC SETTLING TIME
RESIDUE AMPLIFIER
SETTLING TIME
SECOND PHASE OF CONVERSION
2ND 9-BIT CONVERSION
ERROR CORRECTION
Figure 11. ±3 V Input Range Connections
OUTPUT LATCH UPDATE
T he critical performance specification for a reference in a 16-bit
application is noise. T he reference pk-pk noise should be insig-
nificant in comparison to the ADC noise. T he AD7884/
AD7885 has a typical rms noise of 120 µV. For example a rea-
sonable target would be to keep the total rms noise less than
125 µV. T o do this the reference noise needs to be less than
35 µV rms. In the 100 kHz band, the AD780 noise is less than
30 µV rms, making it a very suitable reference.
Figure 9. Tim ing and Control Sequence
USING TH E AD 7884/AD 7885 ANALO G INP UT RANGES
T he AD7884/AD7885 can be set up to have either a ±3 volts
analog input range or a ±5 volts analog input range. Figures 10
and 11 show the necessary corrections for each of these. T he
output code is 2s complement and the ideal code table for both
input ranges is shown in T able I.
T he buffer amplifier used to drive the device VREF+ should have
low enough noise performance so as not to affect the overall
system noise requirement. T he AD845 and AD817 achieve
this.
Refer ence Consider ations
T he AD7884/AD7885 operates from a ±3 volt reference. T his
can be derived simply using the AD780 as shown in Figure 6.
Table I. Ideal O utput Code Table for the AD 7884/AD 7885
Analog Input
؎3 V Range3
D igital O utput
In Term s of FSR2
؎5 V Range4
Code Transitionl
+FSR/2 – 1 LSB
+FSR/2 – 2 LSBs
+FSR/2 – 3 LSBs
2.999908
2.999817
2.999726
4.999847
4.999695
4.999543
011 . . . 111 to 111 . . . 110
011 . . . 110 to 011 . . . 101
011 . . . 101 to 011 . . . 100
AGND + 1 LSB
AGND
AGND – 1 LSB
0.000092
0.000000
–0.000092
0.000153
0.000000
–0.000153
000 . . . 001 to 000 . . . 000
000 . . . 000 to 111 . . . 111
111 . . . 111 to 111 . . . 110
–(FSR/2 – 3 LSBs)
–(FSR/2 – 2 LSBs)
–(FSR/2 – 1 LSB)
–2.999726
–2.999817
–2.999908
–4.999543
–4.999695
–4.999847
100 . . . 011 to 100 . . . 010
100 . . . 010 to 100 . . . 001
100 . . . 001 to 100 . . . 000
NOT ES
1T his table applies for VREF+S = +3 V.
2FSR (Full-Scale Range) is 6 volts for the ±3 V input range and 10 volts for the ±5 V input range.
31 LSB on the ±3 V range is FSR/216 and is equal to 91.5 µV.
41 LSB on the ±5 V range is FSR/216 and is equal to 152.6 µV.
REV. C
–9–
AD7884/AD7885
D ecoupling and Gr ounding
AD 7884/AD 7885 P ERFO RMANCE
T he AD7884 and AD7885A have one AVDD pin and two VDD
pins. T hey also have one AVSS pin and three VSS pins. T he
AD7885 has one AVDD pin, one VDD pin, one AVSS pin and one
VSS pin. Figure 6 shows how a common +5 V supply should be
used for the positive supply pins and a common –5 V supply for
the negative supply pins.
Linear ity
T he linearity of the AD7884/AD7885 is determined by the
on-chip 16-bit D/A converter. T his is a segmented DAC which
is laser trimmed for 16-bit DNL performance to ensure that
there are no missing codes in the ADC transfer function. Figure
13 shows a typical INL plot for the AD7884/AD7885.
For decoupling purposes, the critical pins on both devices are
the AVDD and AVSS pins. Each of these should be decoupled to
system AGND with 10 µF tantalum and 0.1 µF ceramic capaci-
tors right at the pins. With the VDD and VSS pins, it is sufficient
to decouple each of these with ceramic 1 µF capacitors.
2.0
V
V
= +5V
= –5V
= +25°C
DD
SS
1.5
1.0
0.5
0
T
A
AGNDS, AGNDF are the ground return points for the on-chip
9-bit ADC. T hey should be driven by a buffer amplifier as
shown in Figure 6. If they are tied directly together and then
to ground, there will he a marginal degradation in linearity
performance.
0
16384
32768
49152
65535
OUTPUT CODE
T he GND pin is the analog ground return for the on-chip linear
circuitry. It should he connected to system analog ground.
Figure 13. AD7884/AD7885 Typical Linearity Perform ance
Noise
T he DGND pin is the ground return for the on-chip digital
circuitry. It should be connected to the ground terminal of the
VDD and VSS supplies. If a common analog supply is used for
AVDD and VDD then DGND should be connected to the com-
mon ground point.
In an A/D converter, noise exhibits itself as code uncertainty in
dc applications and as the noise floor (in an FFT , for example)
in ac applications.
In a sampling A/D converter like the AD7884/AD7885, all in-
formation about the analog input appears in the baseband from
dc to 1/2 the sampling frequency. An antialiasing filter will re-
move unwanted signals above fS/2 in the input signal but the
converter wideband noise will alias into the baseband. In the
AD7884/AD7885, this noise is made up of sample-and-hold
noise and A/D converter noise. T he sample-and-hold section
contributes 51 µV rms and the ADC section contributes 59 µV
rms. T hese add up to a total rms noise of 78 µV. T his is the in-
put referred noise in the ±3 V analog input range. When operat-
ing in the ±5 V input range, the input gain is reduced to –0.6.
T his means that the input referred noise is now increased by a
factor of 1.66 to 120 µV rms.
P ower Supply Sequencing
AVDD and VDD are connected to a common substrate and there
is typically 17 Ω resistance between them. If they are powered
by separate +5 V supplies, then these should come up simulta-
neously. Otherwise, the one that comes up first will have to
drive +5 V into a 17 Ω load for a short period of time. However,
the standard short-circuit protection on regulators like the 7800
series will ensure that there is no possibility of damage to the
driving device.
AVSS should always come up either before or at the same time
as VSS. If this cannot be guaranteed, Schottky diodes should be
used to ensure that VSS never exceeds AVSS by more than 0.3 V.
Arranging the power supplies as in Figure 6 and using the recom-
mended decoupling ensures that there are no power supply
sequencing issues as well as giving the specified noise performance.
Figure 14 shows a histogram plot for 5000 conversions of a dc
input using the AD7884/AD7885 in the ±5 V input range. T he
analog input was set as close as possible to the center of a code
transition. All codes other than the center code are due to the
ADC noise. In this case, the spread is six codes.
+5V
+5V
–5V
–5V
HP5082-2810
OR
3000
2000
1000
0
EQUIVALENT
AV
V
AV
V
DD
DD
SS
SS
AD7884/AD7885
Figure 12. Schottky Diodes Used to Protect Against
Incorrect Power Supply Sequencing
(X – 2) (X – 1)
(X)
(X + 1) (X + 2) (X + 3)
CODE
Figure 14. Histogram of 5000 Conversions of a DC Input
–10–
REV. C
AD7884/AD7885
16
If the noise in the converter is too high for an application, it can
be reduced by oversampling and digital filtering. T his involves
sampling the input at higher than the required word rate and
then averaging to arrive at the final result. T he very fast conver-
sion time of the AD7884/AD7885 makes it very suitable for
oversampling. For example, if the required input bandwidth is
40 kHz, the AD7884/AD7885 could be oversampled by a factor
of 2. T his yields a 3 dB improvement in the effective SNR per-
formance. T he noise performance in the ±5 volt input range is
now effectively 85 µV rms and the resultant spread of codes for
2500 conversions will be four. T his is shown in Figure 15.
15
14
13
12
11
10
1500
1000
500
0
0
20
40
60
80
FREQUENCY – kHz
Figure 17. Effective Num ber of Bits vs. Frequency
T he effective number of bits for a device can be calculated from
its measured SNR. Figure 17 shows a typical plot of effective
number of bits versus frequency for the AD7884. T he sampling
frequency is 166 kHz.
MICRO P RO CESSO R INTERFACING
T he AD7884/AD7885 is designed on a high speed process
which results in very fast interfacing timing (Data Access T ime
of 57 ns max). T he AD7884 has a full 16-bit parallel bus, and
the AD7885 has an 8-bit wide bus. T he AD7884, with its paral-
lel interface, is suited to 16-bit parallel machines whereas the
AD7885, with its byte interface, is suited to 8-bit machines.
Some examples of typical interface configurations follow.
(X – 1)
(X)
(X + 1) (X + 2)
CODE
Figure 15. Histogram of 2500 Conversions of a DC Input
Using a ×2 Oversam pling Ratio
D ynam ic P er for m ance
AD 7884 to MC68000 Inter face
With a combined conversion and acquisition time of 6 µs, the
AD7884/AD7885 is ideal for wide bandwidth signal processing
applications. Signal to (Noise + Distortion), T otal Harmonic
Distortion, Peak Harmonic or Spurious Noise and Intermodula-
tion Distortion are all specified. Figure 16 shows a typical
FFT plot of a 1.8 kH z, ± 5 V input after being digitized by the
AD7884/AD7885.
Figure 18 shows a general interface diagram for the MC68000,
16-bit microprocessor to the AD7884. In Figure 18, conversion
is initiated by bringing CSA low (i.e., writing to the appropriate
address). T his allows the processor to maintain control over the
complete conversion process. In some cases it may be more
desirable to control conversion independent from the processor.
T his can be done by using an external sampling timer.
0
f
f
= 1.8kHz, ± 5V SINE WAVE
IN
ADDRESS BUS
A23 – A1
MC68000
= 163kHz
SAMPLE
SNR = 87dB
THD = –95dB
–30
–60
ADDRESS
DECODE LOGIC
AD7884
CSB
CSA
CONVST
CS
DTACK
–90
AS
RD
R/W
–120
–150
DB15 – DB0
DATA BUS
D15 – D0
2048 POINT FFT
Figure 18. AD7884 to MC68000 Interface
Figure 16. AD7884/AD7885 FFT Plot
Once conversion has been started, the processor must wait until
it is completed before reading the result. T here are two ways of
ensuring this. T he first way is to simply use a software delay to
wait for 6.5 µs before bringing CS and RD low to read the data.
Effective Num ber of Bits
T he formula for SNR (see T erminology section) is related to
the resolution or number of bits in the converter. Rewriting the
formula, below, gives a measure of performance expressed in
effective number of bits (N).
N = (SNR – 1.76)/6.02
REV. C
–11–
AD7884/AD7885
Figure 19 shows an interface configuration for the AD7884 to
such a system. Note that only signals relevant to the AD7884
are shown. For the full 80286 configuration refer to the iAPX
286 data sheet (Basic System Configuration).
T he second way is to use the BUSY output of the AD7884 to
generate an interrupt in the MC68000. Because of the nature of
its interrupts, the MC68000 requires additional logic (not
shown in Figure 18) to allow it to be interrupted correctly. For
full information on this, consult the MC68000 User’s Manual.
In Figure 19 conversion is started by writing to a selected ad-
dress and causing it CS2 to go low. When conversion is com-
plete, BUSY goes high and initiates an interrupt. T he processor
can then read the conversion result.
AD 7884 to 80286 Inter face
T he 80286 is an advanced high performance processor with spe-
cial capabilities aimed at multiuser and multitasking systems.
MEMORY READ
MRDC
82288 BUS
CONTROLLER
CS1
CS2
DECODE
CIRCUITRY
CLK
CLK
AD7884
82284 CLOCK
GENERATOR
RD
CS
CONVST
8282 OR
8283
LATCH
CLK
A
– A
DB15
23 0
DB0
BUSY
80286
CPU
D
– D
0
15
IR – IR
0
7
8259A
INTERRUPT
CONTROLLER
8286 OR 8287
TRANSCEIVER
Figure 19. AD7884 Interfacing to Basic iAPX 286 System
–12–
REV. C
AD7884/AD7885
AD 7885 to 8088 Inter face
Stand-Alone O per ation
T he AD7885, with its byte (8 + 8) data format, is ideal for use
with the 8088 microprocessor. Figure 20 is the interface dia-
gram. Conversion is started by enabling CSA. At the end of
conversion, data is read into the processor. T he read instruc-
tions are:
If CS and RD are tied permanently low on the AD7884, then,
when a conversion is completed, output data will be valid on the
rising edge of BUSY. T his makes the device very suitable for
stand-alone operation. All that is required to run the device is an
external CONVST pulse which can be supplied by a sample
timer. Figure 22 shows the AD7884 set up in this mode with the
BUSY signal providing the clock for the 74HC574 3-state
latches.
MOV AX, C001 Read 8 MSBs of data
MOV AX, C000 Read 8 LSBs of data
+5 V
MN/MX
A0
A15 – A8
A0
ADDRESS BUS
TIMER
HBEN
HBEN
ADDRESS
IO/M
CONVST
DECODE LOGIC
CSB
CSA
8088
74HC574
DB15 – DB8
CONVST
CS
RD
RD
AD7884
CLK
STB
8282
ALE
AD7885
74HC574
DB7 – DB0
DB7 – DB0
DATA BUS
AD7 – AD0
BUSY
CLK
CS
RD
Figure 20. AD7885 to 8088 Interface
AD 7884 to AD SP -2101 Inter face
Figure 21 shows an intcrface between the AD7884 and the
ADSP-2101. Conversion is initiated using a timer which allows
very accurate control of the sampling instant. T he AD7884
BUSY line provides an interrupt to the ADSP-2101 when con-
version is completed. T he RD pulse width of the processor can
be programmed using the Data Memory Wait State Control
Register. T he result can then be read from the ADC using the
following instruction:
Figure 22. Stand-Alone Operation
D igital Feedthr ough fr om an Active Bus
It is very important when using the AD7884/AD7885 in a
microprocessor-based system to isolate the ADC data bus from
the active processor bus while a conversion is being executed.
T his will yield the best noise performance from the ADC.
Latches like the 74HC574 can be used to do this. If the device
is connected directly to an active bus then the converter noise
will typically increase by a factor of 30%.
MR0 = DM (ADC)
where MR0 is the ADSP-2101 MR0 register, and
where ADC is the AD7884 address.
TIMER
ADDRESS BUS
DMA13 – DMA0
ADSP-2101
ADDRESS
AD7884
DECODE LOGIC
DMS
EN
CONVST
CS
BUSY
RD
IRQn
RD
DB15 – DB0
DATA BUS
DMD15 – DMD0
Figure 21. AD7884 to ADSP-2101 Interface
REV. C
–13–
AD7884/AD7885
O UTLINE D IMENSIO NS
D imensions shown in inches and (mm).
28-P in P lastic D IP (N-28A)
1.450 (36.83)
1.440 (35.576)
28
15
0.550 (13.97)
0.530 (13.462)
14
1
0.606 (15.39)
0.594 (15.09)
0.200
(5.080)
MAX
0.160 (4.06)
0.140 (3.56)
SEATING
PLANE
15°
0°
0.012 (0.305)
0.008 (0.203)
0.175 (4.45)
0.120 (3.05)
0.105 (2.67)
0.095 (2.41)
0.020 (0.508)
0.015 (0.381)
0.06 (1.52)
0.05 (1.27)
LEADS ARE SOLDER DIPPED OR TIN-PLATED ALLOY 42 OR COPPER.
40-P in P lastic D IP (N-40A)
0.005 (0.13) MIN
0.110 (2.79) MAX
40
21
0.55 (13.97)
0.53 (13.46)
PIN 1
1
20
0.620 (15.75)
0.580 (14.73)
2.08 (52.83) MAX
0.060 (1.52)
0.015 (0.38)
0.200
(5.08)
MAX
0.140
(3.56)
MIN
0.175 (4.45)
0.120 (3.05)
0.015 (0.38)
0.008 (0.20)
0.025 (0.64)
0.015 (0.38)
0.060 (1.52)
0.040 (1.02)
SEATING
PLANE
0.100 (2.54)
BSC
0˚-15˚
–14–
REV. C
AD7884/AD7885
44-P in P LCC (P -44A)
0.045 (1.143) TYP
0.045 (1.143) TYP
PIN 1
IDENTIFIER
0.050 ± 0.005
(1.27 ± 0.13)
0.045
(1.143)
TYP
0.045
(1.143)
TYP
0.630 (16.00)
0.590 (14.99)
0.021 (0.533)
0.013 (0.331)
TOP VIEW
0.032 (0.812)
0.026 (0.661)
0.656 (16.662)
0.650 (16.510)
0.020 (0.508) MIN
SQ
SQ
0.120 (3.04)
0.090 (2.29)
0.695 (17.65)
0.685 (17.40)
0.180 (4.57)
0.165 (4.20)
R.020 (0.508) MAX
3 PLCS
REV. C
–15–
–16–
相关型号：
©2020 ICPDF网 联系我们和版权申明