AD8005ARZ-REEL7 [ADI]
270 MHz, 400µA Current Feedback Amplifier;
| 型号： | AD8005ARZ-REEL7 |
| 厂家： | 
ADI |
| 描述： | 270 MHz, 400µA Current Feedback Amplifier 放大器 光电二极管 |
| 文件： | 总17页 (文件大小：410K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
270 MHz, 400 μA
Current Feedback Amplifier
Data Sheet
AD8005
FEATURES
FUNCTIONAL BLOCK DIAGRAMS
Ultralow power
1
2
3
4
8
7
6
5
NC
+V
NC
–IN
+IN
AD8005
400 μA power supply current (4 mW on ±± VS)
Specified for single supply operation
High speed
S
OUT
NC
–V
S
TOP VIEW
270 MHz, −3 dB bandwidth (G = +1)
170 MHz, −3 dB bandwidth (G = +2)
280 V/μs slew rate (G = +2)
(Not to Scale)
NC = NO CONNECT
Figure 1. 8-Lead PDIP and SOIC_N
28 ns settling time to 0.1%, 2 V step (G = +2)
Low distortion/noise
AD8005
OUT
1
2
3
5
+V
S
−63 dBc at 1 MHz, VO = 2 V p-p
−±0 dBc at 10 MHz, VO = 2 V p-p
4.0 nV/√Hz input voltage noise at 10 MHz
Good video specifications (RL = 1 kΩ, G = +2)
Gain flatness 0.1 dB to 30 MHz
0.11% differential gain error
–V
S
+IN
4
–IN
TOP VIEW
(Not to Scale)
Figure 2. 5-Lead SOT-23
0.4° differential phase error
3
2
G = +2
= 200mV p-p
V
APPLICATIONS
OUT
= 1kΩ
R
L
Signal conditioning
1
A/D buffer
0
Power sensitive, high speed systems
Battery powered equipment
Loop/remote power systems
Communication or video test systems
Portable medical instruments
–1
–2
–3
–4
–5
–6
V
= ±5V
S
V
= +5V
S
GENERAL DESCRIPTION
The AD8005 is an ultralow power, high speed amplifier with a
wide signal bandwidth of 170 MHz and slew rate of 280 V/μs.
This performance is achieved while consuming only 400 μA of
quiescent supply current. These features increase the operating
time of high speed battery powered systems without reducing
dynamic performance.
0.1
1
10
100
500
FREQUENCY (MHz)
Figure 3. Frequency Response; G = 2ꢀ VS = +5 V or 5 V
–40
G = +2
= 2V p-p
V
OUT
= 1kΩ
R
L
–50
–60
THIRD HARMONIC
The current feedback design results in gain flatness of 0.1 dB to
30 MHz while offering differential gain and phase errors of 0.11%
and 0.4°. Harmonic distortion is low over a wide bandwidth with
THDs of −63 dBc at 1 MHz and −50 dBc at 10 MHz. Ideal features
for a signal conditioning amplifier or buffer to a high speed A-to-D
converter in portable video, medical or communication systems.
–70
SECOND HARMONIC
–80
The AD8005 is characterized for +5 V and 5 V supplies and
operates over the industrial temperature range of −40°C to
+85°C. The amplifier is supplied in 8-lead PDIP, 8-lead SOIC_N,
and 5-lead SOT-23 packages.
–90
–100
1
10
20
FREQUENCY (MHz)
Figure 4. Distortion vs. Frequency; VS = 5 V
Rev. B
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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
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Tel: 781.329.4700 ©1996–2014 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
AD8005* PRODUCT PAGE QUICK LINKS
Last Content Update: 02/23/2017
COMPARABLE PARTS
View a parametric search of comparable parts.
REFERENCE MATERIALS
Product Selection Guide
• High Speed Amplifiers Selection Table
Tutorials
EVALUATION KITS
• Universal Evaluation Board for Single High Speed
• MT-034: Current Feedback (CFB) Op Amps
• MT-051: Current Feedback Op Amp Noise Considerations
• MT-057: High Speed Current Feedback Op Amps
Operational Amplifiers
DOCUMENTATION
Application Notes
• MT-059: Compensating for the Effects of Input
Capacitance on VFB and CFB Op Amps Used in Current-to-
Voltage Converters
• AN-253: Find Op Amp Noise with Spreadsheet
• AN-257: Careful Design Tames High Speed Op Amps
DESIGN RESOURCES
• AD8005 Material Declaration
• PCN-PDN Information
• Quality And Reliability
• Symbols and Footprints
• AN-356: User's Guide to Applying and Measuring
Operational Amplifier Specifications
• AN-649: Using the Analog Devices Active Filter Design
Tool
• AN-692: Universal Precision Op Amp Evaluation Board
Data Sheet
• AD8005: 270 MHz, 400 µA Current Feedback Amplifier
Data Sheet
DISCUSSIONS
View all AD8005 EngineerZone Discussions.
User Guides
• UG-755: 8-Lead SOIC Amplifier Evaluation Board User
Guide
SAMPLE AND BUY
Visit the product page to see pricing options.
• UG-838: Evaluation Board for Single, High Speed Op Amps
Offered in 5-Lead SOT-23 and 6-Lead SOT-23 Packages
TECHNICAL SUPPORT
Submit a technical question or find your regional support
number.
TOOLS AND SIMULATIONS
• AD8005 SPICE Macro-Model
DOCUMENT FEEDBACK
Submit feedback for this data sheet.
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AD8005
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
ESD Caution...................................................................................5
Typical Performance Characteristics ..............................................6
Applications..................................................................................... 10
Driving Capacitive Loads.......................................................... 10
Single-Supply Level Shifter ....................................................... 10
Single-Ended-to-Differential Conversion............................... 10
Layout Considerations............................................................... 11
Increasing Feedback Resistors.................................................. 11
Outline Dimensions....................................................................... 12
Ordering Guide .......................................................................... 13
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagrams............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
5 V Supplies ................................................................................ 3
+5 V Supply................................................................................... 4
Absolute Maximum Ratings............................................................ 5
Thermal Resistance ...................................................................... 5
Maximum Power Dissipation ..................................................... 5
REVISION HISTORY
3/14—Rev. A to Rev. B
Updated Format..................................................................Universal
Deleted Operating Temperature Range Parameter, Table 1........ 3
Changes to Table 3............................................................................ 5
Change to Figure 11 ......................................................................... 6
Changes to Ordering Guide .......................................................... 13
8/99—Rev. 0 to Rev. A
Rev. B | Page 2 of 16
Data Sheet
AD8005
SPECIFICATIONS
5 V SUPPLIES
At TA = +25°C, VS = 5 V, RL = 1 kΩ, unless otherwise noted.
Table 1.
Parameter
Conditions
Min
Typ
Max
Units
DYNAMIC PERFORMANCE
RF = 3.01 kΩ for N-8 Package or
RF = 2.49 kΩ for R-8 Package or
RF = 2.10 kΩ for RJ-5 Package
G = +1, VO = 0.2 V p-p
G = +2, VO = 0.2 V p-p
G = +2, VO = 0.2 V p-p
G = +10, VO = 4 V p-p, RF = 499 Ω
G = +2, VO = 4 V Step
−3 dB Small Signal Bandwidth
225
140
10
270
170
30
MHz
MHz
MHz
MHz
V/µs
V/µs
ns
Bandwidth for 0.1 dB Flatness
Large Signal Bandwidth
Slew Rate (Rising Edge)
40
280
1500
28
G = –1, VO = 4 V Step, RF = 1.5 kΩ
G = +2, VO = 2 V Step
Settling Time to 0.1%
DISTORTION/NOISE PERFORMANCE
RF = 3.01 kΩ for N-8 Package or
RF = 2.49 kΩ for R-8 Package or
RF = 2.10 kΩ for RJ-5 Package
fC = 1 MHz, VO = 2 V p-p, G = +2
fC = 10 MHz, VO = 2 V p-p, G = +2
NTSC, G = +2
Total Harmonic Distortion
−63
−50
0.11
0.4
4.0
1.1
dBc
dBc
%
Degrees
nV/√Hz
pA/√Hz
pA/√Hz
Differential Gain
Differential Phase
Input Voltage Noise
Input Current Noise
NTSC, G = +2
f = 10 MHz
f = 10 MHz, +IIN
−IIN
9.1
DC PERFORMANCE
Input Offset Voltage
5
30
50
mV
mV
TMIN to TMAX
Offset Drift
+Input Bias Current
40
0.5
µV/°C
µA
1
TMIN to TMAX
TMIN to TMAX
2
10
12
µA
µA
µA
−Input Bias Current
5
Input Bias Current Drift ( )
Open-Loop Transimpedance
INPUT CHARACTERISTICS
Input Resistance
6
nA/°C
kΩ
400
1000
+Input
−Input
+Input
90
MΩ
Ω
pF
V
260
1.6
3.8
54
Input Capacitance
Input Common-Mode Voltage Range
Common-Mode Rejection Ratio
OUTPUT CHARACTERISTICS
Output Voltage Swing
VCM = 2.5 V
46
dB
Positive
Negative
RL = 50 Ω
+3.7
+3.90
−3.90
10
V
V
mA
mA
−3.7
Output Current
Short Circuit Current
POWER SUPPLY
60
Quiescent Current
400
66
475
560
µA
µA
dB
TMIN to TMAX
VS = 4 V to 6 V
Power Supply Rejection Ratio
56
Rev. B | Page 3 of 16
AD8005
Data Sheet
+5 V SUPPLY
At TA = +25°C, VS = +5 V, R L = 1 kΩ to 2.5 V, unless otherwise noted.
Table 2.
Parameter
Conditions
Min
Typ
Max Units
DYNAMIC PERFORMANCE
RF = 3.01 kΩ for N-8 Package or
RF = 2.49 kΩ for R-8 Package or
RF = 2.10 kΩ for RJ-5 Package
G = +1, VO = 0.2 V p-p
G = +2, VO = 0.2 V p-p
G = +2, VO = 0.2 V p-p
G = +10, VO = 4 V p-p, RF = 499 Ω
G = +2, VO = 4 V Step
−3 dB Small Signal Bandwidth
190
110
10
225
130
30
MHz
MHz
MHz
MHz
V/µs
V/µs
ns
Bandwidth for 0.1 dB Flatness
Large Signal Bandwidth
Slew Rate (Rising Edge)
45
260
775
30
G = –1, VO = 4 V Step, RF = 1.5 kΩ
G = +2, VO = 2 V Step
Settling Time to 0.1%
DISTORTION/NOISE PERFORMANCE
RF = 3.01 kΩ for N-8 Package or
RF = 2.49 kΩ for R-8 Package or
RF = 2.10 kΩ for RJ-5 Package
fC = 1 MHz, VO = 2 V p-p, G = +2
fC = 10 MHz, VO = 2 V p-p, G = +2
NTSC, G = +2
Total Harmonic Distortion
−60
−50
0.14
0.70
4.0
dBc
dBc
%
Degrees
nV/√Hz
pA/√Hz
pA/√Hz
Differential Gain
Differential Phase
Input Voltage Noise
Input Current Noise
NTSC, G = +2
f = 10 MHz
f = 10 MHz, +IIN
1.1
9.1
−IIN
DC PERFORMANCE
Input Offset Voltage
5
35
50
mV
mV
TMIN to TMAX
Offset Drift
+Input Bias Current
40
0.5
µV/°C
µA
1
TMIN to TMAX
TMIN to TMAX
2
10
11
µA
µA
µA
−Input Bias Current
5
Input Bias Current Drift ( )
Open-Loop Transimpedance
INPUT CHARACTERISTICS
Input Resistance
8
500
nA/°C
kΩ
50
48
+Input
−Input
+Input
120
300
1.6
1.5 to 3.5
54
MΩ
Ω
pF
V
Input Capacitance
Input Common-Mode Voltage Range
Common-Mode Rejection Ratio
OUTPUT CHARACTERISTICS
Output Voltage Swing
Output Current
VCM = 1.5 V to 3.5 V
RL = 50 Ω
dB
1.1 to 3.9 0.95 to 4.05
V
mA
mA
10
30
Short Circuit Current
POWER SUPPLY
Quiescent Current
350
425
470
µA
µA
dB
TMIN to TMAX
VS = +4 V to +6 V
Power Supply Rejection Ratio
56
66
OPERATING TEMPERATURE RANGE
–40
+85 °C
Rev. B | Page 4 of 16
Data Sheet
AD8005
ABSOLUTE MAXIMUM RATINGS
Table 3.
MAXIMUM POWER DISSIPATION
The maximum power that can be safely dissipated by the AD8005
is limited by the associated rise in junction temperature. The
maximum safe junction temperature for plastic encapsulated
devices is determined by the glass transition temperature of the
plastic, approximately +150°C. Exceeding this limit temporarily
causes a shift in parametric performance due to a change in the
stresses exerted on the die by the package. Exceeding a junction
temperature of +175°C for an extended period can result in
device failure.
Parameter
Rating
Supply Voltage
Internal Power Dissipation1
PDIP Package (N-8)
SOIC_N (R-8)
SOT-23 Package (RJ-5)
Input Voltage (Common Mode)
Differential Input Voltage
Output Short Circuit Duration
Storage Temperature Range
Operating Temperature Range –40°C to +85°C
Lead Temperature Range
(Soldering 10 sec)
12.6 V
1.3 Watts
0.75 Watts
0.5 Watts
VS 1 V
3.5 V
Observe Power Derating Curves
–65°C to +125°C
While the AD8005 is internally short circuit protected, this is
not sufficient to guarantee that the maximum junction temper-
ature (+150°C) is not exceeded under all conditions. To ensure
proper operation, it is necessary to observe the maximum
power derating curves shown in Figure 5.
+300°C
1 See Table 4.
2.0
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
T
= 150°C
J
8-LEAD PDIP PACKAGE
1.5
1.0
0.5
0
8-LEAD SOIC_N PACKAGES
THERMAL RESISTANCE
5-LEAD SOT-23 PACKAGE
θJA is specified for device in free air.
Table 4. Thermal Resistance
Package Type
θJA
90
155
240
Unit
°C/W
°C/W
°C/W
–50 –40 –30 –20 –10
0
10 20 30 40 50 60 70 80 90
8-Lead PDIP Package
8-Lead SOIC_N Package
5-Lead SOT-23 Package
AMBIENT TEMPERATURE (°C)
Figure 5. Maximum Power Dissipation vs. Temperature
ESD CAUTION
Rev. B | Page 5 of 16
AD8005
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
5
5
4
V
V
R
= ±5V
V
V
= ±5V
S
S
= 200mV p-p
= 200mV p-p
4
3
OUT
OUT
= 1kΩ
R = 1kΩ
G = +1
L
L
3
2
2
1
1
G = –1
R = 1.5kΩ
F
0
0
G = +2
–1
–2
–3
–4
–5
–1
–2
–3
–4
–5
G = –10
= 1kΩ
G = +10
= 499Ω
R
F
R
F
1
10
FREQUENCY (MHz)
100
500
1
10
FREQUENCY (MHz)
100
500
Figure 6. Frequency Response; G = +1, +2, +10; VS = 5 V
Figure 9. Frequency Response; G = −1, −10; VS = 5 V
6.2
140
120
100
80
0
G = +2
= 200mV p-p
V
6.1
6.0
5.9
5.8
5.7
5.6
5.5
5.4
5.3
5.2
OUT
R
= 1kΩ
–40
L
PHASE
–80
–120
–160
–200
–240
–280
60
GAIN
40
20
0
0.1
1
10
100
500
1k
10k
100k
1M
10M
100M
1G
FREQUENCY (MHz)
FREQUENCY (Hz)
Figure 7. Gain Flatness; G = +2; VS = 5 V or +5 V
Figure 10. Transimpedance Gain and Phase vs. Frequency
7
6
10
9
8
7
6
5
4
3
2
1
0
V
= ±5V
S
G = +2
R
= 1kΩ
L
5
V
V
= ±5V
S
4
= 2V p-p
OUT
3
V
V
= ±5V
2
S
= 4V p-p
OUT
1
0
–1
–2
1
10
FREQUENCY (MHz)
100
500
0.5
1
10
100
FREQUENCY (MHz)
Figure 8. Large Signal Frequency Response; G = +2, RL = 1 kΩ
Figure 11. Output Swing vs. Frequency; VS = 5 V
Rev. B | Page 6 of 16
Data Sheet
AD8005
–40
–40
–50
–60
–70
–80
–90
–100
G = +2
G = +2
V = 2V p-p
OUT
V
= 2V p-p
OUT
R
= 1kΩ
R = 1kΩ
THIRD HARMONIC
L
L
–50
–60
THIRD HARMONIC
–70
SECOND HARMONIC
SECOND HARMONIC
–80
–90
–100
1
10
20
1
10
20
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 12. Distortion vs. Frequency; VS = 5 V
Figure 15. Distortion vs. Frequency VS = +5 V
MIN = –0.06 MAX = 0.03 p-p/MAX = 0.09
= ±5V
MIN = –0.08 MAX = 0.04 p-p/MAX = 0.12
0.10
0.05
0
0.10
0.05
0
V
V
= +5V
S
S
G = +2
= 1kΩ
G = +2
R
R = 1kΩ TO +1.5V
L
L
–0.05
–0.10
–0.05
–0.10
1.0
MIN = –0.01 MAX = 0.39 p-p = 0.40
MIN = 0.00 MAX = 0.70 p-p = 0.70
0.06
0.04
0.02
0
0.5
0
–0.02
–0.04
–0.06
V
= ±5V
V = +5V
S
G = +2
S
–0.5
–1.0
G = +2
= 1kΩ
R
R
= 1kΩ TO +1.5V
L
L
ST
ND
RD
TH
TH
TH
TH
TH
TH
TH
TH
ST
ND
RD
TH
TH
TH
TH
TH
TH
TH
TH
11
1
2
3
4
5
6
7
8
9
10
11
1
2
3
4
5
6
7
8
9
10
MODULATING RAMP LEVEL (IRE)
MODULATING RAMP LEVEL (IRE)
Figure 13. Differential Gain and Phase, VS = 5 V
Figure 16. Differential Gain and Phase, VS = +5 V
9
8
7
6
5
4
3
2
1
9
8
7
6
5
4
3
2
1
f = 5MHz
G = +2
R
= 1kΩ
V
= ±5V
L
S
V
= +5V
S
0
3
0
10
4
5
6
7
8
9
10
11
100
1k
10k
TOTAL SUPPLY VOLTAGES (V)
LOAD RESISTANCE (Ω)
Figure 17. Output Swing vs. Supply
Figure 14. Output Voltage Swing vs. Load
Rev. B | Page 7 of 16
AD8005
Data Sheet
–5
V
12.5
10.0
7.5
5.0
2.5
0
= +5V OR ±5V
S
G = +2
–10
–15
–20
–25
–30
–35
–40
–45
–50
–55
R
= 1kΩ
L
10
100
1k
10k
100k
1M
10M
0.03
0.1
1
10
100
FREQUENCY (Hz)
FREQUENCY (MHz)
Figure 18. CMRR vs. Frequency; VS = +5 V or 5 V
Figure 21. Noise vs. Frequency; VS = +5 V or 5 V
62.5
50.0
37.5
25.0
12.5
0
V
= +5V OR ±5V
S
G = +2
R
= 1kΩ
L
100
10
1
V
= +5V
S
INVERTING CURRENT
V
= ±5V
S
NONINVERTING CURRENT
0.03
0.1
1
10
100
500
10
100
1k
10k
100k
1M
10M
FREQUENCY (MHz)
FREQUENCY (Hz)
Figure 19. Output Resistance vs. Frequency; VS = 5 V and +5 V
Figure 22. Noise vs. Frequency; VS = +5 V or 5 V
10
V
= +5V OR ±5V
S
–PSRR
G = +2
0
–10
–20
–30
–40
–50
–60
–70
–80
R
= 1kΩ
L
V
OUT
100
90
V
IN
+PSRR
V
= ±5V
S
G = +6
R
= 1kΩ
L
10
0%
1V
2V
150ns
0.03
0.1
1
10
100
500
FREQUENCY (MHz)
Figure 23. Overdrive Recovery, VS = 5 V, VIN = 2 V Step
Figure 20. PSRR vs. Frequency; VS = +5 V or 5 V
Rev. B | Page 8 of 16
Data Sheet
AD8005
R
1.5kΩ
51.1Ω
1.5kΩ
R
G
F
V
V
OUT
V
IN
OUT
R
1kΩ
L
R
1kΩ
L
C
PROBE
C
PROBE
V
IN
+V
+V
–V
S
S
S
50Ω
0.01µF
0.01µF
10µF
10µF
0.01µF
0.01µF
10µF
10µF
–V
S
PROBE: TEK P6137
= 10pF NOMINAL
PROBE: TEK P6137
= 10pF NOMINAL
C
LOAD
C
LOAD
Figure 24. Test Circuit; G = +2; RF = RG = 3.01 kΩ for N-8 Package;
RF = RG = 2.49 kΩ for R-8 and RJ-5 Packages
Figure 27. Test Circuit; G = –1, RF = RG = 1.5 kΩ for N-8, R-8, and RJ-5
Packages
100
90
100
90
10
10
0%
0%
50mV
10ns
50mV
10ns
Figure 25. 200 mV Step Response; G = +2, VS = 2.5 V or 5 V
Figure 28. 200 mV Step Response; G = –1, VS = 2.5 V or 5 V
100
90
100
90
10
10
0%
0%
1V
10ns
1V
10ns
Figure 26. Step Response; G = +2, VS = 5 V
Figure 29. Step Response; G = −1, VS = 5 V
Rev. B | Page 9 of 16
AD8005
Data Sheet
APPLICATIONS
R2
1.5kΩ
DRIVING CAPACITIVE LOADS
5V
Capacitive loads interact with the output impedance of an op
amp to create an extra delay in the feedback path. This reduces
circuit stability and can cause unwanted ringing and oscillation.
A given value of capacitance causes much less ringing when the
amplifier is used with a higher noise gain.
R1
1.5kΩ
0.01µF
10µF
V
IN
AD8005
V
OUT
V
REF
5V
The capacitive load drive of the AD8005 can be increased by
adding a low valued resistor in series with the capacitive load.
Introducing a series resistor tends to isolate the capacitive load
from the feedback loop, thereby diminishing its influence.
Figure 31 shows the effects of a series resistor on capacitive drive
for varying voltage gains. As the closed-loop gain is increased,
the larger phase margin allows for larger capacitive loads with
less overshoot. Adding a series resistor at lower closed-loop
gains accomplishes the same effect. For large capacitive loads,
the frequency response of the amplifier is dominated by the
roll-off of the series resistor and capacitive load.
R3
R4
30.1kΩ
10kΩ
0.1µF
Figure 32. Bipolar to Unipolar Shift Lever
Figure 32 shows a level shifter circuit that can move a bipolar
signal into a unipolar range. A positive reference voltage, derived
from the +5 V supply, sets a bias level of +1.25 V at the nonin-
verting terminal of the op amp. In ac applications, the accuracy
of this voltage level is not important; however, noise is a serious
consideration. A 0.1 mF capacitor provides useful decoupling of
this noise.
R
F
The bias level on the noninverting terminal sets the input common-
mode voltage to +1.25 V. Because the output is always positive,
the op amp can be powered with a single +5 V power supply.
R
S
R
G
AD8005
R
L
C
L
1kΩ
The overall gain function is given by the equation:
R2
R1
R4
R3 + R4
R2
R1
Figure 30. Driving Capacitive Loads
VOUT = −
V
+
1+
V
REF
IN
80
70
60
50
40
30
20
10
0
V
= ±5V
2V OUTPUT STEP
WITH 30% OVERSHOOT
S
In the above example, the equation simplifies to
VOUT = −VIN + 2.5 V
R
= 10Ω
SINGLE-ENDED-TO-DIFFERENTIAL CONVERSION
S
Many single supply ADCs have differential inputs. In such
cases, the ideal common-mode operating point is usually
halfway between supply and ground. Figure 33 shows how to
convert a single-ended bipolar signal into a differential signal
with a common-mode level of 2.5 V.
R
= 5Ω
= 0Ω
S
R
S
+5V
+5V
2.49kΩ
0.1µF
R
1kΩ
IN
0.1µF
BIPOLAR
SIGNAL
±0.5V
1
2
3
4
5
CLOSED-LOOP GAIN (V/V)
AD8005
2.49kΩ
Figure 31. Capacitive Load Drive vs. Closed-Loop Gain
R
F1
2.49kΩ
SINGLE-SUPPLY LEVEL SHIFTER
R
619Ω
G
R
F1
V
In addition to providing buffering, many systems require that an
op amp provide level shifting. A common example is the level
shifting required to move a bipolar signal into the unipolar range
of many modern analog-to-digital converters (ADCs). In general,
single supply ADCs have input ranges that are referenced neither
to ground nor supply. Instead the reference level is some point
in between, usually halfway between ground and supply (+2.5 V
for a single supply 5 V ADC). Because high-speed ADCs typically
have input voltage ranges of 1 V to 2 V, the op amp driving it
must be single supply but not necessarily rail-to-rail.
OUT
3.09kΩ
+5V
0.1µF
+5V
AD8005
2.49kΩ
2.49kΩ
0.1µF
Figure 33. Single-Ended-to-Differential Converter
Rev. B | Page 10 of 16
Data Sheet
AD8005
Amp 1 has its +input driven with the ac-coupled input signal
while the +input of Amp 2 is connected to a bias level of +2.5 V.
Thus the −input of Amp 2 is driven to virtual +2.5 V by its output.
Therefore, Amp 1 is configured for a noninverting gain of five,
(1 + RF1/RG), because RG is connected to the virtual +2.5 V of
the –input of Amp 2.
one end of the capacitor is within 1/8 inch of each power pin
with the other end connected to the ground plane. An additional
large (0.47 µF − 10 µF) tantalum electrolytic capacitor must also
be connected in parallel. This capacitor supplies current for fast,
large signal changes at the output. It must not necessarily be as
close to the power pin as the smaller capacitor.
When the +input of Amp 1 is driven with a signal, the same
signal appears at the −input of Amp 1. This signal serves as an
input to Amp 2 configured for a gain of −5, (−RF2/RG). Thus the
two outputs move in opposite directions with the same gain and
create a balanced differential signal.
Locate the feedback resistor close to the inverting input pin in
order to keep the stray capacitance at this node to a minimum.
Capacitance variations of less than 1.5 pF at the inverting input
significantly affect high-speed performance.
Use stripline design techniques for long signal traces (that is,
greater than about 1 inch). Striplines must have a characteristic
impedance of either 50 Ω or 75 Ω. For the stripline to be effective,
correct termination at both ends of the line is necessary.
This circuit can be simplified to create a bipolar in/bipolar out
single-ended to differential converter. Obviously, a single supply
is no longer adequate and the −VS pins must now be powered
with −5 V. The +input to Amp 2 is tied to ground. The ac coupling
on the +input of Amp 1 is removed and the signal can be fed
directly into Amp 1.
Table 5. Typical Bandwidth vs. Gain Setting Resistors
Small Signal −3 dB BW
(MHz), VS = 5 V
Gain RF
RG
RT
LAYOUT CONSIDERATIONS
−1
1.49 kΩ 1.49 kΩ 52.3
120 MHz
−10
+1
+2
1 kΩ
2.49 kΩ
2.49 kΩ 2.49 kΩ 49.9 Ω
499 Ω 56.2 Ω 49.9 Ω
100 Ω
∞
100 Ω
49.9 Ω
60 MHz
270 MHz
170 MHz
40 MHz
In order to achieve the specified high-speed performance of the
AD8005, the user must be attentive to board layout and component
selection. Proper RF design techniques and selection of components
with low parasitics are necessary.
+10
INCREASING FEEDBACK RESISTORS
The printed circuit board (PCB) must have a ground plane that
covers all unused portions of the component side of the board.
This provides a low impedance path for signals flowing to ground.
Remove the ground plane from the area under and around the
chip (leave about 2 mm between the pin contacts and the
ground plane). This helps to reduce stray capacitance. If both
signal tracks and the ground plane are on the same side of the
PCB, also leave a 2 mm gap between ground plane and track.
Unlike conventional voltage feedback op amps, the choice of
feedback resistor has a direct impact on the closed-loop bandwidth
and stability of a current feedback op amp circuit. Reducing the
resistance below the recommended value makes the amplifier
more unstable. Increasing the size of the feedback resistor
reduces the closed-loop bandwidth.
360µA (rms)
R
R
R
G
F
O
562Ω
4.99kΩ
V
V
OUT
IN
R
T
+5V
+V
S
S
C3
C1
10µF
0.01µF
V
OUT
AD8005
2V (rms)
V
C2
0.01µF
C4
10µF
IN
0.2V (rms)
QUIESCENT CURRENT
475µA (MAX)
–V
INVERTING CONFIGURATION
–5V
Figure 35. Saving Power by Increasing Feedback Resistor Network
R
R
R
R
O
G
F
V
OUT
In power-critical applications where some bandwidth can be
sacrificed, increasing the size of the feedback resistor yields
significant power savings. A good example of this is the gain of
+10 case. Operating from a bipolar supply ( 5 V), the quiescent
current is 475 µA (excluding the feedback network). The recom-
mended feedback and gain resistors are 499 Ω and 56.2 Ω
respectively. In order to drive an rms output voltage of 2 V, t h e
output must deliver a current of 3.6 mA to the feedback network.
Increasing the size of the resistor network by a factor of 10, as
shown in Figure 35, reduces this current to 360 µA; however,
the closed loop bandwidth decreases to 20 MHz.
V
IN
+V
S
S
C3
C1
T
10µF
0.01µF
C2
C4
10µF
0.01µF
–V
NONINVERTING CONFIGURATION
Figure 34. Inverting and Nonconverting Configurations
Chip capacitors have low parasitic resistance and inductance and
are suitable for supply bypassing (see Figure 34). Make sure that
Rev. B | Page 11 of 16
AD8005
Data Sheet
OUTLINE DIMENSIONS
0.400 (10.16)
0.365 (9.27)
0.355 (9.02)
8
1
5
4
0.280 (7.11)
0.250 (6.35)
0.240 (6.10)
0.325 (8.26)
0.310 (7.87)
0.300 (7.62)
0.100 (2.54)
BSC
0.060 (1.52)
MAX
0.195 (4.95)
0.130 (3.30)
0.115 (2.92)
0.210 (5.33)
MAX
0.015
(0.38)
MIN
0.150 (3.81)
0.130 (3.30)
0.115 (2.92)
0.015 (0.38)
GAUGE
0.014 (0.36)
0.010 (0.25)
0.008 (0.20)
PLANE
SEATING
PLANE
0.022 (0.56)
0.018 (0.46)
0.014 (0.36)
0.430 (10.92)
MAX
0.005 (0.13)
MIN
0.070 (1.78)
0.060 (1.52)
0.045 (1.14)
COMPLIANT TO JEDEC STANDARDS MS-001
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.
Figure 36. 8-Lead Plastic Dual In-Line Package [PDIP]
Narrow Body
(N-8)
Dimensions shown in inches and (millimeters)
5.00 (0.1968)
4.80 (0.1890)
8
1
5
4
6.20 (0.2441)
5.80 (0.2284)
4.00 (0.1574)
3.80 (0.1497)
0.50 (0.0196)
0.25 (0.0099)
1.27 (0.0500)
BSC
45°
1.75 (0.0688)
1.35 (0.0532)
0.25 (0.0098)
0.10 (0.0040)
8°
0°
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
1.27 (0.0500)
0.40 (0.0157)
0.25 (0.0098)
0.17 (0.0067)
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MS-012-AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 37. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-8)
Dimensions shown in millimeters and (inches)
Rev. B | Page 12 of 16
Data Sheet
AD8005
3.00
2.90
2.80
5
1
4
3
3.00
2.80
2.60
1.70
1.60
1.50
2
0.95 BSC
1.90
BSC
1.30
1.15
0.90
0.20 MAX
0.08 MIN
1.45 MAX
0.95 MIN
0.55
0.45
0.35
0.15 MAX
0.05 MIN
10°
5°
0°
SEATING
PLANE
0.60
BSC
0.50 MAX
0.35 MIN
COMPLIANT TO JEDEC STANDARDS MO-178-AA
Figure 38. 5-Lead Small Outline Transistor Package [SOT-23]
(RJ-5)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
AD8005ANZ
Temperature Range
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
Package Description
Package Option
Branding Code
8-Lead Plastic Dual In-Line Package [PDIP]
N-8
AD8005ARZ
8-Lead Standard Small Outline Package [SOIC_N] R-8
8-Lead Standard Small Outline Package [SOIC_N] R-8
8-Lead Standard Small Outline Package [SOIC_N] R-8
5-Lead Small Outline Transistor Package [SOT-23] RJ-5
5-Lead Small Outline Transistor Package [SOT-23] RJ-5
Evaluation Board
AD8005ARZ-REEL
AD8005ARZ-REEL7
AD8005ARTZ-R2
AD8005ARTZ-REEL7
AD8005AR-EBZ
AD8005ART-EBZ
H05
H05
Evaluation Board
1 Z = RoHS Compliant Part.
Rev. B | Page 13 of 16
AD8005
NOTES
Data Sheet
Rev. B | Page 14 of 16
Data Sheet
NOTES
AD8005
Rev. B | Page 15 of 16
AD8005
NOTES
Data Sheet
©1996–2014 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D12146-0-3/14(B)
Rev. B | Page 16 of 16
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