AD8230_16 [ADI]
16 V Rail-to-Rail, Zero-Drift, Precision Instrumentation Amplifier;
| 型号： | AD8230_16 |
| 厂家： | 
ADI |
| 描述： | 16 V Rail-to-Rail, Zero-Drift, Precision Instrumentation Amplifier |
| 文件： | 总17页 (文件大小：400K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
16 V Rail-to-Rail, Zero-Drift,
Precision Instrumentation Amplifier
AD8230
CONNECTION DIAGRAM
FEATURES
Resistor programmable gain range: 101 to 1000
Supply voltage range: 4 V to 8 V
Rail-to-rail input and output
Maintains performance over −40°C to +125°C
Excellent ac and dc performance
1
2
3
4
8
7
6
5
–V
+V
V
OUT
S
R
G
S
1
V
V
2
REF
REF
+IN
–IN
AD8230
TOP VIEW
110 dB minimum CMR @ 60 Hz, G = 10 to 1000
10 μV maximum offset voltage (RTI, 5 V operation)
50 nV/°C maximum offset drift
(Not to Scale)
Figure 1. 8-Lead SOIC (R-8)
2.0
1.5
20 ppm maximum gain nonlinearity
APPLICATIONS
1.0
Pressure measurements
Temperature measurements
Strain measurements
0.5
0
Automotive diagnostics
–0.5
–1.0
–1.5
–2.0
GENERAL DESCRIPTION
The AD8230 is a low drift, differential sampling, precision
instrumentation amplifier. Auto-zeroing reduces offset voltage
drift to less than 50 nV/°C. The AD8230 is well-suited for
thermocouple and bridge transducer applications. The
AD8230’s high CMR of 110 dB (minimum) rejects line noise in
measurements where the sensor is far from the instrumentation.
The 16 V rail-to-rail, common-mode input range is useful for
noisy environments where ground potentials vary by several
volts. Low frequency noise is kept to a minimal 3 μV p-p,
making the AD8230 perfect for applications requiring the
utmost dc precision. Moreover, the AD8230 maintains its high
performance over the extended industrial temperature range of
−40°C to +125°C.
–50 –30 –10
10
30
50
70
90
110 130 150
TEMPERATURE (°C)
Figure 2. Relative Offset Voltage vs. Temperature
+5V
–5V
0.1µF
0.1µF
2
4
5
1
V
8
TYPE K THERMOCOUPLE
AD8230
OUT
7
6
34.8kΩ
284Ω
3
Two external resistors are used to program the gain. By using
matched external resistors, the gain stability of the AD8230 is
much higher than instrumentation amplifiers that use a single
resistor to set the gain. In addition to allowing users to program
the gain between 101 and 1000, users can adjust the output
offset voltage.
Figure 3. Thermocouple Measurement
The AD8230 is versatile yet simple to use. Its auto-zeroing
topology significantly minimizes the input and output
transients typical of commutating or chopper instrumentation
amplifiers. The AD8230 operates on 4 V to 8 V (+8 V to +16 V)
supplies and is available in an 8-lead SOIC.
1 The AD8230 can be programmed for a gain as low as 2, but the maximum
input voltage is limited to approximately 750 mV.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2004–2007 Analog Devices, Inc. All rights reserved.
AD8230* Product Page Quick Links
Last Content Update: 11/01/2016
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Documentation
Application Notes
• AN-282: Fundamentals of Sampled Data Systems
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Data Sheet
• AD8230: 16 V Rail-to-Rail, Zero-Drift, Precision
Instrumentation Amplifier Data Sheet
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Technical Books
• A Designer's Guide to Instrumentation Amplifiers, 3rd
Edition, 2006
Technical Support
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number
Reference Materials
Technical Articles
• Auto-Zero Amplifiers
• High-performance Adder Uses Instrumentation Amplifiers
• Input Filter Prevents Instrumentation-amp RF-Rectification
Errors
• The AD8221 - Setting a New Industry Standard for
Instrumentation Amplifiers
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the content on this page does not constitute a change to the revision number of the product data sheet. This content may be
frequently modified.
AD8230
TABLE OF CONTENTS
Features .............................................................................................. 1
Level-Shifting the Output ......................................................... 12
Source Impedance and Input Settling Time ........................... 12
Input Voltage Range................................................................... 13
Input Protection ......................................................................... 13
Power Supply Bypassing............................................................ 13
Power Supply Bypassing for Multiple Channel Systems ....... 13
Layout .......................................................................................... 14
Applications ................................................................................ 14
Outline Dimensions....................................................................... 15
Ordering Guide .......................................................................... 15
Applications....................................................................................... 1
General Description......................................................................... 1
Connection Diagram ....................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 5
Thermal Characteristics .............................................................. 5
ESD Caution.................................................................................. 5
Typical Performance Characteristics ............................................. 6
Theory of Operation ...................................................................... 11
Setting the Gain .......................................................................... 11
REVISION HISTORY
9/07—Rev. A to Rev. B
7/05—Rev. 0 to Rev. A
Changes to Features and Layout..................................................... 1
Changes to Table 1............................................................................ 3
Changes to Table 2............................................................................ 4
Changes to Layout ............................................................................ 5
Inserted Figure 13, Figure 14, and Figure 15; Renumbered
Sequentially ....................................................................................... 7
Changes to Figure 16 and Figure 19............................................... 8
Updated Outline Dimensions....................................................... 15
Changes to Excellent AC and DC Performance............................1
Changes to Table 1.............................................................................3
Changes to Table 2.............................................................................4
Changes to Figure 7 and Figure 8....................................................6
Changes to Figure 10 and Figure 11................................................7
Changes to Level-Shifting the Output Section........................... 11
Changes to Figure 31...................................................................... 11
Inserted Figure 32 and Figure 33; Renumbered Sequentially .. 11
Changes to Source Impedance and Input Settling Time Section,
Input Protection Section and Power Supply Bypassing for
Multiple Channel Systems Section............................................... 12
Changes to Figure 36...................................................................... 13
Changes to Applications Section.................................................. 13
10/04—Revision 0: Initial Version
Rev. B | Page 2 of 16
AD8230
SPECIFICATIONS
VS = 5 V, VREF = 0 V, RF = 100 kΩ, RG = 1 kΩ (@ TA = 25°C, G = 202, RL = 10 kΩ, unless otherwise noted).
Table 1.
Parameter
Conditions
Min
Typ
Max
Unit
VOLTAGE OFFSET
RTI Offset, VOSI
Offset Drift
V+IN = V−IN = 0 V
V+IN = V−IN = 0 V,
10
50
μV
nV/°C
TA = −40°C to +125°C
COMMON-MODE REJECTION (CMR)
CMR to 60 Hz with 1 kΩ Source Imbalance
VOLTAGE OFFSET RTI vs. SUPPLY (PSR)
G = 2
VCM = −5 V to +5 V
G = 2(1 + RF/RG)
110
120
dB
120
120
120
140
dB
dB
G = 202
GAIN
Gain Range
Gain Error2
101
1000
V/V
G = 2
G = 10
G = 100
G = 1000
Gain Nonlinearity
Gain Drift
0.01
0.01
0.01
0.02
0.04
0.04
0.04
0.05
20
%
%
%
%
ppm
G = 2, 10, 102
G = 1002
14
60
ppm/°C
ppm/°C
INPUT
Input Common-Mode Operating Voltage Range
Over Temperature
Input Differential Operating Voltage Range
Average Input Offset Current3
Average Input Bias Current3
OUTPUT
−VS
−VS
+VS
+VS
V
V
mV
pA
nA
T = −40°C to +125°C
750
33
0.15
VCM = 0 V
VCM = 0 V
300
1
Output Swing
−VS + 0.1
−VS + 0.1
+VS − 0.2
+VS − 0.2
V
V
mA
Over Temperature
Short-Circuit Current
REFERENCE INPUT
Voltage Range4
T = −40°C to +125°C
15
−VS + 3.5
+VS − 2.5
V
NOISE
Voltage Noise Density, 1 kHz, RTI
Voltage Noise
VIN+, VIN−, VREF = 0 V
f = 0.1 Hz to 10 Hz
VIN = 500 mV, G = 10
240
3
nV/√Hz
μV p-p
V/μs
SLEW RATE
2
INTERNAL SAMPLE RATE
POWER SUPPLY
6
kHz
Operating Range (Dual Supplies)
Operating Range (Single Supply)
Quiescent Current
TEMPERATURE RANGE
Specified Performance
4
8
8
16
3.5
V
V
mA
T = −40°C to +125°C
2.7
−40
+125
°C
1 The AD8230 can operate as low as G = 2. However, since the differential input range is limited to approximately 750 mV, the AD8230 configured at G < 10 does not
make use of the full output voltage range.
2 Gain drift is determined by the TC match of the external gain setting resistors.
3 Differential source resistance less than 10 kΩ does not result in voltage offset due to input bias current or mismatched series resistors.
4 For G < 10, the reference voltage range is limited to −VS + 4.24 V to +VS – 2.75 V.
Rev. B | Page 3 of 16
AD8230
VS = 8 V, VREF = 0 V, RF = 100 kΩ, RG = 1 kΩ (@ TA = 25°C, G = 202, RL = 10 kΩ, unless otherwise noted).
Table 2.
Parameter
Conditions
Min
Typ
Max
Unit
VOLTAGE OFFSET
RTI Offset, VOSI
Offset Drift
V+IN = V−IN = 0 V
V+IN = V−IN = 0 V,
20
50
μV
nV/°C
T = −40°C to +125°C
COMMON-MODE REJECTION (CMR)
CMR to 60 Hz with 1 kΩ Source Imbalance
VOLTAGE OFFSET RTI vs. SUPPLY (PSR)
G = 2
VCM = −8 V to +8 V
G = 2(1 + RF/RG)
110
120
dB
120
120
120
140
dB
dB
G = 202
GAIN
Gain Range
Gain Error2
101
1000
V/V
G = 2
G = 10
G = 100
G = 1000
Gain Nonlinearity
Gain Drift
0.01
0.01
0.01
0.02
0.04
0.04
0.04
0.05
20
%
%
%
%
ppm
G = 2, 10, 102
G=1002
14
60
ppm/°C
ppm/°C
INPUT
Input Common-Mode Operating Voltage Range
Over Temperature
Input Differential Operating Voltage Range
Average Input Offset Current3
Average Input Bias Current3
OUTPUT
−VS
−VS
+VS
+VS
V
V
mV
pA
nA
T = −40°C to +125°C
750
33
0.15
VCM = 0 V
VCM = 0 V
300
1
Output Swing
−VS + 0.1
−VS + 0.1
+VS − 0.2
+VS − 0.4
V
V
mA
Over Temperature
Short-Circuit Current
REFERENCE INPUT
Voltage Range4
T = −40°C to +125°C
15
−VS + 3.5
+VS − 2.5
V
NOISE
Voltage Noise Density, 1 kHz, RTI
Voltage Noise
VIN+, VIN−, VREF = 0 V
f = 0.1 Hz to 10 Hz
VIN = 500 mV, G = 10
240
3
nV/√Hz
μV p-p
V/μs
SLEW RATE
2
INTERNAL SAMPLE RATE
POWER SUPPLY
6
kHz
Operating Range (Dual Supplies)
Operating Range (Single Supply)
Quiescent Current
TEMPERATURE RANGE
Specified Performance
4
8
8
16
4
V
V
mA
T = −40°C to +125°C
3.2
−40
+125
°C
1 The AD8230 can operate as low as G = 2. However, since the differential input range is limited to approximately 750 mV, the AD8230 configured at G < 10 does not
make use of the full output voltage range.
2 Gain drift is determined by the TC match of the external gain setting resistors.
3 Differential source resistance less than 10 kΩ does not result in voltage offset due to input bias current or mismatched series resistors.
4 For G < 10, the reference voltage range is limited to −VS + 4.24 V to +VS − 2.75V.
Rev. B | Page 4 of 16
AD8230
ABSOLUTE MAXIMUM RATINGS
THERMAL CHARACTERISTICS
Table 3.
Specification is for device in free air SOIC.
Parameter
Rating
Supply Voltage
8 V, +16 V
304 mW
20 mA
VS
VS
Table 4.
Parameter
Internal Power Dissipation
Output Short-Circuit Current
Input Voltage (Common-Mode)
Differential Input Voltage
Storage Temperature Range
Operational Temperature Range
Value
121
Unit
θJA (4-Layer JEDEC Board)
°C/W
−65°C to +150°C
−40°C to +125°C
ESD CAUTION
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rev. B | Page 5 of 16
AD8230
TYPICAL PERFORMANCE CHARACTERISTICS
20
15
TOTAL NUMBER OF
SAMPLES = 2839 FROM 3 LOTS
NORMALIZED FOR V
= 0V
CM
500
400
300
200
100
0
10
5
0
–5
–10
–15
–20
–9
–6
–3
0
3
6
9
–6
–4
–2
0
2
4
6
OFFSET VOLTAGE (µV RTI)
COMMON-MODE VOLTAGE (V)
Figure 4. Offset Voltage (RTI) Distribution at 5 V, CM = 0 V, TA = 25°C
Figure 7. Offset Voltage (RTI) vs. Common-Mode Voltage, VS = 5 V
40
20
TOTAL NUMBER OF SAMPLES = 300 FROM 3 LOTS
NORMALIZED FOR V
= 0V
CM
35
30
25
20
15
10
5
15
10
5
0
–5
–10
–15
–20
0
–50
–30
–10
10
30
50
–10
–8
–6
–4
–2
0
2
4
6
8
10
OFFSET VOLTAGE DRIFT (nV/°C)
COMMON-MODE VOLTAGE (V)
Figure 5. Offset Voltage (RTI) Drift Distribution
Figure 8. Offset Voltage (RTI) vs. Common-Mode Voltage, VS = 8 V
0
0
–1
–2
–3
–4
–2
–4
V
= ±5V
S
–6
–8
–10
–12
–14
–16
–18
–20
V
= ±8V
S
–5
±5V SUPPLY
–6
–7
±8V SUPPLY
–8
–50 –30 –10
10
30
50
70
90
110 130 150
0
1
2
3
4
5
6
TEMPERATURE (°C)
SOURCE IMPEDANCE (kΩ)
Figure 6. Offset Voltage (RTI) vs. Temperature
Figure 9. Offset Voltage (RTI) vs. Source Impedance, 1 μF Across Input Pins
Rev. B | Page 6 of 16
AD8230
40
30
10
8
–856mV, +8.2V
0V, +8.4V
= ±8V
+592mV, +8.2V
NORMALIZED FOR V
= 0V
REF
V
S
6
20
–812mV, +5V
+644mV, +5V
4
0V, +5.5V
10
2
V
= ±5V
S
0
0
–2
–4
–6
–8
–10
–10
–20
–30
–40
–652mV, –5V
+800mV, –5V
0V, –5.5V
0V, –8.4V
–616mV, –8.2V
+840mV, –8.2V
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
–1000 –800 –600 –400 –200
0
200 400 600 800 1000
V
(V)
OUTPUT VOLTAGE (mV)
REF
Figure 13. Input Common-Mode Voltage Range vs. Output Voltage, G = 2
Figure 10. Offset Voltage (RTI) vs. Reference Voltage
10
130
120
110
100
90
V
= ±8V
S
–7.9V, +8V
+7.9V, +8V
CMR WITH NO SOURCE IMBALANCE
8
6
–4.9V, +5V
+4.88V, +5V
4
V
= ±5V
S
2
0
80
–2
–4
–6
–8
–10
70
CMR WITH 1kΩ SOURCE IMBALANCE
60
–4.9V, –5V
+4.88V, –5V
50
–7.9V, –8V
–10 –8 –6
+7.9V, –8V
40
–4
–2
0
2
4
6
8
10
10
100
1k
10k
OUTPUT VOLTAGE (V)
FREQUENCY (Hz)
Figure 14. Input Common-Mode Voltage Range vs. Output Voltage, G = 10
Figure 11. Common-Mode Rejection (CMR) vs. Frequency
130
10
–7.9V, +8V
+7.9V, +8V
128
126
124
122
120
118
116
114
112
110
8
6
V
= ±8V
S
–4.8V, +5.5V
+4.8V, +5.5V
4
2
V
= ±5V
S
±5V SUPPLY
0
–2
–4
–6
–8
–10
±8V SUPPLY
–4.8V, –5.5V
+4.8V, –5.5V
–7.9V, –8V
–10 –8 –6
+7.9V, –8V
8 10
–4
–2
0
2
4
6
0
2
4
6
8
10
12
OUTPUT VOLTAGE (V)
SOURCE IMPEDANCE (kΩ)
Figure 15. Input Common-Mode Voltage Range vs. Output Voltage, G = 100
Figure 12. Common-Mode Rejection (CMR) vs.
Source Impedance, 1.1 μF Across Input Pins
Rev. B | Page 7 of 16
AD8230
90
80
70
60
50
40
30
20
10
0
6.8
6.6
6.4
6.2
6.0
5.8
5.6
±8V
±5V
–10
5.4
–50
–30
–10
10
30
50
70
90
110
130
10
100
1k
10k
100k
TEMPERATURE (°C)
FREQUENCY (Hz)
Figure 16. Clock Frequency vs. Temperature
Figure 19. Gain vs. Frequency, G = 2
1.0
0.8
0.6
0.4
0.2
0
90
80
70
60
50
40
30
20
10
0
+85°C
+125°C
–40°C
–0.2
–0.4
0°C
–0.6
–0.8
–1.0
+25°C
–10
–6
–4
–2
0
2
4
6
10
100
1k
10k
100k
COMMON-MODE VOLTAGE (V)
FREQUENCY (Hz)
Figure 17. Average Input Bias Current vs. Common-Mode Voltage,
−40°C, +25°C, +85°C, +125°C
Figure 20. Gain vs. Frequency, G = 10
3.5
3.4
40
30
G = +20
±8V
3.3
20
3.2
3.1
10
0
3.0
±5V
2.9
–10
–20
–30
–40
2.8
2.7
2.6
2.5
–5
–4
–3
–2
–1
0
1
2
3
4
5
–50
0
50
100
150
V
(V)
TEMPERATURE (°C)
OUT
Figure 18. Supply Current vs. Temperature
Figure 21. Gain Nonlinearity, G = 20
Rev. B | Page 8 of 16
AD8230
90
80
70
60
50
40
30
20
10
0
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0
–10
1
10
100
1k
10k
100k
10
100
1k
10k
100k
100k
20
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 22. Gain vs. Frequency, G = 100
Figure 25. Voltage Noise Spectral Density vs. Frequency
90
80
70
60
50
40
30
20
10
0
3.90
3.70
3.50
3.30
3.10
2.90
2.70
2.50
–10
10
100
1k
10k
2µV/DIV
–50 –30
1s/DIV
110 130
–10
10
30
50
70
90
FREQUENCY (Hz)
TEMPERATURE (°C)
Figure 23. Gain vs. Frequency, G = 1000
Figure 26. 0.1 Hz to 10 Hz RTI Voltage Noise, G = 100
0.010
0.008
0.006
0.004
0.002
0
160
140
120
100
80
G = +1000
G = +100
G = +10
G = +2
–0.002
–0.004
–0.006
–0.008
–0.010
60
40
20
0
0
5
10
15
0.1
1
10
SOURCE IMPEDANCE (kΩ)
FREQUENCY (kHz)
Figure 24. Gain Error vs. Differential Source Impedance
Figure 27. Positive PSR vs. Frequency, RTI
Rev. B | Page 9 of 16
AD8230
140
120
100
80
10
8
V
V
= ±8V
= ±5V
–40°C
S
S
G = +100
6
–40°C
+125°C
+25
°C
4
G = +1000
2
+125°C
+25°C
0
G = +10
60
+25
+25
°
C
C
–2
–4
–6
–8
–10
G = +2
+125°C
V
V
= ±5V
= ±8V
S
S
40
°
–40°C
+125
8
°C
20
–40°C
0
0.1
1
10
0
2
4
6
10
12
FREQUENCY (kHz)
OUTPUT CURRENT (mA)
Figure 28. Negative PSR vs. Frequency, RTI
Figure 29. Output Voltage Swing vs. Output Current,
−40°C, +25°C, +85°C, +125°C
Rev. B | Page 10 of 16
AD8230
THEORY OF OPERATION
Auto-zeroing is a dynamic offset and drift cancellation
technique that reduces input-referred voltage offset to the
μV level and voltage offset drift to the nV/°C level. A further
advantage of dynamic offset cancellation is the reduction of
low frequency noise, in particular the 1/f component.
In Phase B, the differential signal is transferred to the hold
capacitors refreshing the value stored on CHOLD. The output of
the preamplifier is held at a common-mode voltage determined
by the reference potential, VREF. In this manner, the AD8230 is
able to condition the difference signal and set the output voltage
level. The gain amplifier conditions the updated signal stored
The AD8230 is an instrumentation amplifier that uses an
auto-zeroing topology and combines it with high common-
mode signal rejection. The internal signal path consists of an
active differential sample-and-hold stage (preamp) followed by
a differential amplifier (gain amp). Both amplifiers implement
auto-zeroing to minimize offset and drift. A fully differential
topology increases the immunity of the signals to parasitic noise
and temperature effects. Amplifier gain is set by two external
resistors for convenient TC matching.
on the hold capacitors, CHOLD
.
SETTING THE GAIN
Two external resistors set the gain of the AD8230. The gain is
expressed in the following equation:
RF
RG
Gain = 2(1+
)
(1)
+V
S
–V
S
The signal sampling rate is controlled by an on-chip, 6 kHz
oscillator and logic to derive the required nonoverlapping
clock phases. For simplification of the functional description,
two sequential clock phases, A and B, are shown to distinguish
the order of internal operation, as depicted in Figure 30 and
Figure 31, respectively.
0.1µF
10µF
0.1µF
10µF
2
4
5
1
AD8230
V
8
F
R
OUT
G
V
2
7
REF
6
V
1
REF
3
R
G
GAIN AMP
PREAMP
R
–V
S
C
HOLD
V
+IN
–
+
V
OUT
V
DIFF
+V
C
SAMPLE
Figure 32. Gain Setting
CM
–
+
V
–IN
C
HOLD
Table 5. Gains Using Standard 1% Resistors
–V
S
Gain
RF
RG
Actual Gain
2
10
50
100
200
500
1000
0 Ω (short)
8.06 kΩ
12.1 kΩ
9.76 kΩ
10 kΩ
None
2 kΩ
2
10
V
R
G
R
REF
F
Figure 30. Phase A of the Sampling Phase
499 Ω
200 Ω
100 Ω
200 Ω
200 Ω
50.5
99.6
202
501
1002
During Phase A, the sampling capacitors are connected to the
inputs. The input signal’s difference voltage, VDIFF, is stored
across the sampling capacitors, CSAMPLE. Because the sampling
capacitors only retain the difference voltage, the common-mode
voltage is rejected. During this period, the gain amplifier is not
connected to the preamplifier so its output remains at the level
set by the previously sampled input signal held on CHOLD, as
shown in Figure 30.
49.9 kΩ
100 kΩ
Figure 32 and Table 5 provide an example of some gain settings.
As Table 5 shows, the AD8230 accepts a wide range of resistor
values. Because the instrumentation amplifier has finite driving
capability, ensure that the output load in parallel with the sum
of the gain setting resistors is greater than 2 kΩ.
GAIN AMP
PREAMP
–V
S
C
HOLD
RL||(RF + RG) > 2 kΩ
(2)
V
+IN
–
+
V
OUT
V
DIFF
+V
C
SAMPLE
Offset voltage drift at high temperature can be minimized by
CM
–
+
V
–IN
keeping the value of the feedback resistor, RF, small. This is due
to the junction leakage current on the RG pin, Pin 7. The effect
of the gain setting resistor on offset voltage drift is shown in
Figure 33. In addition, experience has shown that wire-wound
resistors in the gain feedback loop may degrade the offset
voltage performance.
C
HOLD
–V
S
V
R
R
REF
G
F
Figure 31. Phase B of the Sampling Phase
Rev. B | Page 11 of 16
AD8230
0
The following steps can be taken to set the gain and level-shift
the output:
–1
–2
–3
–4
1. Select an RF value. Table 5 shows RF values for various gains.
2. Solve for RO using Equation 4.
VR' ×RF
RO = −
(4)
VDESIRED
−LEVEL
R
= 100kΩ, R = 1kΩ
G
F
where:
VR’ is a voltage source, such as a supply voltage.
VDESIRED-LEVEL is the desired output bias voltage.
R
= 10kΩ, R = 100Ω
F
G
3. Solve for RG.
–5
–50
0
50
TEMPERATURE (°C)
100
150
RO
RG
=
(5)
R
R
F
Gain
2
⎛
⎜
⎝
⎞
⎟
⎠
O
−1
−1
Figure 33. Effect of Feedback Resistor on Offset Voltage Drift
LEVEL-SHIFTING THE OUTPUT
+V
S
–V
S
A reference voltage, as shown in Figure 34, can be used to
level-shift the output. The reference voltage, VR, is limited to
−VS + 3.5 V to +VS − 2.5 V. (For G < 10, the reference voltage
range is limited to −VS + 4.24 V to +VS – 2.75 V.) Otherwise, it
is nominally tied to midsupply. The voltage source used to level-
shift the output should have a low output impedance to avoid
contributing to gain error. In addition, it should be able to
source and sink current. To minimize offset voltage, the VREF
pins should be connected either to the local ground or to a
reference voltage source that is connected to the local ground.
0.1µF
0.1µF
8
2
4
1
V
AD8230
OUT
7
5
R
6
F
3
R
G
R
O
V
'
R
+V
S
Figure 35. Level-Shifting the Output Without an
Additional Voltage Reference
–V
S
0.1µF
+5V
–5V
0.1µF
2
0.1µF
4
1
0.1µF
V
8
F
AD8230
OUT
7
2
5
6
4
5
1
R
G
3
V
8
AD8230
OUT
7
R
9.76kΩ
6
3
V
R
203Ω
10.2kΩ
Figure 34. Level-Shifting the Output
+5V
The output can also be level-shifted by adding a resistor, RO, as
shown in Figure 35. The benefit is that the output can be level-
shifted to as low as 100 mV of the negative supply rail and to as
high as 200 mV of the positive supply rail, increasing unipolar
output swing. This can be useful in applications, such as strain
gauges, where the force is only applied in one direction. Another
benefit of this configuration is that a supply rail can be used for
VR’ eliminating the need to add an additional external reference
voltage.
Figure 36. An AD8230 with its Output Biased at −4.8 V;
G = 100; VDESIRED-LEVEL = −4.8 V
SOURCE IMPEDANCE AND INPUT SETTLING TIME
The input stage of the AD8230 consists of two actively driven,
differential switched capacitors, as described in Figure 30 and
Figure 31. Differential input signals are sampled on CSAMPLE such
that the associated parasitic capacitances, 70 pF, are balanced
between the inputs to achieve high common-mode rejection.
On each sample period (approximately 85 μs), these parasitic
capacitances must be recharged to the common-mode voltage
by the signal source impedance (10 kΩ maximum). If resistors
and capacitors are used at the input of the AD8230, care should
be taken to maintain close match to maximize CMRR.
The gain changes with the inclusion of RO. The full expression is
⎛
⎜
⎜
⎝
⎞
⎛
⎜
⎜
⎝
⎞
RF
(
RG + RO
RGRO
)
RF
RO
RF
RG || RO
RF
RO
(3)
⎟
⎟
VOUT = 2
+1 VIN
−
VR' = 2
+1 VIN
−
VR
'
⎟
⎟
⎠
⎠
Rev. B | Page 12 of 16
AD8230
INPUT VOLTAGE RANGE
POWER SUPPLY BYPASSING
The input common-mode range of the AD8230 is rail to rail.
However, the differential input voltage range is limited to
approximately 750 mV. The AD8230 does not phase invert
when its inputs are overdriven.
A regulated dc voltage should be used to power the
instrumentation amplifier. Noise on the supply pins can
adversely affect performance. Bypass capacitors should be
used to decouple the amplifier.
The AD8230 has internal clocked circuitry that requires
adequate supply bypassing. A 0.1 μF capacitor should be placed
as close to each supply pin as possible. As shown in Figure 32, a
10 μF tantalum capacitor can be used further away from the part.
INPUT PROTECTION
The input voltage is limited to within 0.6 V beyond the supply
rails by the internal ESD protection diodes. Resistors and low
leakage diodes can be used to limit excessive, external voltage
and current from damaging the inputs, as shown in Figure 37.
Figure 39 shows an overvoltage protection circuit between the
thermocouple and the AD8230.
POWER SUPPLY BYPASSING FOR MULTIPLE
CHANNEL SYSTEMS
The best way to prevent clock interference in multichannel
systems is to lay out the PCB with a star node for the positive
supply and a star node for the negative supply. Using such a
technique, crosstalk between clocks is minimized. If laying out
star nodes is not feasible, use wide traces to minimize parasitic
inductance and decouple frequently along the power supply
traces. Examples are shown in Figure 38. Care and forethought
go a long way in maximizing performance.
+V
S
–V
S
BAV199
0.1µF
+V –V
S
S
0.1µF
8
2
4
1
2.49kΩ
2.49kΩ
V
AD8230
OUT
7
5
6
19.1kΩ
200Ω
3
+V –V
S
S
BAV199
Figure 37. Overvoltage Input Protection
–V
S
+V
S
1µF
0.1µF
–V
1µF
1µF
0.1µF
–V
1µF
10µF
10µF
0.1µF
1
0.1µF
1
0.1µF
1
–V
–V
–V
S
S
S
S
S
S
S
1
2
3
4
1
2
3
4
8
7
6
5
8
7
6
5
8
8
7
6
5
8
7
6
5
+V
+V
+V
+V
+V
S
S
S
2
3
4
2
3
4
2
3
4
7
6
5
0.1µF
0.1µF
0.1µF
0.1µF
0.1µF
AD8230
AD8230
AD8230
AD8230
AD8230
STAR –V
S
10µF
STAR +V
S
10µF
0.1µF
1
0.1µF
0.1µF
1
0.1µF
–V
–V
–V
S
–V
S
S
S
S
1
2
3
4
1
2
3
4
8
7
6
5
8
7
6
5
8
7
6
8
7
+V
+V
+V
+V
S
S
S
2
3
4
2
3
4
6
0.1µF
0.1µF
0.1µF
0.1µF
5
5
AD8230
AD8230
AD8230
AD8230
Figure 38. Use Star Nodes for +VS and −VS or Use Thick Traces and Decouple Frequently Along the Supply Lines
Rev. B | Page 13 of 16
AD8230
An antialiasing filter reduces unwanted high frequency signals.
The matched 100 MΩ resistors serve to provide input bias
current to the input transistors and serve as an indicator as to
when the thermocouple connection is broken. Well-matched
1% 4.99 kΩ resistors are used to form the antialiasing filter. It is
good practice to match the source impedances to ensure high
CMR. The circuit is configured for a gain of 193, which
provides an overall temperature sensitivity of 10 mV/°C.
LAYOUT
The AD8230 has two reference pins: VREF1 and VREF2. VREF
1
draws current to set the internal voltage references. In contrast,
REF2 does not draw current. It sets the common mode of the
V
output signal. As such, VREF1 and VREF2 should be star-connected to
ground (or to a reference voltage). In addition, to maximize
CMR, the trace between VREF2 and the gain resistor, RG, should
be kept short.
+V
S
–V
APPLICATIONS
S
0.1µF
The AD8230 can be used in thermocouple applications, as
shown in Figure 3 and Figure 39. Figure 39 is an example of
such a circuit for use in an industrial environment. Series
resistors and low leakage diodes serve to clamp overload
voltages (see the Input Protection section for more information).
0.1µF
8
+V
S
2
4
1
4kΩ
V
AD8230
OUT
350Ω
350Ω
350Ω
350Ω
7
1µF
5
6
102kΩ
1kΩ
3
+V
S
BAV199
+V –V
–V
S
S
S
+V
0.1µF
S
0.1µF
8
–V
S
100MΩ
2
Figure 40. Bridge Measurement with Filtered Output
TYPE J
THERMOCOUPLE
4
1
4.99kΩ
4.99kΩ
V
1µF
AD8230
OUT
Measuring load cells in industrial environments can be a
challenge. Often, the load cell is located some distance away
from the instrumentation amplifier. The common-mode
potential can be several volts, exceeding the common-mode
input range of many 5 V auto-zero instrumentation amplifiers.
Fortunately, the wide common-mode input voltage range of the
AD8230 spans 16 V, relieving designers of having to worry
about the common-mode range.
7
5
6
100MΩ
19.1kΩ
200Ω
3
–V
S
+V –V
S
S
BAV199
Figure 39. Type J Thermocouple with Overvoltage Protection and RFI Filter
Rev. B | Page 14 of 16
AD8230
OUTLINE DIMENSIONS
5.00 (0.1968)
4.80 (0.1890)
8
1
5
4
6.20 (0.2441)
5.80 (0.2284)
4.00 (0.1574)
3.80 (0.1497)
0.50 (0.0196)
0.25 (0.0099)
1.27 (0.0500)
BSC
45°
1.75 (0.0688)
1.35 (0.0532)
0.25 (0.0098)
0.10 (0.0040)
8°
0°
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
1.27 (0.0500)
0.40 (0.0157)
0.25 (0.0098)
0.17 (0.0067)
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MS-012-AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 41. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body (R-8)
Dimensions shown in millimeters and (inches)
ORDERING GUIDE
Model
AD8230YRZ1
AD8230YRZ-REEL1
AD8230YRZ-REEL71
AD8230-EVAL
Temperature Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Package Description
Package Option
8-Lead SOIC_N
R-8
R-8
R-8
8-Lead SOIC_N, 13" Tape and Reel
8-Lead SOIC_N, 7" Tape and Reel
Evaluation Board
1 Z = RoHS Compliant Part.
Rev. B | Page 15 of 16
AD8230
NOTES
©2004–2007 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05063-0-9/07(B)
Rev. B | Page 16 of 16
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