AD8386 [ADI]
10-Bit, 12-Channel Output Decimating LCD Driver; 10位， 12通道输出抽取LCD驱动器
| 型号： | AD8386 |
| 厂家： | 
ADI |
| 描述： | 10-Bit, 12-Channel Output Decimating LCD Driver |
| 文件： | 总20页 (文件大小：378K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
10-Bit, 12-Channel Output
Decimating LCD Driver
AD8386
FUNCTIONAL BLOCK DIAGRAM
FEATURES
High voltage drive
To within 1.3 V of supply rails
Output short-circuit protection
High update rates
Fast, 100 Ms/s 10-bit input data update rate
Static power dissipation: 1.4 W
Voltage-controlled video reference (brightness), offset,
and full-scale (contrast) output levels
INV bit reverses polarity of video signal
3.3 V logic, 9 V to 18 V analog supplies
High accuracy voltage outputs
BIAS
BYP
VID0
VID1
VID2
VID3
VID4
VID5
VID6
VID7
VID8
VID9
VID10
VID11
VRH
VRH
VRL
2
SCALING
CONTROL
10
12
TWO-STAGE
LATCH
10-BIT
DACs
DB(0:9)
R/L
CLK
XFR
3
SEQUENCE
CONTROL
INV
CONTROL
Laser trimming eliminates the need for adjustments or
calibration
INV
Flexible logic
GCTL
GSW
TSW
XFR allows parallel AD8386 operation
Fast settling into capacitive loads
35 ns settling time to 0.25% into 150 pF load
Slew rate 400 V/μs
3
3
2
SDI
SCL
SEN
12-BIT
SHIFT
REGISTER
VAO
8-BIT
DAC
Available in 64-lead 9 mm × 9 mm LFCSP_VQ
SVRH
SVRL
SVRL
GENERAL DESCRIPTION
AD8386
The AD8386 provides a fast, 10-bit, latched, decimating digital
input that drives 12 high voltage outputs. Input words with
10 bits are loaded sequentially into 12 separate high speed,
bipolar DACs. Flexible digital input format allows several
AD8386s to be used in parallel in high resolution displays.
The output signal can be adjusted for dc reference, signal
inversion, and contrast for maximum flexibility.
Figure 1.
The AD8386 is fabricated on ADI’s fast bipolar, 26 V XFHV
process, which provides fast input logic, bipolar DACs with
trimmed accuracy and fast settling, high voltage, precision
drive amplifiers on the same chip.
The AD8386 dissipates 1.4 W nominal static power.
The AD8386 is offered in a 64-lead 9 mm × 9 mm LFCSP_VQ
package and operates over the commercial temperature range of
0°C to 85°C.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
© 2005 Analog Devices, Inc. All rights reserved.
AD8386
TABLE OF CONTENTS
Features .............................................................................................. 1
Reference and Control Input Descriptions............................. 13
Transfer Function and Analog Output Voltage...................... 13
Accuracy...................................................................................... 14
3-Wire Serial Interface............................................................... 14
Output Operating Modes.......................................................... 14
Overload Protection................................................................... 14
Applications..................................................................................... 15
Optimized Reliability with the Thermal Protection Circuit 15
Operation in High Ambient Temperature.............................. 15
Power Supply Sequencing ......................................................... 15
Grounded Output Mode During Power-Off .......................... 15
Typical Application Circuits ..................................................... 16
PCB Design for Optimized Thermal Performance ............... 17
AD8386 PCB Design Recommendations ............................... 17
Outline Dimensions....................................................................... 19
Ordering Guide .......................................................................... 19
General Description......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
DecDriver® Section ....................................................................... 3
Serial Interface Section ................................................................ 5
Absolute Maximum Ratings............................................................ 6
Maximum Power Dissipation ..................................................... 6
Overload Protection..................................................................... 6
Exposed Paddle............................................................................. 6
ESD Caution.................................................................................. 6
Operating Temperature Range ................................................... 7
Pin Configuration and Function Descriptions............................. 8
DecDriver Block Diagram and Timing........................................ 10
Serial Interface Block Diagram and Timing ............................... 12
Functional Description.................................................................. 13
REVISION HISTORY
8/05—Revision 0: Initial Version
Rev. 0 | Page 2 of 20
AD8386
SPECIFICATIONS
DECDRIVER® SECTION
At 25°C, AVCC = 15.5 V, DVCC = 3.3 V, TA MIN = 0°C, TA MAX = 85°C, VRH = 9.5 V, VRL = 7 V, unless otherwise noted.
Table 1.
Parameter
VIDEO DC PERFORMANCE1
Conditions
Min
Typ
Max
Unit
TA MIN to TA MAX
VDE
VCME
DAC Code 450 to 800
DAC Code 450 to 800
TA MIN to TA MAX, CL = 150 pF
20% to 80%, VO = 5 V step
20% to 80%, VO = 10 V step
−7.5
−3.5
+7.5
+3.5
mV
mV
VIDEO OUTPUT DYNAMIC PERFORMANCE
Data Switching Slew Rate
Invert Switching Slew Rate
Data Switching Settling Time to 1%
Data Switching Settling Time to 0.25%
Invert Switching Settling Time to 1%
Invert Switching Settling Time to 0.25%
Invert Switching Overshoot
CLK and Data Feedthrough2
All-Hostile Crosstalk3
400
560
24
35
80
250
100
15
V/μs
V/μs
ns
ns
ns
ns
mV
mV p-p
35
50
130
500
200
10 V Step
Amplitude
Glitch Duration
DAC Transition Glitch Energy
VIDEO OUTPUT CHARACTERISTICS
Output Voltage Swing
Output Voltage—Grounded Mode
Data Switching Delay: t9
INV Switching Delay: t10
Output Current
50
30
0.6
mV p-p
ns
nV-s
DAC code 511 to 512
AVCC −VOH, VOL − AGND
1.1
200
14
17
100
29
1.3
V
mV
ns
ns
mA
Ω
4
5 V step
10 V step
12
15
16
19
5
Output Resistance
REFERENCE INPUTS
VRL Range
VRH Range
VRH – VRL Range
VRH Input Resistance
VRL Input Current
VRH Input Current
VRH ≥ VRL
VRH ≥ VRL
VFS = 2 × (VRH − VRL)
To VRL
5.25
VRL
0
AVCC − 4
AVCC
2.75
V
V
V
kΩ
μA
μA
20
−45
125
RESOLUTION
Coding
Binary
10
2
Bits
DIGITAL INPUT CHARACTERISTICS
CIN
IIH
IIL
3
pF
μA
μA
V
0.05
−2
VIH
VIL
0.8
V
VTH
1.65
330
−2
V
IIH TSW
IIL TSW
TSW RPULLDOWN
μA
μA
kΩ
10
Rev. 0 | Page 3 of 20
AD8386
Parameter
Conditions
Min
Typ
Max
Unit
DIGITAL TIMING CHARACTERISTICS
Maximum Input Data Update Rate
Data Setup Time: t1
XFR Setup Time: t3
TA MIN to TA MAX
100
1
0
Ms/s
ns
ns
INV Setup Time: t11
Data Hold Time: t2
XFR Hold Time: t4
0
ns
ns
ns
ns
3.5
4.5
4
INV Hold Time: t12
CLK High Time: t7
6
ns
CLK Low Time: t8
4
ns
1 VDE = differential error voltage. VCME = common-mode error voltage. Full-scale output voltage = VFS = 2 × (VRH − VRL). See the Accuracy section.
2 Measured on two outputs differentially as CLK and DB (0:9) are driven and XFR is held low.
3 Measured on two outputs differentially as the others are transitioning by 5 V. Measured for both states of INV.
4 Measured from 50% of rising CLK edge to 50% of output change. Measurement is made for both states of INV.
5 Measured from 50% of rising CLK edge, which follows a valid XFR, to 50% of output change. See Figure 6 for the definition.
Rev. 0 | Page 4 of 20
AD8386
SERIAL INTERFACE SECTION
At 25°C, AVCC = 15.5 V, DVCC = 3.3 V, TA MIN = 0°C, TA MAX = 85°C, VRH = 9.5 V, VRL = 7 V, unless otherwise noted.
Table 2.
Parameter
Conditions
Min
Typ
Max
Unit
SERIAL DAC DC PERFORMANCE
DNL
INL
Output Offset Error
Scale Factor Error
SERIAL DAC OUTPUT DYNAMIC PERFORMANCE
VAO Settling Time, t26
VAO Settling Time, t26
SERIAL DAC OUTPUT CHARACTERISTICS
VAO Maximum
SVFS = 5 V
SVFS = 5 V
−1
+1
LSB
LSB
LSB
LSB
−1.5
−2.0
−3.0
+1.5
+2.0
+3.0
To 0.5%
CL = 100 pF
CL = 33 μF
1
2
15
μs
ms
SVRH − 1 LSB
V
VAO Minimum
SVRL
150
75
V
VAO − Grounded Mode
VAO Output Resistance
IOUT
CLOAD Low Range1
CLOAD High Range1
REFERENCE INPUTS
SVRH Range
mV
kΩ
mA
μF
μF
All supplies OFF
30
0.002
0.047
SVRL < SVRH
SVRL < SVRH
SVRL + 1
AGND + 1.5
1
AVCC − 3.5
SVRH − 1
8
V
V
V
SVRL Range
SVFS Range
SVRH Input Current
SVRL Input Current
DIGITAL INPUT CHARACTERISTICS
CIN
IIH
IIL
SVRS = 5 V
SVRS = 5 V
0.1
−1.3
μA
mA
−1.6
3
pF
μA
μA
V
0.05
−1
VIH
VIL
2.0
DGND
DVCC
0.8
V
VTH
1.65
V
DIGITAL TIMING CHARACTERISTICS
SEN to SCL Setup Time, t20
SCL, High Level Pulse Width, t21
SCL, Low Level Pulse Width, t22
SCL to SEN Hold Time, t23
SDI Setup Time, t24
SDI Hold Time, t25
POWER SUPPLIES
DVCC, Operating Range
DVCC, Quiescent Current
AVCC Operating Range
Total AVCC Quiescent Current
OPERATING TEMPERATURES
TA MIN to TA MAX
10
10
10
10
10
10
ns
ns
ns
ns
ns
ns
3
9
3.3
54
3.6
75
18
V
mA
V
80
100
mA
2
Ambient Temperature Range, TA
Still air, TSW = HIGH
Still air, TSW = LOW
0
0
70
85
°C
°C
2
Ambient Temperature Range, TA
1 Output VAO is designed to drive capacitive loads less than 0.002 μF or more than 0.047 μF. Load capacitances in the range 0.002 μF − 0.047 μF cause the output
overshoot to exceed 100 mV.
2 Operation at high ambient temperature requires a thermally optimized PCB layout (see the Applications section). In systems with limited or no airflow, the maximum
ambient operating temperature is limited to 70°C with the thermal protection enabled, VFS = 4 V, data update rate = 85 Ms/s. Operation at 85°C ambient temperature
requires the thermal protection circuit turned disabled (TSW = LOW).
Rev. 0 | Page 5 of 20
AD8386
ABSOLUTE MAXIMUM RATINGS
MAXIMUM POWER DISSIPATION
Table 3.
The maximum power that can be safely dissipated by the
AD8386 is limited by its junction temperature. The maximum
safe junction temperature for plastic encapsulated devices, as
determined by the glass transition temperature of the plastic, is
approximately 150°C. Exceeding this limit temporarily may
cause a shift in the parametric performance due to a change in
the stresses exerted on the die by the package. Exceeding a
junction temperature of 175°C for an extended period can
result in device failure.
Parameter
Rating
Supply Voltage
AVCCx − AGNDx
DVCC − DGND
Input Voltage
18 V
4.5 V
Maximum Digital Input Voltage
Minimum Digital Input Voltage
Maximum Analog Input Voltage
Minimum Analog Input Voltage
Internal Power Dissipation1
LFCSP @ TA = 25°C
Operating Temperature Range
Storage Temperature Range
Lead Temperature Range
(Soldering 10 sec)
DVCC + 0.5 V
DGND − 0.5 V
AVCC + 0.5 V
AGND − 0.5 V
OVERLOAD PROTECTION
3.7 W
The AD8386 overload protection circuit consists of an output
current limiter and a thermal protection circuit.
0°C to 85°C
–65°C to +125°C
300°C
When TSW is LOW, the thermal protection circuit is disabled,
and the output current limiter is turned on. The maximum
current at any one output of the AD8386 is internally limited to
100 mA average. In the event of a momentary short circuit
between a video output and a power supply rail (AVCC or
AGND), the output current limit is sufficiently low to provide
temporary protection.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or
any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
When TSW is HIGH, the output current limiter, as well as the
thermal protection circuit, is turned on. The thermal protection
circuit debiases the output amplifier when the junction
temperature reaches the internally set trip point. In the event of
an extended short circuit between a video output and a power
supply rail, the output amplifier current continues to switch
between 0 mA and 100 mA typical with a period determined by
the thermal time constant and the hysteresis of the thermal trip
point. The thermal protection circuit limits the average junction
temperature to a safe level, which provides long-term
protection.
1 64-lead VQ_LFCSP:
θJA = 27°C/W in still air (JEDEC STD, 4-layer PCB with 16 vias on Epad)
θJA = 25°C/W @ 200 lfm airflow (JEDEC STD, 4-layer PCB with 16 vias on Epad)
θJA = 24°C/W @ 400 lfm airflow (JEDEC STD, 4-layer PCB with 16 vias on Epad)
ΨJT = 0.2°C/W in still air (JEDEC STD, 4-layer PCB with 16 vias on Epad)
ΨJB = 13.8°C/W in still air (JEDEC STD, 4-layer PCB with 16 vias on Epad)
EXPOSED PADDLE
To ensure optimal thermal performance, the exposed paddle
must be electrically connected to an external plane, such as
AVCC or GND, as described in the Applications section.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate
on the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. 0 | Page 6 of 20
AD8386
OPERATING TEMPERATURE RANGE
The maximum operating junction temperature is 150°C. The
junction temperature trip point of the thermal protection
circuit is 165°C. Production tests guarantee a minimum
junction temperature trip point of 125°C.
3.00
2.75
2.50
2.25
2.00
1.75
1.50
1.25
1.00
STILL AIR
200LFM
400LFM
Consequently, the maximum guaranteed operating junction
temperature is 125°C when the thermal protection circuit is
enabled and 150°C when the thermal protection circuit is
disabled.
720p HDTV
QUIESCENT
To ensure operation within the specified operating temperature
range, it is necessary to limit the maximum power dissipation as
OVERLOAD
PROTECTION
TJMAX −TA
ENABLED
40
45
70
50
75
55
80
60
85
65
90
70
75
80
85
90
95
PDMAX
≈
Airflow in lfm 0.59
)
DISABLED
65
95 100 105 110 115 120
θJA Still Air − 0.09×
(
AMBIENT TEMPERATURE (°C)
Figure 2. Maximum Power Dissipation vs. Temperature
The AD8386 is on a 4-layer JEDEC PCB with a thermally
optimized landing pattern with 16 vias.
The quiescent power dissipation of the AD8386 is 1.4 W.
When driving a 12-channel 720p HDTV panel with an input
capacitance of 150 pF, the AD8386 dissipates 1.66 W when
displaying 1 pixel wide alternating white and black vertical lines
generated by a standard 720p HDTV input video.
Conditions include the following:
• AVCC = 15.5 V
• DVCC = 3.3 V
• VFS = 5 V
• CL = 150 pF
• fPIXEL = 74.25 MHz
• Black-to-white transition = 4 V
• Active video time = 75%
Figure 2 shows these power dissipations.
Rev. 0 | Page 7 of 20
AD8386
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PIN 1
INDICATOR
NC
NC
1
2
3
4
5
6
7
8
9
48 AGND1, 2
47 VID2
46 AVCC2, 3
45 VID3
44 AGND3, 4
43 VID4
42 AVCC4, 5
41 VID5
40 AGND5, 6
39 VID6
38 AVCC6, 7
37 VID7
36 AGND7, 8
35 VID8
34 AVCC8, 9
33 VID9
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7 10
DB8 11
DB9 12
SDI 13
AD8386
TOP VIEW
(Not to Scale)
SEN 14
SCL 15
GCTL 16
NC = NO CONNECT
Figure 3. 64-Lead LFCSP_VQ Pin Configuration
Rev. 0 | Page 8 of 20
AD8386
Table 4. 64-Lead LFCSP_VQ Pin Function Descriptions
Pin No.
Mnemonic Function
NC No Connect
DB0 to DB9 Data Input
Description
1, 2
3 to 12
13
No Internal Connection.
10-Bit Data Input. MSB = DB(9).
While the SEN input is LOW, one 12-bit serial word is loaded into the
serial DAC on the rising edges of the SCL.
SDI
Serial Data Input
14
SEN
Serial DAC Enable
A falling edge of this input initiates a loading cycle. While this input is held
LOW, the serial DAC is enabled and data is loaded on every rising edge of
SCL. The output is updated on the rising edge of a valid SEN. A valid
SEN must remain LOW for at least three SCL cycles. While this input is
held HIGH, the control DAC is disabled.
15
16
SCL
GCTL
Serial Data Clock
Output Mode Control
Serial Data Clock.
When this input is HIGH, the output mode is determined by the function
programmed into the serial interface. When LOW, the output mode is
controlled by the GSW input.
17
18
GSW
TSW
Output Mode Switch
Thermal Switch
When GCTL is LOW and this input is HIGH, the video outputs and VAO
operate normally. When GCTL and this input are both LOW, the video
outputs and VAO are asynchronously forced to AGND, regardless of
the function programmed into the serial interface. This function operates
when AVCC power is OFF but requires DVCC power supply to be ON.
When this input is LOW, the thermal protection circuit is disabled. When
HIGH, the thermal protection circuit is enabled. This pin has a 10 kΩ
internal pull-down resistor.
19, 64
20, 63
21
DVCC
DGND
AGNDS
Digital Power Supply
Digital Ground
Analog Ground
Digital Power Supply.
Digital Supply Return.
Analog Supply Return.
22, 23, 24
25
26
SVRL, SVRH Serial DAC Reference Voltage The voltage applied between these pins sets the serial DAC full-scale voltage.
VAO
Serial DAC Output
Analog Power Supply
Bypass
This output voltage is updated in the rising edge of the SEN input.
Analog Power Supply.
AVCCS
BYP
27
A 0.1 μF capacitor connected between this pin and AGND ensures
optimum settling time.
28, 32, 36,
AGND11 to Analog Ground
Analog Supply Returns.
40, 44, 48, 52 AGND0
29, 31, 33, 35, VID11 to
37, 39, 41, 43, VID0
45, 47, 49, 51
Analog Output
These pins are directly connected to the analog inputs of the LCD panel.
30, 34, 38,
42, 46, 50
AVCC10, 11 Analog Power Supply
to AVCC0, 1
Analog Power Supplies.
53
VRL
Video Center Reference
The voltage applied to this pin sets the video center voltage. The video
outputs are above this reference while the INV = HIGH and below this
reference while INV = LOW.
54, 55
56
57
VRH
Full-Scale Reference
Analog Power Supply
Analog Ground
Test Pin
The full-scale video output voltage is VFS = 2 × (VRH − VRL).
Analog Power Supply.
Analog Supply Return.
AVCCD
AGNDD
TSTA
58
Connect this pin to AGND.
59
R/L
Right/Left Select
A new data loading sequence begins on the left with Channel 0 when
this input is LOW, and on the right with Channel 11 when this input is HIGH.
60
INV
Invert
When this input is HIGH, the VIDx output voltages are above VRL. When
LOW, the VIDx outputs voltages are below VRL. The state of INV is latched
on the first rising CLK edge after XFR is detected. The VIDx outputs change
on the rising CLK edge after the next XFR is detected.
61
62
XFR
CLK
Transfer/Start Sequence
Clock
The state of XFR is detected on the rising edge of CLK. Data is transferred to
the outputs and a new loading sequence begins on the next rising edge of
CLK after XFR is detected HIGH.
Video Data Clock.
Rev. 0 | Page 9 of 20
AD8386
DECDRIVER BLOCK DIAGRAM AND TIMING
TWO-
10
10
10
10
10
10
10
10
10
10
10
10
VID0
VID2
VID4
VID6
VID8
VID10
DAC
DAC
DAC
DAC
DAC
DAC
STAGE
LATCH
TWO-
STAGE
LATCH
BIAS
BYP
TWO-
STAGE
LATCH
TWO-
STAGE
LATCH
TWO-
STAGE
LATCH
TWO-
STAGE
LATCH
10
10
DB(0:9)
TWO-
STAGE
LATCH
10
10
10
10
10
10
10
10
10
10
10
10
VID1
VID3
VID5
VID7
VID9
VID11
DAC
DAC
DAC
DAC
DAC
DAC
TWO-
STAGE
LATCH
TWO-
STAGE
LATCH
CLK
XFR
R/L
SEQUENCE
CONTROL
TWO-
STAGE
LATCH
TWO-
STAGE
LATCH
TWO-
STAGE
LATCH
INV
CONTROL
INV
SCALING
CONTROL
VRH
VRL
Figure 4. AD8386 DecDriver Section
Rev. 0 | Page 10 of 20
AD8386
tr
tf
t8
CLK
V
TH
t7
t1
t1
t2
t2
DB(0:9)
XFR
V
TH
V
TH
t4
t3
Figure 5. Input Timing
CLK
–9 –8 –7 –6 –5 –4 –3 –2 –1
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
DB(0:9)
XFR
INV
VRL + VFS
VRL
PIXELS
–12, –11, –10, –9, –8, –7, –6, –5, –4, –3, –2, –1
50%
VID(0:11)
t9
t9
VRL
VRL – VFS
t10
t11 MIN
t11 MAX
t12
PIXELS
0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11
Figure 6. Output Timing (R/L LOW)
Table 5.
Parameter
Conditions
Min
1
3.5
0
4.5
6
4
12
15
0
Typ
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Data Setup Time, t1
Data Hold Time, t2
XFR Setup Time, t3
XFR Hold Time, t4
CLK High Time, t7
CLK Low Time, t8
Data Switching Delay, t9
Invert Switching Delay, t10
Invert Setup Time, t11
Invert Hold Time, t12
Input tr, tf = 2 ns
14
17
16
19
4
Rev. 0 | Page 11 of 20
AD8386
SERIAL INTERFACE BLOCK DIAGRAM AND TIMING
SVRH
SVRL
VAO = SVRL + SDI
× (SVRH – SVRL)/256
CODE
SDI
12-BIT SHIFT REGISTER
SCL
SDI
8
CODE
SDAC
SDI
CODE
VAO
SEN
SD0 SD1 SD2 SD3 SD4 SD5 SD6 SD7 SD8 SD9 SD10 SD11
SELECT LOAD
75kΩ
CONTROL
THERMAL
SWITCH
TSW
10kΩ
12
12
VIDEO
DACs
12
VID(0:11)
GSW
GCTL
Figure 7. Serial Interface Block Diagram
SEN
SCL
SEN
SCL
SDI
t22
t20
t23
t21
t24 t25
D11
SDI
D10
D0
D1
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
VAO
VAO
t26
Figure 8. Serial Interface Timing Diagram
Figure 9. Serial Interface Timing Diagram
Table 6.
Parameter
Conditions
Min
10
10
10
10
10
10
Typ
Max
Unit
ns
ns
ns
ns
SEN to SCL Setup Time, t20
SCL, High Level Pulse Width, t21
SCL, Low Level Pulse Width, t22
SCL to SEN Hold Time, t23
SDI Setup Time, t24
ns
ns
SDI Hold Time, t25
VAO Settling Time, t26
VAO Settling Time, t26
SVFS = 5 V, to 0.5 %, CL = 100 pF
SVFS = 5 V, to 0.5 %, CL = 33 μF
1
2
15
μs
ms
Rev. 0 | Page 12 of 20
AD8386
FUNCTIONAL DESCRIPTION
The AD8386 is a system building block designed to
An internal 10 kΩ pull-down resistor disables the thermal
directly drive the columns of LCD microdisplays of the type
popularized for use in projection systems. It has 12 channels of
precision, 10-bit digital-to-analog converters (DACs) loaded
from a single high speed serial input. Precision current feedback
amplifiers, which provide well-damped pulse response and fast
voltage settling into large capacitive loads, buffer the 12 outputs.
Laser trimming at the wafer level ensures low absolute output
errors and tight channel-to-channel matching. Tight part-to-
part matching in high resolution systems is guaranteed by the
use of external voltage references.
switch when this pin is left unconnected.
GCTL, GSW controls—output mode control.
Table 7. GTCL, GSW Truth Table
GTCL GSW Action
0
0
All video outputs and VAO are forced near
AGND. While the outputs are disabled, AVCC can
be removed.
0
1
1
X
All video outputs and VAO operate normally.
Output operating mode is controlled by the
serial interface.
REFERENCE AND CONTROL INPUT DESCRIPTIONS
TRANSFER FUNCTION AND ANALOG OUTPUT
VOLTAGE
Data transfer/start sequence control—input data loading,
data transfer.
The DecDriver has two regions of operation where the video
output voltages are either above or below the reference voltage
VRL. The transfer function defines the video output voltage as
the function of the digital input code as
A valid XFR control input initiates a new six-clock loading
cycle, during which data is transferred to the outputs, and 12
input data-words are loaded sequentially into the 12 internal
channels. Data is loaded on both the rising and falling edges of
CLK. Data loaded from the previous cycle is transferred to the
outputs on the rising CLK edge when the XFR is held HIGH at
the preceding rising CLK edge only. A new loading sequence
begins on the current rising CLK edge when XFR is held HIGH
at the preceding rising CLK edge only.
VIDx(n) = VRL + VFS × (1 − n/1023), for INV = HIGH
VIDx(n) = VRL − VFS × (1 − n/1023), for INV = LOW
where:
n = input code
VFS = 2 × (VRH − VRL)
Right/left control—input data loading.
To facilitate image mirroring, the direction of the loading
sequence is set by the R/L control.
A number of internal limits define the usable range of the video
output voltages, VIDx, shown in Figure 10.
VIDx – VOLTS
A new loading sequence begins at Channel 0 and proceeds to
Channel 11 when the R/L control is held LOW. It begins at
Channel 11 and proceeds to Channel 0 when the R/L control is
held HIGH.
AVCC
≥1.3V
(VRL + VFS)
VOUTN(n)
0 ≤ VFS ≤ 5.5V
INV = HIGH
VRH, VRL inputs—full-scale video reference inputs.
The full-scale output voltage is VFS = 2 × (VRH − VRL).
INV control—analog output inversion.
9V ≤ AVCC
≤ 18V
VRL
INV = LOW
0 ≤ VFS
≤ 5.5V
5.25V ≤ VRL
≤ (AVCC – 4)
VOUTP(n)
(VRL – VFS)
AGND
The analog voltage equivalent of the input code is subtracted
from (VRL + VFS) while INV is held HIGH, and added to
(VRL − VFS) while INV is held LOW.
≥1.3V
0
INPUT CODE (n)
1023
INTERNAL LIMITS AND
USABLE VOLTAGE RANGES
VIDx vs. INPUT CODE
The state of the INV input is latched on the first rising edge of
CLK, immediately following a valid XFR. The VIDx outputs
invert on the first rising CLK edge, immediately following the
next valid XFR.
Figure 10. Transfer Function and Usable Voltage Ranges
TSW control—thermal switch control.
When this input is HIGH, the thermal protection circuit is
enabled. When LOW or left unconnected, the thermal
protection circuit is disabled.
Rev. 0 | Page 13 of 20
AD8386
Table 10. Truth Table @ GCTL = LOW
ACCURACY
SEN SD
Action
To best correlate transfer function errors to image artifacts, the
overall accuracy of the DecDriver is defined by two parameters,
VDE and VCME.
11 10
9
X
X
X
8
X
X
X
X
X
X
0
1
X
No Change to VAO.
Load VAO.
Start a Serial Interface Loading Cycle. No
change to VAO.
VDE, the differential error voltage, measures the difference
between the rms value of the output and the rms value of the
ideal. The defining expression is
Serial DAC
[
VOUTN
(
n
)
−VOUTP
2
(
n
)
]
n
1023
⎛
⎝
⎞
⎟
⎠
The serial DAC is loaded via the serial interface. The output
voltage is determined by
VDE
(
n
)
=
− 1−
×VFS
⎜
VAO = SVRL + (SVRH − SVRL) × n/256
where n is the SD(0:7) serial input code.
VCME, the common-mode error voltage, measures ½ the dc
offset of the output. The defining expression is
1 VOUTN
(
n
)
+VOUTP n
( )
2
⎡
⎤
VCME
(
n
)
=
−VRL
Output VAO is designed to drive capacitive loads less than
0.002 μF or more than 0.047 μF. Load capacitances in the
0.002 μF − 0.047 μF range cause the output overshoot to exceed
100 mV.
⎢
⎥
⎦
2
⎣
3-WIRE SERIAL INTERFACE
The serial interface controls the 8-bit serial DAC and the video
output operating mode via a 12-bit serial word. The two most
significant bits (MSB) select the function and the eight least
significant bits (LSB) are the data for the serial DAC.
OUTPUT OPERATING MODES
In normal operating mode, the voltage of the video outputs is
determined by the inputs.
Table 8. Bit Definitions
In grounded output mode, the video outputs are forced to
(AGND + 0.2 V) typ.
Bit Name
SD (0:7)
SD8
Bit Functionality
8-Bit SDAC Data. MSB = SD7.
Not Used.
OVERLOAD PROTECTION
SD9
Not Used.
The overload protection employs current limiters and a thermal
protection circuit to protect the video output pins against accidental
shorts between any video output pin and AVCC or AGND.
SD10
SD11
VAO Load Selection.
Output Mode Selection When GCTL = 1.
Table 9. Truth Table @ GCTL = HIGH
The junction temperature trip point of the thermal protection
circuit is 165°C. Production tests guarantee a minimum
junction temperature trip point of 125°C. Consequently, the
operating junction temperature should not rise above 125°C
when the thermal protection circuit is enabled.
SEN SD
Action
11 10
9
X
X
X
8
X
X
X
0
0
1
0
1
0
Normal Output Mode. No change to VAO.
Normal Output Mode. Load VAO.
Grounded Output Mode. No change to
VAO.
For systems that operate at high internal ambient temperatures
and require large capacitive loads to be driven by the AD8386 at
high frequencies, junction temperatures above 125°C may be
required. In such systems, the thermal protection circuit should
either be disabled or a minimum airflow of 200 lfm must be
maintained.
1
X
1
X
X
X
X
X
Grounded Output Mode. Load VAO.
Start a Serial Interface Loading Cycle. No
change to VAO.
Rev. 0 | Page 14 of 20
AD8386
APPLICATIONS
OPTIMIZED RELIABILITY WITH THE THERMAL
PROTECTION CIRCUIT
POWER SUPPLY SEQUENCING
As indicated in the Absolute Maximum Ratings section, the
voltage at any input pin cannot exceed its supply voltage by
more than 0.5 V. Power-on and power-off sequencing may be
required to comply with the Absolute Maximum Ratings.
The AD8386 is designed for enhanced reliability through
features that provide protection against accidental shorts that
may occur during PCB assembly repair, such as solder bridging,
or during system assembly, such as a misaligned flat panel cable
in the connector.
Failure to comply with the Absolute Maximum Ratings may
result in functional failure or damage to the internal ESD
diodes. Damaged ESD diodes may cause temporary parametric
failures, which may result in image artifacts. Damaged ESD
diodes cannot provide full ESD protection, reducing reliability.
While internal current limiters provide short-term protection
against temporary shorts at the outputs, the thermal shutdown
provides protection against persistent shorts lasting for several
seconds. To optimize reliability, the following sequence of
operations is recommended.
The following power supply sequencing ensures that the
Absolute Maximum Ratings are not violated.
Initial Power-Up after PCB Assembly or Repair
Power-on sequence is:
Disable grounded output mode and enable thermal protection.
• Turn ON AVCC and analog reference voltages.
• Turn ON DVCC and digital signals.
Power-off sequence is:
Ensure that the GCTL and GSW pins are LOW and the TSW
pin is HIGH upon initial power-up and remains unchanged
throughout this procedure.
• Execute the initial power-up.
• Turn OFF AVCC and analog reference voltages.
• Turn OFF DVCC and digital signals.
GROUNDED OUTPUT MODE DURING POWER-OFF
• Identify any shorts at the outputs.
• Power-down, repair shorts, and repeat the initial power-up
sequence until proper system functionality is verified.
Certain applications require that the video outputs be held near
AGND during power-down. The following power-off sequence
ensures that the outputs are near ground during power-off and
the Absolute Maximum Ratings are not violated.
Power-Up during Normal Operation
Disable grounded output mode and disable the thermal
protection circuit using either of the following two methods:
• GCTL = HIGH, TSW = HIGH and serial code
0XXXXXXXXXXX sent immediately following a power-up,
places all outputs into normal operating mode and disables
the thermal protection circuit.
• Enable grounded output mode in one of two ways:
GTCL = LOW and GSW = LOW, or GCTL = HIGH
and code 1XXXXXXXXXXX sent via the serial interface.
• Turn OFF AVCC and analog reference voltages.
• Turn OFF DVCC and digital signals.
• TSW = LOW disables the thermal protection circuit.
GCTL = LOW and GSW = HIGH puts all outputs into
normal operating mode.
OPERATION IN HIGH AMBIENT TEMPERATURE
To extend the maximum operating junction temperature of the
AD8386 to 150°C, keep the thermal protection circuit disabled
(TSW = LOW) during normal operation.
Rev. 0 | Page 15 of 20
AD8386
TYPICAL APPLICATION CIRCUITS
12-CHANNEL
LCD
VID0
VID1
VID2
VID3
VID4
VID5
VID6
VID7
VID8
VID9
VID10
VID11
CHANNEL 0
CHANNEL 1
CHANNEL 2
CHANNEL 3
CHANNEL 4
CHANNEL 5
CHANNEL 6
CHANNEL 7
CHANNEL 8
CHANNEL 9
CHANNEL 10
CHANNEL 11
DB(0:9)
PIXEL
DB(0:9)
CLK
R/L
÷2
CLK
CLK
AD8386
R/L
XFR
INV
XFR
INV
IMAGE
PROCESSOR
VRH
VRL
REFERENCES
SVRH
SVRL
SDI SCL
SEN
VAO
μP
Figure 11. 12-Channel System
VID0
CHANNEL 0
CHANNEL 1
CHANNEL 2
CHANNEL 3
CHANNEL 4
CHANNEL 5
CHANNEL 6
CHANNEL 7
CHANNEL 8
CHANNEL 9
CHANNEL 10
CHANNEL 11
DB(0:9)
PIXEL
DB(0:9)
CLK
R/L
VID1
VID2
VID3
VID4
VID5
VID6
VID7
VID8
VID9
VID10
VID11
÷2
CLK
CLK
AD8386
R/L
XFR
INV
XFR
INV
SCL
SDI
SEN
VAO
μP
REFERENCES
24-CHANNEL
LCD
IMAGE
PROCESSOR
VRH
VID0
VID1
VID2
VID3
VID4
VID5
VID6
VID7
VID8
VID9
VID10
VID11
CHANNEL 12
CHANNEL 13
CHANNEL 14
CHANNEL 15
CHANNEL 16
CHANNEL 17
CHANNEL 18
CHANNEL 19
CHANNEL 20
CHANNEL 21
CHANNEL 22
CHANNEL 23
SCL
SDI
SEN
CLK
R/L
XFR
DB(0:9)
INV
DB(0:9)
INV
AD8386
VAO
Figure 12. 24-Channel System
Rev. 0 | Page 16 of 20
AD8386
Bottom PCB Layer
PCB DESIGN FOR OPTIMIZED THERMAL
PERFORMANCE
It is recommended that the bottom thermal pad be thermally
connected to a plane. The connection should be direct such that
the thermal pad becomes part of the plane.
The total maximum power dissipated by the AD8386 is partly
load dependent. In a 12-channel, 60 Hz XGA system running at
a 65 MHz pixel rate, the total maximum power dissipated is
1.7 W, assuming a 15.5 V analog power supply, a 4 V white-to-
black swing, and a 150 pF LCD input capacitance.
The use of thermal spokes is not recommended when
connecting the thermal pads or via structure to a plane.
Solder Masking
To limit the operating junction temperature at or below the
guaranteed maximum, the package in conjunction with the
PCB must effectively conduct heat away from the junction.
To minimize the formation of solder voids due to solder flowing
into the via holes (solder wicking), the via diameter should be
small. Optional solder masking of the via holes on the top layer
of the PCB plug the via holes, inhibiting solder flow into the
holes. To optimize the thermal pad coverage, the solder mask
diameter should be no more than 0.1 mm larger than the via
hole diameter.
The AD8386 package is designed to provide enhanced thermal
characteristics through the exposed die paddle on the bottom
surface of the package. In order to take full advantage of this
feature, the exposed paddle must be in direct thermal contact
with the PCB, which then serves as a heat sink.
Pads are set by the customer’s PCB design rules, and thermal
vias are 0.25 mm diameter circular mask, centered on the vias.
A thermally effective PCB must incorporate two thermal pads
and a thermal via structure. The thermal pad on the top PCB
layer provides a solderable contact surface on the top surface of
the PCB. The thermal pad on the bottom PCB layer provides a
surface in direct contact with the ambient air. The thermal via
structure provides a thermal path to the inner and bottom
layers of the PCB to remove heat.
Thermal Pad Design
To minimize thermal performance degradation of production
PCBs, the contact area between the thermal pad and the PCB
should be maximized. Therefore, the size of the thermal pad on
the top PCB layer should match the exposed paddle size. The
second thermal pad of at least the same size should be placed on
the bottom side of the PCB. At least one thermal pad should be
in direct thermal contact with a plane, such as AVCC or GND.
Figure 13. Land Patter—Top PCB Layer
Figure 14. Land Patter—Bottom PCB Layer
Figure 15. Solder Mask—Top Layer
Thermal via Structure Design
Effective heat transfer from the top to the inner and bottom
layers of the PCB requires thermal vias incorporated into the
thermal pad design. Thermal performance increases
logarithmically with the number of vias.
Near optimum thermal performance of production PCBs is
attained when tightly spaced thermal vias are placed on the full
extent of the thermal pad only.
AD8386 PCB DESIGN RECOMMENDATIONS
Table 11. Top PCB Layer
0.25 mm × 0.4 mm
Pad Size
0.5 mm
Pad Pitch
4.7 mm × 4.7 mm
0.25 mm diameter vias on a 0.5 mm grid
Thermal Pad Size
Thermal via Structure
Rev. 0 | Page 17 of 20
AD8386
0.5
0.5
9.00
4.7 SQ CU w/4.8 SQ SOLDER MASK
R 0.05 OPTIONAL FILLETS
VIA ARRAY ON 0.5 GRID
0.25 DRILL, 0.35 SOLDER MASK SWELL
0.05
SOLDER MASK
SWELL
0.25
R 0.05
OPTIONAL FILLETS
Figure 16. Suggested Land Pattern
Dimensions shown in millimeters
Rev. 0 | Page 18 of 20
AD8386
OUTLINE DIMENSIONS
0.30
0.25
0.18
9.00
BSC SQ
0.60 MAX
0.60 MAX
PIN 1
INDICATOR
64
49
48
1
PIN 1
INDICATOR
*
4.85
4.70 SQ
4.55
8.75
BSC SQ
TOP
VIEW
EXPOSED PAD
(BOTTOM VIEW)
0.45
0.40
0.35
33
32
16
17
7.50
REF
0.80 MAX
0.65 TYP
1.00
0.85
0.80
12° MAX
0.05 MAX
0.02 NOM
0.50 BSC
0.20 REF
SEATING
PLANE
*
COMPLIANT TO JEDEC STANDARDS MO-220-VMMD
EXCEPT FOR EXPOSED PAD DIMENSION
Figure 17. 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
9 mm × 9 mm Body, Very Thin Quad (CP-64-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model
AD8386JCPZ1
Temperature Range
Package Description
Package Option
CP-64-1
0°C to 85°C
64-Lead Lead Frame Chip Scale Package (LFCSP_VQ)
1 Z = Pb-free part.
Rev. 0 | Page 19 of 20
AD8386
NOTES
©
2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05687–0–8/05(0)
Rev. 0 | Page 20 of 20
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