AD842 [ADI]
Wideband, High Output Current, Fast Settling Op Amp; 宽带，高输出电流，快速建立运算放大器
| 型号： | AD842 |
| 厂家： | 
ADI |
| 描述： | Wideband, High Output Current, Fast Settling Op Amp |
| 文件： | 总10页 (文件大小：477K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Wideband, High Output Current,
Fast Settling Op Amp
a
AD842*
CONNECTION DIAGRAMS
FEATURES
AC PERFORMANCE
Plastic DIP (N) Package
and
Cerdip (Q) Package
LCC (E) Package
Gain Bandwidth Product: 80 MHz (Gain = 2)
Fast Settling: 100 ns to 0.01% for a 10 V Step
Slew Rate: 375 V/s
Stable at Gains of 2 or Greater
Full Power Bandwidth: 6.0 MHz for 20 V p-p
1
2
3
4
5
6
7
14
13
12
11
10
9
NC
NC
NC
AD842
BALANCE
NC
DC PERFORMANCE
Input Offset Voltage: 1 mV max
Input Offset Drift: 14 V/؇C
Input Voltage Noise: 9 nV/√Hz typ
Open-Loop Gain: 90 V/mV into a 500 ⍀ Load
Output Current: 100 mA min
NC
–IN
NC
+IN
NC
4
5
6
7
8
18 NC
BALANCE
–INPUT
+INPUT
17
16
+V
S
V+
NC
+
OUTPUT
NC
+
15 OUTPUT
14
AD842
NC
V–
8
NC
NC
TOP VIEW
Quiescent Supply Current: 14 mA max
NC = NO CONNECT
NC = NO CONNECT
APPLICATIONS
Line Drivers
DAC and ADC Buffers
TO-8 (H) Package
SOIC (R-16) Package
Video and Pulse Amplifiers
Available in Plastic DIP, Hermetic Metal Can,
Hermetic Cerdip, SOIC and LCC Packages and in
Chip Form
MIL-STD-883B Parts Available
Available in Tape and Reel in Accordance with
EIA-481A Standard
NC
NC
BALANCE
NC
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
NC
BALANCE
BALANCE
BALANCE
AD842
V+
–INPUT
+V
S
AD842
NC
NC
–INPUT
OUTPUT
+
+INPUT
NC
OUTPUT
NC
+
+INPUT
V–
NC
NC
–V
S
NC
NC
PRODUCT DESCRIPTION
NC
NC
TOP VIEW
The AD842 is a member of the Analog Devices family of wide
bandwidth operational amplifiers. This device is fabricated using
Analog Devices’ junction isolated complementary bipolar (CB)
process. This process permits a combination of dc precision and
wideband ac performance previously unobtainable in a mono-
lithic op amp. In addition to its 80 MHz gain bandwidth, the
AD842 offers extremely fast settling characteristics, typically
settling to within 0.01% of final value in less than 100 ns for a
10 volt step.
TOP VIEW
NOTE: CAN BE TIED TO V+
NC = NO CONNECT
NC = NO CONNECT
AD842 is also appropriate for other applications such as high
speed DAC and ADC buffer amplifiers and other wide band-
width circuitry.
APPLICATION HIGHLIGHTS
The AD842 also offers a low quiescent current of 13 mA, a high
output current drive capability (100 mA minimum), a low input
voltage noise of 9 nV√Hz and a low input offset voltage (1 mV
maximum).
1. The high slew rate and fast settling time of the AD842 make
it ideal for DAC and ADC buffers amplifiers, lines drivers
and all types of video instrumentation circuitry.
2. The AD842 is a precision amplifier. It offers accuracy to
0.01% or better and wide bandwidth; performance previously
available only in hybrids.
The 375 V/µs slew rate of the AD842, along with its 80 MHz
gain bandwidth, ensures excellent performance in video and
pulse amplifier applications. This amplifier is ideally suited for
use in high frequency signal conditioning circuits and wide
bandwidth active filters. The extremely rapid settling time of
the AD842 makes this amplifier the preferred choice for data
acquisition applications which require 12-bit accuracy. The
3. Laser-wafer trimming reduces the input offset voltage of
1 mV max, thus eliminating the need for external offset
nulling in many applications.
4. Full differential inputs provide outstanding performance in
all standard high frequency op amp applications where the
circuit gain will be 2 or greater.
*Covered by U.S. Patent Nos. 4,969,823 and 5,141,898.
5. The AD842 is an enhanced replacement for the HA2542.
REV. E
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
World Wide Web Site: http://www.analog.com
© Analog Devices, Inc., 2000
(@ +25؇C and ؎15 V dc, unless otherwise noted)
AD842–SPECIFICATIONS
Model
AD842J/JR1
AD842K
Typ Max
AD842S2
Typ
Conditions
Min
Typ
Max
Min
Min
Max
Units
INPUT OFFSET VOLTAGE3
0.5
1.5
2.5/3
0.3
1.0
1.5
0.5
1.5
3.5
mV
mV
T
MIN–TMAX
Offset Drift
14
14
14
µV/°C
INPUT BIAS CURRENT
4.2
8
3.5
5
6
0.2
0.3
4.2
8
µA
µA
µA
µA
T
MIN–TMAX
10
0.4
0.5
12
0.4
0.6
Input Offset Current
0.1
0.05
0.1
TMIN–TMAX
INPUT CHARACTERISTICS
Input Resistance
Input Capacitance
Differential Mode
100
2.0
100
2.0
100
2.0
kΩ
pF
INPUT VOLTAGE RANGE
Common Mode
Common-Mode Rejection
؎10
86
80
؎10
90
86
؎10
86
80
V
dB
dB
VCM
TMIN–TMAX
=
10 V
115
115
115
INPUT VOLTAGE NOISE
Wideband Noise
f = 1 kHz
10 Hz to 10 MHz
9
28
9
28
9
28
nV/√Hz
µV rms
OPEN-LOOP GAIN
VO = 10 V
RLOAD ≥ 500 Ω
TMIN–TMAX
40/30
20/15
90
50
25
90
40
20
90
V/mV
V/mV
OUTPUT CHARACTERISTICS
Voltage
Current
RLOAD ≥ 500 Ω
؎10
100
؎10
100
؎10
100
V
mA
Ω
VOUT
=
10 V
Open Loop
5
5
5
FREQUENCY RESPONSE
Gain Bandwidth Product
Full Power Bandwidth4
V
OUT = 90 mV
80
80
80
MHz
VO = 20 V p-p
RLOAD ≥ 500 Ω
AVCL = –2
AVCL = –2
AVCL = –2
4.7
6
4.7
6
4.7
6
MHz
ns
%
Rise Time5
Overshoot5
Slew Rate5
10
20
375
10
20
375
10
20
375
300
300
300
V/µs
Settling Time5
10 V Step
to 0.1%
80
80
80
ns
to 0.01%
100
100
100
ns
Differential Gain
Differential Phase
f = 4.4 MHz
f = 4.4 MHz
0.015
0.035
0.015
0.035
0.015
0.035
%
Degree
POWER SUPPLY
Rated Performance
Operating Range
Quiescent Current
15
15
13
15
13
V
V
mA
mA
dB
dB
؎5
؎18
؎5
؎18
14
16
؎5
؎18
14
19
13/14 14/16
16/19.5
100
T
MIN–TMAX
Power Supply Rejection Ratio
VS = 5 V to 18 V
TMIN–TMAX
86
80
90
86
105
86
80
100
TEMPERATURE RANGE
Rated Performance6
0
+75
0
+75
–55
+125
°C
PACKAGE OPTIONS
Plastic (N-14)
Cerdip (Q-14)
SOIC (R-16)
AD842JN
AD842JQ
AD842JR-16
AD842KN
AD842KQ
AD842SQ, AD842SQ/883B
Tape and Reel
AD842JR-16-REEL
AD842JR-16-REEL7
AD842JH
TO-8 (H-12A)
LCC (E-20A)
Chips
AD842KH
AD842SH
AD842SE/883B
AD842SCHIPS
AD842JCHIPS
NOTES
1AD842JR specifications differ from those of the AD842JN, JQ and JH due to the thermal characteristics of the SOIC package.
2Standard Military Drawing available 5962-8964201xx
2A – (SE/883B); XA – (SH/883B); CA – (SQ/883B).
3Input offset voltage specifications are guaranteed after 5 minutes at TA = +25°C.
4Full power bandwidth = slew rate/2 π VPEAK
.
5Refer to Figures 22 and 23.
6“S” grade TMIN–TMAX specifications are tested with automatic test equipment at TA = –55°C and TA = +125°C.
All min and max specifications are guaranteed. Specifications shown in boldface are tested on all production units.
Specifications subject to change without notice.
REV. E
–2–
AD842
ABSOLUTE MAXIMUM RATINGS1
NOTES
1Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V
Internal Power Dissipation2
Plastic (N) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 W
Cerdip (Q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 W
TO-8 (H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 W
SOIC (R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 W
LCC (E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0 W
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VS
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . 6 V
Storage Temperature Range
Q, H, E . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
N, R . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to +125°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +175°C
Lead Temperature Range (Soldering 60 sec) . . . . . . . . +300°C
2Maximum internal power dissipation is specified so that TJ does not exceed
+150°C at an ambient temperature of +25°C.
Thermal Characteristics:
θJC
θJA
θSA
Plastic Package
Cerdip Package
TO-8 Package
16-Lead SOIC Package 30°C/W
20-Lead LCC Package 35°C/W
Recommended Heat Sink: Aavid Engineering© #602B
30°C/W
30°C/W
30°C/W
100°C/W
110°C/W
100°C/W
100°C/W
150°C/W
38°C/W
27°C/W
METALIZATION PHOTOGRAPH
Contact factory for latest dimensions.
Dimensions shown in inches and (mm).
REV. E
–3–
AD842–Typical Characteristics(at +25؇C and V = ؎15 V, unless otherwise noted)
S
20
20
15
10
30
25
20
15
؎ 15V SUPPLIES
15
10
؎ V
OUT
V
IN
10
5
0
5
0
5
0
10
100
1k
10k
0
5
10
15
20
0
5
10
15
20
SUPPLY VOLTAGE – ؎Volts
SUPPLY VOLTAGE – ؎ Volts
LOAD RESISTANCE – ⍀
Figure 1. Input Common-Mode
Range vs. Supply Voltage
Figure 2. Output Voltage Swing
vs. Supply Voltage
Figure 3. Output Voltage Swing
vs. Load Resistance
18
16
14
12
10
–5
–4
100
10
1
–3
–2
0.1
0.01
10k
0
5
10
15
20
100k
1M
10M
100M
–60 –40 –20
0
20 40 60 80 100 120 140
SUPPLY VOLTAGE – ؎ Volts
TEMPERATURE – ؇C
FREQUENCY – Hz
Figure 4. Quiescent Current vs.
Supply Voltage
Figure 5. Input Bias Current vs.
Temperature
Figure 6. Output Impedance vs.
Frequency
85
80
300
18
17
16
15
14
13
12
275
250
225
200
175
150
+ OUTPUT CURRENT
75
70
65
–OUTPUT CURRENT
125
100
11
10
–60 –40 –20
0
20 40 60 80 100 120 140
TEMPERATURE – ؇C
–60 –40 –20
0
20 40 60 80 100 120 140
–60 –40 –20
0
20 40 60 80 100 120 140
AMBIENT TEMPERATURE – ؇C
TEMPERATURE – ؇C
Figure 7. Quiescent Current vs.
Temperature
Figure 8. Short-Circuit Current
Limit vs. Temperature
Figure 9. Gain Bandwidth Product
vs. Temperature
REV. E
–4–
AD842
120
100
100
80
120
100
80
110
105
100
95
+ SUPPLY
80
60
40
60
40
20
60
– SUPPLY
500⍀ LOAD
40
500⍀ LOAD
20
0
0
20
0
90
100
1k
10k
100k
1M
10M 100M
0
5
10
15
20
100
1k
10k
100k
1M
10M 100M
SUPPLY VOLTAGE – ؎V
FREQUENCY – Hz
FREQUENCY – Hz
Figure 10. Open-Loop Gain and
Phase Margin vs. Frequency
Figure 11. Open-Loop Gain vs.
Supply Voltage
Figure 12. Power Supply Rejection
vs. Frequency
120
10
8
30
25
20
15
10
5
R
= 1kV
V
V
= ؎ 15V
L
S
+25؇C
= ؎15V
= 1V p-p
CM
V
+ 25؇C
S
100
80
6
4
2
0.1% 0.01%
0
0.1% 0.01%
60
–2
–4
40
20
–6
–8
–10
0
1M
1k
10k
100k
1M
10M
100M
10M
100M
30 40
50
60
70
80
90 100 110
FREQUENCY – Hz
SETTLING TIME – ns
FREQUENCY – Hz
Figure 13. Common-Mode
Rejection vs. Frequency
Figure 14. Large Signal Frequency
Response
Figure 15. Output Swing and
Error vs. Settling Time
50
40
30
20
–80
–90
550
500
450
400
350
3V RMS
L
R
= 1k⍀
–100
–110
–120
2ND HARMONIC
10
0
3RD HARMONIC
10k
–130
–140
300
250
0
100
1k
100k
10
100
1k
10k
100k
1M
10M
–60 –40 –20
20 40 60 80 100 120 140
TEMPERATURE – ؇C
FREQUENCY – Hz
FREQUENCY – Hz
Figure 16. Harmonic Distortion vs.
Frequency
Figure 17. Input Voltage vs.
Frequency
Figure 18. Slew Rate vs.
Temperature
REV. E
–5–
AD842
RF = 1k⍀
0.1F
2.2F
+VS
RIN
499⍀
=
HP3314A
FUNCTION
GENERATOR
OR
–
VOUT
AD842
+
49.9⍀
EQUIVALENT
0.1F
2.2F
499⍀
332⍀
–VS
Figure 19a. Inverting Amplifier
Configuration (DIP Pinout)
Figure 19b. Inverter Large Signal
Pulse Response
Figure 19c. Inverter Small Signal
Pulse Response
R1 = 205⍀
R
= 205⍀
F
0.1F
2.2F
+V
S
–
V
OUT
HP3314A
FUNCTION
GENERATOR
OR
AD842
+
V
IN
100⍀
0.1F
2.2F
499⍀
49.9⍀
EQUIVALENT
–V
S
Figure 20b. Noninverting Large
Signal Pulse Response
Figure 20c. Noninverting Small
Signal Pulse Response
Figure 20a. Noninverting Amplifier
Configuration (DIP Pinout)
REV. E
–6–
AD842
OFFSET NULLING
The input offset voltage of the AD842 is very low for a high
speed op amp, but if additional nulling is required, the circuit
shown in Figure 21 can be used.
ERROR
AMP
(
؋
15) TEK
7A13
TEK
7603
OSCILLOSCOPE
AD842 SETTLING TIME
Figures 22 and 24 show the settling performance of the AD842
in the test circuit shown in Figure 23.
TEK
7A16
HP6263
DDD5109
FLAT-TOP
PULSE
499⍀
499⍀
1k⍀
1k⍀
Settling time is defined as:
GENERATOR
The interval of time from the application of an ideal step
function input until the closed-loop amplifier output has
entered and remains within a specified error band.
0.1F
50⍀
+15V
2.2F
This definition encompasses the major components which com-
prise settling time. They include (1) propagation delay through
the amplifier; (2) slewing time to approach the final output value;
(3) the time of recovery from the overload associated with slew-
ing and (4) linear settling to within the specified error band.
FET PROBE
TEK P6201
AD842
0.1F
2.2F
499⍀
499⍀
–15V
Expressed in these terms, the measurement of settling time is
obviously a challenge and needs to be done accurately to assure
the user that the amplifier is worth consideration for the
application.
Figure 23. Settling Time Test Circuit
Figure 23 shows how measurement of the AD842’s 0.01% set-
tling in 100 ns was accomplished by amplifying the error signal
from a false summing junction with a very high-speed propri-
etary hybrid error amplifier specially designed to enable testing
of small settling errors. The device under test was driving a
300 Ω load. The input to the error amp is clamped in order to
avoid possible problems associated with the overdrive recovery
of the oscilloscope input amplifier. The error amp gains the
error from the false summing junction by 15, and it contains a
gain vernier to fine trim the gain.
+V
S
0.1F
2.2F
10k⍀
–
INPUT
OUTPUT
AD842
+
0.1F
2.2F
R
L
–V
S
Figure 24 shows the “long term” stability of the settling charac-
teristics of the AD842 output after a 10 V step. There is no
evidence of settling tails after the initial transient recovery time.
The use of a junction isolated process, together with careful
layout, avoids these problems by minimizing the effects of tran-
sistor isolation capacitance discharge and thermally induced
shifts in circuit operating points. These problems do not occur
even under high output current conditions.
Figure 21. Offset Nulling (DIP Pinout)
Figure 22. 0.01% Settling Time
REV. E
–7–
AD842
GROUNDING AND BYPASSING
USING A HEAT SINK
In designing practical circuits with the AD842, the user must
remember that whenever high frequencies are involved, some
The AD842 draws less quiescent power than most precision
high speed amplifiers and is specified for operation without a
heat sink. However, when driving low impedance loads, the cur-
rent to the load can be 10 times the quiescent current. This will
create a noticeable temperature rise. Improved performance can
be achieved by using a small heat sink such as the Aavid Engi-
neering #602B.
TERMINATED LINE DRIVER
The AD842 is optimized for high speed line driver applications.
Figure 25 shows the AD842 driving a doubly terminated cable
in a gain-of-2 follower configuration. The AD842 maintains a
typical slew rate of 375 V/µs, which means it can drive a 10 V,
6.0 MHz signal or a 3 V, 19.9 MHz signal.
The termination resistor, RT, (when equal to the characteristic
impedance of the cable) minimizes reflections from the far end
of the cable. A back-termination resistor (RBT, also equal to the
characteristic impedance of the cable) may be placed between
the AD842 output and the cable in order to damp any stray
signals caused by a mismatch between RT and the cable’s char-
acteristic impedance. This will result in a “cleaner” signal. With
this circuit, the voltage on the line equals VIN because one half
Figure 24. AD842 Settling Demonstrating No Settling
Tails
special precautions are in order. Circuits must be built with
short interconnect leads. Large ground planes should be used
whenever possible to provide a low resistance, low inductance
circuit path, as well as minimizing the effects of high frequency
coupling. Sockets should be avoided because the increased
interlead capacitance can degrade bandwidth.
of VOUT is dropped across RBT
.
Feedback resistors should be of low enough value to assure that
the time constant formed with the circuit capacitances will not
limit the amplifier performance. Resistor values of less than
5 kΩ are recommended. If a larger resistor must be used, a small
(<10 pF) feedback capacitor connected in parallel with the feed-
back resistor, RF, may be used to compensate for these stray
capacitances and optimize the dynamic performance of the
amplifier in the particular application.
The AD842 has 100 mA minimum output current and, there-
fore, can drive 5 V into a 50 Ω cable.
The feedback resistors, R1 and R2, must be chosen carefully.
Large value resistors are desirable in order to limit the amount
of current drawn from the amplifier output. But large resistors
can cause amplifier instability because the parallel resistance
R1ʈR2 combines with the input capacitance (typically 2–5 pF) to
create an additional pole. Also, the voltage noise of the AD842
is equivalent to a 5 kΩ resistor, so large resistors can signifi-
cantly increase the system noise. Resistor values of 1 kΩ or 2 kΩ
are recommended.
Power supply leads should be bypassed to ground as close as
possible to the amplifier pins. A 2.2 µF capacitor in parallel with
a 0.1 µF ceramic disk capacitor is recommended.
If termination is not used, cables appear as capacitive loads and
can be decoupled from the AD842 by a resistor in series with
the output.
CAPACITIVE LOAD DRIVING ABILITY
Like all wideband amplifiers, the AD842 is sensitive to capaci-
tive loading. The AD842 is designed to drive capacitive loads of
up to 20 pF without degradation of its rated performance. Ca-
pacitive loads of greater than 20 pF will decrease the dynamic
performance of the part although instability should not occur
unless the load exceeds 100 pF.
2.2F
+V
S
0.1F
50⍀ OR 75⍀
CABLE
V
+
IN
R
ST
AD842
–
TERMINATION
RESISTOR FOR
INPUT SIGNAL
0.1F
2.2F
R
T
R1
–VS
R
= R = CABLE CHARACTERISTIC
ST
T
IMPEDANCE
R2
Figure 25. Line Driver Configuration
REV. E
–8–
AD842
2.2F
0.1F
OVERDRIVE RECOVERY
Figure 26 shows the overdrive recovery capability of the AD842.
Typical recovery time is 80 ns from negative overdrive and
400 ns from positive overdrive.
+V
S
–
HP3314A
OUTPUT
PULSE GENERATOR
OR EQUIVALENT
AD842
+
0.1F
2.2F
1k⍀
1s, ؎1V SQUARE
WAVE INPUT
50⍀
–V
S
Figure 27. Overdrive Recovery Test Circuit
Figure 26. Overdrive Recovery
REV. E
–9–
AD842
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
14-Lead Cerdip Package
(Q-14)
14-Lead Plastic Package
(N-14)
0.005 (0.13) MIN
14
0.098 (2.49) MAX
0.795 (20.19)
0.725 (18.42)
8
14
8
0.310 (7.87)
0.280 (7.11)
0.220 (5.59)
7
0.240 (6.10)
7
1
1
0.325 (8.25)
0.300 (7.62)
PIN 1
0.320 (8.13)
0.290 (7.37)
PIN 1
0.785 (19.94) MAX
0.100 (2.54)
BSC
0.060 (1.52)
0.015 (0.38)
0.060 (1.52)
0.015 (0.38)
0.195 (4.95)
0.115 (2.93)
0.210 (5.33)
0.200 (5.08)
MAX
MAX
0.130
(3.30)
MIN
0.150
(3.81)
MIN
0.160 (4.06)
0.115 (2.93)
0.200 (5.08)
0.125 (3.18)
0.015 (0.381)
0.008 (0.204)
0.015 (0.38)
0.008 (0.20)
SEATING
PLANE
0.022 (0.558) 0.070 (1.77)
0.014 (0.356) 0.045 (1.15)
SEATING
PLANE
0.023 (0.58)
0.014 (0.36)
0.100
(2.54)
BSC
0.070 (1.78)
0.030 (0.76)
15°
0°
20-Terminal Leadless Ceramic Chip Carrier Package
(E-20A)
16-Lead SOIC Package
(R-16)
0.200 (5.08)
BSC
0.4133 (10.50)
0.3977 (10.00)
0.075
(1.91)
REF
0.100 (2.54)
0.064 (1.63)
0.100 (2.54) BSC
0.015 (0.38)
MIN
16
1
9
8
0.095 (2.41)
0.075 (1.90)
3
4
19
18
0.2992 (7.60)
0.2914 (7.40)
20
0.028 (0.71)
0.022 (0.56)
0.358
1
0.358 (9.09)
0.342 (8.69)
SQ
0.011 (0.28)
0.007 (0.18)
R TYP
0.075 (1.91)
REF
(9.09)
MAX
SQ
BOTTOM
VIEW
0.4193 (10.65)
0.3937 (10.00)
0.050 (1.27)
BSC
8
14
13
9
45° TYP
PIN 1
0.1043 (2.65)
0.0926 (2.35)
0.0291 (0.74)
0.0098 (0.25)
0.050 (1.27)
BSC
0.088 (2.24)
0.054 (1.37)
0.055 (1.40)
0.045 (1.14)
0.150 (3.81)
BSC
؋
45؇ 8؇
0؇
0.0192 (0.49)
0.0138 (0.35)
0.0118 (0.30)
0.0040 (0.10)
SEATING
PLANE
0.0500 (1.27)
0.0157 (0.40)
0.0125 (0.32)
0.0091 (0.23)
12-Lead Metal Can Package
(TO-8 Style)
REFERENCE PLANE
0.375 (9.53)
0.181 (4.60)
0.148 (3.76)
0.200 (5.08)
BSC
MIN
0.050 (1.27) MAX
0.100 (2.54)
BSC
7
3
8
9
1
10
11
12
6
5
4
0.400
(10.16)
BSC
0.200
(5.08)
BSC
2
0.019 (0.48)
0.016 (0.41)
0.036 (0.91)
0.026 (0.66)
0.040 (1.02) MAX
0.045 (1.14)
0.037 (0.94)
0.026 (0.66)
0.021 (0.53)
0.016 (0.41)
0.000 (0.00)
BASE & SEATING PLANE
REV. E
–10–
相关型号：
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