AD9430_10 [ADI]
12-Bit, 170/210 MSPS 3.3 V A/D Converter; 12位，二百一分之一百七十〇 MSPS 3.3 V A / D转换器
| 型号： | AD9430_10 |
| 厂家： | 
ADI |
| 描述： | 12-Bit, 170/210 MSPS 3.3 V A/D Converter |
| 文件： | 总44页 (文件大小：1513K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
12-Bit, 170/210 MSPS
3.3 V A/D Converter
AD9430
FUNCTIONAL BLOCK DIAGRAM
FEATURES
SNR = 65 dB @ fIN = 70 MHz @ 210 MSPS
ENOB of 10.6 @ fIN = 70 MHz @ 210 MSPS (–0.5 dBFS)
SFDR = 80 dBc @ fIN = 70 MHz @ 210 MSPS (–0.5 dBFS)
Excellent linearity:
DRGND DRVDD
AGND
AVDD
SENSE
VREF
AD9430
SCALABLE
REFERENCE
DNL = 0.3 LSB (typical)
INL = 0.5 LSB (typical)
2 output data options:
Demultiplexed 3.3 V CMOS outputs each @ 105 MSPS
Interleaved or parallel data output option
LVDS at 210 MSPS
700 MHz full-power analog bandwidth
On-chip reference and track-and-hold
Power dissipation = 1.3 W typical @ 210 MSPS
1.5 V input voltage range
LVDS
OUTPUTS
ADC
VIN+
VIN–
DATA,
12
TRACK-
AND-HOLD
12-BIT
PIPELINE
CORE
OVERRANGE
IN LVDS OR
2-PORT CMOS
CMOS
OUTPUTS
DS+
DS–
SELECT CMOS
OR LVDS
DCO+
DCO–
CLOCK
MANAGEMENT
CLK+
CLK–
3.3 V supply operation
S1
S2
S4
S5
Output data format option
Figure 1.
Data sync input and data clock output provided
Clock duty cycle stabilizer
APPLICATIONS
GENERAL DESCRIPTION
Wireless and wired broadband communications
Cable reverse path
Communications test equipment
Radar and satellite subsystems
Power amplifier linearization
The AD9430 is a 12-bit, monolithic, sampling analog-to-digital
converter (ADC) optimized for high performance, low power,
and ease of use. The product operates up to a 210 MSPS
conversion rate and is optimized for outstanding dynamic
performance in wideband carrier and broadband systems. All
necessary functions, including a track-and-hold (T/H) and
reference, are included on the chip to provide a complete
conversion solution.
PRODUCT HIGHLIGHTS
1. High performance.
Maintains 65 dB SNR @ 210 MSPS with a 65 MHz input.
2. Low power.
Consumes only 1.3 W @ 210 MSPS.
3. Ease of use.
The ADC requires a 3.3 V power supply and a differential
ENCODE clock for full performance operation. The digital
outputs are TTL/CMOS or LVDS compatible and support either
twos complement or offset binary format. Separate output
power supply pins support interfacing with 3.3 V CMOS logic.
LVDS output data and output clock signal allow interface
to current FPGA technology. The on-chip reference and
sample-and-hold provide flexibility in system design. Use
of a single 3.3 V supply simplifies system power supply
design.
Two output buses support demultiplexed data up to 105 MSPS
rates in CMOS mode. A data sync input is supported for proper
output data port alignment in CMOS mode, and a data clock
output is available for proper output data timing. In LVDS
mode, the chip provides data at the ENCODE clock rate.
4. Out of range (OR) feature.
The OR output bit indicates when the input signal is
beyond the selected input range.
5. Pin compatible with 10-bit AD9411 (LVDS only).
Fabricated on an advanced BiCMOS process, the AD9430 is
available in a 100-lead, surface-mount plastic package
(100 e-PAD TQFP) specified over the industrial temperature
range (–40°C to +85°C).
.
Rev. E
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2005–2010 Analog Devices, Inc. All rights reserved.
AD9430
TABLE OF CONTENTS
DC Specifications ............................................................................. 4
Analog Inputs ............................................................................. 28
Gain.............................................................................................. 28
ENCODE..................................................................................... 28
Voltage Reference ....................................................................... 28
Data Format Select..................................................................... 28
I/P Timing Select........................................................................ 28
Timing Controls ......................................................................... 28
CMOS Data Outputs.................................................................. 29
Crystal Oscillator........................................................................ 29
Optional Amplifier..................................................................... 29
Troubleshooting.......................................................................... 30
Evaluation Board, LVDS Mode .................................................... 36
Power Connector........................................................................ 36
Analog Inputs ............................................................................. 36
Gain.............................................................................................. 36
Clock ............................................................................................ 36
Voltage Reference ....................................................................... 36
Data Format Select..................................................................... 36
Data Outputs............................................................................... 36
Crystal Oscillator........................................................................ 36
Outline Dimensions....................................................................... 42
Ordering Guide .......................................................................... 42
AC Specifications.............................................................................. 6
Digital Specifications........................................................................ 7
Switching Specifications .................................................................. 8
Timing Diagrams.............................................................................. 9
Absolute Maximum Ratings.......................................................... 10
Explanation of Test Levels......................................................... 10
ESD Caution................................................................................ 10
Pin Configurations and Function Descriptions ......................... 11
Equivalent Circuits......................................................................... 15
Typical Performance Characteristics ........................................... 16
Terminology .................................................................................... 23
Application Notes ........................................................................... 25
Theory of Operation .................................................................. 25
Encode Input............................................................................... 25
Analog Input ............................................................................... 26
DS Inputs (DS+, DS–)................................................................ 26
CMOS Outputs ........................................................................... 26
LVDS Outputs............................................................................. 27
Voltage Reference ....................................................................... 27
Noise Power Ratio Testing (NPR)............................................ 27
Evaluation Board, CMOS Mode................................................... 28
Power Connector........................................................................ 28
Rev. E | Page 2 of 44
AD9430
REVISION HISTORY
Add New AD9430 EVALUATION BOARD, LVDS MODE
Section ......................................................................................... 27
Updated OUTLINE DIMENSIONS ........................................... 32
9/10—Rev. D to Rev. E
Change to General Description Section.........................................1
Change to Operating Temperature Range Parameter, Table 5..10
Change to Figure 4 ..........................................................................11
Change to Figure 5 ..........................................................................13
Added Exposed Pad Notation to Outline Dimensions ..............42
3/03—Rev. 0 to Rev. A
Upgraded for AD9430-210 ..............................................Universal
Changes to FEATURES ................................................................. 1
Changes to PRODUCT HIGHLIGHTS ...................................... 1
Changes to SPECIFICATIONS ..................................................... 2
Changes to Figure 2 ........................................................................ 5
Changes to ORDERING GUIDE .................................................. 6
Change to PIN FUNCTION DESCRIPTIONS .......................... 7
Edits to Output Propagation Delay section. .............................. 10
Added TPCs 5–8, 10–12, 14, 16, 18, 20, 22, 27, 31–32, 34 ...... 12
Changes to TPCs............................................. 17, 19, 26, 35–36, 38
Added text to ENCODE INPUT section ................................... 18
Added DS INPUTS section ..........................................................19
Change to Table I ..........................................................................19
Changes to LVDS Outputs section.............................................. 20
Changes to Voltage Reference section.........................................20
Replaced Figure 12......................................................................... 20
Change to Troubleshooting section .............................................22
Updated OUTLINE DIMENSIONS.............................................27
8/05—Rev. C to Rev. D
Change to IVREF Spec Units ...............................................................4
Changes to Minimum ENOB Specification...................................6
Added Footnote for Pin 33 in LVDS Mode ...................................7
Change to LVDS Output Section ..................................................27
Added New Evaluation Board, CMOS Mode Section................32
Updated Outline Dimensions........................................................42
11/04—Rev. B to Rev. C
Changes to Specifications ................................................................4
Changes to Figure 60 .................................................................... 31
Changes to LVDS PCB BOM ....................................................... 35
Changes to Figure 68 (Evaluation Board—LVDS Mode) ......... 36
Updated Outline Dimensions ...................................................... 40
7/03—Rev. A to Rev. B
Changed order of Figure 1 and Figure 2 ...................................... 5
Updated TPC 13 .............................................................................14
Changes to LVDS OUTPUTS section..........................................20
5/02—Revision 0: Initial Version
Rev. E | Page 3 of 44
AD9430
DC SPECIFICATIONS
AVDD = 3.3 V, DRVDD = 3.3 V, TMIN = –40°C, TMAX = +85°C, fIN = –0.5 dBFS, internal reference, full scale = 1.536 V, LVDS output mode,
unless otherwise noted.
Table 1.
AD9430-170
AD9430-210
Typ
Test
Level Min
Parameter
Temp
Typ
Max
Min
Max
Unit
RESOLUTION
12
Bits
ACCURACY
No Missing Codes
Offset Error
Gain Error
Full
VI
I
I
I
VI
I
VI
Guaranteed
Guaranteed
25°C
25°C
25°C
Full
25°C
Full
–3
–5
–1
–1
–1.5
–2.25
+3
+5
+1
+1.5
+1.5
+2.25
–3
–5
–1
–1
–1.75
–2.5
+3
+5
+1
+1.5
+1.75
+2.5
mV
% FS
LSB
LSB
LSB
LSB
Differential Nonlinearity (DNL)
ꢀ.3
ꢀ.3
ꢀ.5
ꢀ.5
ꢀ.3
ꢀ.3
ꢀ.3
ꢀ.3
Integral Nonlinearity (INL)
TEMPERATURE DRIFT
Offset Error
Gain Error
Reference Out (VREF)
REFERENCE
Full
Full
Full
V
V
V
58
ꢀ.ꢀ2
+ꢀ.12/–ꢀ.24
58
ꢀ.ꢀ2
+ꢀ.12/–ꢀ.24
μV/°C
%/°C
mV/°C
Reference Out (VREF)
Output Current1
IVREF Input Current2
ISENSE Input Current2
ANALOG INPUTS (VIN+, VIN–)3
25°C
25°C
25°C
25°C
I
IV
I
1.15
1.235
1.6
1.3
3.ꢀ
2ꢀ
1.15
1.235
1.6
1.3
3.ꢀ
2ꢀ
V
mA
μA
mA
I
5.ꢀ
5.ꢀ
Differential Input Voltage Range
(S5 = GND)
Differential Input Voltage Range
(S5 = AVDD)
Full
Full
V
V
1.536
ꢀ.766
1.536
ꢀ.766
V
V
Input Common-Mode Voltage
Input Resistance
Input Capacitance
POWER SUPPLY (LVDS Mode)
AVDD
Full
Full
25°C
VI
VI
V
2.65
2.2
2.8
3
5
2.9
3.8
2.65
2.2
2.8
3
5
2.9
3.8
V
kΩ
pF
Full
Full
IV
IV
3.1
3.ꢀ
3.3
3.3
3.6
3.6
3.2
3.ꢀ
3.3
3.3
3.6
3.6
V
V
DRVDD
Supply Currents
IANALOG (AVDD = 3.3 V)4
IDIGITAL (DRVDD = 3.3 V)4
Power Dissipation4
Power Supply Rejection
Full
Full
Full
25°C
VI
VI
VI
V
335
55
1.29
–7.5
372
62
1.43
39ꢀ
55
1.5
45ꢀ
62
1.7
mA
mA
W
–7.5
mV/V
Rev. E | Page 4 of 44
AD9430
AD9430-170
Typ
AD9430-210
Typ
Test
Level Min
Parameter
Temp
Max
Min
Max
Unit
POWER SUPPLY (CMOS Mode)
AVDD
DRVDD
Full
Full
IV
IV
3.1
3.ꢀ
3.3
3.3
3.6
3.6
3.2
3.ꢀ
3.3
3.3
3.6
3.6
V
V
Supply Currents
IAVDD (AVDD = 3.3 V)5
IDRVDD (DRVDD = 3.3 V)5
Power Dissipation5
Power Supply Rejection
Full
Full
Full
25°C
IV
IV
IV
V
335
24
1.1
372
3ꢀ
39ꢀ
3ꢀ
1.3
45ꢀ
3ꢀ
mA
mA
W
–7.5
–7.5
mV/V
1 Internal reference mode; SENSE = Floats.
2 External reference mode; SENSE = DRVDD, VREF driven by external 1.23 V reference.
3 S5 (Pin 1) = GND. See the Analog Input section. S5 = GND in all dc and ac tests, unless otherwise noted.
4 IAVDD and IDRVDD are measured with an analog input of 1ꢀ.3 MHz, –ꢀ.5 dBFS, sine wave, rated ENCODE rate, and in LVDS output mode. See Typical Performance
Characteristics and Application Notes sections for IDRVDD. Power consumption is measured with a dc input at rated ENCODE rate in LVDS output mode.
5 IAVDD and IDRVDD are measured with an analog input of 1ꢀ.3 MHz, –ꢀ.5 dBFS, sine wave, rated ENCODE rate, and in CMOS output mode. See Typical Performance
Characteristics and Application Notes sections for IDRVDD. Power consumption is measured with a dc input at rated ENCODE rate in CMOS output mode.
Rev. E | Page 5 of 44
AD9430
AC SPECIFICATIONS
AVDD = 3.3 V, DRVDD = 3.3 V, TMIN = –40°C, TMAX = +85°C, fIN = –0.5 dBFS, internal reference, full scale = 1.536 V, LVDS output mode,
unless otherwise noted.1
Table 2.
AD9430-170
AD9430-210
Parameter
Temp
Test Level
Min
Typ
Max
Min
Typ
Max
Unit
SNR
Analog Input @ –ꢀ.5 dBFS
1ꢀ MHz
7ꢀ MHz
1ꢀꢀ MHz
24ꢀ MHz
25°C
25°C
25°C
25°C
I
I
V
V
63.5
63
65
65
65
61
62.5
62.5
64.5
64.5
64.5
61
dB
dB
dB
dB
SINAD
Analog Input @ –ꢀ.5 dBFS
1ꢀ MHz
7ꢀ MHz
1ꢀꢀ MHz
24ꢀ MHz
25°C
25°C
25°C
25°C
I
I
V
V
63.5
63
65
65
65
6ꢀ
62.5
62.5
64.5
64.5
64.5
6ꢀ
dB
dB
dB
dB
EFFECTIVE NUMBER OF BITS (ENOB)
1ꢀ MHz
7ꢀ MHz
1ꢀꢀ MHz
24ꢀ MHz
25°C
25°C
25°C
25°C
I
I
V
V
1ꢀ.3
1ꢀ.3
1ꢀ.6
1ꢀ.6
1ꢀ.6
9.8
1ꢀ.2
1ꢀ.2
1ꢀ.5
1ꢀ.5
1ꢀ.5
9.8
Bits
Bits
Bits
Bits
WORST HARMONIC (2nd or 3rd)
Analog Input @ –ꢀ.5 dBFS, 1ꢀ MHz
1ꢀ MHz
7ꢀ MHz
1ꢀꢀ MHz
24ꢀ MHz
25°C
25°C
25°C
25°C
I
I
V
V
–85
–85
–77
–63
–75
–75
–84
–84
–77
–63
–74
–74
dBc
dBc
dBc
dBc
WORST HARMONIC (4th or Higher)
Analog Input @ –ꢀ.5 dBFS, 1ꢀ MHz
1ꢀ MHz
7ꢀ MHz
1ꢀꢀ MHz
24ꢀ MHz
25°C
25°C
25°C
25°C
I
I
V
V
–87
–87
–77
–63
–78
–78
–87
–87
–77
–63
–77
–77
dBc
dBc
dBc
dBc
TWO-TONE IMD2
D
F1, F2 @ −7 dBFS
25°C
25°C
V
V
–75
7ꢀꢀ
–75
7ꢀꢀ
dBc
ANALOG INPUT BANDWIDTH
MHz
1 All ac specifications tested by differentially driving CLK+ and CLK−.
2 F1 = 28.3 MHz, F2 = 29.3 MHz.
Rev. E | Page 6 of 44
AD9430
DIGITAL SPECIFICATIONS
AVDD = 3.3 V, DRVDD = 3.3 V, TMIN = –40°C, TMAX = +85°C, unless otherwise noted.
Table 3.
Test
AD9430-170
Typ
AD9430-210
Typ
Parameter
Temp
Level
Min
Max
Min
Max
Unit
ENCODE AND DS INPUTS
(CLK+, CLK–, DS+, DS–)1
Differential Input Voltage2
Common-Mode Voltage3
Input Resistance
Full
Full
Full
25°C
IV
VI
VI
V
ꢀ.2
1.375
3.2
ꢀ.2
1.375
3.2
V
V
kΩ
pF
1.5
5.5
4
1.575
6.5
1.5
5.5
4
1.575
6.5
Input Capacitance
LOGIC INPUTS (S1, S2, S4, S5)
Logic 1 Voltage
Logic ꢀ Voltage
Logic 1 Input Current
Logic ꢀ Input Current
Input Resistance
Full
Full
Full
Full
25°C
25°C
IV
IV
VI
VI
V
2.ꢀ
2.ꢀ
V
V
μA
μA
kΩ
pF
ꢀ.8
19ꢀ
1ꢀ
ꢀ.8
19ꢀ
1ꢀ
3ꢀ
4
3ꢀ
4
Input Capacitance
V
LOGIC OUTPUTS (CMOS Mode)
Logic 1 Voltage4
Full
Full
IV
IV
DRVDD
–ꢀ.ꢀ5
DRVDD
–ꢀ.ꢀ5
V
V
Logic ꢀ Voltage4
ꢀ.ꢀ5
ꢀ.ꢀ5
LOGIC OUTPUTS (LVDS Mode)4, 5
VOD Differential Output Voltage
VOS Output Offset Voltage
Output Coding
Full
Full
VI
VI
247
1.125
454
1.375
247
1.125
454
1.375
mV
V
Twos complement or binary
Twos complement or binary
1 ENCODE (Clock) and DS inputs identical on the chip. See the Equivalent Circuits section.
2 All ac specifications tested by driving CLK+ and CLK– differentially, |(CLK+) – (CLK–)| > 2ꢀꢀ mV.
3 ENCODE (Clock) inputs’ common-mode can be externally set, such that ꢀ.9 V < (CLK+ or CLK−) < 2.6 V.
4 Digital output logic levels: DRVDD = 3.3 V, CLOAD = 5 pF.
5 LVDS RTERM = 1ꢀꢀ Ω, LVDS output current set resistor (RSET) = 3.74 kΩ (1% tolerance).
Rev. E | Page 7 of 44
AD9430
SWITCHING SPECIFICATIONS
AVDD = 3.3 V, DRVDD = 3.3 V, TMIN = –40°C, TMAX = +85°C, unless otherwise noted.
Table 4.
Test
Level
VI
AD9430-170
AD9430-210
Parameter (Conditions)
Maximum Conversion Rate1
Minimum Conversion Rate1
CLK+ Pulse Width High (tEH)1
Temp
Full
Full
Full
Full
Full
Full
Min
Typ
Max
Min
Typ
Max
Unit
MSPS
MSPS
ns
17ꢀ
21ꢀ
V
4ꢀ
4ꢀ
IV
2
12.5
12.5
2
12.5
12.5
CLK+ Pulse Width Low (tEL)1
IV
2
2
ns
2
DS Input Setup Time (tSDS
)
IV
IV
–ꢀ.5
1.75
–ꢀ.5
1.75
ns
ns
2
DS Input Hold Time (tHDS
OUTPUT (CMOS Mode)
Valid Time (tV)
)
Full
Full
25°C
25°C
Full
Full
Full
Full
IV
IV
V
2
2
ns
ns
ns
ns
ns
ns
Cycles
Cycles
Propagation Delay (tPD)
3.8
1
5
3.8
1
5
Rise Time (tR) (2ꢀ% to 8ꢀ%)
Fall Time (tF) (2ꢀ% to 8ꢀ%)
DCO Propagation Delay (tCPD
V
1
1
)
)
IV
IV
IV
IV
3.8
ꢀ
5
+ꢀ.5
3.8
ꢀ
5
+ꢀ.5
Data to DCO Skew (tPD to tCPD
–ꢀ.5
2.ꢀ
–ꢀ.5
2.ꢀ
Interleaved Mode (A, B Latency)
Parallel Mode (A, B Latency)
OUTPUT (LVDS Mode)
14, 14
15, 14
14, 14
15, 14
Valid Time (tV)
Full
Full
25°C
25°C
Full
VI
VI
V
ns
ns
ns
ns
ns
ns
Cycles
ns
Propagation Delay (tPD)
Rise Time (tR) (2ꢀ% to 8ꢀ%)
Fall Time (tF) (2ꢀ% to 8ꢀ%)
DCO Propagation Delay (tCPD
Data to DCO Skew (tPD – tCPD
3.2
ꢀ.5
ꢀ.5
2.7
ꢀ.5
14
4.3
3.2
ꢀ.5
ꢀ.5
2.7
ꢀ.5
14
4.3
V
)
)
VI
IV
IV
V
1.8
ꢀ.2
3.8
ꢀ.8
1.8
ꢀ.2
3.8
ꢀ.8
Full
Full
Latency
APERTURE DELAY (tA)
25°C
25°C
25°C
1.2
ꢀ.25
1.2
ꢀ.25
APERTURE UNCERTAINTY (Jitter, tJ)
V
ps rms
Cycles
OUT OF RANGE RECOVERY TIME (CMOS and LVDS)
V
1
1
1 All ac specifications tested by differentially driving CLK+ and CLK−.
2 DS inputs used in CMOS mode only.
Rev. E | Page 8 of 44
AD9430
TIMING DIAGRAMS
CLK+
CLK–
DS+
DS–
tSDS
tHDS
tPD
tV
14 CYCLES
INVALID
INTERLEAVED DATA OUT
STATIC
PORT A
DA11–DA0
INVALID
N
N+2
PORT B
DB11–DB0
STATIC
INVALID
N+1
N+3
PARALLEL DATA OUT
STATIC
PORT A
DA11–DA0
INVALID
INVALID
INVALID
INVALID
N
N+2
N+3
PORT B
DB11–DB0
STATIC
STATIC
N+1
tCPD
DCO–
DCO+
Figure 2. CMOS Timing Diagram
N–1
N
N+1
A
IN
tEL
tEH
1/f
S
CLK+
CLK–
tPD
N–14
N
N+1
N–13
DATA OUT
14 CYCLES
DCO+
DCO–
tCPD
Figure 3. LVDS Timing Diagram
Rev. E | Page 9 of 44
AD9430
ABSOLUTE MAXIMUM RATINGS
Table 5.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational section
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Parameter
Rating
AVDD, DRVDD
4 V
Analog Inputs
Digital Inputs
REFIN Inputs
−ꢀ.5 V to AVDD + ꢀ.5 V
−ꢀ.5 V to DRVDD + ꢀ.5 V
–ꢀ.5 V to AVDD + ꢀ.5 V
2ꢀ mA
−4ꢀ°C to +85°C
−65°C to +15ꢀ°C
15ꢀ°C
Digital Output Current
Operating Temperature Range
Storage Temperature Range
Maximum Junction Temperature
Maximum Case Temperature
EXPLANATION OF TEST LEVELS
Table 6.
Level
Description
15ꢀ°C
25°C/W, 32°C/W
1
I
1ꢀꢀ% production tested.
θJA
II
1ꢀꢀ% production tested at 25°C and sample tested at
specified temperatures.
Sample tested only.
1 Typical θJA = 32°C/W (heat slug not soldered); typical θJA = 25°C/W (heat slug
soldered) for multilayer board in still air with solid ground plane.
III
IV
Parameter is guaranteed by design and
characterization testing.
V
Parameter is a typical value only.
VI
1ꢀꢀ% production tested at 25°C; guaranteed by
design and characterization testing for industrial
temperature range; 1ꢀꢀ% production tested at
temperature extremes for military devices.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4ꢀꢀꢀ V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. E | Page 1ꢀ of 44
AD9430
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
75
74
73
72
DRVDD
DRGND
DA4
1
S5
PIN 1
2
DNC
3
S4
DA3
4
AGND
71 DA2
5
S2
70 DA1
6
S1
69 DA0
7
DNC
68 DNC
67 DRGND
8
AVDD
9
AGND
AD9430
DNC
66
65
64
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
SENSE
VREF
AGND
AGND
AVDD
AVDD
AGND
AGND
AVDD
AVDD
AGND
VIN+
CMOS PINOUT
TOP VIEW
(Not to Scale)
DNC
DCO+
63 DCO–
62 DRVDD
61 DRGND
60 OR_B
59 DB11
58 DB10
57 DB9
56
55
54
53
52
51
DB8
DB7
DRVDD
DRGND
DB6
VIN–
AGND
AVDD
AGND
DB5
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
NOTES
1. THE AD9430 HAS A CONDUCTIVE HEAT SLUG TO HELP DISSIPATE HEAT AND ENSURE RELIABLE OPERATION OF
THE DEVICE OVER THE FULL INDUSTRIAL TEMPERATURE RANGE. THE SLUG IS EXPOSED ON THE BOTTOM OF
THE PACKAGE AND ELECTRICALLY CONNECTED TO CHIP GROUND. IT IS RECOMMENDED THAT NO PCB SIGNAL
TRACES OR VIAS BE LOCATED UNDER THE PACKAGE THAT COULD COME IN CONTACT WITH THE CONDUCTIVE
SLUG. ATTACHING THE SLUG TO A GROUND PLANE WILL REDUCE THE JUNCTION TEMPERATURE OF THE
DEVICE WHICH MAY BE BENEFICIAL IN HIGH TEMPERATURE ENVIRONMENTS.
Figure 4. CMOS Dual-Mode Pin Configuration
Table 7. CMOS Mode Pin Function Descriptions
Pin Number
Mnemonic Description
1
S5
Full-Scale Adjust Pin. AVDD sets fS = 0.768 V p-p differential,
GND sets fS = 1.536 V p-p differential.
2, 7, 42, 43, 65, 66, 68
3
4, 9, 12, 13, 16, 17, 20, 23, 25, 26, 30, 31, 35, 38, 41, 86,
87, 91, 92, 93, 96, 97, 100
DNC
S4
AGND1
Do Not Connect.
Interleaved, Parallel Select Pin. High = interleaved.
Analog Ground.
5
6
S2
S1
Output Mode Select. Low = dual-port CMOS, high = LVDS.
Data Format Select. Low = binary, high = twos complement for
both CMOS and LVDS modes.
8, 14, 15, 18, 19, 24, 27, 28, 29, 34, 39, 40, 88, 89, 90, 94,
95, 98, 99
AVDD
3.3 V Analog Supply.
10
11
21
22
32
33
SENSE
VREF
VIN+
VIN–
DS+
Reference Mode Select Pin. Float for internal reference operation.
1.235 V Reference I/O—Function Dependent on SENSE.
Analog Input—True.
Analog Input—Complement.
Data Sync (Input)—True. Tie low if not used.
Data Sync (Input)—Complement. Tie high if not used.
DS–2
Rev. E | Page 11 of 44
AD9430
Pin Number
Mnemonic Description
36
37
44
45
CLK+
CLK–
DB0
DB1
DB2
DRVDD
DRGND1
DB3
DB4
DB5
DB6
DB7
DB8
DB9
DB10
DB11
OR_B
DCO–
DCO+
DA0
Clock Input—True.
Clock Input—Complement.
B Port Output Data Bit (LSB).
B Port Output Data Bit.
B Port Output Data Bit.
3.3 V Digital Output Supply (3.0 V to 3.6 V).
Digital Output Ground.
B Port Output Data Bit.
B Port Output Data Bit.
B Port Output Data Bit.
B Port Output Data Bit.
B Port Output Data Bit.
B Port Output Data Bit.
B Port Output Data Bit.
B Port Output Data Bit.
B Port Output Data Bit (MSB).
B Port Overrange.
Data Clock Output—Complement.
Data Clock Output—True.
A Port Output Data Bit (LSB).
A Port Output Data Bit.
A Port Output Data Bit.
A Port Output Data Bit.
A Port Output Data Bit.
A Port Output Data Bit.
A Port Output Data Bit.
A Port Output Data Bit.
A Port Output Data Bit.
A Port Output Data Bit.
A Port Output Data Bit.
A Port Output Data Bit (MSB).
A Port Overrange.
46
47, 54, 62, 75, 83
48, 53, 61, 67, 74, 82
49
50
51
52
55
56
57
58
59
60
63
64
69
70
71
72
73
76
77
78
79
80
81
84
85
DA1
DA2
DA3
DA4
DA5
DA6
DA7
DA8
DA9
DA10
DA11
OR_A
1 AGND and DRGND should be tied together to a common ground plane.
2 DS Complement (DS−); can be tied to AVDD (as recommended) or left floating with no ill effects.
Rev. E | Page 12 of 44
AD9430
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
75
74
73
72
71
70
DRVDD
DRGND
D8+
1
S5
DNC
PIN 1
2
3
S4
D8–
4
AGND
S2
D7+
5
D7–
6
S1
69 D6+
7
LVDSBIAS
AVDD
AGND
SENSE
VREF
AGND
AGND
AVDD
AVDD
AGND
AGND
AVDD
AVDD
AGND
VIN+
68 D6–
8
67 DRGND
66 D5+
9
AD9430
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
LVDS PINOUT
TOP VIEW
(Not to Scale)
D5–
65
64
DCO+
63 DCO–
62 DRVDD
61 DRGND
60 D4+
59 D4–
58 D3+
57 D3–
56 D2+
55
54
53
52
51
D2Ð
DRVDD
DRGND
D1+
VIN–
AGND
AVDD
AGND
D1–
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
NOTES
1. THE AD9430 HAS A CONDUCTIVE HEAT SLUG TO HELP DISSIPATE HEAT AND ENSURE RELIABLE OPERATION OF
THE DEVICE OVER THE FULL INDUSTRIAL TEMPERATURE RANGE. THE SLUG IS EXPOSED ON THE BOTTOM OF
THE PACKAGE AND ELECTRICALLY CONNECTED TO CHIP GROUND. IT IS RECOMMENDED THAT NO PCB SIGNAL
TRACES OR VIAS BE LOCATED UNDER THE PACKAGE THAT COULD COME IN CONTACT WITH THE CONDUCTIVE
SLUG. ATTACHING THE SLUG TO A GROUND PLANE WILL REDUCE THE JUNCTION TEMPERATURE OF THE
DEVICE WHICH MAY BE BENEFICIAL IN HIGH TEMPERATURE ENVIRONMENTS.
Figure 5. LVDS Mode Pin Configuration
Table 8. LVDS Mode Pin Function Descriptions
Pin Number
Mnemonic Description
1
S5
Full-Scale Adjust Pin. AVDD sets fS = 0.768 V p-p differential,
GND sets fS = 1.536 V p-p differential.
Do Not Connect.
Control Pin for CMOS Mode. Tie low when operating in LVDS
mode.
2, 42 to 46
3
DNC
S4
4, 9, 12, 13, 16, 17, 20, 23, 25, 26, 30, 31, 35, 38, 41, 86, 87, 91,
92, 93, 96, 97, 100
AGND1
Analog Ground.
5
6
7
S2
S1
LVDSBIAS
Output Mode Select. GND = dual-port CMOS; AVDD = LVDS.
Data Format Select. GND = binary, AVDD = twos complement.
Set Pin for LVDS Output Current. Place 3.74 kW resistor
terminated to ground.
8, 14, 15, 18, 19, 24, 27, 28, 29, 33, 34, 39, 40, 88, 89, 90, 94, 95,
98, 99
10
AVDD2
SENSE
3.3 V Analog Supply.
Reference Mode Select Pin. Float for internal reference
operation.
11
21
VREF
VIN+
1.235 V Reference I/O—Function Dependent on SENSE.
Analog Input—True.
Rev. E | Page 13 of 44
AD9430
Pin Number
Mnemonic Description
22
32
36
37
VIN–
GND
CLK+
CLK–
DRVDD
DRGND1
D0–
D0+
D1–
D1+
D2–
Analog Input—Complement.
Data Sync (Input)—Not Used in LVDS Mode. Tie to GND.
Clock Input—True (LVPECL Levels).
Clock Input—Complement (LVPECL Levels).
3.3 V Digital Output Supply (3.0 V to 3.6 V).
Digital Output Ground.
D0 Complement Output Bit (LSB).
D0 True Output Bit (LSB).
D1 Complement Output Bit.
D1 True Output Bit.
D2 Complement Output Bit.
D2 True Output Bit.
D3 Complement Output Bit.
D3 True Output Bit.
D4 Complement Output Bit.
D4 True Output Bit.
Data Clock Output—Complement.
Data Clock Output—True.
D5 Complement Output Bit.
D5 True Output Bit.
D6 Complement Output Bit.
D6 True Output Bit.
D7 Complement Output Bit.
D7 True Output Bit.
D8 Complement Output Bit.
D8 True Output Bit.
D9 Complement Output Bit.
D9 True Output Bit.
D10 Complement Output Bit.
D10 True Output Bit.
D11 Complement Output Bit.
D11 True Output Bit.
Overrange Complement Output Bit.
Overrange True Output Bit.
47, 54, 62, 75, 83
48, 53, 61, 67, 74, 82
49
50
51
52
55
56
57
58
59
60
63
64
65
66
68
69
70
71
72
73
76
77
78
79
80
81
84
85
D2+
D3–
D3+
D4–
D4+
DCO–
DCO+
D5–
D5+
D6–
D6+
D7–
D7+
D8–
D8+
D9–
D9+
D10–
D10+
D11–
D11+
OR–
OR+
1 AGND and DRGND should be tied together to a common ground plane.
2 Pin 33 can be tied to AVDD (as recommended) or left floating with no ill effects
Rev. E | Page 14 of 44
AD9430
EQUIVALENT CIRCUITS
FULL
SCALE
K
AVDD
S5 = 0 —> K = 1.24
S5 = 1 —> K = 0.62
0.1μF
VREF
12kΩ
12kΩ
10kΩ
+
–
CLK–
OR
DS–
CLK+
OR
DS+
A1
1V
150Ω
150Ω
200
Ω
10kΩ
SENSE
1kΩ
DISABLE
A1
VDD
Figure 6. ENCODE and DS Input
Figure 9. VREF, SENSE I/O
AVDD
VIN–
DRVDD
3.5kΩ
3.5k
Ω
DX
VIN+
20kΩ
20kΩ
Figure 7. Analog Inputs
Figure 10. Data Outputs (CMOS Mode)
DRVDD
VDD
V
V
DX–
V
DX+
V
S1, S2,
S4, S5
30k
Ω
Figure 8. S1 to S5 Inputs
Figure 11. Data Outputs (LVDS Mode)
Rev. E | Page 15 of 44
AD9430
TYPICAL PERFORMANCE CHARACTERISTICS
Charts at 170 MSPS, 210 MSPS for –170, –210 grades, respectively. AVDD, DRVDD = 3.3 V, T = 25°C, AIN differential drive, full
scale = 1.536 V, internal reference unless otherwise noted.
0
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
SNR = 62.99dBFS
SINAD = 61.45dBFS
H2 = –66.8dBc
H3 = –82.5dBc
SFDR = 66.1dBc
SNR = 65.2dB
SINAD = 65.1dB
H2 = –88.8dBc
H3 = –88.1dBc
SFDR = 87dBc
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
0
10
20
30
40
MHz
50
60
70
80 85
0
10
20
30
40
MHz
50
60
70
80 85
Figure 12. FFT: fs = 170 MSPS, AIN = 10.3 MHz @ −0.5 dBFS, LVDS Mode
Figure 15. FFT: fs = 170 MSPS, AIN = 10.3 MHz @ –0.5 dBFS,
Single-Ended Input, Full Scale = 0.76 V, LVDS Mode
0
0
SNR = 63.6dB
SINAD = 62.9dB
H2 = –82.5dBc
H3 = –78.6dBc
SFDR = 77.7dBc
SNR = 65.1dB
SINAD = 64.9dB
FUND = –0.50dBFS
H2 = –88.6dBc
H3 = –94.6dBc
SFDR = 85.9dBc
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
0
10
20
30
40
MHz
50
60
70
80 85
0
15
30
45
60
75
90
105
MHz
Figure 13. FFT: fs = 170 MSPS, AIN = 65 MHz @ –0.5 dBFS, LVDS Mode
Figure 16. FFT: fs = 210 MSPS, AIN = 10.3 MHZ @ –0.5 dBFS, LVDS Mode
0
0
SNR = 63.1dB
SINAD = 62.8dB
H2 = –81.1dBc
H3 = –76dBc
SNR = 64.93dB
SINAD = 64.85dB
FUND = –0.44dBFS
H2 = –92.1dBc
H3 = –90.1dBc
SFDR = 75.6dBc
–10
–10
–20
–20
–30
–40
–50
–60
–70
–80
–90
–100
SFDR = –76dBc
–30
–40
–50
–60
–70
–80
–90
–100
0
10
20
30
40
MHz
50
60
70
80 85
0
15
30
45
60
75
90
105
MHz
Figure 17. FFT: fs = 210 MSPS, AIN = 65 MHz @ –0.5 dBFS, CMOS Mode
Figure 14. FFT: fs = 170 MSPS, AIN = 65 MHz @ –0.5 dBFS, CMOS Mode
Rev. E | Page 16 of 44
AD9430
0
–10
–20
0
–10
–20
–30
–40
SNR = 63.5dB
SINAD = 62.6dB
H2 = –79dBc
H3 = –76.1dBc
SFDR = 75.2dBc
SNR = 63.3dB
SINAD = 63.1dB
H2 = –80.38dBc
H3 = –81.8dBc
SFDR = 80.8dBc
–30
–40
–50
–60
–70
–50
–60
–70
–80
–80
–90
–90
–100
–100
0
15
30
45
60
75
90
105
0
15
30
45
60
75
90
105
MHz
MHz
Figure 18. FFT: fs = 210 MSPS, AIN = 65 MHz @ –0.5 dBFS, LVDS Mode
Figure 21. FFT: fs = 213 MSP, AIN = 100 MHz @ –0.5 dBFS, LVDS Mode
85
80
85
80
75
70
65
SFDR
75
70
65
SNR
SNR
60
55
60
SINAD
55
FULL SCALE = 1.5
SINAD
FULL SCALE = 0.75
50
50
45
40
45
40
0
50
100
150
200
(MHz)
250
300
350
400
0
50
100
150
200
A (MHz)
IN
250
300
350
400
A
IN
Figure 19. SNR, SINAD, and SFDR vs. AIN Frequency, fS = 210 MSPS,
AIN @ –0.5 dBFS, LVDS Mode
Figure 22. SNR and SINAD vs. AIN Frequency, fs = 210 MSPS,
AIN @ –0.5 dBFS, LVDS Mode, Full Scale = 0.76 V
100
100
THIRD
90
90
80
70
60
50
40
THIRD
SECOND
80
SFDR
SECOND
SFDR
70
60
50
40
0
50
100
150
200
(MHz)
250
300
350
400
0
50
100
150
200
250
300
350
400
A
A
(MHz)
IN
IN
Figure 23. Harmonic Distortion (2nd and 3rd) and
SFDR vs. AIN Frequency, fs = 170 MSPS, CMOS Mode
Figure 20. Harmonic Distortion (2nd and 3rd
and SFDR vs. AIN Frequency
)
Rev. E | Page 17 of 44
AD9430
70
68
66
64
62
60
58
56
54
52
0
–30
–170 SNR
–210 SNR
–60
SFDR = 63dBc
–210 SINAD
–170 SINAD
–90
50
0
–120
50
100
150
200
(MHz)
250
300
350
400
0
10
20
30
40
50
MHz
60
70
80
90 100
A
IN
Figure 24. SNR and SINAD vs. AIN Frequency, fs = 170 MSPS/210 MSPS,
AIN @ –0.5 dBFS, LVDS Mode
Figure 27. Two-Tone Intermodulation Distortion (59 MHz and 60 MHz),
LVDS Mode, fs = 210 MSPS
95
90
85
85
80
75
SFDR
SFDR
70
80
65
75
70
65
SNR
60
55
SINAD
SINAD
50
60
45
40
55
50
0
50
100
150
200
(MHz)
250
300
350
400
0
50
100
150
200
250
MHz
A
IN
Figure 28. SINAD and SFDR vs. Clock Rate
(AIN = 10.3 MHz @ –0.5 dBFS, LVDS Mode), –170 Grade
Figure 25. SNR and SINAD, SFDR vs. AIN Frequency,
fs = 210 MSPS, AIN @ –0.5 dBFS, CMOS Mode
85
80
75
70
65
60
55
50
45
40
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
SFDR = 75dBc
SFDR
SNR
SINAD
0
50
100
150
200
250
0
10
20
30
40
MHz
50
60
70
80 85
MHz
Figure 26. Two-Tone Intermodulation Distortion
(28.3 MHz and 29.3 MHz, LVDS Mode, fs = 170 MSPS)
Figure 29. SNR and SINAD, SFDR vs. Clock Rate
(AIN = 10.3 MHz, @ –0.5 dBFS), LVDS Mode, –210 Grade
Rev. E | Page 18 of 44
AD9430
80
75
70
65
60
55
50
400
350
300
250
200
150
100
50
80
60
40
20
0
ANALOG SUPPLY
CURRENT CMOS
MODE
SFDR
ANALOG SUPPLY
CURRENT LVDS
MODE
OUTPUT SUPPLY
CURRENT LVDS
MODE
SNR
SINAD
OUTPUT SUPPLY
CURRENT CMOS
MODE
0
100
20
30
40
50
60
70
80
120
140
160
180
200
220
ENCODE POSITIVE DUTY CYCLE (%)
ENCODE (MSPS)
Figure 30. IAVDD and IDRVDD vs. Clock Rate (AIN = 10.3 MHz @ –0.5 dBFS)
170 MSPS Grade, CLOAD = 5 pF
Figure 33. SNR, SINAD, and SFDR vs. ENCODE Pulse Width High,
(AIN = 10.3 MHz @ –0.5 dBFS, 210 MSPS, LVDS)
450
400
350
300
250
200
150
100
50
90
80
70
60
50
40
30
20
10
0
1.4
ANALOG SUPPLY
CURRENT LVDS MODE
1.2
R
= 13Ω TYP
O
ANALOG SUPPLY
CURRENT CMOS MODE
1.0
0.8
0.6
0.4
0.2
0
OUTPUT SUPPLY
CURRENT LVDS MODE
OUTPUT SUPPLY
CURRENT CMOS MODE
0
100
120
140
160
180
200
220
240
0
1
2
3
4
5
6
7
8
ENCODE (MSPS)
I
(mA)
LOAD
Figure 34. VREFOUT vs. ILOAD
Figure 31. IAVDD and IDRVDD vs. Clock Rate
(AIN = 10.3 MHz @ –0.5 dBFS), 210 MSPS Grade, CLOAD = 5 pF
85
2.0
1.5
80
75
70
65
60
55
50
SFDR
1.0
0.5
% GAIN ERROR
USING EXT REF
0
SNR
–0.5
–1.0
–1.5
–2.0
SINAD
10
20
30
40
50
60
70
80
90
–50
–30
–10
10
30
50
70
90 95
ENCODE POSITIVE DUTY CYCLE (%)
TEMPERATURE (°C)
Figure 35. Full-Scale Gain Error vs. Temperature
(AIN = 10.3 MHz @ –0.5 dBFS, 170 MSPS/210 MSPS, LVDS)
Figure 32. SINAD and SFDR vs. Clock Pulse Width High
(AIN = 10.3 MHz @ –0.5 dBFS, 170 MSPS, LVDS)
Rev. E | Page 19 of 44
AD9430
1.250
1.00
0.75
0.50
0.25
0
1.245
1.240
1.235
–0.25
–0.50
–0.75
–1.00
1.230
1.225
2.5
2.7
2.9
3.1
3.3
3.5
3.7
3.9
0
500
1000 1500 2000 2500 3000
CODE
3500 4000
AVDD (V)
Figure 36. VREF Output Voltage vs. AVDD
Figure 39. Typical INL Plot (AIN = 10.3 MHz @ –0.5 dBFS, 170 MSPS, LVDS)
95
90
85
80
75
70
65
1.00
0.75
0.50
0.25
0
THIRD
SECOND
SFDR
–0.25
–0.50
–0.75
–1.00
SNR
SINAD
70 90
60
–50
–30
–10
10
30
50
0
500
1000
1500
2000
2500
3000
3500
4000
TEMPERATURE (°C)
CODE
Figure 40. Typical DNL Plot (AIN = 10.3 MHz @ –0.5 dBFS)
Figure 37. SNR, SINAD, and SFDR vs. Temperature
(AIN = 10.3 MHz @ –0.5 dBFS, 170 MSPS)
100
90
80
70
60
50
40
30
20
10
0
65
64
63
62
61
60
59
58
57
56
55
AVDD = 3.6
AVDD = 3.3
SFDR –dBFS
AVDD = 3.135
SFDR –dBc
80dB
REFERENCE LINE
AVDD = 3.0
–100 –90 –80 –70 –60 –50 –40 –30 –20 –10
0
–45
–25
–5
15
35
55
75
ANALOG INPUT LEVEL (dBFS)
TEMPERATURE (°C)
Figure 41. SFDR vs. AIN Input Level ,
AIN @ 10.3 MHz, 170 MSPS, LVDS Mode
Figure 38. SINAD vs. Temperature, AVDD
(AIN = 70 MHz @ –0.5 dB, 210 MSPS, LVDS Mode)
Rev. E | Page 2ꢀ of 44
AD9430
90
80
70
60
50
40
30
20
10
0
0
–20
SFDR dBc
LVDS MODE
FULL SCALE = 1.5
–40
SFDR dBc
CMOS MODE
FULL SCALE = 1.5
19.2
–60
–80
80dB REFERENCE LINE
–100
0
–90
–80
–70
–60
–50
–40
–30
–20
–10
19.2
38.4
MHz
47.6
Figure 42. SFDR vs. AIN Input Level, AIN @ 10.3 MHz, 210 MSPS,
LVDS/CMOS Modes
Figure 45. W-CDMA Four Channels Centered at 38.4 MHz,
fs = 153.6 MHz, LVDS Mode
90
90
80
70
60
50
40
30
20
10
0
SFDR
SNR
80
70
SFDR dBc
LVDS MODE
FULL SCALE = 1.5
60
50
40
30
20
10
0
SINAD
SFDR dBc
LVDS MODE
FULL SCALE = 0.75
80dB REFERENCE LINE
0
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
0.5
1.0
1.5
2.0
2.5
FULL-SCALE RANGE (V)
Figure 46. SNR, SINAD, and SFDR vs. Full-Scale Range, S5 = 0,
Full-Scale Range Varied by Adjusting VREF, 170 MSPS
Figure 43. SFDR vs. AIN Input Level, AIN @ 10.3 MHz, 210 MSPS, LVDS Mode,
Full Scale = 0.76 V/1.536 V
4.5
0
NPR = 56.95dB
ENCODE = 170MSPS
–20
NOTCH @ 19MHz
–40
4.0
–60
–80
3.5
TPD
–100
–120
–140
3.0
TCPD
2.5
2.65
21.25
MHz
42.5
–40
–20
0
20
40
60
80
100
TEMPERATURE (°C)
Figure 47. Propagation Delay vs. Temperature, LVDS Mode,
170 MSPS/210 MSPS
Figure 44. Noise Power Ratio Plot
Rev. E | Page 21 of 44
AD9430
4.5
900
800
700
600
500
400
300
200
100
0
1.4
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
V
OS
TCPD (CLOCKOUT RISING)
4.0
3.5
3.0
TPDF (DATA FALLING)
V
OD
TPDR (DATA RISING)
2.5
–40
–20
0
20
40
60
80
100
0
2
4
6
8
10
12
14
TEMPERATURE (°C)
RSET (kΩ)
Figure 48. Propagation Delay vs. Temperature,
CMOS Mode, 170 MSPS/210 MSPS
Figure 49. LVDS Output Swing, Common-Mode Voltage vs. RSET,
Placed at LVDSBIAS, 170 MSPS/210 MSPS
Rev. E | Page 22 of 44
AD9430
TERMINOLOGY
Analog Bandwidth
Full-Scale Input Power
Expressed in dBm. Computed using the following equation:
The analog input frequency at which the spectral power of the
fundamental frequency (as determined by the FFT analysis) is
reduced by 3 dB.
⎛
⎜
⎞
⎟
2
V
FULL SCALE rms
ZINPUT
0.001
⎜
⎟
PowerFULL SCALE = 10 log
⎜
⎜
⎝
⎟
⎟
⎠
Aperture Delay
The delay between the 50% point of the rising edge of the
ENCODE command and the instant at which the analog input
is sampled.
Gain Error
The difference between the measured and ideal full-scale input
voltage range of the ADC.
Aperture Uncertainty (Jitter)
The sample-to-sample variation in aperture delay.
Harmonic Distortion, Second
The ratio of the rms signal amplitude to the rms value of the
second harmonic component, reported in dBc.
Crosstalk
Coupling onto one channel being driven by a low level
(–40 dBFS) signal when the adjacent interfering channel is
driven by a full-scale signal.
Harmonic Distortion, Third
The ratio of the rms signal amplitude to the rms value of the
third harmonic component, reported in dBc.
Differential Analog Input Resistance, Differential Analog
Input Capacitance, and Differential Analog Input Impedance
The real and complex impedances measured at each analog
input port. The resistance is measured statically and the
capacitance and differential input impedances are measured
with a network analyzer.
Integral Nonlinearity
The deviation of the transfer function from a reference line
measured in fractions of 1 LSB using a best straight line
determined by a least square curve fit.
Minimum Conversion Rate
Differential Analog Input Voltage Range
The ENCODE rate at which the SNR of the lowest analog
signal frequency drops by no more than 3 dB below the
guaranteed limit.
The peak-to-peak differential voltage that must be applied to
the converter to generate a full-scale response. Peak differential
voltage is computed by observing the voltage on a single pin
and subtracting the voltage from the other pin, which is
180° out of phase. Peak-to-peak differential is computed by
rotating the input phase 180° and again taking the peak
measurement. The difference is then computed between both
peak measurements.
Maximum Conversion Rate
The ENCODE rate at which parametric testing is performed.
Output Propagation Delay
The delay between a differential crossing of CLK+ and CLK– and
the time when all output data bits are within valid logic levels.
Differential Nonlinearity
The deviation of any code width from an ideal 1 LSB step.
Noise (for Any Range Within the ADC)
Calculated as follows:
Effective Number of Bits (ENOB)
Calculated from the measured SNR based on the equation
FS
− SNRdBc − SignaldBFS
⎛
⎜
⎞
⎟
dBM
VNOISE
= Z ×0.001×10
10
⎝
⎠
SNRMEASURED −1.76dB
ENOB =
6.02
where:
Z is the input impedance.
ENCODE Pulse Width/Duty Cycle
FS is the full scale of the device for the frequency in question.
SNR is the value of the particular input level.
Signal is the signal level within the ADC, reported in dB below
full scale. This value includes input levels both thermal and
quantization noise.
Pulse width high is the minimum amount of time the ENCODE
pulse (clock pulse) should be left in a Logic 1 state to achieve
rated performance; pulse width low is the minimum time the
ENCODE pulse should be left in a low state. See the timing
implications of changing tEH in the Encode Input section. At
a given clock rate, these specifications define an acceptable
ENCODE duty cycle.
Rev. E | Page 23 of 44
AD9430
Two-Tone SFDR
Power Supply Rejection Ratio
The ratio of the rms value of either input tone to the rms value
of the peak spurious component. The peak spurious component
may or may not be an IMD product. Reported in dBc (degrades
as signal level is lowered) or in dBFS (always related back to
converter full scale).
The ratio of a change in input offset voltage to a change in
power supply voltage.
Signal-to-Noise and Distortion (SINAD)
The ratio of the rms signal amplitude (set 1 dB below full scale)
to the rms value of the sum of all other spectral components,
including harmonics but excluding dc.
Worst Other Spur
The ratio of the rms signal amplitude to the rms value of the
worst spurious component (excluding the second and third
harmonic) reported in dBc.
Signal-to-Noise Ratio (Without Harmonics)
The ratio of the rms signal amplitude (set at 1 dB below full
scale) to the rms value of the sum of all other spectral
components, excluding the first five harmonics and dc.
Transient Response Time
The time it takes for the ADC to reacquire the analog input
after a transient from 10% above negative full scale to
10% below positive full scale.
Spurious-Free Dynamic Range (SFDR)
The ratio of the rms signal amplitude to the rms value of the
peak spurious spectral component. The peak spurious
component may or may not be a harmonic. Reported in dBc
(degrades as signal level is lowered) or dBFS (always related
back to converter full scale).
Out-of-Range Recovery Time
The time it takes for the ADC to reacquire the analog input
after a transient from 10% above positive full scale to 10% above
negative full scale, or from 10% below negative full scale to
10% below positive full scale.
Two-Tone Intermodulation Distortion Rejection
The ratio of the rms value of either input tone to the rms
value of the worst third-order intermodulation product
reported in dBc.
;
Rev. E | Page 24 of 44
AD9430
APPLICATION NOTES
THEORY OF OPERATION
The AD9430 architecture is optimized for high speed and ease
of use. The analog inputs drive an integrated high bandwidth
track-and-hold circuit that samples the signal prior to
quantization by the 12-bit core. For ease of use, the part
includes an on-board reference and input logic that accepts
TTL, CMOS, or LVPECL levels. The digital output logic levels
are user selectable as standard 3 V CMOS or LVDS (ANSI-644
compatible) via Pin S2.
with it that needs to be considered in applications where the
clock rate can change dynamically, requiring a wait time of
1.5 μs to 5 μs after a dynamic clock frequency increase before
valid data is available. This circuit is always on and cannot be
disabled by the user.
The clock inputs are internally biased to 1.5 V (nominal) and
support either differential or single-ended signals. For best
dynamic performance, a differential signal is recommended. An
MC100LVEL16 performs well in the circuit to drive the clock
inputs, as illustrated in Figure 50. (For trace lengths >2 inches, a
standard LVPECL termination is recommended rather than the
simple pull-down as shown.) Note that for this low voltage
PECL device, the ac coupling is optional.
ENCODE INPUT
Any high speed ADC is extremely sensitive to the quality of the
sampling clock provided by the user. A track-and-hold circuit is
essentially a mixer, and any noise, distortion, or timing jitter on
the clock is combined with the desired signal at the A/D output.
For that reason, considerable care has been taken in the design
of the clock inputs of the AD9430, and the user is advised to
give careful thought to the clock source.
AD9430
0.1μF
CLK+
PECL
GATE
CLK–
The AD9430 has an internal clock duty cycle stabilization
circuit that locks to the rising edge of CLK+ and optimizes
timing internally. This allows for a wide range of input duty
cycles at the input without degrading performance. Jitter in
the rising edge of the input is still of paramount concern and
is not reduced by the internal stabilization circuit. The duty
cycle control loop does not function for clock rates less than
30 MHz nominally. The loop has a time constant associated
0.1μF
510Ω
510Ω
Figure 50. Driving Clock Inputs with LVEL16
In interleaved mode, output data on Port A is offset from output
data changes on Port B by one-half output clock cycle, as shown
in Figure 51.
INTERLEAVED MODE
PARALLEL MODE
Figure 51.
Table 9. Output Select Coding
S11
S21
S41
(I/P Select)
S51
(Data Format Select)
(LVDS/CMOS Mode Select)2
(Full-Scale Select)3
Mode
1
ꢀ
X
X
X
X
X
X
X
ꢀ
ꢀ
1
X
X
X
X
1
ꢀ
X
X
X
X
X
X
X
X
1
ꢀ
Twos complement
Offset binary
Dual-mode CMOS interleaved
Dual-mode CMOS parallel
LVDS mode
Full scale = ꢀ.768 V
Full scale = 1.536 V
1 X = don’t care.
2 S4 used in CMOS mode only (S2 = ꢀ). S1 to S5 all have 3ꢀ kΩ resistive pull-downs on chip.
3 S5 full-scale adjust (see the Analog Input section).
Rev. E | Page 25 of 44
AD9430
DS INPUTS (DS+, DS–)
ANALOG INPUT
In CMOS output mode, the data sync inputs (DS+, DS–) can be
used in applications that require a given sample to appear at a
specific output port (A or B) relative to a given external timing
signal. The DS inputs can also be used to synchronize two or
more ADCs in a system to maintain phasing between Port A
and Port B on separate ADCs (in effect, synchronizing multiple
DCO outputs). When DS+ is held high (DS– low), the ADC
data outputs and clock do not switch and are held static.
Synchronization is accomplished by the assertion (falling edge)
of DS+ within the timing constraints tSDS and tHDS, relative to a
clock rising edge. (On initial synchronization, tHDS is not
The analog input to the AD9430 is a differential buffer. For
best dynamic performance, impedances at VIN+ and VIN
–
should match. The analog input is optimized to provide
superior wideband performance and requires that the analog
inputs be driven differentially. SNR and SINAD performance
degrades significantly if the analog input is driven with a single-
ended signal.
A wideband transformer such as the Mini-Circuit® ADT1-1WT
can provide the differential analog inputs for applications that
require a single-ended-to-differential conversion. Both analog
inputs are self-biased by an on-chip resistor divider to a
nominal 2.8 V. (See the Equivalent Circuits section.)
relevant.) If DS+ falls within the required setup time (tSDS
)
before a given clock rising edge, N, the analog value at that
point in time is digitized and available at Port A, 14 cycles later
in interleaved mode.
Special care was taken in the design of the analog input section
of the AD9430 to prevent damage and corruption of data when
the input is overdriven. The nominal differential input range is
approximately 1.5 V p-p ~ (768 mV × 2). Note that the best
SNR performance is achieved with S5 = 0 (full scale = 1.5).
The very next sample, N + 1, is sampled by the next rising clock
edge and available at Port B, 14 cycles after that clock edge. In
dual-parallel mode, Port A has a 15-cycle latency and Port B
has a 14-cycle latency, but data is available at the same time.
Driving the DS inputs of each ADC by the same sync signal
accomplishes this. An easy way to accomplish synchronization
is by a one-time sync at power-on reset. Note that when
running the AD9430 in LVDS mode, set DS+ to ground and
DS– to 3.3 V, as the DS inputs are relevant only in CMOS
output mode, simplifying the design for some applications as
well as affording superior SNR/SINAD performance at higher
encode/analog frequencies.
S5 = GND
VIN+
768mV
2.8V
2.8V
VIN–
CMOS OUTPUTS
DIGITALOUT = ALL 1s
DIGITALOUT = ALL 0s
The off-chip drivers on the chip can be configured to provide
CMOS-compatible output levels via Pin S2. The CMOS digital
outputs (S2 = 0) are TTL/CMOS compatible for lower power
consumption. The outputs are biased from a separate supply
(DRVDD), allowing easy interface to external logic. The outputs
are CMOS devices that swing from ground to DRVDD (with no
dc load). It is recommended to minimize the capacitive load the
ADC drives by keeping the output traces short (<1 inch, for a
total CLOAD < 5 pF). When operating in CMOS mode, it is also
recommended to place low value (20 Ω) series damping
resistors on the data lines to reduce switching transient effects
on performance.
Figure 52. Differential Analog Input Range
S5 = AVDD
VIN+
768mV 2.8V
2.8V
VIN– = 2.8V
Figure 53. Single-Ended Analog Input Range
Rev. E | Page 26 of 44
AD9430
LVDS OUTPUTS
FULL
SCALE
K
The off-chip drivers on the chip can be configured to provide
LVDS-compatible output levels via Pin S2. LVDS outputs are
available when S2 = VDD and a 3.74 kΩ RSET resistor is placed
at Pin 7 (LVDSBIAS) to ground. The RSET resistor current is
ratioed on-chip, setting the output current at each output equal
to a nominal 3.5 mA (11 × IRSET). A 100 Ω differential
termination resistor placed at the LVDS receiver inputs results
in a nominal 350 mV swing at the receiver. LVDS mode
facilitates interfacing with LVDS receivers in custom ASICs and
FPGAs that have LVDS capability for superior switching
performance in noisy environments. Single point-to-point net
topologies are recommended with a 100 Ω termination resistor
as close to the receiver as possible. It is recommended to keep
the trace length three to four inches maximum and to keep
differential output trace lengths as equal as possible.
—
S5 = 0 > K = 1.24
—
S5 = 1 > K = 0.62
0.1μF
VREF
+
A1
1V
+
EXTERNAL 1.23V
REFERENCE
200Ω
SENSE
+
1kΩ
3.3V
DISABLE
A1
V
DD
Figure 54. Using an External Reference
NOISE POWER RATIO TESTING (NPR)
NPR is a test that is commonly used to characterize the return
path of cable systems where the signals are typically QAM
signals with a noise-like frequency spectrum. NPR performance
of the AD9430 was characterized in the lab yielding an effective
NPR = 56.9 dB at an analog input of 19 MHz. This agrees with
a theoretical maximum NPR of 57.1 dB for an 11-bit ADC at
13.6 dB backoff. The rms noise power of the signal inside the
notch is compared with the rms noise level outside the notch
using an FFT. Sufficiently long record lengths to guarantee a
sufficient number of samples inside the notch are a
CLOCK OUTPUTS (DCO+, DCO–)
The input ENCODE is divided by two (in CMOS mode) and
available off chip at DCO+ and DCO–. These clocks can
facilitate latching off chip, providing a low skew clocking
solution (see Figure 2). The on-chip clock buffers should not
drive more than 5 pF of capacitance to limit switching transient
effects on performance. Note that the output clocks are CMOS
levels when CMOS mode is selected (S2 = 0) and are LVDS
levels when in LVDS mode (S2 = VDD), requiring a 100 Ω
differential termination at receiver in LVDS mode. The output
clock in LVDS mode switches at the ENCODE rate.
requirement, as well as a high order band-stop filter that
provides the required notch depth for testing.
VOLTAGE REFERENCE
A stable and accurate 1.23 V voltage reference is built into the
AD9430 (VREF). The analog input full-scale range is linearly
proportional to the voltage at VREF. Note that an external
reference can be used by connecting the SENSE pin to VDD
(disabling internal reference) and driving VREF with the
external reference source. No appreciable degradation in
performance occurs when VREF is adjusted 5%. A 0.1 μF
capacitor to ground is recommended at the VREF pin in
internal and external reference applications. Float the SENSE
pin for internal reference operation.
Rev. E | Page 27 of 44
AD9430
EVALUATION BOARD, CMOS MODE
GAIN
The AD9430 evaluation board offers an easy way to test the
AD9430 in CMOS mode. It requires a clock source, an analog
input signal, and a 3.3 V power supply. The clock source is
buffered on the board to provide the clocks for the ADC,
latches, and data ready signals. The digital outputs and output
clocks are available at two 40-pin connectors, P3 and P23. The
PCB interfaces directly with ADI standard dual-channel data
capture board (HSC-ADC-EVAL-DC) which, together with
ADI ADC Analyzer software, allows for quick ADC evaluation.
The board has several different modes of operation and is
shipped in the following configurations:
Full scale is set at E17, E18, and E19. Connecting E17 to E18
sets S5 low, full scale = 1.5 V differential; connecting E17 to E19
sets S5 high, full scale = 0.75 V differential.
ENCODE
The ENCODE clock is terminated to ground through 50 ꢀ at
SMB Connector J5. The input is ac coupled to a high speed
differential receiver (LVEL16) that provides the required
low jitter, fast edge rates needed for optimum performance.
J5 input should be >0.5 V p-p. Power to the EL16 is set at
Jumper E47. Connecting E47 to E45 powers the buffer from
AVDD; connecting E47 to E46 powers the buffer from
VCLK/V_XTAL.
•
•
•
•
Offset binary
Internal voltage reference
CMOS parallel timing
Full-scale adjust = low
VOLTAGE REFERENCE
The AD9430 has an internal 1.23 V voltage reference. The ADC
uses the internal reference as the default when jumpers E24 to
E27 and E25 to E26 are left open. The full scale can be increased
by placing optional Resistor R3. The required value varies with
the process and needs to be tuned for the specific application.
Full scale can similarly be reduced by placing R4; tuning is
required here as well. An external reference can be used by
shorting the SENSE pin to 3.3 V (place Jumper E26 to E25).
The E27 to E24 jumper connects the ADC VREF pin to the
EXT_VREF pin at the power connector.
POWER CONNECTOR
Power is supplied to the board via a detachable 12-lead power
strip (three 4-pin blocks). AVDD, DRVDD, and VDL are the
minimum required power connections.
Table 10. Power Connector, CMOS Mode
AVDD 3.3 V
DRVDD 3.3 V
VDL 3.3 V
EXT_VREF
VCLK/V_XTAL
VAMP
Analog supply for ADC (35ꢀ mA)
Output supply for ADC (28 mA)
Supply for support logic and DAC (35ꢀ mA)
Optional external reference input
Supply for clock buffer/optional CRYSTAL
Supply for optional amp
DATA FORMAT SELECT
Data format select sets the output data format of the ADC.
Setting DFS (E1 to E2) low sets the output format to be offset
binary; setting DFS high (E1 to E3) sets the output to twos
complement.
ANALOG INPUTS
The evaluation board accepts a 1.3 V p-p analog input signal
centered at ground at SMB connector J4. This signal is
terminated to ground through 50 Ω by R16. The input can be
alternatively terminated at the transformer T1 secondary by
R13 and R14. T1 is a wideband RF transformer providing the
single-ended-to-differential conversion, allowing the ADC to be
driven differentially and minimizing even-order harmonics.
An optional second transformer, T2, can be placed following
T1 if desired. This provides some performance advantage
(~1 dB to 2 dB) for high analog input frequencies (>100 MHz).
If T2 is placed, two shorting traces at the pads need to be cut.
The analog signal is low-pass filtered by R41, C12 and R42, and
C13 at the ADC input.
I/P TIMING SELECT
Output timing is set at E11, E12 and E13. E12 to E11 sets S4
low for parallel output timing mode. E11 to E13 sets S4 high
for interleaved timing mode.
TIMING CONTROLS
Flexibility in latch clocking and output timing is accomplished
by allowing for clock inversion at the timing controls section of
the PCB. Each buffered clock is buffered by an XOR and can be
inverted by moving the appropriate jumper for that clock.
Rev. E | Page 28 of 44
AD9430
OPTIONAL AMPLIFIER
CMOS DATA OUTPUTS
The evaluation board as shipped uses a wideband RF
transformer in its analog path. A user can modify the board to
use the AD8351 op amp for ac- or dc-coupled applications
(see Figure 59 and Figure 60). Figure 60 shows the AD8351 in
an ac-coupled topology, while Figure 57 shows the AD8351 in
a dc-coupled application. Optimum performance is obtained
with the AD8351 ac coupled.
The ADC CMOS digital outputs are latched on the board by
four LVT574s; the latch outputs are available at the two 40-pin
connectors at Pin 11 through Pin 33 on P23 (Channel A) and
Pin 11 through Pin 33 on P3 (Channel B). The latch output
clocks (data ready) are available at Pin 37 on P23 (Channel A)
and Pin 37 on P3 (Channel B). The data-ready clocks can be
inverted at the timing controls section if needed.
R
F
∆: 4.6ns
C1 FREQ
84.65608MHz
INHI
100nF
25
OPHI
R1
50
AIN+
SINGLE-
ENDED
50
5pF
R
G
AD9430
AIN–
AD8351
DIGITAL
OUT
25
OPLO
VOCM
100nF
SOURCE
INLO
100nF
2.8V
25
1
2
Figure 57. Using the AD8351 on the AD9430 PCB
CH1
2.00V
CH2
2.00V M 5.00ns
CH2
Figure 55. Data Output and Clock @ 80-Pin Connector
CRYSTAL OSCILLATOR
An optional crystal oscillator can be placed on the board to
serve as a clock source for the PCB. Power to the oscillator is
through the VCLK pin at the power connector (also called
VCLK/V_XTAL). If an oscillator is used, ensure proper
termination for best results. The board has been tested with a
Valpey Fisher VF561 and a Vectron JN00158-163.84. Test
results for the VF561 are shown in Figure 56.
0
ENCODE 163.84MHz
ANALOG 65.02MHz
SNR 63.93dB
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
SINAD 63.87dB
FUND –0.45dBFS
2ND –85.62dBc
3RD –91.31dBc
4TH –90.54dBc
5TH –90.56dBc
6TH –91.12dBc
THD –82.21dBc
SFDR 83.93dBc
SAMPLES 8k
NOISEFLR –100.44dBFS
WORSTSP –83.93dBc
0
20
40
60
80
MHz
Figure 56. FFT—Using VF561 Crystal as Clock Source
Rev. E | Page 29 of 44
AD9430
TROUBLESHOOTING
If the board does not seem to be working correctly, try the
following:
The AD9430 evaluation board is provided as a design
example for customers of Analog Devices, Inc. ADI makes
no warranties, express, statutory, or implied, regarding
merchantability or fitness for a particular purpose.
•
•
Verify power at IC pins.
Check that all jumpers are in the correct position for the
desired mode of operation.
•
•
Verify that VREF is at 1.23 V.
Run the clock and analog inputs at low speeds (10 MSPS/
1 MHz) and monitor latch and ADC for toggling.
3.3V
3.3V
3.3V
–
–
–
+
+
+
AVDD GND DRVDDGND
VDL GND
SIGNAL
ANALOG
J4
GENERATOR
BAND-PASS
FILTER
REFIN
DATA
CAPTURE
AND
AD9430 EVALUATION BOARD
PROCESSING
10MHz
REFOUT
CLOCK
J5
SIGNAL
GENERATOR
Figure 58. Evaluation Board Connections
Rev. E | Page 3ꢀ of 44
AD9430
Table 11. CMOS PCB Evaluation Board Bill of Material
No. Quantity Reference Designator Device
Package
Value
Comments
1
47
C1, C3–C11, C15–C44,
C47, C48, C58–C62
Capacitor
ꢀ4ꢀ2
ꢀ.1 μF
C11, C18, C3ꢀ, C33,
C34, C39, C4ꢀ, C48
Not placed
2
3
4
1
1
29
C2
C12
Capacitor
Capacitor
Capacitor
ꢀ4ꢀ2
ꢀ4ꢀ2
ꢀ4ꢀ2
1ꢀ pF
2ꢀ pF
ꢀ.ꢀ1 μF
Not placed
Not placed
All .ꢀ1uF caps not
placed
C13, C14, C45, C46, C5ꢀ–C57,
C68-C84
5
6
6
8
C49, C63–C67
Capacitor
3-pin
header/jumper
CAPL
1ꢀ μF
(E3, E1, E2),( E19, E17, E18),
(E13, E11, E12),( E46, E47, E45),
(E35, E33, E34),( E32, E3ꢀ, E31),
(E29, E23, E28),( E22, E16, E21)
7
1
E26, E25, E27, E24
4-pin
header/jumper
8
9
1ꢀ
4
2
3
J1, J2, J4, J5
P3, P231
P4, P21, P22
SMA
Connector
4-pin power
connector
4-pin power
connector
SMA
Post
J2 not placed
Z5.531.3425.ꢀ
25.6ꢀ2.5453.ꢀ
Wieland
Wieland
11
3
P4, P21, P22
Detachable
connector
12
13
14
15
16
4
3
8
2
17
R1, R5, R16, R27
R2, R3, R4
R6–R8, R1ꢀ, R33–R36
R9, R11
R12, R15, R21–R26, R28–R31, R37,
R38, R43, R46, R47
Resistor
Resistor
Resistor
Resistor
Resistor
ꢀ4ꢀ2
ꢀ4ꢀ2
ꢀ6ꢀ3
ꢀ4ꢀ2
ꢀ4ꢀ2
5ꢀ Ω
3.8K Ω
1ꢀꢀ Ω
ꢀ Ω
User selected
R1 not placed
R3, R4 not placed
R34 not placed
All 17 not placed
17
18
6
2
R13, R14, R41, R42, R44, R45
Resistor
Resistor
ꢀ4ꢀ2
ꢀ4ꢀ2
25 Ω
R13, R14, R44, R45 not
placed
R17, R18
51ꢀ Ω
19
2ꢀ
2
2
R19, R2ꢀ
R39, R4ꢀ
Resistor
Resistor
ꢀ4ꢀ2
ꢀ4ꢀ2
15ꢀ Ω
1 kΩ
21
8
RZ1, RZ2, RZ3, RZ4, RZ5, RZ6, RZ7,
RZ8
Resistor pack 22ꢀ Ω SO16RES
742C163221JTR
User selected
Mini-Circuits
ADT1–1WT
CTS
22
23
1
2
L1
T1,T4
Inductor
ꢀ6ꢀ3
Not placed
T4 not placed
Transformer
CD542
24
2
T2,T3
Optional Macom
Transformer
SM-22
ETC1–1–13
Not placed
25
26
1
1
U1
U2
AD943ꢀBSV (−21ꢀ)
MC1ꢀꢀLVEL16D
TQFP1ꢀꢀ
SO8NB
ADC
Clock buffer
27
28
29
1
4
1
U3
VCX86
LVT574
JNꢀꢀ158
SO14NB
SO2ꢀ
XOR
U4, U5, U6, U7
U8
Optional XTAL
Amp
Not placed
3ꢀ
1
U9
AD8351
1 P3 and P23 are implemented as one physical 8ꢀ-pin connector, the SAMTEC TSW-14ꢀ-ꢀ8-L-D-RA.
Rev. E | Page 31 of 44
AD9430
7 6
7 7
7 8
7 9
8 0
8 1
8 2
8 3
8 4
8 5
8 6
8 7
8 8
8 9
9 0
9 1
9 2
9 3
9 4
9 5
9 6
9 7
9 8
9 9
1 0 0
5 0
4 9
4 8
4 7
4 6
4 5
4 4
4 3
4 2
4 1
4 0
3 9
3 8
3 7
3 6
3 5
3 4
3 3
3 2
3 1
3 0
2 9
2 8
2 7
2 6
D
D
G N
D V D D R
D
G N
D D D R V
G N
D
D
C
C
C
D
D
D
C
C
D
D
C
C
D
G N
G N
V C
V C
V C
G N
G N
G N
V C
V C
G N
G N
V C
V C
G N
C V C
C
D
V C
G N
C
– E N
D
C
G N
V C
D
D
C
C
C
D
G N
G N
V C
V C
V C
G N
4
T M P I C A 4 0
T M P I C A 0
4
T M P I C A 0
P 2 2
P 4
P 2 1
Figure 59. Evaluation Board Schematic—CMOS
Rev. E | Page 32 of 44
AD9430
VCC
+
C23
0.1μF
C22
0.1μF
C25
0.1μF
C24
0.1μF
C20
0.1μF
C27
0.1μF
C26
0.1μF
C29
0.1μF
C28
0.1μF
C31
0.1μF
C32
0.1μF
C64
10μF
C16
0.1μF
C17
0.1μF
C19
0.1μF
C35
0.1μF
C21
0.1μF
C38
0.1μF
GND
VCC
C68
0.01μF
C69
0.01μF
C70
0.01μF
C71
0.01μF
C72
0.01μF
C73
0.01μF
C74
0.01μF
C75
0.01μF
C76
0.01μF
C77
0.01μF
C78
0.01μF
C79
0.01μF
C80
0.01μF
C81
0.01μF
C82
0.01μF
C83
0.01μF
C84
0.01μF
GND
VCLK
GND
VAMP
GND
VDL
VREF
+
+
+
+
C67
10μF
C46
0.01μF
C50
0.01μF
C51
0.01μF
C52
0.01μF
C45
0.01μF
C44
0.1μF
C42
0.1μF
C41
0.1μF
C15
0.1μF
C37
0.1μF
C66
10μF
C14
0.01μF
C49
10μF
C48
0.1μF
C63
10μF
GND
GND
DRVDD
+
C61
C65
C62
C60
C59
C58
C53
C54
C55
C56
C57
0.1μF
10μF
0.1μF
0.1μF
0.1μF
0.1μF
0.01μF
0.01μF
0.01μF
0.01μF
0.01μF
GND
R26
R28
1kΩ
1kΩ
PLACE R30 OR R31
(POWER DOWN)
OPTIN
GND
VAMP
TO USE VF561C CRYSTAL
GND
C18
0.1μF
GND VAMP
L1
X
C30
0.1μF
R37
25Ω
L IS OPTIONAL
GND
10
VCLK
R31
1kΩ
R30
1kΩ
R15
100Ω
VOCM
VPOS
OPHI
PWDN
JN00158
1
2
R21
100Ω
C39
0.1μF
RGP1
INHI
9
8
7
R46
25Ω
6
1
2
VAMP
GND
RGP1
E/D
NC
VCC
VCLK
3
4
5
4
AMPINB
AMPIN
OUTPUTB
OUTPUT
P1
INLO
OPLO
3
GND
R38
100Ω
GND
GND
R22
100Ω
R43
25Ω
R29
0Ω
R47
25Ω
C11
0.1μF
C40
0.1μF
5
6
RGP2
COMM
U8
AD8351
U9
GND
VCLK
RGP1
R12
25Ω
R25
1.2kΩ
R23
100Ω
OPIN
P2
T2
T3
GND
ETC1-1-13
ETC1-1-13
R24
100Ω
15
15
GND
2
2
34
34
GND
GND
PR SEC
PR SEC
OPINB
INX
Figure 60. Evaluation Board Schematic—CMOS (continued)
Rev. E | Page 33 of 44
AD9430
Figure 61. PCB Top-Side Silkscreen
Figure 63. PCB Ground Layer
Figure 62. PCB Top-Side Copper
Figure 64. PCB Split Power Plane
Rev. E | Page 34 of 44
AD9430
Figure 65. PCB Bottom-Side Copper
Figure 66. PCB Bottom-Side Silkscreen
Rev. E | Page 35 of 44
AD9430
EVALUATION BOARD, LVDS MODE
The AD9430 evaluation board offers an easy way to test the
AD9430 in LVDS mode. (The board is also compatible with the
AD9411.) It requires a clock source, an analog input signal, and
a 3.3 V power supply. The clock source is buffered on the board
to provide the clocks for the ADC, latches, and a data-ready
signal. The digital outputs and output clocks are available at a
40-pin connector, P23. The board has several different modes of
operation and is shipped in the following configurations:
GAIN
Full scale is set at E17 to E19, E17 to E18 sets S5 low, full scale =
1.5 V differential; E17 to E19 sets S5 high, full scale = 0.75 V
differential. Best performance is obtained at 1.5 V full scale.
CLOCK
The CLOCK input is terminated to ground through a 50 Ω
resistor at SMB connector J5. The input is ac coupled to a high
speed differential receiver (LVEL16) that provides the required
low jitter, fast edge rates needed for optimum performance.
J5 input should be >0.5 V p-p. Power to the LVEL16 is set at
Jumper E47. E47 to E45 powers the buffer from AVDD; E47 to
E46 powers the buffer from VCLK/V_XTAL (not in Table 11).
•
•
•
Offset binary
Internal voltage reference
Full-scale adjust = low
Note that the AD9430 LVDS evaluation board does not
interface directly with the standard Analog Devices dual-
channel data capture board (HSC-ADC-EVAL-DC). An LVDS-
to-CMOS translation board is required and is available from
Analog Devices. (No translation board is required for the
AD9430 CMOS evaluation board.)
VOLTAGE REFERENCE
The AD9430 has an internal 1.23 V voltage reference. The ADC
uses the internal reference as the default when jumpers E24 to
E27 and E25 to E26 are left open. The full scale can be increased
by placing optional resistor R3. The required value varies with
the process and needs to be tuned for the specific application.
Full scale can similarly be reduced by placing R4; tuning is
required here as well. An external reference can be used by
shorting the SENSE pin to 3.3 V (place jumper E26 to E25).
Jumper E27 to E24 connects the ADC VREF pin to the
EXT_VREF pin at the power connector.
POWER CONNECTOR
Power is supplied to the board via a detachable 8-lead power
strip (two 4-pin blocks). In Table 12, VCC, DRVDD, and VDL
are the minimum required power connections, and the
LVEL16 clock buffer can be powered from VCC or VDL at
the E47 jumper.
Table 12. Power Connector, LVDS Mode
DATA FORMAT SELECT
VCC 3.3 V
DRVDD 3.3 V
VDL 3.3 V
Analog supply for ADC (35ꢀ mA)
Output supply for ADC (5ꢀ mA)
Supply for support logic
Data format select (DFS) sets the output data format of the ADC.
Setting DFS low (E1 to E2) sets the output format to be offset
binary; setting DFS high (E1 to E3) sets the output to twos
complement.
EXT_VREF
Optional external reference input
DATA OUTPUTS
ANALOG INPUTS
The ADC LVDS digital outputs are routed directly to the
connector at the card edge. Resistor pads have been placed at
the output connector to allow for termination if the connector
receiving logic does not have the required differential
termination for the data bits and DCO. Each output trace pair
should be terminated differentially at the far end of the line
with a single 100 ꢀ resistor.
The evaluation board accepts a 1.3 V p-p analog input signal
centered at ground at SMB Connector J4. This signal is
terminated to ground through 50 Ω by R16. The input can be
alternatively terminated at the T1 transformer secondary by
R13 and R14. T1 is a wideband RF transformer providing the
single-ended-to-differential conversion, allowing the ADC to
be driven differentially and minimizing even-order harmonics.
An optional second transformer, T2, can be placed following T1
if desired. This provides some performance advantage
(~1 to 2 dB) for high analog input frequencies (>100 MHz). If
T2 is placed, two shorting traces at the pads need to be cut. The
analog signal can be low-pass filtered by R41, C12 and R42, and
C13 at the ADC input. A wideband differential amplifier
(AD8351) can be configured on the PCB for dc-coupled
applications. Remove C6, C15, and C30 to prevent transformer
loading of the amp. See Figure 67, Figure 68, and Figure 69 for
more information.
CRYSTAL OSCILLATOR
An optional crystal oscillator can be placed on the board to
serve as a clock source for the PCB. Power to the oscillator is
through the VDL pin at the power connector. If an oscillator is
used, ensure proper termination for best results. The board has
been tested with a Valpey Fisher VF561 and a Vectron JN00158-
163.84.
Rev. E | Page 36 of 44
AD9430
Table 13. LVDS PCB Evaluation Board Bill of Material
No. Quantity Reference Designator Device
Package
Value
Comment
1
33
C1, C4–C11, C15–C17, C19–C32,
C35, C36, C58–C62
Capacitors
ꢀ6ꢀ3
ꢀ.1 μF
C3, C18, C39, C4ꢀ not
placed
C3, C18, C39, C4ꢀ
2
4
C33, C34, C37, C38
Capacitor
ꢀ4ꢀ2
ꢀ.1 μF
C33, C34, C37, C38 not
placed
3
4
5
6
7
4
1
2
2
2
C63–C66
C2
C12, C13
J4, J5
Capacitor
Capacitor
Capacitor
Jacks
Power connectors
Top
Power connectors
Posts
4ꢀ-pin right-angle
connector
TAJD CAPL
ꢀ6ꢀ3
ꢀ6ꢀ3
1ꢀ uF
1ꢀ pF
2ꢀ pF
C2 not placed
C12, C13 not placed
SMB
P21, P22
25.6ꢀ2.5453.ꢀ
Wieland
Z5.531.3425.ꢀ
Wieland
Digi-Key
S2131-2ꢀ-ND
ꢀ4ꢀ2
8
2
P21, P22
9
1
P23
1ꢀ
16
R1, R6–R12, R15, R31–R37
Resistor
1ꢀꢀ Ω
R1, R6–R12, R15, R31–37
Not placed
11
12
13
14
15
16
17
18
19
1
3
2
2
2
2
2
2
6
R2
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
ꢀ6ꢀ3
ꢀ6ꢀ3
ꢀ6ꢀ3
ꢀ6ꢀ3
ꢀ6ꢀ3
ꢀ6ꢀ3
ꢀ6ꢀ3
ꢀ6ꢀ3
ꢀ6ꢀ3
3.8 kΩ
5ꢀ Ω
51ꢀ Ω
15ꢀ Ω
1 kΩ
25 Ω
3.8 kΩ
25 Ω
R5, R16, R27
R17, R18
R19, R2ꢀ
R29, R3ꢀ
R41, R42
R3, R4
R13, R14
R22, R23, R24, R25, R26, R28
R13, R14 not placed
R22, R23, R24, R25, R26,
R28 not placed
1ꢀꢀ Ω
2ꢀ
4
R39, R4ꢀ, R45, R47
Resistor
ꢀ4ꢀ2
25 Ω
R39, R4ꢀ, R45, R47
not placed
21
22
23
24
25
2
1
3
2
1
R43, R44
R46
R38, R48, R49
R5ꢀ, R51
T1
T2
Resistor
Resistor
Resistor
Resistor
ꢀ4ꢀ2
ꢀ4ꢀ2
ꢀ4ꢀ2
ꢀ4ꢀ2
Mini-Circuits
ADT1-1WT
AD8351
JNꢀꢀ158 or
VF561
1ꢀ kΩ
1.2 kΩ
25 Ω
R43, R44 not placed
R46 not placed
R38, R48, R49 not placed
R5ꢀ, R51 not placed
T2 not placed
1 kΩ
RF transformer
26
27
1
1
U2
U9
RF amp
Optional crystal
oscillator
28
29
1
1
U1
U3
AD943ꢀ
MC1ꢀꢀLVEL16
TQFP-1ꢀꢀ
SO8NB
Rev. E | Page 37 of 44
AD9430
7 6
7 7
7 8
7 9
8 0
8 1
8 2
5 0
4 9
4 8
4 7
4 6
4 5
4 4
4 3
4 2
4 1
4 0
3 9
3 8
3 7
3 6
3 5
3 4
3 3
G N D
D R V D D
G N D
D R V D D 8 3
8 4
8 5
G N D
8 6
8 7
8 8
8 9
9 0
9 1
9 2
9 3
G N D
G N D
V C C
V C C
V C C
G N D
G N D
G N D
V C C
V C C
G N D
G N D
V C C
V C C
G N D
V C C
V C C
G N D
~ E N C
G N D
V C C
9 4
9 5
3 2
3 1
G N D
G N D
V C C
V C C
V C C
G N D
9 6
9 7
9 8
9 9
3 0
2 9
2 8
2 7
2 6
1 0 0
C 1 R O 4 P T M
P 2 1
C 1 R O 4 P T M
P 2 2
Figure 67. Evaluation Board Schematic—LVDS
Rev. E | Page 38 of 44
AD9430
VCC
GND
+
C64
10μF
C23
0.1μF
C22
0.1μF
C25
0.1μF
C24
0.1μF
C27
0.1μF
C26
0.1μF
C29
0.1μF
C28
0.1μF
C31
0.1μF
C16
0.1μF
C17
0.1μF
C32
0.1μF
C35
0.1μF
C19
0.1μF
C21
0.1μF
C20
0.1μF
VDL
DRVDD
VREF
+
C66
10μF
+
C63
10μF
+
C65
10μF
C61
0.1μF
C62
0.1μF
C18
0.1μF
C60
0.1μF
C59
0.1μF
C58
0.1μF
GND
GND
GND
TO USE VF561 CRYSTAL
GND
VDL
R28
100Ω
JN00158
R23
100Ω
1
2
3
E/D
VCC
6
5
4
VDL
NC
OUTPUTB
OUTPUT
P4
R22
100Ω
GND
GND
R25
100Ω
U9
GND
VDL
R24
100Ω
P5
R26
100Ω
GND
Figure 68. Evaluation Board Schematic—LVDS (continued)
R51
1kΩ
R50
1kΩ
VDL
GND
VDL
POWER DOWN
USE R43 OR R44
C38
0.1μF
C37
0.1μF
VDL
GND
GND
GND
R43
10kΩ
R44
10kΩ
U2
AD8351
R47
25Ω
GND
R38
1
2
3
4
5
PWUP
VOCM 10
C39
0Ω
C33
R49
25Ω
R39
RGP1
INHI
VPOS
OPHI
9
8
7
6
0.1μF
0.1μF
25Ω
AMPINB
AMPIN
INLO
OPLO
C40
0.1μF
C34
0.1μF
R40
25Ω
R48
25Ω
AMP IN
AMP
GND
RPG2
COMM
R45
25Ω
R46
1.2kΩ
Figure 69. Evaluation Board Schematic—LVDS (continued)
Rev. E | Page 39 of 44
AD9430
F
Figure 70. PCB Top-Side Silkscreen—LVDS
Figure 72. PCB Ground Layer—LVDS
Figure 71. PCB Top-Side Copper—LVDS
Figure 73. PCB Split Power Plane—LVDS
Rev. E | Page 4ꢀ of 44
AD9430
Figure 74. PCB Bottom-Side Copper—LVDS
Figure 75. PCB Bottom-Side Silkscreen—LVDS
Rev. E | Page 41 of 44
AD9430
OUTLINE DIMENSIONS
16.00 BSC SQ
1.20
0.75
0.60
0.45
MAX
14.00 BSC SQ
100
1
76
75
76
100
75
1
SEATING
PLANE
PIN 1
BOTTOM VIEW
(PINS UP)
TOP VIEW
(PINS DOWN)
CONDUCTIVE
HEAT SINK
51
51
25
25
26
50
50
26
0.20
0.09
1.05
1.00
0.95
6.50
NOM
7°
3.5°
0°
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.15
0.05
COPLANARITY
0.08
0.27
0.22
0.17
0.50 BSC
SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MS-026-AED-HD
Figure 76.100-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP]
(SV-100-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
AD943ꢀBSV-17ꢀ
AD943ꢀBSVZ-17ꢀ
AD943ꢀBSV-21ꢀ
AD943ꢀBSVZ-21ꢀ
Temperature Range
−4ꢀ°C to +85°C
−4ꢀ°C to +85°C
−4ꢀ°C to +85°C
−4ꢀ°C to +85°C
Package Description
Package Option
SV-1ꢀꢀ-1
SV-1ꢀꢀ-1
SV-1ꢀꢀ-1
SV-1ꢀꢀ-1
1ꢀꢀ-Lead Thin Quad Flat Package, Exposed Pad (TQFP_EP)
1ꢀꢀ-Lead Thin Quad Flat Package, Exposed Pad (TQFP_EP)
1ꢀꢀ-Lead Thin Quad Flat Package, Exposed Pad (TQFP_EP)
1ꢀꢀ-Lead Thin Quad Flat Package, Exposed Pad (TQFP_EP)
1 Z = RoHS Compliant Part.
Rev. E | Page 42 of 44
AD9430
NOTES
Rev. E | Page 43 of 44
AD9430
NOTES
©2005–2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D02607-0-9/10(E)
Rev. E | Page 44 of 44
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