AD9524BCPZ_技术文档

Jitter Cleaner and Clock Generator with

6 Differential or 13 LVCMOS Outputs

Data Sheet

AD9524

FEATURES

FUNCTIONAL BLOCK DIAGRAM

Output frequency: <1 MHz to 1 GHz

Start-up frequency accuracy: < 100 ppm (determined by

VCXO reference accuracy)

OSC

REFA,

AD9524

REFA

OUT0,

REFB,

Zero delay operation

PLL1

PLL2

OUT0

Input-to-output edge timing: < 150 ps

6 outputs: configurable LVPECL, LVDS, HSTL, and LVCMOS

6 dedicated output dividers with jitter-free adjustable delay

Adjustable delay: 63 resolution steps of ½ period of VCO

output divider

REFB

OUT1,

OUT1

REF_TEST

SCLK/SCL

SDIO/SDA

SDO

CONTRO

INTERFACE

(SPI AND I C)

L

OUT4,

OUT4

2

Output-to-output skew: < 50 ps

ZERO

DELAY

Duty-cycle correction for odd divider settings

Automatic synchronization of all outputs on power-up

Absolute output jitter: <200 fs at 122.88 MHz

Integration range: 12 kHz to 20 MHz

Distribution phase noise floor: −160 dBc/Hz

Digital lock detect

Nonvolatile EEPROM stores configuration settings

SPI- and I²C-compatible serial control port

Dual PLL architecture

OUT5,

OUT5

6-CLOCK

DISTRIBUTION

EEPROM

ZD_IN, ZD_IN

Figure 1.

GENERAL DESCRIPTION

The AD9524 provides a low power, multi-output, clock

PLL1

distribution function with low jitter performance, along with an

on-chip PLL and VCO. The on-chip VCO tunes from 3.6 GHz to

4.0 GHz.

Low bandwidth for reference input clock cleanup with

external VCXO

Phase detector rate up to 130 MHz

Redundant reference inputs

Automatic and manual reference switchover modes

Revertive and nonrevertive switching

Loss of reference detection with holdover mode

Low noise LVCMOS output from VCXO used for RF/IF

synthesizers

The AD9524 is defined to support the clock requirements for

long term evolution (LTE) and multicarrier GSM base station

designs. It relies on an external VCXO to provide the reference

jitter cleanup to achieve the restrictive low phase noise require-

ments necessary for acceptable data converter SNR performance.

The input receivers, oscillator, and zero delay receiver provide

both single-ended and differential operation. When connected

to a recovered system reference clock and a VCXO, the device

generates six low noise outputs with a range of 1 MHz to 1 GHz,

and one dedicated buffered output from the input PLL (PLL1).

The frequency and phase of one clock output relative to another

clock output can be varied by means of a divider phase select

function that serves as a jitter-free coarse timing adjustment in

increments that are equal to one-half the period of the signal

coming out of the VCO.

PLL2

Phase detector rate of up to 259 MHz

Integrated low noise VCO

APPLICATIONS

LTE and multicarrier GSM base stations

Wireless and broadband infrastructure

Medical instrumentation

Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs

Low jitter, low phase noise clock distribution

Clock generation and translation for SONET, 10Ge, 10G FC,

and other 10 Gbps protocols

An in-package EEPROM can be programmed through the serial

interface to store user defined register settings for power-up and

chip reset.

Forward error correction (G.710)

High performance wireless transceivers

ATE and high performance instrumentation

Rev. F

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AD9524* PRODUCT PAGE QUICK LINKS

Last Content Update: 02/23/2017

COMPARABLE PARTS

View a parametric search of comparable parts.

REFERENCE MATERIALS

Product Selection Guide

• RF Source Booklet

Technical Articles

EVALUATION KITS

• AD9524 Evaluation Board

• Dual-Loop Clock Generator Cleans Jitter, Provides

Multiple High-Frequency Outputs

DOCUMENTATION

DESIGN RESOURCES

• AD9524 Material Declaration

• PCN-PDN Information

• Quality And Reliability

• Symbols and Footprints

Application Notes

• AN-1066: Power Supply Considerations for AD9523,

AD9524, and AD9523-1 Low Noise Clocks

Data Sheet

• AD9524: Jitter Cleaner and Clock Generator with 6

Differential or 13 LVCMOS Outputs Data Sheet

User Guides

DISCUSSIONS

View all AD9524 EngineerZone Discussions.

• UG-169: Evaluating the AD9523/AD9524 Clock Generator

TOOLS AND SIMULATIONS

• ADIsimCLK Design and Evaluation Software

• AD9524 IBIS Model

SAMPLE AND BUY

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TECHNICAL SUPPORT

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AD9524

Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

Terminology.................................................................................... 18

Theory of Operation ...................................................................... 19

Detailed Block Diagram ............................................................ 19

Overview ..................................................................................... 19

Component Blocks—Input PLL (PLL1).................................. 20

Component Blocks—Output PLL (PLL2) .............................. 21

Clock Distribution ..................................................................... 23

Zero Delay Operation................................................................ 25

Lock Detect ................................................................................. 25

Reset Modes ................................................................................ 26

Power-Down Mode .................................................................... 26

Serial Control Port ......................................................................... 27

SPI/I²C Port Selection................................................................ 27

I²C Serial Port Operation .......................................................... 27

SPI Serial Port Operation.......................................................... 30

SPI Instruction Word (16 Bits)................................................. 31

SPI MSB/LSB First Transfers .................................................... 31

EEPROM Operations..................................................................... 34

Writing to the EEPROM ........................................................... 34

Reading from the EEPROM ..................................................... 34

Programming the EEPROM Buffer Segment......................... 35

Power Dissipation and Thermal Considerations ....................... 37

Clock Speed and Driver Mode ................................................. 37

Evaluation of Operating Conditions........................................ 37

Thermally Enhanced Package Mounting Guidelines............ 38

Control Registers............................................................................ 39

Control Register Map ................................................................ 39

Control Register Map Bit Descriptions ................................... 43

Outline Dimensions....................................................................... 56

Ordering Guide .......................................................................... 56

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description......................................................................... 1

Revision History ............................................................................... 3

Specifications..................................................................................... 4

Conditions..................................................................................... 4

Supply Current.............................................................................. 4

Power Dissipation......................................................................... 6

REFA

REFB

OSC_IN

, and ZD_IN,

REFA,

ZD_IN

, REFB,

, OSC_IN,

Input Characteristics...................................................... 6

OSC_CTRL Output Characteristics .......................................... 7

REF_TEST Input Characteristics ............................................... 7

PLL1 Characteristics .................................................................... 7

PLL1 Output Characteristics ...................................................... 7

OUT0

Distribution Output Characteristics (OUT0,

to OUT5,

OUT5

)............................................................................................ 8

Timing Alignment Characteristics ............................................ 9

Jitter and Noise Characteristics .................................................. 9

PLL2 Characteristics .................................................................... 9

PD SYNC RESET

, EEPROM_SEL,

Logic Input Pins—

,

REF_SEL...................................................................................... 10

Status Output Pins—STATUS1, STATUS0 ............................. 10

Serial Control Port—SPI Mode ................................................ 10

Serial Control Port—I²C Mode ................................................ 11

Absolute Maximum Ratings.......................................................... 12

Thermal Resistance .................................................................... 12

ESD Caution................................................................................ 12

Pin Configuration and Function Descriptions........................... 13

Typical Performance Characteristics ........................................... 15

Input/Output Termination Recommendations.......................... 17

Rev. F | Page 2 of 56

Data Sheet

AD9524

REVISION HISTORY

9/15—Rev. E to Rev. F

Changes to Bit 4, Bits [3:2] Descriptions, Table 47.....................48

Changes to Bit 3 Descriptions Table 48........................................49

Changed Bit 6 Name from Status PLL2 Feedback Clock to Status

PLL1 Feedback Clock, Table 54 ......................................................52

Changes to Features Section ............................................................1

Changes to Table 7 ............................................................................7

Changes to Table 12 ..........................................................................9

Changes to Table 40 ........................................................................44

Changes to Table 47 ........................................................................47

3/11—Rev. A to Rev. B

Added Table Summary, Table 8.......................................................7

Changes to Table 9 ............................................................................8

Changes to EEPROM Operations Section and Writing to the

EEPROM Section ............................................................................32

Changes to Addr (Hex) 0x01A, Bits[4:3], Table 30 ....................37

Changes to Bits[4:3], Table 40 .......................................................43

1/14—Rev. D to Rev. E

Change Pin 34 from VDD1.8_OUT[0:3] to VDD1.8_OUT[2:3]

and Pin 42 from NC to VDD1.8_OUT[0:1]................................13

Changes to Writing to the EEPROM Section.................................34

Added Register 0x190.....................................................................40

Changes to EEPROM Buffer Registers.........................................41

Added Table 51 ................................................................................50

1/11—Rev. 0 to Rev. A

Changes to General Description Section.......................................1

Changes to Specifications Summary Statement............................4

Changes to Test Conditions/Comments for VDD3_PLL1,

Supply Voltage for PLL1 Parameter, Table 2..................................4

Changes to Typical Configuration and Low Power Typical

Configuration Parameters, Table 3 .................................................5

Changes to Input High Voltage and Input Low Voltage

Parameters; Added Input Threshold Voltage Parameter,

Table 4 .................................................................................................5

Changed Differential Output Voltage Swing Parameters to

Differential Output Voltage Magnitude; Changes to Test

Conditions/Comments, Table 8 ......................................................7

Changed Junction Temperature Parameter from 150°C to

115°C, Table 16................................................................................11

Added Figure 14; Renumbered Sequentially...............................15

Changes to Figure 15, Figure 17, and Figure 19; Change to

Caption of Figure 21 .......................................................................16

Added PLL1 Lock Detect Section.................................................19

Changes to VCO Calibration Section...........................................21

Changed Output Mode Section to Multimode Output

Drivers; Changes to Multimode Output Drivers Section..........22

Changes to Figure 29 ......................................................................24

Changes to SPI/I2C Port Selection Section .................................25

Change to SPI Instruction Word (16 Bits) Section.....................29

Added Power Dissipation and Thermal Considerations

Section ..............................................................................................35

Changes to Table 34 to Table 36 and Table 38.............................42

Change to Register 0x0F3, Bit 1 Description, Table 47..............45

Change to Register 0x198, Bits[7:2], Table 50.............................47

Changes to Table 52 ........................................................................48

Changes to Register 0x230 and Register 0x231, Table 54..........49

2/13—Rev. C to Rev. D

Deleted VDD1.8_PLL2................................................. Throughout

Changes to Data Sheet Title ............................................................1

Added T_Jof 115°C, Table 1 ..............................................................4

Changed VDD3_PLL1, Supply Voltage for PLL1 Typical

Parameter from 22 mA to 37 mA and Changed VDD3_PLL1,

Supply Voltage for PLL1 Maximum Parameter from 25.2 mA to

43 mA, Table 2 ...................................................................................4

Changes to Table 3 ............................................................................6

Added PLL1 Characteristics Section and Table 7, Renumbered

Sequentially ........................................................................................7

Changes to Table 9 Summary Statement and Changed Differen-

tial Output Voltage Magnitude Unit from mV t o V, Table 9 ...........8

Changed Output Timing Skew Between LVPECL, HSTL, and

LVDS Outputs from 164 ps to 234 ps; Added Endnote 1;

Table 10...............................................................................................9

Changes to Pin 5 Description, Table 19 .......................................13

Changed Pin 42 from VDD1.8_PLL2 to NC, Table 19 ..............14

Changes to Figure 24 ......................................................................21

Changes to Multimode Output Drivers Section .........................24

Changes to Clock Distribution Synchronization Section..........25

Changes to Figure 29 and Added Lock Detect Section...............26

Added Reset Modes Section and Power-Down Mode Section .... 27

Changes to Pin Descriptions Section and Read Section............31

Added Figure 38; Renumbered Sequentially...............................33

Changes to Register Section Definition Group Section.............36

Changes to Power Dissipation and Thermal Considerations

Section ..............................................................................................38

Changes to Table 31 ........................................................................40

Change to Bit 4 and Bits[1:0] Description, Table 40...................45

Changes to Bit 2 Description, Table 41 and Bits[7:6]

Description, Table 42 ......................................................................46

Changes to Bits[1:0] Description, Table 43..................................47

7/10—Revision 0: Initial Version

Rev. F | Page 3 of 56

AD9524

Data Sheet

SPECIFICATIONS

f_VCXO= 122.88 MHz single-ended, REFA and REFB on differential at 30.72 MHz, f_VCO= 3932.16 MHz, doubler is off, channel control

low power mode off, divider phase =1, unless otherwise noted. Typical is given for VDD = 3.3 V 5%, and T_A= 25°C, unless otherwise

noted. Minimum and maximum values are given over the full VDD and T_A(−40°C to +85°C) variation, as listed in Table 1.

CONDITIONS

Table 1.

Parameter

Min Typ Max

Unit

Test Conditions/Comments

SUPPLY VOLTAGE

VDD3_PLL1, Supply Voltage for PLL1

VDD3_PLL2, Supply Voltage for PLL2

VDD3_REF, Supply Voltage Clock Output Drivers Reference

VDD3_OUT[x:y],¹Supply Voltage Clock Output Drivers

VDD1.8_OUT[x:y],¹Supply Voltage Clock Dividers

TEMPERATURE

3.3

1.8

V

3.3 V 5%

1.8 V 5%

Ambient Temperature Range, T_A

Junction Temperature, T_J

−40 +25 +85

115

°C

1

OUT0

x and y are the pair of differential outputs that share the same power supply. For example, VDD3_OUT[0:1] is Supply Voltage Clock Output OUT0,

(Pin 41 and Pin 40,

OUT1

respectively) and Supply Voltage Clock Output OUT1,

(Pin 38 and Pin 37, respectively).

SUPPLY CURRENT

Table 2.

Parameter

Min Typ

Max

Unit Test Conditions/Comments

SUPPLIES OTHER THAN CLOCK OUTPUT DRIVERS

VDD3_PLL1, Supply Voltage for PLL1

37

67

43

mA

Decreases by 9 mA typical if REFB is turned

off

VDD3_PLL2, Supply Voltage for PLL2

77.7

VDD3_REF, Supply Voltage Clock Output Drivers

Reference

LVPECL Mode

5

4

6

mA

Only one output driver turned on; for each

additional output that is turned on, the current

increments by 1.2 mA maximum

Only one output driver turned on; for each

additional output that is turned on, the current

increments by 1.2 mA maximum

LVDS Mode

4.8

HSTL Mode

3

3.6

4.2

mA

Values are independent of the number of

outputs turned on

Values are independent of the number of

outputs turned on

Current for each divider: f = 245.76 MHz

Channel x control register, Bit 4 = 0

CMOS Mode

3

VDD1.8_OUT[x:y],¹Supply Voltage Clock Dividers²

3.5

CLOCK OUTPUT DRIVERS—LOWER POWER MODE OFF

LVDS Mode, 7 mA

VDD3_OUT[x:y],¹Supply Voltage Clock Output Drivers

LVDS Mode, 3.5 mA

11.5

40

13.2

45

mA

f = 122.88 MHz

f = 983.04 MHz

VDD3_OUT[x:y],¹Supply Voltage Clock Output Drivers

LVPECL Compatible Mode

6.5

23

7.5

26.3

mA

f = 122.88 MHz

f = 983.04 MHz

VDD3_OUT[x:y],¹Supply Voltage Clock Output Drivers

HSTL Mode, 8 mA

13

41

14.4

46.5

mA

f = 122.88 MHz

f = 983.04 MHz

VDD3_OUT[x:y],¹Supply Voltage Clock Output Drivers

14

16.3

2.4

mA

f = 122.88 MHz

CMOS Mode (Single-Ended)

VDD3_OUT[x:y],¹Supply Voltage Clock Output Drivers

2

f = 15.36 MHz, 10 pF load

Rev. F | Page 4 of 56

Data Sheet

AD9524

Parameter

Min Typ

Max

Unit Test Conditions/Comments

CLOCK OUTPUT DRIVERS—LOWER POWER MODE ON

LVDS Mode, 7 mA

Channel x control register, Bit 4 = 1

VDD3_OUT[x:y],¹Supply Voltage Clock Output Drivers

LVDS Mode, 3.5 mA

10

27

10.8

29.8

mA

f = 122.88 MHz

f = 983.04 MHz

VDD3_OUT[x:y],¹Supply Voltage Clock Output Drivers

LVPECL Compatible Mode

6.5

23

7.5

26.3

mA

f = 122.88 MHz

f = 983.04 MHz

VDD3_OUT[x:y],¹Supply Voltage Clock Output Drivers

HSTL Mode, 16 mA

11

28

12.4

31.2

mA

f = 122.88 MHz

f = 983.04 MHz

VDD3_OUT[x:y],¹Supply Voltage Clock Output Drivers

HSTL Mode, 8 mA

20

50

24.3

59.1

mA

f = 122.88 MHz

f = 983.04 MHz

VDD3_OUT[x:y],¹Supply Voltage Clock Output Drivers

11

27

12.7

31.8

mA

f = 122.88 MHz

f = 983.04 MHz

1

OUT0

x and y are the pair of differential outputs that share the same power supply. For example, VDD3_OUT[0:1] is Supply Voltage Clock Output OUT0,

OUT1

(Pin 41 and Pin 40,

respectively) and Supply Voltage Clock Output OUT1,

(Pin 38 and Pin 37, respectively).

²The current for Pin 34 (VDD1.8_OUT[0:3]) is 2× that of the other VDD1.8_OUT[x:y] pairs.

Rev. F | Page 5 of 56

AD9524

Data Sheet

POWER DISSIPATION

Table 3.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

POWER DISSIPATION

Typical Configuration

559

593

mW

Clock distribution outputs running as follows: four LVPECL outputs

at 122.88 MHz, two LVDS outputs (3.5 mA) at 122.88 MHz,

one differential input reference at 30.72 MHz; f_VCXO= 122.88 MHz,

f_VCO= 3932.16 MHz; PLL2 BW = 530 kHz; doubler is off

PD, Power-Down

101

389

132.2

450.4

mW

PD pin pulled low, with typical configuration conditions

INCREMENTAL POWER DISSIPATION

Low Power Typical Configuration

Absolute total power with clock distribution; one LVPECL output

running at 122.88 MHz; one differential input reference at

30.72 MHz; f_VCXO= 122.88 MHz, f_VCO= 3932.16 MHz; doubler is off

Switched to One Input,

Reference Single-Ended Mode

Switched to Two Inputs,

Reference Differential Mode

−28.5

26

−8

mW

Running at 30.72 MHz

44.6

−5.1

Switched to Two Inputs,

−27.5

Reference Single-Ended Mode

Output Distribution, Driver On

LVDS

Incremental power increase (OUT1) from low power typical (3.3 V)

Single 3.5 mA LVDS output at 245.76 MHz

Single 7 mA LVDS output at 61.44 MHz

15.3

47.8

50.1

40.2

43.7

6.6

18.4

55.4

54.9

46.3

50.3

7.9

mW

LVPECL Compatible

HSTL

Single LVPECL output at 122.88 MHz

Single 8 mA HSTL output at 122.88 MHz

Single 16 mA HSTL output at 122.88 MHz

Single 3.3 V CMOS output at 15.36 MHz

Dual complementary 3.3 V CMOS output at 15.36 MHz

Dual in-phase 3.3 V CMOS output at 15.36 MHz

CMOS

9.9

11.9

REFA, REFA, REFB, REFB, OSC_IN, OSC_IN, AND ZD_IN, ZD_IN INPUT CHARACTERISTICS

Table 4.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

DIFFERENTIAL MODE

Input Frequency Range

Input Slew Rate (OSC_IN)

Common-Mode Internally

Generated Input Voltage

Input Common-Mode Range

Differential Input Voltage,

Sensitivity Frequency < 250 MHz

400

MHz

V/µs

V

400

0.6

Minimum limit imposed for jitter performance

For dc-coupled LVDS (maximum swing)

0.7

0.8

1.025

100

1.475

V

mV p-p Capacitive coupling required; can accommodate single-ended

input by ac grounding of unused input; the instantaneous voltage

on either pin must not exceed the 1.8 V dc supply rails

Differential Input Voltage,

Sensitivity Frequency > 250 MHz

200

mV p-p Capacitive coupling required; can accommodate single-ended

input by ac grounding of unused input; the instantaneous voltage

on either pin must not exceed the 1.8 V dc supply rails

Differential Input Resistance

Differential Input Capacitance

Duty Cycle

4.8

1

kΩ

pF

Duty cycle bounds are set by pulse width high and pulse width low

Pulse Width Low

Pulse Width High

1

ns

CMOS MODE SINGLE-ENDED INPUT

Input Frequency Range

Input High Voltage

250

MHz

V

1.6

Input Low Voltage

0.52

V

Input Threshold Voltage

1.0

V

When ac coupling to the input receiver, the user must dc bias the

input to 1 V; the single-ended CMOS input is 3.3 V compatible

Rev. F | Page 6 of 56

Data Sheet

AD9524

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

Input Capacitance

Duty Cycle

1

pF

Duty cycle bounds are set by pulse width high and pulse width low

Pulse Width Low

Pulse Width High

1.6

ns

OSC_CTRL OUTPUT CHARACTERISTICS

Table 5.

Parameter

OUTPUT VOLTAGE

High

Min

Typ

Max

Unit Test Conditions/Comments

VDD3_PLL1 − 0.15

V

R_LOAD> 20 kΩ

Low

150

mV

REF_TEST INPUT CHARACTERISTICS

Table 6.

Parameter

Min

Max

250

0.8

Unit Test Conditions/Comments

REF_TEST INPUT

Input Frequency Range

Input High Voltage

Input Low Voltage

MHz

V

2.0

PLL1 CHARACTERISTICS

Table 7.

Parameter

Min

Typ

−226

Max

Unit

Test Conditions/Comments

PLL1 FIGURE OF MERIT (FOM)

MAXIMUM PFD FREQUENCY

dBc/Hz

High is the initial PLL1 antibacklash pulse

width setting. The user must program

Register 0x019[4] = 1b to enable SPI control

of the antibacklash pulse width to the

setting defined in Register 0x019[3:2] and

Table 40.

Antibacklash Pulse Width

Minimum

Low

High

130

90

65

MHz

Maximum

45

PLL1 OUTPUT CHARACTERISTICS

Table 8.

Parameter¹

Min

Typ

Max

Unit Test Conditions/Comments

MAXIMUM OUTPUT FREQUENCY

Rise/Fall Time (20% to 80%)

Duty Cycle

250

387

50

MHz

ps

%

665

55

15 pF load

f = 250 MHz

45

OUTPUT VOLTAGE HIGH

Output driver static

Load current = 10 mA

Load current = 1 mA

Output driver static

Load current = 10 mA

Load current = 1 mA

VDD3_PLL1 − 0.25

VDD3_PLL1 − 0.1

V

OUTPUT VOLTAGE LOW

0.2

0.1

V

¹CMOS driver strength = strong (see Table 53).

Rev. F | Page 7 of 56

AD9524

Data Sheet

DISTRIBUTION OUTPUT CHARACTERISTICS (OUT0, OUT0 TO OUT5, OUT5)

Duty cycle performance is specified with the invert divider bit set to 1, and the divider phase bits set to 0.5. (For example, for Channel 0,

0x196[7] = 1 and 0x198[7:2] = 000001.) Output Voltage Reference VDD in Table 9 refers to the 3.3 V supply VDD3_OUT[x:y] supply.

Table 9.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

LVPECL MODE¹

Maximum Output Frequency

Rise Time/Fall Time (20% to 80%)

Duty Cycle

1

GHz

ps

%

Minimum VCO/maximum dividers

100 Ω termination across output pair

f < 500 MHz

f = 500 MHz to 800 MHz

f = 800 MHz to 1 GHz

117

50

48

49

775

147

52

54

924

47

43

40

Differential Output Voltage Magnitude 643

mV

V

Voltage across pins; output driver static

Output driver static

Common-Mode Output Voltage

SCALED HSTL MODE, 16 mA

Maximum Output Frequency

Rise Time/Fall Time (20% to 80%)

Duty Cycle

VDD − 1.5

VDD − 1.4 VDD − 1.25

1

112

50

48

49

GHz

ps

%

Minimum VCO/maximum dividers

100 Ω termination across output pair

f < 500 MHz

f = 500 MHz to 800 MHz

f = 800 MHz to 1 GHz

141

52

51

47

44

40

54

Differential Output Voltage Magnitude 1.3

1.6

1.7

V

Voltage across pins, output driver static;

nominal supply

Supply Sensitivity

0.6

mV/mV Change in output swing vs. VDD3_OUT[x:y]

(ΔV_OD/ΔVDD3)

Common-Mode Output Voltage

LVDS MODE, 3.5 mA

VDD − 1.76 VDD − 1.6 VDD − 1.42

V

Maximum Output Frequency

Rise Time/Fall Time (20% to 80%)

Duty Cycle

1

138

51

49

GHz

161

53

ps

%

100 Ω termination across output pair

f < 500 MHz

f = 500 MHz to 800 MHz

f = 800 MHz to 1 GHz

48

43

41

55

Differential Output Voltage Magnitude

Balanced

Unbalanced

247

454

50

mV

Voltage across pins; output driver static

Absolute difference between voltage

magnitude of normal pin and inverted pin

Common-Mode Output Voltage

Common-Mode Difference

1.125

1.375

50

V

mV

Output driver static

Voltage difference between output pins;

output driver static

Short-Circuit Output Current

CMOS MODE

3.5

24

mA

Output driver static

Maximum Output Frequency

Rise Time/Fall Time (20% to 80%)

Duty Cycle

250

387

50

MHz

ps

%

665

55

15 pF load

f = 250 MHz

45

Output Voltage High

Output driver static

Load current = 10 mA

Load current = 1 mA

Output driver static

Load current = 10 mA

Load current = 1 mA

VDD − 0.25

VDD − 0.1

V

Output Voltage Low

0.2

0.1

V

¹See the Multimode Output Drivers section.

Rev. F | Page 8 of 56

Data Sheet

AD9524

TIMING ALIGNMENT CHARACTERISTICS

Table 10.

Parameter

Min Typ Max Unit

Test Conditions/Comments

OUTPUT TIMING SKEW

Delay off on all outputs; maximum deviation

between rising edges of outputs; all outputs are on,

unless otherwise noted.

Between LVPECL, HSTL, and LVDS Outputs

Between CMOS Outputs

Adjustable Delay

38

234

ps

100 300

63

Single-ended true phase high-Z mode

0

Steps Resolution step; for example, 8 × 0.5/1 GHz

Resolution Step

Zero Delay

Between Input Clock Edge on REFA or

REFB to ZD_IN Input Clock Edge,

External Zero Delay Mode

500

ps

½ period of 1 GHz

150 500

PLL1 settings: PFD = 7.68 MHz, I_CP= 63.5 µA, R_ZERO= 10 kΩ,

antibacklash pulse width is at maximum, BW = 40 Hz,

REFA and ZD_IN are set to differential mode

JITTER AND NOISE CHARACTERISTICS

Table 11.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

OUTPUT ABSOLUTE RMS TIME JITTER

Application example based on a typical setup

(see Table 3); f = 122.88 MHz

LVPECL Mode, HSTL Mode, LVDS Mode

125

136

169

212

223

fs

Integrated BW = 200 kHz to 5 MHz

Integrated BW = 200 kHz to 10 MHz

Integrated BW = 12 kHz to 20 MHz

Integrated BW = 10 kHz to 61 MHz

Integrated BW = 1 kHz to 61 MHz

PLL2 CHARACTERISTICS

Table 12.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

VCO (ON CHIP)

Frequency Range

Gain

3600

4000

MHz

MHz/V

dBc/Hz

45

PLL2 FIGURE OF MERIT (FOM)

MAXIMUM PFD FREQUENCY

−226

High is the initial PLL1 antibacklash pulse width setting.

The user must program Register 0x019[4] = 1b to enable

SPI control of the antibacklash pulse width to the

setting defined in Register 0x0F2[3:2] and Table 47.

Antibacklash Pulse Width

Minimum

Low

High

259

200

135

80

MHz

Maximum

Rev. F | Page 9 of 56

AD9524

Data Sheet

LOGIC INPUT PINS—PD, SYNC, RESET, EEPROM_SEL, REF_SEL

Table 13.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

VOLTAGE

Input High

2.0

V

Input Low

0.8

V

INPUT LOW CURRENT

80

3

250

µA

The minus sign indicates that, due to the

internal pull-up resistor, current is flowing

out of the AD9524

CAPACITANCE

pF

RESET TIMING

Pulse Width Low

Inactive to Start of Register Programming

SYNC TIMING

50

100

ns

Pulse Width Low

1.5

ns

High speed clock is CLK input signal

STATUS OUTPUT PINS—STATUS1, STATUS0

Table 14.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

VOLTAGE

Output High

Output Low

2.94

V

0.4

SERIAL CONTROL PORT—SPI MODE

Table 15.

Parameter

CS (INPUT)

Voltage

Min

Max

Unit

Test Conditions/Comments

CS has an internal 40 kΩ pull-up resistor

Input Logic 1

Input Logic 0

Current

2.0

0.8

V

Input Logic 1

Input Logic 0

30

−110

µA

The minus sign indicates that, due to the

internal pull-up resistor, current is flowing out

of the AD9524

Input Capacitance

2

pF

SCLK (INPUT) IN SPI MODE

SCLK has an internal 40 kΩ pull-down resistor

in SPI mode but not in I²C mode

Voltage

Input Logic 1

Input Logic 0

2.0

0.8

V

Current

Input Logic 1

Input Logic 0

Input Capacitance

SDIO (WHEN INPUT IS IN BIDIRECTIONAL MODE)

Voltage

240

1

2

µA

pF

Input Logic 1

Input Logic 0

2.0

0.8

V

Current

Input Logic 1

Input Logic 0

Input Capacitance

1

2

µA

pF

Rev. F | Page 10 of 56

Data Sheet

AD9524

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

SDIO, SDO (OUTPUTS)

Output Logic 1 Voltage

Output Logic 0 Voltage

TIMING

Clock Rate (SCLK, 1/t_SCLK

Pulse Width High, t_HIGH

Pulse Width Low, t_LOW

SDIO to SCLK Setup, t_DS

SCLK to SDIO Hold, t_DH

2.7

V

0.4

25

)

MHz

ns

8

12

3.3

0

SCLK to Valid SDIO and SDO, t_DV

CS to SCLK Setup, t_S

14

ns

10

0

CS to SCLK Setup and Hold, t_S, t_C

CS Minimum Pulse Width High, t_PWH

ns

6

ns

SERIAL CONTROL PORT—I²C MODE

VDD = VDD3_REF, unless otherwise noted.

Table 16.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

SDA, SCL (WHEN INPUTTING DATA)

Input Logic 1 Voltage

Input Logic 0 Voltage

Input Current with an Input Voltage Between

0.1 × VDD and 0.9 × VDD

0.7 × VDD

V

µA

0.3 × VDD

+10

−10

Hysteresis of Schmitt Trigger Inputs

0.015 × VDD

V

Pulse Width of Spikes That Must Be

Suppressed by the Input Filter, t_SPIKE

50

ns

SDA (WHEN OUTPUTTING DATA)

Output Logic 0 Voltage at 3 mA Sink Current

Output Fall Time from VIH_MINto VIL_MAXwith

a Bus Capacitance from 10 pF to 400 pF

0.4

250

V

ns

1

20 + 0.1 C_B

TIMING

Note that all I²C timing values are referred to

VIH_MIN(0.3 × VDD) and VIL_MAXlevels (0.7 × VDD)

Clock Rate (SCL, f_I2C)

Bus Free Time Between a Stop and Start

Condition, t_IDLE

Setup Time for a Repeated Start Condition,

t_{SET; STR}

Hold Time (Repeated) Start Condition, t_{HLD; STR}

400

kHz

µs

1.3

0.6

µs

After this period, the first clock pulse is

generated

Setup Time for Stop Condition, t_{SET; STP}

Low Period of the SCL Clock, t_LOW

High Period of the SCL Clock, t_HIGH

SCL, SDA Rise Time, t_RISE

SCL, SDA Fall Time, t_FALL

Data Setup Time, t_{SET; DAT}

0.6

1.3

0.6

20 + 0.1 C_B

µs

ns

1

300

1

100

Data Hold Time, t_{HLD; DAT}

880

400

This is a minor deviation from the original I²C

specification of 0 ns minimum²

1

Capacitive Load for Each Bus Line, C_B

pF

¹C_Bis the capacitance of one bus line in picofarads (pF).

²According to the original I²C specification, an I²C master must also provide a minimum hold time of 300 ns for the SDA signal to bridge the undefined region of the SCL

falling edge.

Rev. F | Page 11 of 56

AD9524

Data Sheet

ABSOLUTE MAXIMUM RATINGS

Table 17.

Parameter

THERMAL RESISTANCE

Rating

θ_JAis specified for the worst-case conditions, that is, a device

soldered in a circuit board for surface-mount packages.

VDD3_PLL1, VDD3_PLL2, VDD3_REF,

VDD3_OUT, LDO_VCO to GND

−0.3 V to +3.6 V

REFA, REFA, REFIN, REFB, REFB to GND

−0.3 V to +3.6 V

Table 18. Thermal Resistance

SCLK/SCL, SDIO/SDA, SDO, CS to GND

Airflow

Velocity

Package Type (m/sec)

OUT0, OUT0, OUT1, OUT1, OUT2, OUT2,

OUT3, OUT3, OUT4, OUT4, OUT5, OUT5,

to GND

1, 2

1, 3

1, 4

1, 2

θ_JA

θ_JC

1.7

θ_JB

13.8

Ψ_JT

0.2

0.3

Unit

°C/W

48-Lead LFCSP,

7 mm ×

7 mm

0

26.1

22.8

20.4

SYNC, RESET, PD to GND

−0.3 V to +3.6 V

2 V

1.0

2.5

STATUS0, STATUS1 to GND

SP0, SP1, EEPROM_SEL to GND

VDD1.8_OUT, LDO_PLL1, LDO_PLL2 to

GND

Storage Temperature Range

Lead Temperature (10 sec)

¹Per JEDEC 51-7, plus JEDEC 51-5 2S2P test board.

²Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air).

³Per MIL-Std 883, Method 1012.1.

⁴Per JEDEC JESD51-8 (still air).

−65°C to +150°C

300°C

For information about power dissipation, refer to the Power

Dissipation and Thermal Considerations section.

Stresses at or above those listed under Absolute Maximum Ratings

may cause permanent damage to the product. This is a stress rating

only; functional operation of the product at these or any other

conditions above those indicated in the operational section of this

specification is not implied. Operation beyond the maximum

operating conditions for extended periods may affect product

reliability.

ESD CAUTION

Rev. F | Page 12 of 56

Data Sheet

AD9524

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

REFA

REFB

1

2

3

4

5

6

7

8

36 STATUS0/SP0

35 STATUS1/SP1

34 VDD1.8_OUT[2:3]

33 OUT2

REFB

32

OUT2

LF1_EXT_CAP

OSC_CTRL

OSC_IN

AD9524

TOP VIEW

(Not to Scale)

31 VDD3_OUT[2:3]

30 OUT3

29 OUT3

OSC_IN

9

10

28

27

26

LF2_EXT_CAP

EEPROM_SEL

PD

RESET

LDO_PLL2

VDD3_PLL2 11

LDO_VCO 12

25 REF_TEST

NOTES

1. PINS LABELED NC CAN BE ALLOWED TO FLOAT, BUT IT IS BETTER TO CONNECT THESE PINS TO GROUND.

AVOID ROUTING HIGH SPEED SIGNALS THROUGH THESE PINS BECAUSE NOISE COUPLING MAY RESULT.

ON EXISTING PCB DESIGNS, IT ISACCEPTABLE TO LEAVE PIN 42 CONNECTED TO 1.8V SUPPLY.

2. THE EXPOSED PADDLE IS THE GROUND CONNECTION ON THE CHIP. IT MUST BE

SOLDERED TO THE ANALOG GROUND OF THE PCB TO ENSURE PROPER FUNCTIONALITY

AND HEAT DISSIPATION, NOISE, AND MECHANICAL STRENGTH BENEFITS.

Figure 2. Pin Configuration

Table 19. Pin Function Descriptions

No.

Mnemonic

Type¹

Description

1

2

3

4

REFA

I

REFA

Reference Clock Input A. Along with , this pin is the differential input for the PLL reference.

Alternatively, this pin can be programmed as a single-ended 3.3 V CMOS input.

Complementary Reference Clock Input A. Along with REFA, this pin is the differential input for

the PLL reference. Alternatively, this pin can be programmed as a single-ended 3.3V CMOS input.

REFA

REFB

I

REFB

Reference Clock Input B. Along with

, this pin is the differential input for the PLL reference.

Alternatively, this pin can be programmed as a single-ended 3.3 V CMOS input.

Complementary Reference Clock Input B. Along with REFB, this pin is the differential input for

the PLL reference. Alternatively, this pin can be programmed as a single-ended 3.3 V CMOS input.

5

6

7

LF1_EXT_CAP

OSC_CTRL

OSC_IN

O

I

PLL1 External Loop Filter Capacitor. Connect a loop filter capacitor to this pin and to ground.

Oscillator Control Voltage. Connect this pinto the voltage control pin of the external oscillator.

OSC_IN

, this pin is the differential input for the PLL reference.

PLL1 Oscillator Input. Along with

Alternatively, this pin can be programmed as a single-ended 3.3 V CMOS input.

8

OSC_IN

I

Complementary PLL1 Oscillator Input. Along with OSC_IN, this pin is the differential input for the

PLL reference. Alternatively, this pin can be programmed as a single-ended 3.3 V CMOS input.

9

10

LF2_EXT_CAP

LDO_PLL2

O

P/O

PLL2 External Loop Filter Capacitor Connection. Connect a capacitor to this pin and LDO_VCO.

LDO Decoupling Pin for PLL2 1.8 V Internal Regulator. Connect a 0.47 μF decoupling capacitor

from this pin to ground. Note that for best performance, the LDO bypass capacitor must be

placed in close proximity to the device.

11

12

VDD3_PLL2

LDO_VCO

P

3.3 V Supply for PLL2.

P/O

2.5 V LDO Internal Regulator Decoupling Pin for VCO. Connect a 0.47 ꢀF decoupling capacitor

from this pin to ground. Note that, for best performance, the LDO bypass capacitor must be

placed in close proximity to the device.

13

SYNC

I

Manual Synchronization. This pin initiates a manual synchronization and has an internal

40 kΩ pull-up resistor.

14

15

VDD3_REF

CS

P

I

3.3 V Supply for Output Clock Drivers Reference.

Serial Control Port Chip Select, Active Low. This pin has an internal 40 kΩ pull-up resistor.

Rev. F | Page 13 of 56

AD9524

Data Sheet

No.

Mnemonic

Type¹

Description

16

SCLK/SCL

I

Serial Control Port Clock Signal for SPI Mode (SCLK) or I²C Mode (SCL). Data clock for serial programming.

This pin has an internal 40 kΩ pull-down resistor in SPI mode but is high impedance in I²C mode.

17

18

SDIO/SDA

SDO

I/O

O

Serial Control Port Bidirectional Serial Data In/Data Out for SPI Mode (SDIO) or I²C Mode (SDA).

Serial Data Output. Use this pin to read data in 4-wire mode (high impedance in 3-wire mode).

There is no internal pull-up/pull-down resistor on this pin.

19

20

OUT5

O

Complementary Clock Output 5. This pin can be configured as one side of a differential

LVPECL/LVDS/HSTL output or as a single-ended CMOS output.

Clock Output 5. This pin can be configured as one side of a differential LVPECL/LVDS/HSTL output or as a

single-ended CMOS output.

21

22

VDD3_OUT[4:5]

OUT4

P

O

3.3 V Supply for Output 4 and Output 5 Clock Drivers.

Complementary Clock Output 4. This pin can be configured as one side of a differential

LVPECL/LVDS/HSTL output or as a single-ended CMOS output.

Clock Output 4. This pin can be configured as one side of a differential LVPECL/LVDS/HSTL output or as a

single-ended CMOS output.

23

OUT4

O

24

25

26

VDD1.8_OUT[4:5]

REF_TEST

RESET

P

I

1.8 V Supply for Output 4 and Output 5 Clock Dividers.

Test Input to PLL1 Phase Detector.

Digital Input, Active Low. Resets internal logic to default states. This pin has an internal

40 kΩ pull-up resistor.

27

28

PD

Chip Power-Down, Active Low. This pin has an internal 40 kΩ pull-up resistor.

EEPROM_SEL

I

EEPROM Select. Setting this pin high selects the register values stored in the internal EEPROM to

be loaded at reset and/or power-up. Setting this pin low causes the AD9524 to load the hard-

coded default register values at power-up/reset. This pin has an internal 40 kΩ pull-down resistor.

Complementary Clock Output 3. This pin can be configured as one side of a differential

LVPECL/LVDS/HSTL output or as a single-ended CMOS output.

29

30

OUT3

O

Square Wave Clocking Output 3. This pin can be configured as one side of a differential

LVPECL/LVDS/HSTL output or as a single-ended CMOS output.

31

32

VDD3_OUT[2:3]

OUT2

P

O

3.3 V Supply Output 2 and Supply Output 3 Clock Drivers.

Complementary Clock Output 2. This pin can be configured as one side of a differential

LVPECL/LVDS/HSTL output or as a single-ended CMOS output.

33

OUT2

O

Clock Output 2. This pin can be configured as one side of a differential LVPECL/LVDS/HSTL output or as a

single-ended CMOS output.

34

35

36

37

VDD1.8_OUT[2:3]

STATUS1/SP1

STATUS0/SP0

OUT1

P

1.8 V Supply for Output 2 and Output 3 Clock Dividers.

I/O

O

Lock Detect and Other Status Signals (STATUS1)/I²C Address (SP1).

Lock Detect and Other Status Signals (STATUS0)/I²C Address (SP0).

Complementary Clock Output 1. This pin can be configured as one side of a differential

LVPECL/LVDS/HSTL output or as a single-ended CMOS output.

38

OUT1

O

Clock Output 1. This pin can be configured as one side of a differential LVPECL/LVDS/HSTL output or as a

single-ended CMOS output.

39

40

VDD3_OUT[0:1]

OUT0

P

O

3.3 V Supply Output 0 and Supply Output 1 Clock Drivers.

Complementary Clock Output 0. This pin can be configured as one side of a differential

LVPECL/LVDS/HSTL output or as a single-ended CMOS output.

41

OUT0

O

Clock Output 0. This pin can be configured as one side of a differential LVPECL/LVDS/HSTL output or as a

single-ended CMOS output.

42

43

VDD1.8_OUT[0:1]

ZD_IN

P

I

1.8 V Supply for Output 0 and Output 1 Clock Dividers.

External Zero Delay Clock Input. Along with

ZD_IN

, this pin is the differential input for the PLL

reference. Alternatively, this pin can be programmed as a single-ended 3.3 V CMOS input.

Complementary External Zero Delay Clock Input. Along with ZD_IN, this pin is the differential input

for the PLL reference. Alternatively, this pin can be programmed as a single-ended 3.3 V CMOS input.

Reference Input Select. This pin has an internal 40 kΩ pull-down resistor.

Single-Ended CMOS Output from PLL1. This pin has settings for weak and strong in

Register 0x1BA, Bit 4 (see Table 53).

44

ZD_IN

I

45

46

REF_SEL

PLL1_OUT

I

O

47

LDO_PLL1

P/O

1.8 V Internal LDO Regulator Decoupling Pin for PLL1. Connect a 0.47 µF decoupling capacitor

from this pin to ground. Note that, for best performance, the LDO bypass capacitor must be

placed in close proximity to the device.

48

EP

VDD3_PLL1

EP, GND

P

GND

3.3 V Supply PLL1. Use the same supply as VCXO.

Exposed Paddle. The exposed paddle is the ground connection on the chip. It must be soldered

to the analog ground of the PCB to ensure proper functionality and heat dissipation, noise, and

mechanical strength benefits.

¹P = power, I = input, O = output, I/O = input/output, P/O = power/output, GND = ground.

Rev. F | Page 14 of 56

Data Sheet

AD9524

TYPICAL PERFORMANCE CHARACTERISTICS

f_VCXO= 122.88 MHz, REFA differential at 30.72 MHz, f_VCO= 3686.4 MHz, and doubler is off, unless otherwise noted.

60

50

40

30

20

10

0

35

30

25

20

15

10

5

20pF

HSTL = 16mA

10pF

2pF

HSTL = 8mA

0

200

400

600

800

1000

1200

0

100

200

300

400

500

FREQUENCY (MHz)

Figure 3. VDD3_OUT[x:y] Current (Typical) vs. Frequency;

HSTL Mode, 16 mA and 8 mA

Figure 6. VDD3_OUT[x:y] Current (Typical) vs. Frequency;

CMOS Mode, 20 pF, 10 pF, and 2 pF Load

45

40

35

30

25

20

15

10

5

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

HSTL = 16mA

HSTL = 8mA

LVDS = 7mA

LVDS = 3.5mA

0

200

400

600

800

1000

1200

0

200

400

600

800

1000

1200

FREQUENCY (MHz)

Figure 7. Differential Voltage Swing vs. Frequency;

HSTL Mode, 16 mA and 8 mA

Figure 4. VDD3_OUT[x:y] Current (Typical) vs. Frequency;

LVDS Mode, 7 mA and 3.5 mA

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0

45

40

35

30

25

20

15

10

5

0

200

400

600

800

1000

1200

0

200

400

600

800

1000

1200

FREQUENCY (MHz)

Figure 8. Differential Voltage Swing vs. Frequency,

LVPECL Mode

Figure 5. VDD3_OUT[x:y] Current (Typical) vs. Frequency, LVPECL Mode

Rev. F | Page 15 of 56

AD9524

Data Sheet

1.4

1.2

1.0

0.8

0.6

0.4

0.2

–70

–80

1: 100Hz, –85.0688dBc/Hz

2: 1kHz, –113.3955dBc/Hz

3: 8kHz, –125.8719dBc/Hz

4: 16kHz, –129.5942dBc/Hz

5: 100kHz, –134.5017dBc/Hz

6: 1MHz, –145.2872dBc/Hz

7: 10MHz, –156.2706dBc/Hz

8: 40MHz, –157.4153dBc/Hz

x: START 12kHz

LVDS = 7mA

1

–90

–100

–110

–120

–130

–140

–150

–160

–170

STOP 80MHz

CENTER 40.006MHz

SPAN 79.988MHz

LVDS = 3.5mA

3

5

NOISE:

ANALYSIS RANGE X: BAND MARKER

ANALYSIS RANGE Y: BAND MARKER

INTG NOISE: –75.94595dBc/39.99MHz

RMS NOISE: 225.539µRAD

7

12.9224mdeg

RMS JITTER: 194.746fsec

RESIDUAL FM: 2.81623kHz

0

200

400

600

800

1000

1200

100

1k

10k

100k

1M

10M

FREQUENCY (Hz)

FREQUENCY (MHz)

Figure 9. Differential Voltage Swing vs. Frequency;

LVDS Mode, 7 mA and 3.5 mA

Figure 12. Phase Noise, Output = 184.32 MHz

(VCXO = 122.88 MHz, Crystek VCXO CVHD-950)

–70

3.5

3.3

3.1

2.9

2.7

2.5

2.3

2.1

1.9

1.7

1: 100Hz, –89.0260dBc/Hz

2: 1kHz, –116.9949dBc/Hz

3: 8kHz, –129.5198dBc/Hz

4: 16kHz, –133.3916dBc/Hz

5: 100kHz, –137.7680dBc/Hz

6: 1MHz, –148.3519dBc/Hz

7: 10MHz, –158.3307dBc/Hz

8: 40MHz, 159.1629–dBc/Hz

x: START 12kHz

2pF

–80

–90

1

10pF

20pF

–100

–110

–120

–130

–140

–150

–160

–170

STOP 80MHz

CENTER 40.006MHz

SPAN 79.988MHz

3

5

NOISE:

ANALYSIS RANGE X: BAND MARKER

ANALYSIS RANGE Y: BAND MARKER

INTG NOISE: –78.8099dBc/39.99MHz

RMS NOISE: 162.189µRAD

9.29276mdeg

RMS JITTER: 210.069fsec

RESIDUAL FM: 2.27638kHz

7

0

100

200

300

400

500

100

1k

10k

100k

1M

10M

FREQUENCY (Hz)

FREQUENCY (MHz)

Figure 13. Phase Noise, Output = 122.88 MHz

(VCXO = 122.88 MHz, Crystek VCXO CVHD-950; Doubler Is Off)

Figure 10. Amplitude vs. Frequency and Capacitive Load;

CMOS Mode, 2 pF, 10 pF, and 20 pF

1

CH1 200mV

2.5ns/DIV

40.0GS/s

A CH1

104mV

CH1 500mV Ω

2.5ns/DIV

40.0GS/s

A CH1

80mV

Figure 14. Output Waveform (Differential), HSTL at 16 mA, 122.88 MHz

Figure 11. Output Waveform (Differential), LVPECL at 122.88 MHz

Rev. F | Page 16 of 56

Data Sheet

AD9524

INPUT/OUTPUT TERMINATION RECOMMENDATIONS

0.1µF

AD9524

HIGH

100Ω IMPEDANCE

HIGH

100Ω IMPEDANCE

LVDS

OUTPUT

HSTL

OUTPUT

DOWNSTREAM

DEVICE

DOWNSTREAM

DEVICE

INPUT

0.1µF

Figure 15. AC-Coupled LVDS Output Driver

Figure 19. AC-Coupled HSTL Output Driver

AD9524

HIGH

IMPEDANCE

INPUT

HIGH

IMPEDANCE

INPUT

LVDS

OUTPUT

HSTL

OUTPUT

DOWNSTREAM

DEVICE

DOWNSTREAM

DEVICE

100Ω

Figure 16. DC-Coupled LVDS Output Driver

Figure 20. DC-Coupled HSTL Output Driver

0.1µF

AD9524

0.1µF

AD9524

SELF-BIASED

REF, VCXO,

ZERO DELAY

INPUTS

LVPECL-

COMPATIBLE

OUTPUT

HIGH

100Ω IMPEDANCE

INPUT

100Ω

(OPTIONAL )

DOWNSTREAM

DEVICE

1

0.1µF

1

RESISTOR VALUE DEPENDS UPON

REQUIRED TERMINATION OF SOURCE.

Figure 17. AC-Coupled LVPECL Output Driver

Figure 21. REF, VCXO, and Zero Delay Input, Differential Mode (When In

CMOS Single-Ended Input Mode, the Unused Input Can Be Left Unconnected)

AD9524

LVPECL-

COMPATIBLE 100Ω

OUTPUT

HIGH

IMPEDANCE

INPUT

DOWNSTREAM

DEVICE

Figure 18. DC-Coupled LVPECL Output Driver

Rev. F | Page 17 of 56

AD9524

Data Sheet

TERMINOLOGY

Phase Jitter and Phase Noise

wave, the time jitter is a displacement of the edges from their

ideal (regular) times of occurrence. In both cases, the variations in

timing from the ideal are the time jitter. Because these variations

are random in nature, the time jitter is specified in seconds root

mean square (rms) or 1 sigma (Σ) of the Gaussian distribution.

An ideal sine wave can be thought of as having a continuous

and even progression of phase with time from 0° to 360° for

each cycle. Actual signals, however, display a certain amount

of variation from ideal phase progression over time. This

phenomenon is called phase jitter. Although many causes can

contribute to phase jitter, one major cause is random noise,

which is characterized statistically as being Gaussian (normal)

in distribution.

Time jitter that occurs on a sampling clock for a DAC or an

ADC decreases the signal-to-noise ratio (SNR) and dynamic

range of the converter. A sampling clock with the lowest possible

jitter provides the highest performance from a given converter.

This phase jitter leads to a spreading out of the energy of the

sine wave in the frequency domain, producing a continuous

power spectrum. This power spectrum is usually reported as a

series of values whose units are dBc/Hz at a given offset in

frequency from the sine wave (carrier). The value is a ratio

(expressed in decibels) of the power contained within a 1 Hz

bandwidth with respect to the power at the carrier frequency.

For each measurement, the offset from the carrier frequency is

also given.

Additive Phase Noise

Additive phase noise is the amount of phase noise that can be

attributed to the device or subsystem being measured. The phase

noise of any external oscillators or clock sources is subtracted.

This makes it possible to predict the degree to which the device

impacts the total system phase noise when used in conjunction

with the various oscillators and clock sources, each of which

contributes its own phase noise to the total. In many cases, the

phase noise of one element dominates the system phase noise.

When there are multiple contributors to phase noise, the total

is the square root of the sum of squares of the individual

contributors.

It is meaningful to integrate the total power contained within

some interval of offset frequencies (for example, 10 kHz to

10 MHz). This is called the integrated phase noise over that

frequency offset interval and can be readily related to the time

jitter due to the phase noise within that offset frequency interval.

Additive Time Jitter

Additive time jitter is the amount of time jitter that can be

attributed to the device or subsystem being measured. The time

jitter of any external oscillators or clock sources is subtracted. This

makes it possible to predict the degree to which the device impacts

the total system time jitter when used in conjunction with the

various oscillators and clock sources, each of which contributes

its own time jitter to the total. In many cases, the time jitter of the

external oscillators and clock sources dominates the system

time jitter.

Phase noise has a detrimental effect on the performance of ADCs,

DACs, and RF mixers. It lowers the achievable dynamic range of

the converters and mixers, although they are affected in somewhat

different ways.

Time Jitter

Phase noise is a frequency domain phenomenon. In the time

domain, the same effect is exhibited as time jitter. When observing

a sine wave, the time of successive zero crossings varies. In a square

Rev. F | Page 18 of 56

Data Sheet

AD9524

THEORY OF OPERATION

DETAILED BLOCK DIAGRAM

VCXO

STATUS0/ STATUS1/

PLL1_OUT

VDD1.8_OUT[X:Y] VDD3_OUT[X:Y]

SP0

SP1

VDD3_PLL1 LDO_PLL1

LF1_EXT_CAP

OSC_CTRL OSC_IN

LF2_EXT_CAP

LDO_VCO

STATUS MONITOR

LOCK DETECT/

SERIAL PORT

ADDRESS

RESYNCH

SYNC

SIGNAL

OUT5

Δt

÷D

EDGE

REFA

LOCK

DETECT

REFA

÷D1

÷R

SWITCH-

OVER

CONTROL

Δt

EDGE

OUT4

REF_SEL

LOOP

FILTER

LOCK

DETECT

REFB

P

F

D

CHARGE

PUMP

P

F

×2

OUT3

CHARGE

LOOP

FILTER

Δt

EDGE

÷M1

VCO

PUMP

D

REF_TEST

÷R

÷N1

÷N2

OUT2

Δt

EDGE

PLL1

PLL2

SDIO/SDA

OUT1

SDO

SCLK/SCL

Δt

÷D

CONTROL

EDGE

INTERFACE

CS

RESET

PD

2

(SPI AND I C)

OUT0

Δt

EDGE

EEPROM

EEPROM_SEL

ZD_IN

TO SYNC

SYNC

AD9524

LDO_PLL2

VDD3_PLL2

NC

Figure 22. Top Level Diagram

OVERVIEW

The AD9524 is a clock generator that employs integer-N-based

phase-locked loops (PLL). The device architecture consists of

two cascaded PLL stages. The first stage, PLL1, consists of an

integer division PLL that uses an external voltage-controlled

crystal oscillator (VCXO) of up to 250 MHz. PLL1 has a narrow-

loop bandwidth that provides initial jitter cleanup of the input

reference signal. The second stage, PLL2, is a frequency

multiplying PLL that translates the first stage output frequency

to a range of 3.6 GHz to 4.0 GHz. PLL2 incorporates an integer-

based feedback divider that enables integer frequency multipli-

cation. Programmable integer dividers (1 to 1024) follow PLL2,

establishing a final output frequency of 1 GHz or less.

AD9524 supports a holdover mode. A reference select pin

(REF_SEL, Pin 45) is available to manually select which input

reference is active (see Table 43). The accuracy of the holdover

is dependent on the external VCXO frequency stability at half

supply voltage.

Any of the divider settings are programmable via the serial

programming port, enabling a wide range of input/output

frequency ratios under program control. The dividers also

include a programmable delay to adjust timing of the output

signals, if required.

The output is compatible with LVPECL, LVDS, or HSTL logic

levels (see the Input/Output Termination Recommendations

section); however, the AD9524 is implemented only in CMOS.

The AD9524 includes reference signal processing blocks that

enable a smooth switching transition between two reference

inputs. This circuitry automatically detects the presence of the

reference input signals. If only one input is present, the device

uses it as the active reference. If both are present, one becomes

the active reference and the other becomes the backup reference.

If the active reference fails, the circuitry automatically switches

to the backup reference (if available), making it the new active

reference. A register setting determines what action to take if the

failed reference is once again available: either stay on Reference B

or revert to Reference A. If neither reference can be used, the

The loop filters of each PLL are integrated and programmable.

Only a single external capacitor for each of the two PLL loop

filters is required.

The AD9524 operates over the extended industrial temperature

range of −40°C to +85°C.

Rev. F | Page 19 of 56

AD9524

Data Sheet

PLL1 Loop Filter

COMPONENT BLOCKS—INPUT PLL (PLL1)

The PLL1 loop filter requires the connection of an external

capacitor from LF1_EXT_CAP (Pin 5) to ground. The value of the

external capacitor depends on the use of an external VCXO, as

well as such configuration parameters as input clock rate and

desired bandwidth. Normally, a 0.3 µF capacitor allows the loop

bandwidth to range from 10 Hz to 100 Hz and ensures loop

stability over the intended operating parameters of the device

(see Table 44 for R_ZEROvalues).

PLL1 General Description

Fundamentally, the input PLL (referred to as PLL1) consists of

a phase-frequency detector (PFD), charge pump, passive loop

filter, and an external VCXO operating in a closed loop.

PLL1 has the flexibility to operate with a loop bandwidth of

approximately 10 Hz to 100 Hz. This relatively narrow loop

bandwidth gives the AD9524 the ability to suppress jitter that

appears on the input references (REFA and REFB). The output

of PLL1 then becomes a low jitter phase-locked version of the

reference input system clock.

LF1_EXT_CAP

LDO_PLL1

AD9524

PLL1 Reference Clock Inputs

The AD9524 features two separate differential reference clock

inputs, REFA and REFB. These inputs can be configured to

operate in full differential mode or single-ended CMOS mode.

R

ZERO

C

POLE2

POLE1

TO VCXO

TUNE

V

OSC_CTRL

CHARGE

PUMP

R

1kΩ

POLE2

In differential mode, these pins are internally self biased. If

0.3µF

BUFFER

REFA

REFA or REFB is driven single-ended, the unused side (

REFB

,

Figure 23. PLL1 Loop Filter

) should be decoupled via a suitable capacitor to a quiet

ground. Figure 21 shows the equivalent circuit of REFA or REFB.

It is possible to dc couple to these inputs, but the dc operation

point should be set as specified in the Specifications tables.

Table 20. PLL1 Loop Filter Programmable Values

R_ZERO

(kΩ)

C_POLE1

(nF)

R_POLE2

(kΩ)

C_POLE2

(nF)

LF1_EXT_CAP¹

(µF)

To operate either the REFA or the REFB inputs in 3.3 V CMOS

mode, the user must set Bit 5 or Bit 6, respectively, in Register

0x01A (see Table 41). The single-ended inputs can be driven by

either a dc-coupled CMOS level signal or an ac-coupled sine

wave or square wave.

883

677

341

135

1.5 fixed

165 fixed

0.337 fixed 0.3

10

The differential reference input receiver is powered down when

the differential reference input is not selected, or when the PLL

is powered down. The single-ended buffers power-down when

the PLL is powered down, when their respective individual power-

down registers are set, or when the differential receiver is selected.

External

¹External loop filter capacitor.

An external R-C low-pass filter should be used at the OSC_CTRL

output. The values shown in Figure 23 add an additional low-pass

pole at ~530 Hz. This R-C network filters the noise associated with

the OSC_CTRL buffer to achieve the best noise performance at the

1 kHz offset region.

The REFB R divider uses the same value as the REFA R divider

unless Bit 7, the enable REFB R divider independent division

control bit in Register 0x01C, is programmed as shown in Table 43.

LF1_EXT_CAP

REFA

DIVIDE BY

1, 2, ...1024

R

ZERO

SWITCH-

OVER

CONTROL

REF_SEL

CHARGE

PUMP

R

POLE2

P

F

D

OSC_CTRL

VCXO

REFB

DIVIDE BY

1, 2, ...1024

7 BITS,

0.5µA LSB

C

POLE2

3.3V CMOS

POLE1

OR 1.8V

DIFFERENTIAL

OSC_IN

DIVIDE BY

1, 2, ...1024

DIVIDE BY

1, 2, ...63

REF_TEST

1.8V LDO

AD9524

VDD3_PLL1

LDO_PLL1

Figure 24. Input PLL (PLL1) Block Diagram

Rev. F | Page 20 of 56

Data Sheet

AD9524

signals. When the device switches to holdover, the charge pump

PLL1 Input Dividers

tristates. The device continues operating in this mode until a

reference signal becomes available. Then the device exits holdover

mode, and PLL1 resynchronizes with the active reference. In

addition to tristate, the charge pump can be forced to VCC/2

during holdover (see Table 43, Bit 6 in Register 0x01C).

Each reference input feeds a dedicated reference divider block.

The input dividers provide division of the reference frequency

in integer steps from 1 to 1023. They provide the bulk of the

frequency prescaling that is necessary to reduce the reference

frequency to accommodate the bandwidth that is typically

desired for PLL1.

COMPONENT BLOCKS—OUTPUT PLL (PLL2)

PLL2 General Description

PLL1 Reference Switchover

The output PLL (referred to as PLL2) consists of an optional input

reference doubler, phase-frequency detector (PFD), a partially

integrated analog loop filter (see Figure 25), an integrated

voltage-controlled oscillator (VCO), and a feedback divider.

The VCO produces a nominal 3.8 GHz signal with an output

divider that is capable of division ratios of 4 to 11.

The reference monitor verifies the presence/absence of the

prescaled REFA and REFB signals (that is, after division by the

input dividers). The status of the reference monitor guides the

activity of the switchover control logic. The AD9524 supports

automatic and manual PLL reference clock switching between

REFA

REFA (the REFA and

REFB

pins) and REFB (the REFB and

pins). This feature supports networking and infrastructure

The PFD of the output PLL drives a charge pump that increases,

decreases, or holds constant the charge stored on the loop filter

capacitors (both internal and external). The stored charge results

in a voltage that sets the output frequency of the VCO. The

feedback loop of the PLL causes the VCO control voltage to

vary in a way that phase locks the PFD input signals.

applications that require redundant references.

There are several configurable modes of reference switchover.

The manual switchover is achieved either via a programming

register setting or by using the REF_SEL pin. The automatic

switchover occurs when REFA disappears and there is a reference

on REFB.

The gain of PLL2 is proportional to the current delivered by the

charge pump. The loop filter bandwidth is chosen to reduce noise

contributions from PLL sources that could degrade phase noise

requirements.

The reference automatic switchover can be set to work as follows:

•

Nonrevertive: stay on REFB. Switch from REFA to REFB

when REFA disappears, but do not switch back to REFA

if it reappears. If REFB disappears, then go back to REFA.

Revert to REFA. Switch from REFA to REFB when REFA

disappears. Return to REFA from REFB when REFA returns.

The output PLL has a VCO with multiple bands spanning a

range of 3.6 GHz to 4.0 GHz. However, the actual operating

frequency within a particular band depends on the control

voltage that appears on the loop filter capacitor. The control

voltage causes the VCO output frequency to vary linearly within

the selected band. This frequency variability allows the control

loop of the output PLL to synchronize the VCO output signal

with the reference signal applied to the PFD. Typically, the

device automatically selects the appropriate band as part of its

calibration process (invoked via the VCO control register at

Address 0x0F3).

See Table 43 for the PLL1 miscellaneous control register bit

settings.

PLL1 Holdover

In the absence of both input references, the device enters holdover

mode. Holdover is a secondary function that is provided by PLL1.

Because PLL1 has an external VCXO available as a frequency

source, it continues to operate in the absence of the input reference

LF2_EXT_CAP

LDO_VCO

VDD3_PLL2

LDO_PLL2

PLL1_OUT

AD9524

LDO

R

ZERO

PLL_1.8V

DIVIDE BY

1, 2, 4, 8, 16

C

POLE2

POLE1

CHARGE PUMP

8 BITS, 3.5µA LSB

DIVIDE BY

4, 5, 6, ...11

PFD

R

×2

POLE2

TO DIST/

RESYNC

A/B

COUNTERS

DIVIDE-BY-4

PRESCALER

N DIVIDER

Figure 25. Output PLL (PLL2) Block Diagram

Rev. F | Page 21 of 56

AD9524

Data Sheet

Input 2× Frequency Multiplier

VCO Divider

The 2× frequency multiplier provides the option to double

the frequency at the PLL2 input. This allows the user to take

advantage of a higher frequency at the input to the PLL (PFD)

and, thus, allows for reduced in-band phase noise and greater

separation between the frequency generated by the PLL and the

modulation spur associated with PFD. However, increased

reference spur separation results in harmonic spurs introduced

by the frequency multiplier that increase as the duty cycle deviates

from 50% at the OSC_IN inputs. As such, beneficial use of the

frequency multiplier is application-specific. Typically, a VCXO

with proper interfacing has a duty cycle that is approximately

50% at the OSC_IN inputs. Note that the maximum output

frequency of the 2× frequency multipliers must not exceed the

maximum PFD rate that is specified in Table 12.

The VCO divider provides frequency division between the internal

VCO and the clock distribution. The VCO divider can be set to

divide by 4, 5, 6, 7, 8, 9, 10, or 11.

VCO Calibration

The AD9524 on-chip VCO must be manually calibrated to ensure

proper operation over process and temperature. This is accom-

plished by setting the calibrate VCO bit (Register 0x0F3, Bit 1)

to 1. (This bit is not self clearing.) The setting can be performed

as part of the initial setup before executing the IO_Update bit

(Register 0x234, Bit 0 = 1). A readback bit, VCO calibration

in progress (Register 0x22D, Bit 0), indicates when a VCO

calibration is in progress by returning a logic true (that is, Bit 0

= 1). If the EEPROM is in use, setting the calibrate VCO bit

(Register 0x0F3, Bit 1) to 1 before saving the register settings

to the EEPROM ensures that the VCO calibrates automatically

after the EEPROM has loaded. After calibration, it is recommended

that a sync be initiated (for more information, see the Clock

Distribution Synchronization section).

PLL2 Feedback Divider

PLL2 has a feedback divider (N divider) that enables it to provide

integer frequency up-conversion. The PLL2 N divider is a com-

bination of a prescaler (P) and two counters, A and B. The total

divider value is

Note that the calibrate VCO bit defaults to 0. This bit must

change from 0 to 1 to initiate a calibration sequence. Therefore,

any subsequent calibrations require the following sequence:

N = (P × B) + A

where P = 4.

1. Register 0x0F3, Bit 1 (calibrate VCO bit) = 0

2. Register 0x234, Bit 0 (IO_Update bit) = 1

3. Register 0x0F3, Bit 1 (calibrate VCO bit) = 1

4. Register 0x234, Bit 0 (IO_Update bit) = 1

The feedback divider is a dual modulus prescaler architecture,

with a nonprogrammable P that is equal to 4. The value of the B

counter can be from 4 to 63, and the value of the A counter can

be from 0 to 3. However, due to the architecture of the divider,

there are constraints, as listed in Table 46.

VCO calibration is controlled by a calibration controller that runs

off the VCXO input clock. The calibration requires that PLL2 be

set up properly to lock the PLL2 loop and that the VCXO clock

be present.

PLL2 Loop Filter

The PLL2 loop filter requires the connection of an external

capacitor from LF2_EXT_CAP (Pin 9) to LDO_VCO (Pin 12),

as illustrated in Figure 25. The value of the external capacitor

depends on the operating mode and the desired phase noise

performance. For example, a loop bandwidth of approximately

500 kHz produces the lowest integrated jitter. A lower bandwidth

produces lower phase noise at 1 MHz but increases the total

integrated jitter.

During power-up or reset, the distribution section is automatically

held in sync until the first VCO calibration is finished. Therefore,

no outputs can occur until VCO calibration is complete and PLL2

is locked.

Initiate a VCO calibration under the following conditions:

•

After changing any of the PLL2 B counter and A counter

settings or after a change in the PLL2 reference clock

frequency. This means that a VCO calibration should be

initiated any time that a PLL2 register or reference clock

changes such that a different VCO frequency is the result.

Whenever system calibration is desired. The VCO is designed

to operate properly over extremes of temperature even when

it is first calibrated at the opposite extreme. However, a VCO

calibration can be initiated at any time, if desired.

Table 21. PLL2 Loop Filter Programmable Values

R_ZERO

(Ω)

C_POLE1

(pF)

R_POLE2

(Ω)

C_POLE2

(pF)

LF2_EXT_CAP¹

(pF)

3250

3000

2750

2500

2250

2100

2000

1850

48

40

32

24

16

8

900

450

300

225

Fixed at 16 Typical at 1000

•

0

¹External loop filter capacitor.

Rev. F | Page 22 of 56

Data Sheet

AD9524

If the output channel is ac-coupled to the circuit to be clocked,

changing the mode varies the voltage swing to determine sensi-

tivity to the drive level. For example, in LVDS mode, a current of

3.5 mA causes a 350 mV peak voltage. Likewise, in LVPECL

compatible mode, a current of 8 mA causes an 800 mV peak

voltage at the 100 Ω load resistor. Using any termination other

than those specified in the Input/Output Termination

Recommendations section may results in damage or decrease

end of life performance.

CLOCK DISTRIBUTION

The clock distribution block provides an integrated solution for

generating multiple clock outputs based on frequency dividing

the PLL2 VCO divider output. The distribution output consists

of six channels (OUT0 to OUT5). Each of the output channels

has a dedicated divider and output driver, as shown in Figure 25.

The AD9524 also has the capability to route the VCXO output

to two of the outputs (OUT0 and OUT1).

Clock Dividers

In addition to the four mode bits, each of the six Channel 0 to

Channel 5 control registers includes the following control bits:

The output clock distribution dividers are referred to as D0 to D5,

corresponding to output channels OUT0 through OUT5,

respectively. Each divider is programmable with 10 bits of division

depth that is equal to 1 to 1024. Dividers have duty cycle correction

to always give 50% duty cycle, even for odd divides.

•

Invert divider output. Enables the user to choose between

normal polarity and inverted polarity. Normal polarity is the

default state. Inverted polarity reverses the representation of

Logic 0 and Logic 1, regardless of the logic family.

Output Power-Down

SYNC

•

Ignore sync. Makes the divider ignore the

from any source.

signal

Each of the output channels offers independent control of the

power-down functionality via the Channel 0 to Channel 5 control

registers (see Table 52). Each output channel has a dedicated

power-down bit for powering down the output driver. However,

if all six outputs are powered down, the entire distribution output

enters a deep sleep mode. Although each channel has a channel

power-down control signal, it may sometimes be desirable to

power down an output driver while maintaining the divider’s

synchronization with the other channel dividers. This is accom-

plished by placing the output in tristate mode (this works in

CMOS mode, as well).

•

Power-down channel. Powers down the entire channel.

Lower power mode.

Driver mode.

Channel divider.

Divider phase.

VDD3_OUT[x:y]

1.25V LVDS

VDD – 1.3V LVPECL

HSTL

50Ω

ENABLED

CM

Multimode Output Drivers

COMMON-MODE

CIRCUIT

The user has independent control of the operating mode of each of

the fourteen output channels via the Channel 0 to Channel 5

control registers (see Table 52). The operating mode control

includes the following:

P

N

CM

•

Logic family and pin functionality

Output drive strength

Output polarity

+

–

100Ω LOAD

N

P

The four least significant bits (LSBs) of each of the six Channel 0 to

Channel 5 control registers comprise the driver mode bits. The

mode value selects the desired logic family and pin functionality

of an output channel, as listed in Table 52. This driver design

allows a common 100 Ω external resistor for all the different

driver modes of operation that are illustrated in Figure 26.

3.5mA/8mA

LVDS/LVPECL

ENABLED

HSTL

ENABLED

50Ω

Figure 26. Multimode Driver

Rev. F | Page 23 of 56

AD9524

Data Sheet

Clock Distribution Synchronization

As indicated, the primary synchronization signal originates

from one of the following sources:

A block diagram of the clock distribution synchronization

functionality is shown in Figure 27. The synchronization

sequence begins with the primary synchronization signal,

which ultimately results in delivery of a synchronization strobe

to the clock distribution logic.



Direct synchronization source via the sync dividers bit (see

Register 0x232, Bit 0 in Table 56)

SYNC



Device pin,

(Pin 13)

An automatic synchronization of the divider is initiated the first

time that PLL2 locks after a power-up or reset event. Subsequent

lock/unlock events do not initiate a resynchronization of the

distribution dividers unless they are preceded by a power-down

or reset of the part.

OUTx

DIVIDE

PHASE

DRIVER

OUT

DIVIDER

SYNC

OUTx

VCO OUTPUT DIVIDER

FAN OUT

SYNC (PIN 13)

SYNC

SYNC DIVIDERS BIT

Figure 27. Clock Output Synchronization Block Diagram

SYNC

VCO DIVIDER OUTPUT CLOCK

DIVIDE = 2, PHASE = 0

DIVIDE = 2, PHASE = 6

CONTROL

6 × 0.5 PERIODS

Figure 28. Clock Output Synchronization Timing Diagram

Rev. F | Page 24 of 56

Data Sheet

AD9524

Both sources of the primary synchronization signal are logic OR’d;

therefore, any one of them can synchronize the clock distribution

output at any time. When using the sync dividers bit, the user

first sets and then clears the bit.

through a mux. PLL1 synchronizes the phase/edge of the output

of Channel Divider 0 with the phase/edge of the reference input.

Because the channel dividers are synchronized to each other,

the outputs of the channel divider are synchronous with the

reference input.

The synchronization event is the clearing operation (that is, the

Logic 1 to Logic 0 transition of the bit). The dividers are all

automatically synchronized to each other when PLL2 is ready.

The dividers support programmable phase offsets from 0 to 63

steps, in half periods of the input clock (for example, the VCO

divider output clock). The phase offsets are incorporated in the

dividers through a preset for the first output clock period of each

divider. Phase offsets are supported only by programming the

initial phase and divide value and then issuing a sync to the

distribution (automatically at startup or manually, if desired).

ZD_IN

OUT0

ENB

FEEDBACK

DELAY

INTERNAL FB

REFA

SYNC

When using the

output pipe line delays plus one period of the clock from the

SYNC

pin (Pin 17), there are 11 VCO divider

PFD

REF

DELAY

rising edge of

to the clock output. There is at least one

SYNC

extra VCO divider period of uncertainty because the

signal and the VCO divider output are asynchronous.

AD9524

Figure 29. Zero Delay Function

In normal operation, the phase offsets are already programmed

through the EEPROM or the SPI/I²C port before the AD9524

starts to provide outputs. Although the user cannot adjust the

phase offsets while the dividers are operating, it is possible to

adjust the phase of all the outputs together without powering

down PLL1 and PLL2. This is accomplished by programming

the new phase offset, using Bits[7:2] in Register 0x198 (see

Table 52) and then issuing a divide sync signal by using the

External Zero Delay Mode

The external zero delay function of the AD9524 is achieved by

feeding OUT0 back to the ZD_IN input and, ultimately, back to

the PLL1 N divider. In Figure 29, the change in signal routing

for external zero delay is external to the AD9524.

Bit 5 in Register 0x01B is used to select the external zero delay

mode. In external zero delay mode, OUT0 must be routed back

to PLL1 (the N divider) through the ZD_IN and

SYNC

pin or the sync dividers bit (Register 0x232, Bit 0).

ZD_IN

pins.

All outputs that are not programmed to ignore the sync are

disabled temporarily while the sync is active. Note that, if an

output is used for the zero delay path, it also disappears

momentarily. However, this is desirable because it ensures that

all the synchronized outputs have a deterministic phase relation-

ship with respect to the zero delay output and, therefore, also

with respect to the input.

PLL1 synchronizes the phase/edge of the feedback output clock

with the phase/edge of the reference input. Because the channel

dividers are synchronized to each other, the clock outputs are

synchronous with the reference input. Both the reference path

delay and the feedback delay from ZD_IN are designed to have

the same propagation delay from the output drivers and PLL

components to minimize the phase offset between the clock

output and the reference input to achieve zero delay.

ZERO DELAY OPERATION

Zero delay operation aligns the phase of the output clocks with

the phase of the external PLL reference input. The OUT0 output

is designed to be used as the output for zero delay. There are

two zero delay modes on the AD9524: internal and external (see

Figure 29). Note that the external delay mode provides better

matching than the internal delay mode because the output

drivers are included in the zero delay path. Setting the anitbacklash

pulse width control of PLL1 to maximum gives the best zero

delay matching.

LOCK DETECT

PLL1 and PLL2 lock detectors issue an unlock condition when

the frequency error is greater than the threshold of the lock

detector. When the PLL is unlocked, there is a random phase

between the reference clock and feedback clock. Due to the

random phase relationship that exists the unlock condition

could take between 2¹⁵× T_PFDcycles to 1 × T_PFDcycles. For a

lock condition it will always take 2¹⁶× T_PFDto lock, but it could

potentially take 2³¹× T_PFDcycles depending on how big the

phase jump is and when it occurs in relation to the lock detect

restart.

Internal Zero Delay Mode

The internal zero delay function of the AD9524 is achieved

by feeding the output of Channel Divider 0 back to the PLL1

N divider. Bit 5 in Register 0x01B is used to select internal zero

delay mode (see Table 42). In the internal zero delay mode, the

output of Channel Divider 0 is routed back to the PLL1 (N divider)

Rev. F | Page 25 of 56

AD9524

Data Sheet

chip enters a reset mode and restores the chip either to the setting

RESET MODES

stored in EEPROM (EEPROM pin = 1) or to the on-chip setting

(EEPROM pin = 0), except for Register 0x000. Except for the

self clearing bits, Bit 2 and Bit 5, Register 0x000 retains its

previous value prior to reset. During the internal reset, the

outputs hold static. Bit 2 and Bit 5 are self clearing. However,

the self clearing operation does not complete until an additional

serial port SCLK cycle completes, and the AD9524 is held in

reset until Bit 2 and Bit 5 self clear.

The AD9524 has a power-on reset (POR) and several other ways to

apply a reset condition to the chip.

Power-On Reset

During chip power-up, a power-on reset pulse is issued when

3.3 V supply reaches ~2.6 V (<2.8 V) and restores the chip

either to the setting stored in EEPROM (EEPROM pin = 1) or

to the on-chip setting (EEPROM pin = 0). At power-on, the

AD9524 executes a SYNC operation, which brings the outputs

into phase alignment according to the default settings. The

output drivers are held in sync for the duration of the internally

generated power-up sync timer (~70 ms). The outputs begin to

toggle after this period.

Reset to Settings in EEPROM when EEPROM Pin = 0 via the

Serial Port

The serial port control register allows the chip to be reset to settings

in EEPROM when the EEPROM pin = 1 via Register 0xB02, Bit 1.

This bit is self clearing. This bit does not have any effect when the

EEPROM pin = 0. It takes ~40 ms for the outputs to begin toggling

after the Soft_EEPROM register is cleared.

RESET

Reset via the

, a reset (an asynchronous hard reset is executed by briefly

RESET

pulling

low), restores the chip either to the setting stored in

POWER-DOWN MODE

EEPROM (EEPROM pin = 1) or to the on-chip setting (EEPROM

pin = 0). A reset also executes a sync operation, which brings the

outputs into phase alignment according to the default settings.

When EEPROM is inactive (EEPROM pin = 0), it takes ~2 µs for

PD

Chip Power-Down via

PD

Place the AD9524 into a power-down mode by pulling the

low. Power-down turns off most of the functions and currents

inside the AD9524. The chip remains in this power-down state

is returned to a logic high state. When taken out of power-

down mode, the AD9524 returns to the settings programmed into

its registers prior to the power-down, unless the registers are

RESET

the outputs to begin toggling after

EEPROM is active (EEPROM pin = 1), it takes ~40 ms for the

RESET

is issued. When

PD

until

outputs to toggle after

Reset via the Serial Port

is brought high.

PD

changed by new programming while the

pin is held low.

The serial port control register allows for a reset by setting Bit 2

and Bit 5 in Register 0x000. When Bit 5 and Bit 2 are set, the

Rev. F | Page 26 of 56

Data Sheet

AD9524

SERIAL CONTROL PORT

The AD9524 serial control port is a flexible, synchronous serial

communications port that allows an easy interface with many

industry-standard microcontrollers and microprocessors. The

AD9524 serial control port is compatible with most synchronous

transfer formats, including Philips IꢀC®, Motorola® SPI, and

Intel® SSR protocols. The AD9524 IꢀC implementation deviates

from the classic IꢀC specification in two specifications, and

these deviations are documented in Table 16 of this data sheet.

The serial control port allows read/write access to all registers

that configure the AD9524.

I²C Bus Characteristics

Table 23. I²C Bus Definitions

Abbreviation

Definition

S

Start

Sr

P

Repeated start

Stop

A

W

R

Acknowledge

No acknowledge

Write

Read

SPI/I²C PORT SELECTION

One pulse on the SCL clock line is generated for each data bit

that is transferred.

The AD9524 has two serial interfaces, SPI and IꢀC. Users can select

either the SPI or IꢀC, depending on the states (logic high, logic low)

of the two logic level input pins, SP1 and SP0, when power is

The data on the SDA line must not change during the high period

of the clock. The state of the data line can change only when the

clock on the SCL line is low.

RESET

applied or after a

(each pin has an internal 40 kΩ pull-

down resistor). When both SP1 and SP0 are low, the SPI interface

is active. Otherwise, I2C is active with three different I2C slave

address settings (seven bits wide), as shown in Table 22. The

five MSBs of the slave address are hardware coded as 11000, and

the two LSBs are determined by the logic levels of the SP1 and

SP0 pins.

DATA LINE

STABLE;

DATA VALID

CHANGE

OF DATA

ALLOWED

SDA

SCL

Figure 30. Valid Bit Transfer

Table 22. Serial Port Mode Selection

A start condition is a transition from high to low on the SDA

line while SCL is high. The start condition is always generated

by the master to initialize the data transfer.

SP1

Low

High

SP0

Low

High

Low

High

Address

SPI

I²C: 1100000

I²C: 1100001

I²C: 1100010

A stop condition is a transition from low to high on the SDA

line while SCL is high. The stop condition is always generated

by the master to end the data transfer.

I²C SERIAL PORT OPERATION

SDA

The AD9524 IꢀC port is based on the IꢀC fast mode standard.

The AD9524 supports both IꢀC protocols: standard mode

(100 kHz) and fast mode (400 kHz).

SCL

S

P

START

STOP

The AD9524 IꢀC port has a 2-wire interface consisting of a serial

data line (SDA) and a serial clock line (SCL). In an IꢀC bus system,

the AD9524 is connected to the serial bus (data bus SDA and clock

bus SCL) as a slave device, meaning that no clock is generated by

the AD9524. The AD9524 uses direct 16-bit (two bytes) memory

addressing instead of traditional 8-bit (one byte) memory

addressing.

CONDITION

Figure 31. Start and Stop Conditions

A byte on the SDA line is always eight bits long. An acknowledge

bit must follow every byte. Bytes are sent MSB first.

Rev. F | Page 27 of 56

AD9524

Data Sheet

SDA

SCL

MSB

ACKNOWLEDGE FROM

SLAVE-RECEIVER

ACKNOWLEDGE FROM

SLAVE-RECEIVER

1

2

3 TO 7

8

9

1

2

3 TO 7

8

9

10

P

S

Figure 32. Acknowledge Bit

SDA

SCL

MSB = 0

ACKNOWLEDGE FROM

SLAVE-RECEIVER

ACKNOWLEDGE FROM

SLAVE-RECEIVER

1

2

3 TO 7

8

9

1

2

3 TO 7

8

9

10

P

Figure 33. Data Transfer Process (Master Write Mode, 2-Byte Transfer Used for Illustration)

MSB = 1

SDA

SCL

ACKNOWLEDGE FROM

MASTER-RECEIVER

NO ACKNOWLEDGE

FROM

SLAVE-RECEIVER

1

2

3 TO 7

8

9

1

2

3 TO 7

8

9

10

P

Figure 34. Data Transfer Process (Master Read Mode, 2-Byte Transfer Used for Illustration)

immediately after the slave address byte are the internal memory

(control registers) address bytes with the high address byte first.

This addressing scheme gives a memory address of up to ꢀ¹⁶− 1 =

65,535. The data bytes after these two memory address bytes are

register data written into the control registers. In read mode, the

data bytes after the slave address byte are register data read from

the control registers. A single I^ꢀC transfer can contain multiple data

bytes that can be read from or written to control registers whose

address is automatically incremented starting from the base

memory address.

The acknowledge bit is the ninth bit attached to any 8-bit data byte.

An acknowledge bit is always generated by the receiving device

(receiver) to inform the transmitter that the byte has been received.

It is accomplished by pulling the SDA line low during the ninth

clock pulse after each 8-bit data byte.

The no acknowledge bit is the ninth bit attached to any 8-bit data

byte. A no acknowledge bit is always generated by the receiving

device (receiver) to inform the transmitter that the byte has not

been received. It is accomplished by leaving the SDA line high

during the ninth clock pulse after each 8-bit data byte.

When all data bytes are read or written, stop conditions are

established. In write mode, the master (transmitter) asserts a stop

condition to end data transfer during the 10th clock pulse following

the acknowledge bit for the last data byte from the slave device

(receiver). In read mode, the master device (receiver) receives the

last data byte from the slave device (transmitter) but does not pull

it low during the ninth clock pulse. This is known as a no acknowl-

edge bit. Upon receiving the no acknowledge bit, the slave device

knows that the data transfer is finished and releases the SDA line.

The master then takes the data line low during the low period

before the 10th clock pulse and high during the 10th clock pulse

to assert a stop condition.

Data Transfer Process

The master initiates data transfer by asserting a start condition.

This indicates that a data stream follows. All I2C slave devices

connected to the serial bus respond to the start condition.

The master then sends an 8-bit address byte over the SDA line,

consisting of a 7-bit slave address (MSB first), plus an R/ bit.

This bit determines the direction of the data transfer, that is,

whether data is written to or read from the slave device

(0 = write, 1 = read).

W

The peripheral whose address corresponds to the transmitted

address responds by sending an acknowledge bit. All other

devices on the bus remain idle while the selected device waits

A repeated start (Sr) condition can be used in place of a stop

condition. Furthermore, a start or stop condition can occur at

any time, and partially transferred bytes are discarded.

For an I^ꢀC data write transfer containing multiple data bytes,

the peripheral drives a no acknowledge for the data byte that

follows a write to Register 0xꢀ34, thereby ending the I^ꢀC transfer.

For an I^ꢀC data read transfer containing multiple data bytes,

the peripheral drives data bytes of 0x00 for subsequent reads that

follow a read from Register 0xꢀ34.

W

for data to be read from or written to it. If the R/ bit is 0, the

W

master (transmitter) writes to the slave device (receiver). If the R/

bit is 1, the master (receiver) reads from the slave device (trans-

mitter). The format for these commands is described in the

Data Transfer Format section.

Data is then sent over the serial bus in the format of nine clock

pulses: one data byte (eight bits) from either master (write mode)

or slave (read mode), followed by an acknowledge bit from the

receiving device. The number of bytes that can be transmitted per

transfer is unrestricted. In write mode, the first two data bytes

Rev. F | Page 28 of 56

Data Sheet

AD9524

Data Transfer Format

Send byte format. The send byte protocol is used to set up the register address for subsequent commands.

S

Slave Address

W

A

RAM Address High Byte

A

RAM Address Low Byte

A

P

Write byte format. The write byte protocol is used to write a register address to the RAM, starting from the specified RAM address.

RAM Address

High Byte

RAM Address

Low Byte

RAM

Data 0

RAM

Data 1

RAM

Data 2

S

Slave Address

W

A

P

Receive byte format. The receive byte protocol is used to read the data byte(s) from the RAM, starting from the current address.

Slave Address RAM Data 0 RAM Data 1 RAM Data 2

S

R

A

Read byte format. The combined format of the send byte and the receive byte.

Slave

Address

RAM Address

High Byte

RAM Address

Low Byte

Slave

Sr Address

RAM

Data 0

RAM

Data 1

RAM

Data 2

A

S

W

A

R

A

P

I²C Serial Port Timing

SDA

t_RISE

t_{SET; DAT}

t_RISE

t_SPIKE

t_FALL

t_IDLE

t_{HLD; STR}

t_LOW

SCL

t_{SET; STP}

t_{HLD; STR}

t_{SET; STR}

t_HIGH

S

t_{HLD; DAT}

Sr

P

S

Figure 35. I²C Serial Port Timing

Table 24. IꢀC Timing Definitions

Parameter

Description

f_I2C

I²C clock frequency

t_IDLE

Bus idle time between stop and start conditions

Hold time for repeated start condition

Setup time for repeated start condition

Setup time for stop condition

Hold time for data

t_{HLD; STR}

t_{SET; STR}

t_{SET; STP}

t_{HLD; DAT}

t_{SET; DAT}

t_LOW

Setup time for data

Duration of SCL clock low

Duration of SCL clock high

SCL/SDA rise time

t_HIGH

t_RISE

t_FALL

SCL/SDA fall time

t_SPIKE

Voltage spike pulse width that must be suppressed by the input filter

Rev. F | Page 29 of 56

AD9524

Data Sheet

CS

First Transfers section).

must be raised at the end of the last

SPI SERIAL PORT OPERATION

Pin Descriptions

byte to be transferred, thereby ending streaming mode.

Communication Cycle—Instruction Plus Data

SCLK (serial clock) is the serial shift clock. This pin is an input.

SCLK is used to synchronize serial control port reads and writes.

Write data bits are registered on the rising edge of this clock,

and read data bits are registered on the falling edge. This pin

is internally pulled down by a 40 kΩ resistor to ground.

There are two parts to a communication cycle with the AD9524.

The first part writes a 16-bit instruction word into the AD9524,

coincident with the first 16 SCLK rising edges. The instruction

word provides the AD9524 serial control port with information

regarding the data transfer, which is the second part of the

communication cycle. The instruction word defines whether

the upcoming data transfer is a read or a write, the number of

bytes in the data transfer, and the starting register address for

the first byte of the data transfer.

SDIO (serial data input/output) is a dual-purpose pin and acts

either as an input only (unidirectional mode) or as an input/

output (bidirectional mode). The AD9524 defaults to the

bidirectional I/O mode.

SDO (serial data out) is used only in the unidirectional I/O mode

Write

CS

as a separate output pin for reading back data. (chip select bar)

If the instruction word is for a write operation, the second part

is the transfer of data into the serial control port buffer of the

AD9524. Data bits are registered on the rising edge of SCLK.

is an active low control that gates the read and write cycles. When

CS

is high, the SDO and SDIO pins enter a high impedance state.

This pin is internally pulled up by a 40 kΩ resistor to VDD3_REF.

The length of the transfer (one, two, or three bytes or streaming

mode) is indicated by two bits (W1, W0) in the instruction byte.

CS

AD9524

CS

When the transfer is one, two, or three bytes, but not streaming,

can be raised after each sequence of eight bits to stall the bus

SCLK/SCL

SERIAL

CONTROL

SDIO/SDA

PORT

(except after the last byte, where it ends the cycle). When the bus

SDO

CS

is stalled, the serial transfer resumes when

is lowered. Raising

pin on a nonbyte boundary resets the serial control port.

CS

the

Figure 36. Serial Control Port

During a write, streaming mode does not skip over reserved or

blank registers, and the user can write 0x00 to the reserved

register addresses.

SPI Mode Operation

In SPI mode, single or multiple byte transfers are supported,

as well as MSB first or LSB first transfer formats. The AD9524

serial control port can be configured for a single bidirectional

I/O pin (SDIO only) or for two unidirectional I/O pins (SDIO/

SDO). By default, the AD9524 is in bidirectional mode. Short

instruction mode (8-bit instructions) is not supported. Only

long (16-bit) instruction mode is supported. A write or a read

Because data is written into a serial control port buffer area, and

not directly into the actual control registers of the AD9524, an

additional operation is needed to transfer the serial control port

buffer contents to the actual control registers of the AD9524,

thereby causing them to become active. The update registers

operation consists of setting the self clearing IO_Update bit,

Bit 0 of Register 0x234 (see Table 58). Any number of data bytes

can be changed before executing an update registers operation.

The update registers simultaneously actuates all register changes

that have been written to the buffer since any previous update.

CS

operation to the AD9524 is initiated by pulling

low.

stalled high mode is supported in data transfers where

three or fewer bytes of data (plus instruction data) are transferred

CS

The

(see Table 25). In this mode, the

high on any byte boundary, allowing time for the system controller

CS

pin can temporarily return

Read

to process the next byte.

can go high only on byte boundaries;

The AD9524 supports only the long instruction mode. If the

instruction word is for a read operation, the next N × 8 SCLK

cycles clock out the data from the address specified in the

instruction word, where N is 1 to 3 as determined by Bits[W1:W0].

If N = 4, the read operation is in streaming mode, continuing

however, it can go high during either phase (instruction or data)

of the transfer.

During this period, the serial control port state machine enters

a wait state until all data is sent. If the system controller decides

to abort the transfer before all of the data is sent, the state machine

must be reset either by completing the remaining transfers or by

CS

until

is raised. During an SPI read, serial data on SDIO (or

SDO in the case of 4-wire mode) transitions on the SCLK falling

edge, and is normally sampled on the SCLK rising edge. To read

the last bit correctly, the SPI host must be able to tolerate a zero

hold time. In cases where zero hold time is not possible, the user

CS

returning

low for at least one complete SCLK cycle (but

CS

fewer than eight SCLK cycles). Raising the

pin on a nonbyte

boundary terminates the serial transfer and flushes the buffer.

CS

can either use streaming mode and delay the rising edge of , or

In streaming mode (see Table 25), any number of data bytes can

be transferred in a continuous stream. The register address is

automatically incremented or decremented (see the SPI MSB/LSB

sample the serial data on the SCLK falling edge. However, to

sample the data correctly on the SCLK falling edge, the user must

ensure that the setup time is greater than t_DV(time data valid).

Streaming mode does not skip over reserved or blank registers.

Rev. F | Page 30 of 56

Data Sheet

AD9524

The default mode of the AD9524 serial control port is the

bidirectional mode. In bidirectional mode, both the sent data

and the readback data appear on the SDIO pin. It is also possible to

set the AD9524 to unidirectional mode. In unidirectional mode,

the readback data appears on the SDO pin.

Bit 3. This makes it irrelevant whether LSB first or MSB first is

in effect. The default for the AD9524 is MSB first.

When LSB first is set by Register 0x000, Bit 1 and Register 0x000,

Bit 6, it takes effect immediately because it affects only the

operation of the serial control port and does not require that

an update be executed.

A readback request reads the data that is in the serial control port

buffer area or the data that is in the active registers (see Figure 37).

When MSB first mode is active, the instruction and data bytes

must be written from MSB to LSB. Multibyte data transfers in

MSB first format start with an instruction byte that includes the

register address of the most significant data byte. Subsequent

data bytes must follow in order from the high address to the

low address. In MSB first mode, the serial control port internal

address generator decrements for each data byte of the multibyte

transfer cycle.

CS

SERIAL

CONTROL

PORT

SCLK/SCL

SDIO/SDA

SDO

UPDATE

REGISTERS

ACTIVE

REGISTERS

BUFFER

REGISTERS

Figure 37. Relationship Between Serial Control Port Buffer Registers and

Active Registers

When LSB first mode is active, the instruction and data bytes

must be written from LSB to MSB. Multibyte data transfers in

LSB first format start with an instruction byte that includes the

register address of the least significant data byte, followed by

multiple data bytes. In a multibyte transfer cycle, the internal

byte address generator of the serial port increments for each byte.

SPI INSTRUCTION WORD (16 BITS)

W

The MSB of the instruction word is R/ , which indicates

whether the instruction is a read or a write. The next two bits

([W1:W0]) indicate the length of the transfer in bytes. The final

13 bits are the address ([A12:A0]) at which to begin the read or

write operation.

The AD9524 serial control port register address decrements

from the register address just written toward 0x000 for multibyte

I/O operations if the MSB first mode is active (default). If the

LSB first mode is active, the register address of the serial control

port increments from the address just written toward 0x234 for

multibyte I/O operations. Unused addresses are not skipped for

these operations.

For a write, the instruction word is followed by the number of

bytes of data indicated by Bits[W1:W0] (see Table 25).

Table 25. Byte Transfer Count

W1

W0

Bytes to Transfer

0

1

For multibyte accesses that cross Address 0x234 or Address 0x000

in MSB first mode, the SPI internally disables writes to subsequent

registers and returns zeros for reads to subsequent registers.

0

1

0

1

2

3

Streaming mode

Streaming mode always terminates when crossing address

boundaries (as shown in Table 26).

Bits[A12:A0] select the address within the register map that is

written to or read from during the data transfer portion of the

communications cycle. Only Bits[A11:A0] are needed to cover

the range of the 0x234 registers used by the AD9524. Bit A12

must always be 0. For multibyte transfers, this address is the

starting byte address. In MSB first mode, subsequent bytes

decrement the address.

Table 26. Streaming Mode (No Addresses Are Skipped)

Write Mode Address Direction Stop Sequence

MSB First

Decrement

…, 0x001, 0x000, stop

SPI MSB/LSB FIRST TRANSFERS

The AD9524 instruction word and byte data can be MSB first

or LSB first. Any data written to Register 0x000 must be mirrored:

Bit 7 is mirrored to Bit 0, Bit 6 to Bit 1, Bit 5 to Bit 2, and Bit 4 to

Table 27. Serial Control Port, 16-Bit Instruction Word, MSB First

MSB

LSB

I15

I14

I13

I12

I11

I10

I9

I8

I7

I6

I5

I4

I3

I2

I1

I0

R/W

W1

W0

A12 = 0 A11

A10

A9

A8

A7

A6

A5

A4

A3

A2

A1

A0

Rev. F | Page 31 of 56

AD9524

Data Sheet

t_DS

t_HIGH

t_S

t_C

t_SCLK

t_DH

t_LOW

CS

SCLK

SDIO

DON'T CARE

R/W

W1

W0

A12

A11

A10

A9

A8

A7

A6

A5

D4

D3

D2

D1 D0

HIGH-IMEPDANCE

Figure 38. Serial Control Port Read—MSB First, 16-Bit Instruction, One Byte of Data

CS

SCLK DON'T CARE

DON'T CARE

SDIO

R/W W1 W0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0

16-BIT INSTRUCTION HEADER REGISTER (N) DATA REGISTER (N – 1) DATA

Figure 39. Serial Control Port Write—MSB First, 16-Bit Instruction, Two Bytes of Data

CS

SCLK

DON'T CARE

R/W W1 W0 A12 A11A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

DON'T CARE

SDIO

D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0

SDO DON'T CARE

16-BIT INSTRUCTION HEADER

REGISTER (N) DATA

REGISTER (N – 1) DATA

REGISTER (N – 2) DATA

REGISTER (N – 3) DATA

DON'T

CARE

Figure 40. Serial Control Port Read—MSB First, 16-Bit Instruction, Four Bytes of Data

t_HIGH

t_DS

t_S

t_C

t_CLK

t_DH

t_LOW

CS

SCLK

SDIO

DON'T CARE

R/W

W1

W0

A12

A11

A10

A9

A8

A7

A6

A5

D4

D3

D2

D1

D0

Figure 41. Serial Control Port Write—MSB First, 16-Bit Instruction, Timing Measurements

CS

SCLK

t_DV

SDIO

SDO

DATA BIT N

DATA BIT N – 1

Figure 42. Timing Diagram for Serial Control Port Register Read

CS

SCLK DON'T CARE

DON'T CARE

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 W0 W1 R/W D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7

16-BIT INSTRUCTION HEADER REGISTER (N) DATA REGISTER (N + 1) DATA

DON'T CARE

SDIO

Figure 43. Serial Control Port Write—LSB First, 16-Bit Instruction, Two Bytes of Data

Rev. F | Page 32 of 56

Data Sheet

AD9524

t_S

t_C

CS

t_CLK

t_HIGH

t_LOW

t_DS

SCLK

SDIO

t_DH

BIT N

BIT N + 1

Figure 44. Serial Control Port Timing—Write

Table 28. Serial Control Port Timing

Parameter

Description

t_DS

t_DH

t_CLK

t_S

Setup time between data and rising edge of SCLK

Hold time between data and rising edge of SCLK

Period of the clock

Setup time between the CS falling edge and SCLK rising edge (start of communication cycle)

Setup time between the SCLK rising edge and CS rising edge (end of communication cycle)

Minimum period that SCLK should be in a logic high state

t_C

t_HIGH

t_LOW

t_DV

Minimum period that SCLK should be in a logic low state

SCLK to valid SDIO and SDO (see Figure 42)

Rev. F | Page 33 of 56

AD9524

Data Sheet

EEPROM OPERATIONS

The AD9524 contains an internal EEPROM (nonvolatile memory).

The EEPROM can be programmed by the user to create and store a

user defined register setting file when the power is off. This setting

file can be used for power-up and chip reset as a default setting. The

EEPROM size is 512 bytes. Descriptions of the EEPROM registers

that control EEPROM operation can be found in Table 59 and

Table 60.

AD9524 registers, or if they want to control the register

setting update sequence during power-up or chip reset.

4. Set the enable EEPROM write bit (Bit 0, Register 0xB02)

to 1 to enable the EEPROM.

5. Set the REG2EEPROM bit (Bit 0, Register 0xB03) to 1. This

starts the process of writing data into the EEPROM to create

the EEPROM setting file. This enables the EEPROM

controller to transfer the current register values, as well as the

memory address and instruction bytes from the EEPROM

buffer segment, into the EEPROM. After the write process

is completed, the internal controller sets bit REG2EEPROM

back to 0.

During the data transfer process, the write and read registers are

generally not available via the serial port, except for one readback

bit: Status_EEPROM (Register 0xB00, Bit 0).

To determine the data transfer state through the serial port in

SPI mode, users can read the value of the Status_EEPROM bit

(1 = data transfer in process and 0 = data transfer complete).

Bit 0 of the Status_EEPROM register (Register 0xB00) is used

to indicate the data transfer status between the EEPROM and

the control registers (1 = data transfer in process, and 0 = data

transfer complete). At the beginning of the data transfer, the

Status_EEPROM bit is set to 1 by the EEPROM controller and

cleared to 0 at the end of the data transfer. The user can access

Status_EEPROM via the STATUS0 pin when the STATUS0

pin is programmed to monitor the Status_EEPROM bit.

Alternatively, the user can monitor the Status_EEPROM bit

directly.

In I²C mode, the user can address the AD9524 slave port with

the external I²C master (send an address byte to the AD9524). If

the AD9524 responds with a no acknowledge bit, the data transfer

was not received. If the AD9524 responds with an acknowledge bit,

the data transfer process is complete. The user can monitor the

Status_EEPROM bit or use Register 0x232, Bit 4 to program

the STATUS0 pin to monitor the status of the data transfer (see

Table 56).

6. When the data transfer is complete (Status_EEPROM = 0),

set the enable EEPROM write bit (Bit 0 in Register 0xB02)

to 0. Clearing the enable EEPROM write bit to 0 disables

writing to the EEPROM.

To transfer all 512 bytes to the EEPROM, it takes approximately

46 ms. To transfer the contents of the EEPROM to the active

register, it takes approximately 40 ms.

RESET

, a hard reset (an asynchronous hard reset is executed by

To ensure that the data transfer has completed correctly, verify

that the EEPROM data error bit (Bit 0 in Register 0xB01) = 0.

A value of 1 in this bit indicates a data transfer error.

RESET

briefly pulling

low), restores the chip either to the setting

stored in EEPROM (the EEPROM pin = 1) or to the on-chip

setting (the EEPROM pin = 0). A hard reset also executes a SYNC

operation, which brings the outputs into phase alignment

according to the default settings. When EEPROM is inactive (the

EEPROM pin = 0), it takes ~2 µs for the outputs to begin

READING FROM THE EEPROM

The following reset-related events can start the process of

restoring the settings stored in the EEPROM to the control

registers. When the EEPROM_SEL pin is set high, do any of

the following to initiate an EEPROM read:

RESET

toggling after

EEPROM pin = 1), it takes ~40 ms for the outputs to toggle after

RESET

is issued. When EEPROM is active (the

is brought high.

•

Power up the AD9524.

Perform a hardware chip reset by pulling the

WRITING TO THE EEPROM

RESET

The EEPROM cannot be programmed directly through the serial

port interface. To program the EEPROM and store a register

setting file, follow these steps:

RESET

low and then releasing

.

•

Set the self clearing soft reset bit (Bit 5, Register 0x000) to 1.

When the EEPROM_SEL pin is set low, set the self clearing

Soft_EEPROM bit (Bit 1, Register 0xB02) to 1. The AD9524 then

starts to read the EEPROM and loads the values into the AD9524

registers. If the EEPROM_SEL pin is low during reset or power-up,

the EEPROM is not active, and the AD9524 default values are

loaded instead.

1. Program the AD9524 registers to the desired circuit state.

If the user wants PLL2 to lock automatically after power-up,

the calibrate VCO bit (Bit 1, Register 0x0F3) must be set to 1.

This allows VCO calibration to start automatically after

register loading. Note that a valid input reference signal

must be present during VCO calibration.

2. Set the IO_Update bit (Bit 0, Register 0x234) to 1.

3. Program the EEPROM buffer registers, if necessary (see

the Programming the EEPROM Buffer Segment section).

This step is necessary only if users want to use the EEPROM

to control the default settings of some (but not all) of the

When using the EEPROM to automatically load the AD9524

register values and lock the PLL, the calibrate VCO bit (Bit 1,

Register 0x0F3) must be set to 1 when the register values are

written to the EEPROM. This allows VCO calibration to start

automatically after register loading. A valid input reference

signal must be present during VCO calibration.

Rev. F | Page 34 of 56

Data Sheet

AD9524

To ensure that the data transfer has completed correctly, verify

that the EEPROM data error bit (Bit 0 in Register 0xB01) is set

to 0. A value of 1 in this bit indicates a data transfer error.

The next two bytes are the high byte and low byte of the

memory address (16 bits) of the first register in this group.

IO_Update (Operational Code 0x80)

PROGRAMMING THE EEPROM BUFFER SEGMENT

The EEPROM controller uses this operational code to generate

an IO_Update signal to update the active control register bank

from the buffer register bank during the download process.

The EEPROM buffer segment is a register space that allows the

user to specify which groups of registers are stored to the EEPROM

during EEPROM programming. Normally, this segment does not

need to be programmed by the user. Instead, the default power-up

values for the EEPROM buffer segment allow the user to store

all of the register values from Register 0x000 to Register 0x234

to the EEPROM.

At a minimum, there should be at least one IO_Update operational

code after the end of the final register section definition group. This

is needed so that at least one IO_Update occurs after all of the

AD9524 registers are loaded when the EEPROM is read. If this

operational code is absent during a write to the EEPROM, the

register values loaded from the EEPROM are not transferred to

the active register space, and these values do not take effect after

they are loaded from the EEPROM to the AD9524.

For example, if the user wants to load only the output driver

settings from the EEPROM without disturbing the PLL register

settings currently stored in the EEPROM, the EEPROM buffer

segment can be modified to include only the registers that apply

to the output drivers and exclude the registers that apply to the

PLL configuration.

End-of-Data (Operational Code 0xFF)

The EEPROM controller uses this operational code to terminate

the data transfer process between EEPROM and the control

register during the upload and download process. The last item

appearing in the EEPROM buffer segment should be either this

operational code or the pseudo-end-of-data operational code.

There are two parts to the EEPROM buffer segment: register

section definition groups and operational codes. Each register

section definition group contains the starting address and

number of bytes to be written to the EEPROM.

Pseudo-End-of-Data (Operational Code 0xFE)

If the AD9524 register map were continuous from Address 0x000

to Address 0x234, only one register section definition group

would consist of a starting address of 0x000 and a length of

563 bytes. However, this is not the case. The AD9524 register

map is noncontiguous, and the EEPROM is only 512 bytes long.

Therefore, the register section definition group tells the EEPROM

controller how the AD9524 register map is segmented.

The AD9524 EEPROM buffer segment has 23 bytes that can

contain up to seven register section definition groups. If users

want to define more than seven register section definition groups,

the pseudo-end-of-data operational code can be used. During

the upload process, when the EEPROM controller receives the

pseudo-end-of-data operational code, it halts the data transfer

process, clears the REG2EEPROM bit (Bit 0, Register 0xB03),

and enables the AD9524 serial port. Users can then program the

EEPROM buffer segment again and reinitiate the data transfer

process by setting the REG2EEPROM bit to 1 and the IO_Update

bit (Bit 0, Register 0x234) to 1. The internal I²C master then begins

writing to the EEPROM, starting from the EEPROM address

held from the last writing.

There are three operational codes: IO_Update, end-of-data, and

pseudo-end-of-data. It is important that the EEPROM buffer

segment always have either an end-of-data or a pseudo-end-of-data

operational code and that an IO_Update operation code appear at

least once before the end-of-data operational code.

Register Section Definition Group

This sequence enables more discrete instructions to be written

to the EEPROM than would otherwise be possible due to the

limited size of the EEPROM buffer segment. It also permits the

user to write to the same register multiple times with a different

value each time.

The register section definition group is used to define a continuous

register section for the EEPROM profile. It consists of three bytes.

The first byte defines how many continuous register bytes are in

this group. If the user puts 0x000 in the first byte, it means there is

only one byte in this group. If the user puts 0x001, it means there

are two bytes in this group. The maximum number of registers in

one group is 128.

Rev. F | Page 35 of 56

AD9524

Data Sheet

Table 29. Example of an EEPROM Buffer Segment

Register Address (Hex)

Bit 7 (MSB)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0 (LSB)

Start EEPROM Buffer Segment

0xA00

0xA01

0xA02

0xA03

0xA04

0xA05

0xA06

0xA07

0xA08

0xA09

0xA0A

0

Number of bytes of the first group of registers (Bits[6:0])

Address of the first group of registers (Bits[15:8])

Address of the first group of registers (Bits[7:0])

Number of bytes of the second group of registers (Bits[6:0])

Address of the second group of registers (Bits[15:8])

Address of the second group of registers (Bits[7:0])

Number of bytes of the third group of registers (Bits[6:0])

Address of the third group of registers (Bits[15:8])

Address of the third group of registers (Bits[7:0])

IO_Update operational code (0x80)

End-of-data operational code (0xFF)

Rev. F | Page 36 of 56

Data Sheet

AD9524

POWER DISSIPATION AND THERMAL CONSIDERATIONS

The AD9524 is a multifunctional, high speed device that targets

a wide variety of clock applications. The numerous innovative

features contained in the device each consume incremental power.

If all outputs are enabled in the maximum frequency and mode

that have the highest power, the safe thermal operating conditions

of the device may be exceeded. Careful analysis and consideration

of power dissipation and thermal management are critical

elements in the successful application of the AD9524 device.

CLOCK SPEED AND DRIVER MODE

Clock speed directly and linearly influences the total power

dissipation of the device and, therefore, the junction temperature.

Two operating frequencies are listed under the incremental power

dissipation parameter in Table 3. Using linear interpretation is

a sufficient approximation for frequency not listed in the table.

When calculating power dissipation for thermal consideration,

the amount of power dissipated in the 100 Ω resistor should be

removed. If using the data in Table 2, this power is already

removed. If using the current vs. frequency graphs provided in

the Typical Performance Characteristics section, the power into

the load must be subtracted, using the following equation:

The AD9524 device is specified to operate within the industrial

ambient temperature range of –40°C to +85°C. This specification is

conditional, however, such that the absolute maximum junction

temperature is not exceeded (as specified in Table 17). At high

operating temperatures, extreme care must be taken when

operating the device to avoid exceeding the junction temperature

and potentially damaging the device.

Differential Output Voltage Swing²

100 Ω

EVALUATION OF OPERATING CONDITIONS

A maximum junction temperature is listed in Table 1 with the

ambient operating range. The ambient range and maximum

junction temperature specifications ensure the performance of the

device as guaranteed in the Specifications section.

The first step in evaluating the operating conditions is to determine

the maximum power consumption (PD) internal to the AD9524.

The maximum PD excludes power dissipated in the load resistors

of the drivers because such power is external to the device. Use the

power dissipation specifications listed in Table 3 to calculate the

total power dissipated for the desired configuration. The base

typical configuration parameter in Table 3 lists a power of 428 mW,

which includes one LVPECL output at 122.88 MHz. If the

frequency of operation is not listed in Table 3, see the Typical

Performance Characteristics section, current vs. frequency and

driver mode, to calculate the power dissipation; then add 20% for

maximum current draw. Remove the power dissipated in the load

resistor to achieve the most accurate power dissipation internal

to the AD9524. See Table 30 for a summary of the incremental

power dissipation from the base power configuration for two

different examples.

Many variables contribute to the operating junction temperature

within the device, including

•

Selected driver mode of operation

Output clock speed

Supply voltage

Ambient temperature

The combination of these variables determines the junction

temperature within the AD9524 device for a given set of

operating conditions.

The AD9524 is specified for an ambient temperature (T_A). To

ensure that T_Ais not exceeded, an airflow source can be used.

Use the following equation to determine the junction

temperature on the application PCB:

Table 30. Temperature Gradient Examples

Frequency

(MHz)

Maximum

Power (mW)

T_J= T_CASE+ (Ψ_JT× PD)

Description

Example 1

Mode

where:

T_Jis the junction temperature (°C).

Base Typical

Configuration

428

T

_CASEis the case temperature (°C) measured by the user at the

top center of the package.

_JTis the value from Table 18.

Output Driver

Total Power

Example 2

5 × LVPECL

122.88

983.04

275

703

Ψ

PD is the power dissipation of the AD9524.

Base Typical

Configuration

428

Values of θ_JAare provided for package comparison and PCB

design considerations. θ_JAcan be used for a first-order

approximation of T_Jby the equation

Output Driver

5 × LVPECL

795

Total Power

1223

T_J= T_A+ (θ_JA× PD)

where T_Ais the ambient temperature (°C).

The second step is to multiply the power dissipated by the

thermal impedance to determine the maximum power

Values of θ_JCare provided for package comparison and PCB design

considerations when an external heat sink is required.

gradient. For this example, a thermal impedance of θ_JA

20.1°C/W was used.

=

Values of Ψ_JBare provided for package comparison and PCB design

considerations.

Rev. F | Page 37 of 56

AD9524

Data Sheet

Example 1

THERMALLY ENHANCED PACKAGE MOUNTING

GUIDELINES

(703 mW × 20.1°C/W) = 14.1°C

Refer to the AN-772 Application Note, A Design and

Manufacturing Guide for the Lead Frame Chip Scale Package

(LFCSP), for more information about mounting devices with

an exposed paddle.

With an ambient temperature of 85°C, the junction temperature is

T_J= 85°C + 14.1°C = 99°C

This junction temperature is below the maximum allowable.

Example 2

(1223 mW × 20.1°C/W) = 24.6°C

With an ambient temperature of 85°C, the junction temperature is

T_J= 85°C + 24.6°C = 109°C

This junction temperature is below the maximum allowable.

Rev. F | Page 38 of 56

Data Sheet

AD9524

CONTROL REGISTERS

CONTROL REGISTER MAP

Register addresses that are not listed in Table 31 are not used, and writing to those registers has no effect. Registers that are marked as

reserved should never have their values changed. When writing to registers with bits that are marked reserved, the user should take care

to always write the default value for the reserved bits.

Table 31. Control Register Map

Default

Addr

(Hex)

Register

Name

(MSB)

Bit 7

(LSB)

Bit 0

Value

(Hex)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Serial Port Configuration

0x000

SPI mode

serial port

configuration

I²C mode

serial port

configuration

SDO

active

LSB first/

address

increment

Soft reset

Reserved

Reserved Soft reset

Reserved Reserved

LSB first/

address

increment

SDO active

Reserved

0x00

Reserved

Soft reset

Reserved

0x004

Readback

control

Reserved

Read back

active registers

0x005

0x006

EEPROM

customer

version ID

EEPROM customer version ID[7:0] (LSB)

EEPROM customer version ID[15:8] (MSB)

0x00

Input PLL (PLL1)

0x010

0x011

PLL1 REFA

R divider

control

10-bit REFA R divider[7:0] (LSB)

0x00

Reserved

10-bit REFA R divider[9:8]

(MSB)

0x012

0x013

PLL1 REFB

R divider

control

10-bit REFB R divider[7:0] (LSB)

Reserved

0x00

10-bit REFB R divider[9:8]

(MSB)

0x014

PLL1 reference Reserved

test divider

Reserved

REF_TEST divider

0x00

0x015

0x016

0x017

PLL1 reserved Reserved

Reserved

Reserved Reserved

Reserved

0x00

PLL1 feedback

N divider

control

10-bit PLL1 feedback divider[7:0] (LSB)

Reserved

10-bit PLL1 feedback

divider[9:8] (MSB)

0x018

0x019

0x01A

PLL1 charge

pump control

PLL1

PLL1 charge pump control

0x0C

0x00

charge

pump

tristate

Reserved

REFB

differential differential enable

receiver

enable

Reserved

REFA

Enable SPI

control of

Antibacklash pulse

width control

PLL1 charge pump mode

antibacklash

pulse width

PLL1

input receiver

control

REF_TEST

input

receiver

enable

REFB receiver

REFA

Input

OSC_IN

receiver

enable

REFA, REFB

receiver

power-

down

differential

receiver

mode enable

single-ended

receiver

mode enable

(CMOS mode)

receiver

enable

control

enable

0x01B

0x01C

REF_TEST,

REFA, REFB,

and ZD_IN

control

Reserved

Zero delay

mode

OSC_IN signal

feedback

for PLL1

ZD_IN

single-

ended

receiver

mode

enable

(CMOS

mode)

ZD_IN

REFB

REFA

0x00

differen.

receiver

mode

single-ended single-ended

receiver mode receiver

enable

mode enable

enable

(CMOS mode) (CMOS mode)

PLL1

Enable

OSC_CTRL

control

Reserved

Reference selection mode

Reserved

miscellaneous REFB

control R divider

voltage to

VCC/2

when ref

indepen.

division

control

clock fails

Rev. F | Page 39 of 56

AD9524

Data Sheet

Default

Value

(Hex)

Addr

(Hex)

Register

Name

(MSB)

Bit 7

(LSB)

Bit 0

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

0x01D

PLL1 loop

Reserved

PLL1 loop filter, R_ZERO

0x00

filter zero

resistor control

Output PLL (PLL2)

0x0F0

PLL2 charge

pump control

PLL2 charge pump control

0x00

0x04

0x0F1

PLL2

A counter

B counter

feedback

N divider

control

0x0F2

0x0F3

PLL2 control

PLL2 lock

detector

power-

down

Reserved

Enable

frequency

doubler

Enable SPI

control of

antibacklash

Antibacklash pulse

width control

PLL2 charge pump mode

0x03

0x00

pulse width

VCO control

Reserved

Force release

of distribution

sync when

PLL2 is

Reserved Force

VCO to

Calibrate VCO Reserved

(not auto-

clearing)

midpoint

frequency

unlocked

0x0F4

VCO divider

control

Reserved

VCO

VCO divider

0x00

divider

power-

down

0x0F5

0x0F6

PLL2 loop

filter control

(9 bits)

Pole 2 resistor (R_POLE2

)

Zero resistor (R_ZERO

Reserved

)

Pole 1 capacitor (C_POLE1)

Reserved

Reserved Reserved

Reserved

Bypass internal 0x00

_ZEROresistor

Reserved

R

0x0F9

Reserved

0x00

Clock Distribution

0x190

0x196

Reserved

Lower power

mode

0x00

Channel 0

control

Invert

divider

Ignore

sync

Power-

down

Driver mode

output

channel

0x197

0x198

0x199

10-bit channel divider[7:0] (LSB)

0x1F

Divider phase[5:0]

10-bit channel divider[9:8] (MSB) 0x04

Channel 1

control

Invert

divider

output

Ignore

sync

Power-

down

channel

Lower power

mode

Driver mode

0x20

0x19A

0x19B

0x19C

10-bit channel divider[7:0] (LSB)

0x1F

Divider phase[5:0]

10-bit channel divider[9:8] (MSB) 0x04

Channel 2

control

Invert

divider

Ignore

sync

Power-

down

Lower power

mode

Driver mode

0x00

output

channel

0x19D

0x19E

0x19F

10-bit channel divider[7:0] (LSB)

0x1F

Divider phase[5:0]

10-bit channel divider[9:8] (MSB) 0x04

Channel 3

control

Invert

divider

output

Ignore

sync

Power-

down

channel

Lower power

mode

Driver mode[3:0]

0x20

0x1A0

0x1A1

0x1AE

10-bit channel divider[7:0] (LSB)

0x1F

Divider phase[5:0]

10-bit channel divider[9:8] (MSB) 0x04

Channel 4

control

Invert

divider

Ignore

sync

Power-

down

Lower power

mode

Driver mode

0x00

output

channel

0x1AF

0x1B0

0x1B1

10-bit channel divider[7:0] (LSB)

0x1F

Divider phase[5:0]

10-bit channel divider[9:8] (MSB) 0x04

Channel 5

control

Invert

divider

output

Ignore

sync

Power-

down

channel

Lower power

mode

Driver mode

0x20

0x1B2

0x1B3

10-bit channel divider[7:0] (LSB)

0x1F

Divider phase[5:0]

10-bit channel divider[9:8] (MSB) 0x04

Rev. F | Page 40 of 56

Data Sheet

AD9524

Default

Value

(Hex)

Addr

(Hex)

Register

Name

(MSB)

Bit 7

(LSB)

Bit 0

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

0x1BA

PLL1 output

control

Reserved

PLL1 output

CMOS driver

strength

PLL1 output divider

0x00

0x1BB

PLL1 output

channel

control

PLL1

Reserved

Reserved Reserved

Route VCXO

clock to Ch 1

divider input

Route VCXO

clock to Ch 0

divider input

0x80

output

driver

power-

down

Readback

0x22C

Readback 0

Status

PLL2

Status

PLL1

Status

VCXO

Status

REF_TEST

Status

REFB

Status

REFA

Lock detect

PLL2

Lock detect

PLL1

reference

clock

feedback

clock

0x22D

Readback 1

Reserved

Holdover Selected

Reserved

VCO

active

reference

(in auto

mode)

calibration

in progress

Other

0x230

0x231

0x232

Status signals

Reserved

Status Monitor 0 control

Status Monitor 1 control

STATUS1 STATUS0

0x00

Reserved

Enable Status_

EEPROM on

Reserved

Sync dividers

(manual

STATUS0 pin

divider

enable

divider

enable

control)

0: sync signal

inactive

1: dividers

held in sync

(same as

SYNC

pin low)

0x233

0x234

Power-down

control

Reserved

Reserved PLL1

power-

down

PLL2

power-down

Distribution

power-down

0x07

0x00

Update all

registers

IO_Update

EEPROM Buffer

Serial port

0xA00

0xA01

0xA02

0xA03

0xA04

0xA05

0xA06

0xA07

0xA08

0xA09

0xA0A

0xA0B

0xA0C

0xA0D

0xA0E

Size of transfer: one byte

0x00

0x02

0x00

0x04

0x0E

0x00

0x10

0x0E

0x00

0xF0

0x2B

0x01

0x90

configuration

Starting address: 0x0000

Readback

control and

EEPROM

customer

version ID

Size of transfer: three bytes

Starting address: 0x0004

PLL1

Size of transfer: 15 bytes

Starting address: 0x0010

PECL/CMOS

output

Size of transfer: 15 bytes

Starting address: 0x00F0

Dividers

Size of transfer: 44 bytes

Starting address: 0x0190

Rev. F | Page 41 of 56

AD9524

Data Sheet

Default

Value

(Hex)

Addr

(Hex)

Register

Name

(MSB)

Bit 7

(LSB)

Bit 0

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

0xA0F

0xA10

0xA11

0xA12

0xA13

0xA14

Clock input

and REF

Size of transfer: two bytes

0x01

0xE0

0x03

0x02

0x30

Starting address: 0x01E0

Other

Size of transfer: four bytes

Starting address: 0x0230

0xA15

0xA16

IO_UPDATE

End of data

Command: IO_UPDATE

Command: End of data

0x80

0xFF

EEPROM Control

0xB00

Status_

EEPROM

(read only)

Reserved

Reserved Reserved

Reserved

Status_

EEPROM

(read only)

0x00

0xB01

EEPROM error Reserved

checking

EEPROM

data error

readback

(read only)

0xB02

0xB03

EEPROM

Control 1

Reserved

Reserved Reserved

Soft_EEPROM Enable

EEPROM write

REG2EEPROM

0x00

EEPROM

Control 2

Reserved

Rev. F | Page 42 of 56

Data Sheet

AD9524

CONTROL REGISTER MAP BIT DESCRIPTIONS

Serial Port Configuration (Address 0x000 to Address 0x006)

Table 32. SPI Mode Serial Port Configuration

Address Bits Bit Name

Description

0x000

7

SDO active

Selects unidirectional or bidirectional data transfer mode. This bit is ignored in I²C mode.

0: SDIO pin used for write and read; SDO is high impedance (default).

1: SDO used for read; SDIO used for write; unidirectional mode.

6

LSB first/

address

increment

SPI MSB or LSB data orientation. This bit is ignored in I²C mode.

0: data-oriented MSB first; addressing decrements (default).

1: data-oriented LSB first; addressing increments.

5

4

Soft reset

Soft reset.

1 (self clearing): soft reset; restores default values to internal registers.

Reserved

Reserved.

[3:0] Mirror[7:4]

Bits[3:0] should always mirror Bits[7:4] so that it does not matter whether the part is in MSB first or LSB

first mode (see Register 0x000, Bit 6). Set bits as follows:

Bit 0 = Bit 7.

Bit 1 = Bit 6.

Bit 2 = Bit 5.

Bit 3 = Bit 4.

0x004

0

Read back

active registers

For buffered registers, serial port readback reads from actual (active) registers instead of from the buffer.

0 (default): reads values currently applied to the internal logic of the device.

1: reads buffered values that take effect on the next assertion of the I/O update.

Table 33. I²C Mode Serial Port Configuration

Address Bits Bit Name

Description

0x000 [7:6] Reserved

Reserved.

5

4

Soft reset

Reserved

Soft reset.

1 (self clearing): soft reset; restores default values to internal registers.

Reserved.

[3:0] Mirror[7:4]

Bits[3:0] should always mirror Bits[7:4]. Set bits as follows:

Bit 0 = Bit 7.

Bit 1 = Bit 6.

Bit 2 = Bit 5.

Bit 3 = Bit 4.

0x004

0

Read back

active registers

For buffered registers, serial port readback reads from actual (active) registers instead of from the buffer.

0 (default): reads values currently applied to the internal logic of the device.

1: reads buffered values that take effect on the next assertion of the I/O update.

Table 34. EEPROM Customer Version ID

Address Bits Bit Name Description

0x005

[7:0] EEPROM

customer

16-bit EEPROM ID, Bits[7:0]. This register, along with Register 0x006, allows the user to store a unique

ID to identify which version of the AD9524 register settings is stored in the EEPROM. It does not affect

version ID (LSB) AD9524 operation in any way (default: 0x00).

0x006

[7:0] EEPROM

customer

16-bit EEPROM ID, Bits[15:8]. This register, along with Register 0x005, allows the user to store a unique

ID to identify which version of the AD9524 register settings is stored in the EEPROM. It does not affect

version ID (MSB) AD9524 operation in any way (default: 0x00).

Rev. F | Page 43 of 56

AD9524

Data Sheet

Input PLL (PLL1) (Address 0x010 to Address 0x01D)

Table 35. PLL1 REFA R Divider Control

Address Bits

Bit Name

Description

[7:0]

REFA R divider

10-bit REFA R divider, Bits[7:0] (LSB). Divide-by-1 to divide-by-1023.

00000000, 00000001: divide-by-1.

0x010

0x011

[1:0]

10-bit REFA R divider, Bits[9:8] (MSB)

Table 36. PLL1 REFB R Divider Control¹

Address Bits

Bit Name

Description

[7:0]

REFB R divider

10-bit REFB R divider, Bits[7:0] (LSB). Divide-by-1 to divide-by-1023.

00000000, 00000001: divide-by-1.

0x012

0x013

[1:0]

10-bit REFB R divider, Bits[9:8] (MSB)

¹Requires Register 0x01C, Bit 7 = 1 for division that is independent of REFA division.

Table 37. PLL1 Reference Test Divider

Address Bits

Bit Name

Description

0x014

[7:6]

[5:0]

Reserved

REF_TEST divider

6-bit reference test divider. Divide-by-1 to divide-by-63.

000000, 000001: divide-by-1.

Table 38. PLL1 Reserved

Address Bits Bit Name

0x015 [7:0] Reserved

Description

Reserved

Table 39. PLL1 Feedback N Divider Control

Address Bits

Bit Name

Description

[7:0]

PLL1 feedback N divider control

(N_PLL1)

10-bit feedback divider, Bits[7:0] (LSB). Divide-by-1 to divide-by-1023.

00000000, 00000001: divide-by-1.

0x016

0x017

[1:0]

10-bit feedback divider, Bits[1:0] (MSB)

Table 40. PLL1 Charge Pump Control

Address Bits

Bit Name

Description

0x018

7

PLL1 charge pump tristate

PLL1 charge pump control

Tristates the PLL1 charge pump.

[6:0]

These bits set the magnitude of the PLL1 charge pump current. Granularity is ~0.5 μA

with a full-scale magnitude of ~63.5 μA.

0x019

[7:5]

4

Reserved

Reserved.

Enable SPI control of antibacklash

pulse width

Controls the functionality of Register 0x019, Bits[3:2].

0 (default): the device automatically controls the antibacklash period to high

(equivalent to Register 0x019, Bits[3:2] = 10).

1: antibacklash period defined by Register 0x019, Bits[3:2].

[3:2]

[1:0]

Antibacklash pulse width control Controls the PFD antibacklash period. These bits default to the high setting unless

reprogrammed using Register 0x019[4] = 1b. The high setting decreases the

maximum allowable PLL1 PFD rate. See Table 7 for ranges.

00: minimum.

01: low.

10: high (initial state unless changed via Register 0x019[4] = 1b).

11: maximum.

PLL1 charge pump mode

Controls the mode of the PLL1 charge pump.

00: (default) tristate.

01: pump up.

10: pump down.

11: normal.

Rev. F | Page 44 of 56

Data Sheet

AD9524

Table 41. PLL1 Input Receiver Control

Address Bits

Bit Name

Description

0x01A

7

6

5

4

REF_TEST input receiver enable

1: enabled.

0: disabled (default).

REFB differential receiver enable

REFA differential receiver enable

REFB receiver enable

1: differential receiver mode.

0: single-ended receiver mode (also depends on Register 0x01B, Bit 1) (default).

1: differential receiver mode.

0: single-ended receiver mode (also depends on Register 0x01B, Bit 0) (default).

REFB receiver power-down control mode only when Bit 2 = 1.

1: enable REFB receiver.

0: power-down (default).

3

2

1

REFA receiver enable

REFA receiver power-down control mode only when Bit 2 = 1.

1: enable REFA receiver.

0: power-down (default).

Input REFA and REFB receiver

power-down control enable

Enables power-down control of the input receivers, REFA and REFB.

1: power-down control enabled.

0: both receivers enabled (default).

OSC_IN single-ended receiver

mode enable (CMOS mode)

Selects which single-ended input pin is enabled when in the single-ended receiver

mode (Register 0x01A, Bit 0 = 0).

1: negative receiver from oscillator input (OSC_IN pin) selected.

0: positive receiver from oscillator input (OSC_IN pin) selected (default).

0

OSC_IN differential receiver mode 1: differential receiver mode.

enable 0: single-ended receiver mode (also depends on Bit 1) (default).

Table 42. REF_TEST, REFA, REFB, and ZD_IN Control

Address Bits

Bit Name

Description

0x01B [7:6] Reserved

0: reserved (default).

5

4

3

Zero delay mode

Selects the zero delay mode used (via the ZD_IN pin) when Register 0x01B, Bit 4 = 0.

Otherwise, this bit is ignored.

1: internal zero delay mode. The zero delay receiver is powered down. The internal

zero delay path from Distribution Divider Channel 0 is used.

0: external zero delay mode. The ZD_IN receiver is enabled.

OSC_IN signal feedback for PLL1

Controls the input PLL feedback path, local feedback from the OSC_IN receiver or

zero delay mode.

1: OSC_IN receiver input used for the input PLL feedback (non-zero delay mode).

0: zero delay mode enabled (also depends on Register 0x01B, Bit 4 to select the

zero delay path.

ZD_IN single-ended receiver

mode enable (CMOS mode)

Selects which single-ended input pin is enabled when in the single-ended receiver

mode (Register 0x01B, Bit 2 = 0).

1: ZD_IN pin enabled.

0: ZD_IN pin enabled.

2

1

ZD_IN differential receiver mode

enable

1: differential receiver mode.

0: single-ended receiver mode (also depends on Register 0x01B, Bit 3).

REFB single-ended receiver mode Selects which single-ended input pin is enabled when in single-ended receiver mode

(Register 0x01A, Bit 6 = 0).

1: REFB pin enabled.

0: REFB pin enabled.

enable (CMOS mode)

0

REFA single-ended receiver mode Selects which single-ended input pin is enabled when in single-ended receiver mode

(Register 0x01A, Bit 5 = 0).

1: REFA pin enabled.

0: REFA pin enabled.

enable (CMOS mode)

Rev. F | Page 45 of 56

AD9524

Data Sheet

Table 43. PLL1 Miscellaneous Control

Address Bits Bit Name

Description

0x01C

7

Enable REFB R divider

independent division control

1: REFB R divider is controlled by Register 0x012 and Register 0x013.

0: REFB R divider is set to the same setting as the REFA R divider (Register 0x010

and Register 0x011). This requires that, for the loop to stay locked, the REFA and

REFB input frequencies must be the same.

6

OSC_CTRL control voltage to

VCC/2 when reference clock fails

High permits the OSC_CTRL control voltage to be forced to midsupply when the

feedback or input clocks fail. Low tristates the charge pump output.

1: OSC_CTRL control voltage goes to VCC/2.

0: OSC_CTRL control voltage tracks the tristated (high impedance) charge pump

(through the buffer).

5

Reserved

Reserved.

[4:2] Reference selection mode

Programs the REFA, REFB mode selection (default = 000).

REF_SEL

X¹

0

Bit 4

Bit 3

0

Bit 2

0

Description

0

1

Nonrevertive: stay on REFB.

Revert to REFA.

0

1

0

Select REFA.

1

Select REFB.

X¹

REF_SEL pin = 0 (low): REFA.

REF_SEL pin = 1 (high): REFB.

1

[1:0] Reserved

0: reserved (default).

¹X = don’t care.

Table 44. PLL1 Loop Filter Zero Resistor Control

Address

Bits Bit Name

Description

0x01D

[7:4] Reserved

Reserved.

[3:0] PLL1 loop filter, R_ZERO

Programs the value of the zero resistor, R_ZERO.

Bit 3

Bit 2

Bit 1

Bit 0

R_ZEROValue (kΩ)

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

883

677

341

135

10

Use external resistor

Rev. F | Page 46 of 56

Data Sheet

AD9524

Output PLL (PLL2) (Address 0x0F0 to Address 0x0F9)

Table 45. PLL2 Charge Pump Control

Address Bits Bit Name

Description

0x0F0

[7:0] PLL2 charge pump control

These bits set the magnitude of the PLL2 charge pump current. Granularity is ~3.5 μA

with a full-scale magnitude of ~900 μA.

Table 46. PLL2 Feedback N Divider Control

Address

Bits Bit Name

[7:6] A counter

[5:0] B counter

Description

0x0F1

A counter word

B counter word

Feedback Divider Constraints

A Counter (Bits[7:6])

A = 0 or A = 1

B Counter (Bits[5:0])

Allowed N Division (4 × B + A)

16, 17

B = 4

B = 5

B = 6

B ≥ 7

A = 0 to A = 2

20, 21, 22

A = 0 to A = 2

24, 25, 26

A = 0 to A = 3

28, 29 … continuous to 255

Table 47. PLL2 Control

Address Bits Bit Name

Description

0x0F2

7

PLL2 lock detector power-down

Controls power-down of the PLL2 lock detector.

1: lock detector powered down.

0: lock detector active.

6

5

Reserved

Default = 0; value must remain 0.

Enable frequency doubler

Enables doubling of the PLL2 reference input frequency.

1: enabled.

0: disabled.

4

Enable SPI control of antibacklash

pulse width

Controls the functionality of Register 0x0F2, Bits[3:2]. Set the antibacklash pulse

width to the minimum setting. By setting Bit 4 to 1 from the default of 0, Bits[3:2]

consequently default to 00.

0 (default): device automatically controls the antibacklash period to high

(equivalent to Register 0x0F2, Bits[3:2] = 10).

1: antibacklash period defined by Register 0x0F2, Bits[2:1] (recommended setting).

[3:2]

Antibacklash pulse width control

PLL2 charge pump mode

Controls the PFD antibacklash period. These bits default to the high setting unless

reprogrammed using Register 0x0F2[4] = 1b. The high setting decreases the

maximum allowable PLL2 PFD rate. See Table 12 for ranges.

00 minimum.

01: low.

10: high (initial state unless changed via Register 0x0F2[4] = 1b).

11: maximum.

[1:0]

Controls the mode of the PLL2 charge pump.

00: tristate.

01: pump up.

10: pump down.

11 (default): normal.

Rev. F | Page 47 of 56

AD9524

Data Sheet

Table 48. VCO Control

Address Bits Bit Name

Description

0x0F3

[7:5] Reserved

Reserved.

4

Force release of distribution sync

when PLL2 is unlocked

0 (default): distribution is held in sync (static) until the output PLL locks. Then it is

automatically released from sync with all dividers synchronized.

1: overrides the PLL2 lock detector state; forces release of the distribution from

sync.

3

2

Reserved

0 (default): value must remain 0.

Force VCO to midpoint frequency Selects VCO control voltage functionality.

0 (default): normal VCO operation.

1: forces VCO control voltage to midscale.

1

0

Calibrate VCO (not autoclearing)

Reserved

1: initiates VCO calibration (this is not an autoclearing bit).

0: resets the VCO calibration.

Reserved.

Table 49. VCO Divider Control

Address Bits Bit Name

Description

Reserved.

0x0F4

[7:4] Reserved

3

VCO divider power-down 1: powers down the divider.

0: normal operation.

[2:0] VCO divider

Note that the VCO divider connects to all output channels.

Bit 2

Bit 1

Bit 0

Divider Value

Divide-by-4

Divide-by-5

Divide-by-6

Divide-by-7

Divide-by-8

Divide-by-9

Divide-by-10

Divide-by-11

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Rev. F | Page 48 of 56

Data Sheet

AD9524

Table 50. PLL2 Loop Filter Control

Address Bits

Bit Name

Description

0x0F5

[7:6]

Pole 2 resistor (R_POLE2

)

R_POLE2

(Ω)

Bit 7

Bit 6

0

1

0

1

0

1

900

450

300

225

[5:3]

Zero resistor (R_ZERO

)

R_ZERO

(Ω)

Bit 5

Bit 4

Bit 3

0

1

0

1

0

1

0

1

0

1

0

1

0

1

3250

2750

2250

2100

3000

2500

2000

1850

[2:0]

Pole 1 capacitor (C_POLE1

)

C_POLE1

(pF)

Bit 2

Bit 1

Bit 0

0

1

0

1

0

1

0

1

0

1

0

1

0

8

0

16

24

32

40

48

0

1

0x0F6

[7:1]

0

Reserved

Reserved.

Bypass internal R_ZERO

resistor

Bypasses the internal R_ZEROresistor (R_ZERO= 0 Ω). Requires the use of a series external zero resistor.

This bit is the MSB of the loop filter control register (Address 0x0F5 and Address 0x0F6).

Rev. F | Page 49 of 56

AD9524

Data Sheet

Reserved (Address 0x190)

Table 51. Reserved Register

Address Bits Bit Name

Description

0x190

[7:5] Reserved

Reserved. The default value for this register is 0x00. It is recommended to write a value

of 0x20 to this register.

Clock Distribution (Address 0x196 to Address 0x1A1, Address 0x1AE to Address 0x1B3, Address 0x1BA, and Address

0x1BB)

Table 52. Channel 0 to Channel 5 Control (This same map applies to all six channels.)

Address Bits

Bit Name

Description

0x196

7

6

Invert divider output

Ignore sync

Inverts the polarity of the divider’s output clock.

0: obeys chip-level SYNC signal (default).

1: ignores chip-level SYNC signal.

5

4

Power-down channel

1: powers down the entire channel.

0: normal operation.

Lower power mode

(differential modes only)

Reduces power used in the differential output modes (LVDS/LVPECL/HSTL). This

reduction may result in power savings, but at the expense of performance. Note that

this bit does not affect output swing and current, just the internal driver power.

1: low strength/lower power.

0: normal operation.

[3:0] Driver mode

Driver mode.

Bit 3 Bit 2 Bit 1 Bit 0 Driver Mode

0

1

0

1

0

1

0

1

0

1

0

1

0

Tristate output

LVPECL (8 mA)

LVDS (3.5 mA)

LVDS (7 mA)

HSTL-0 (16 mA)

HSTL-1 (8 mA)

CMOS (both outputs in phase)

+ Pin: true phase relative to divider output

− Pin: true phase relative to divider output

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

CMOS (opposite phases on outputs)

+ Pin: true phase relative to divider output

− Pin: complement phase relative to divider output

CMOS

+ Pin: true phase relative to divider output

− Pin: high-Z

CMOS

+ Pin: high-Z

− Pin: true phase relative to divider output

CMOS

+ Pin: high-Z

− Pin: high-Z

CMOS (both outputs in phase)

+ Pin: complement phase relative to divider output

− Pin: complement phase relative to divider output

CMOS (both outputs out of phase)

+ Pin: complement phase relative to divider output

− Pin: true phase relative to divider output

CMOS

+ Pin: complement phase relative to divider output

− Pin: high-Z

CMOS

+ Pin: high-Z

− Pin: complement phase relative to divider output

Rev. F | Page 50 of 56

Data Sheet

AD9524

Address Bits

Bit Name

Description

1

Tristate output

0x197

0x198

[7:0] Channel divider, Bits[7:0] (LSB) Division = Channel Divider Bits[9:0] + 1. For example, [9:0] = 0 is divided by 1, [9:0] = 1

is divided by 2 … [9:0] = 1023 is divided by 1024. 10-bit channel divider, Bits[7:0] (LSB).

[7:2] Divider phase

Divider initial phase after a sync is asserted relative to the divider input clock (from the

VCO divider output). LSB = ½ of a period of the divider input clock.

Phase = 0: no phase offset.

Phase = 1: ½ period offset, …

Phase = 63: 31 period offset.

[1:0] Channel divider, Bits[9:8] (MSB) 10-bit channel divider, Bits[9:8] (MSB).

Table 53. PLL1 Output Control (PLL1_OUT, Pin 46)

Address Bits Bit Name Description

0x1BA [7:5] Reserved

PLL1 output CMOS driver

strength

Reserved

4

CMOS driver strength

1: weak

0: strong

[3:0] PLL1 output divider

0000: divide-by-1

0001: divide-by-2 (default)

0010: divide-by-4

0100: divide-by-8

1000: divide-by-16

No other inputs permitted

Table 54. PLL1 Output Channel Control

Address Bits Bit Name

Description

0x1BB

7

PLL1 output driver power-down PLL1 output driver power-down

[6:2] Reserved

Reserved

1

Route VCXO clock to

Channel 1 divider input

1: channel uses VCXO clock. Routes VCXO clock to divider input

0: channel uses VCO divider output clock

0

Route VCXO clock to

Channel 0 divider input

1: channel uses VCXO clock. Routes VCXO clock to divider input

0: channel uses VCO divider output clock

Readback (Address 0x22C to Address 0x22D)

Table 55. Readback Registers (Readback 0 and Readback 1)

Address Bits Bit Name Description

0x22C

7

6

5

4

3

2

1

0

Status PLL2 reference clock

Status PLL1 feedback clock

Status VCXO

1: OK

0: off/clocks are missing

1: OK

0: off/clocks are missing

1: OK

0: off/clocks are missing

Status REF_TEST

Status REFB

1: OK

0: off/clocks are missing

1: OK

0: off/clocks are missing

Status REFA

1: OK

0: off/clocks are missing

Lock detect PLL2

Lock detect PLL1

1: locked

0: unlocked

1: locked

0: unlocked

Rev. F | Page 51 of 56

AD9524

Data Sheet

Address Bits Bit Name

Description

0x22D

[7:4] Reserved

Reserved

3

Holdover active

1: holdover is active (both references are missing)

0: normal operation

2

Selected reference

(in auto mode)

Selected reference (applies only when the device automatically selects the reference;

for example, not in manual control mode)

1: REFB

0: REFA

1

0

Reserved

VCO calibration in progress

1: VCO calibration in progress

0: VCO calibration not in progress

Other (Address 0x230 to Address 0x234)

Table 56. Status Signals

Address Bits Bit Name

0x230 [7:6] Reserved

[5:0] Status Monitor 0 control Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Muxout

Description

Reserved

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

GND

PLL1 and PLL2 locked

PLL1 locked

PLL2 locked

Both references are missing (REFA and REFB)

Both references are missing and PLL2 is locked

REFB selected (applies only to auto select mode)

REFA is OK

REFB is OK

REF_TEST is OK

VCXO is OK

PLL1 feedback is OK

PLL2 reference clock is OK

Reserved

REFA and REFB are OK

All clocks are OK (except REF_TEST)

PLL1 feedback is divide-by-2

PLL1 PFD down divide-by-2

PLL1 REF divide-by-2

PLL1 PFD up divide-by-2

GND

Note that all bit combinations after 010111 are reserved.

Rev. F | Page 52 of 56

Data Sheet

AD9524

Address Bits Bit Name

Description

0x231

[7:6] Reserved

Reserved.

[5:0] Status Monitor 1 control Bit 5

Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Muxout

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

GND

PLL1 and PLL2 locked

PLL1 locked

PLL2 locked

Both references are missing (REFA and REFB)

Both references are missing and PLL2 is locked

REFB selected (applies only to auto select mode)

REFA is OK

REFB is OK

REF_TEST is OK

VCXO is OK

PLL1 feedback is OK

PLL2 reference clock is OK

Reserved

REFA and REFB are OK

All clocks are OK (except REF_TEST)

GND

PLL2 feedback is divide-by-2

PLL2 PFD down divide-by-2

PLL2 REF divide-by-2

PLL2 PFD up divide-by-2

Note that all bit combinations after 010111 are reserved.

Reserved.

0x232

[7:5] Reserved

4

Enable Status_EEPROM

on STATUS0 pin

Enables the EEPROM status on the STATUS0 pin.

1: enable status.

3

STATUS1 pin divider

enable

Enables a divide-by-4 on the STATUS1 pin, allowing dynamic signals to be viewed at a lower

frequency (such as the PFD input clocks). Not to be used with dc states on the status pins,

which occur when the settings of Register 0x231, Bits[5:0] are in the range of 000000 to 001111.

1: enabled.

0: disabled.

2

STATUS0 pin divider

enable

Enables a divide-by-4 on the STATUS0 pin, allowing dynamic signals to be viewed at a lower

frequency (such as the PFD input clocks). Not to be used with dc states on the status pins,

which occur when the settings of Register 0x230, Bits[5:0] are in the range of 000000 to 001111.

1: enable.

0: disable.

1

0

Reserved

Reserved.

Sync dividers

Set bit to put dividers in sync; clear bit to release. Functions like SYNC pin low.

(manual control)

1: sync.

0: normal.

Rev. F | Page 53 of 56

AD9524

Data Sheet

Table 57. Power-Down Control

Address Bits Bit Name

Description

0x233

[7:3] Reserved

Reserved.

2

1

0

PLL1 power-down

1: power-down (default).

0: normal operation.

PLL2 power-down

1: power-down (default).

0: normal operation.

Distribution power-

down

Powers down the distribution.

1: power-down (default).

0: normal operation.

Table 58. Update All Registers

Address Bits Bit Name

Description

0x234

[7:1] Reserved

IO_Update

Reserved.

0

This bit must be set to 1 to transfer the contents of the buffer registers into the active registers,

which happens on the next SCLK rising edge. This bit is self clearing; that is, it does not have to

be set back to 0.

1 (self clearing): update all active registers to the contents of the buffer registers.

EEPROM Buffer (Address 0xA00 to Address 0xA16)

Table 59. EEPROM Buffer Segment

Address Bits Bit Name

Description

0xA00

to

[7:0] EEPROM Buffer

The EEPROM buffer segment section stores the starting address and number of bytes that are to

Segment Register 1 to be stored and read back to and from the EEPROM. Because the register space is noncontiguous,

0xA16

EEPROM Buffer

Segment Register 23

the EEPROM controller needs to know the starting address and number of bytes in the register

space to store and retrieve from the EEPROM. In addition, there are special instructions for the

EEPROM controller: operational codes (that is, IO_Update and end-of-data) that are also stored

in the EEPROM buffer segment. The on-chip default setting of the EEPROM buffer segment

registers is designed such that all registers are transferred to/from the EEPROM, and an

IO_Update is issued after the transfer (see the Programming the EEPROM Buffer Segment section).

EEPROM Control (Address 0xB00 to Address 0xB03)

Table 60. Status_EEPROM

Address Bits

0xB00 [7:1] Reserved

Status_EEPROM

(read only)

Bit Name

Description

Reserved.

0

This read-only bit indicates the status of the data transferred between the EEPROM and the

buffer register bank during the writing and reading of the EEPROM. This signal is also available

at the STATUS0 pin when Register 0x232, Bit 4 is set.

0: data transfer is complete.

1: data transfer is not complete.

Table 61. EEPROM Error Checking Readback

Address Bits

0xB01 [7:1] Reserved

EEPROM data error

(read only)

Bit Name

Description

Reserved.

0

This read-only bit indicates an error during the data transfer between the EEPROM and the buffer.

0: no error; data is correct.

1: incorrect data detected.

Rev. F | Page 54 of 56

Data Sheet

AD9524

Table 62. EEPROM Control 1

Address Bits

Bit Name

Description

0xB02 [7:2] Reserved

Reserved.

1

0

Soft_EEPROM

When the EEPROM_SEL pin is tied low, setting the Soft_EEPROM bit resets the AD9524 using

the settings saved in EEPROM.

1: soft reset with EEPROM settings (self clearing).

Enable EEPROM write

Enables the user to write to the EEPROM.

0: EEPROM write protection is enabled. User cannot write to EEPROM (default).

1: EEPROM write protection is disabled. User can write to EEPROM.

Table 63. EEPROM Control 2

Address Bits Bit Name

0xB03 [7:1] Reserved

REG2EEPROM

Description

Reserved.

0

Transfers data from the buffer register to the EEPROM (self clearing).

1: setting this bit initiates the data transfer from the buffer register to the EEPROM (writing

process); it is reset by the I²C master after the data transfer is done.

Rev. F | Page 55 of 56

AD9524

Data Sheet

OUTLINE DIMENSIONS

7.10

7.00 SQ

6.90

0.30

0.23

0.18

0.60 MAX

PIN 1

INDICATOR

37

36

48

1

PIN 1

INDICATOR

0.50

REF

6.85

5.25

5.10 SQ

4.95

EXPOSED

PAD

6.75 SQ

6.65

25

24

12

13

0.50

0.40

0.30

0.25 MIN

TOP VIEW

5.50 REF

0.80 MAX

0.65 TYP

12° MAX

1.00

0.85

0.80

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

0.05 MAX

0.02 NOM

COPLANARITY

SECTION OF THIS DATA SHEET.

SEATING

PLANE

0.08

0.20 REF

COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2

Figure 45. 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

7 × 7 mm Body, Very Thin Quad

(CP-48-1)

Dimensions shown in millimeters

ORDERING GUIDE

Model¹

Temperature Range

Package Description

Package Option

CP-48-1

AD9524BCPZ

AD9524BCPZ-REEL7

AD9524/PCBZ

−40°C to +85°C

48-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

Evaluation Board

¹Z = RoHS Compliant Part.

I²C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).

registered trademarks are the property of their respective owners.

D09081-0-9/15(F)

Rev. F | Page 56 of 56


型号：	AD9524BCPZ
厂家：	ADI
描述：	6 Output, Dual Loop Clock Generator 时钟外围集成电路晶体
文件：	总57页 (文件大小：968K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AD9524BCPZ [ADI]

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