AD9640BCPZ-150_技术文档

14-Bit, 80/105/125/150 MSPS, 1.8 V

Dual Analog-to-Digital Converter

AD9640

Preliminary Technical Data

FEATURES

APPLICATIONS

SNR = 71.7 dBc (72.7dBFS) to 70 MHz @ 150 MSPS

SFDR = 85 dBc to 70 MHz @ 150 MSPS

Low Power: 780 mW

Communications

Diversity radio systems

Multimode digital receivers:

1.8V analog supply operation

GSM, EDGE, PHS, UMTS, WCDMA, CDMA-ONE,

IS95, CDMA2000, IMT-2000, WiMax

I/Q demodulation systems

Smart antenna systems

General-purpose software radios

Broadband data applications

1.8V to 3.3V CMOS output supply or 1.8V LVDS supply

Integer 1 to 8 Input Clock Divider

IF sampling frequencies to 450 MHz

Internal ADC voltage reference

Integrated ADC sample-and-hold inputs

Flexible analog input: 1 V p-p to 2 V p-p range

Differential analog inputs with 650MHz bandwidth

ADC clock duty cycle stabilizer

95 dB channel isolation/crosstalk

Serial Port Control

User-configurable built-in self-test (BIST) capability

Energy-saving power-down modes

Integrated Receive Features:

Fast Detect/Threshold Bits

Composite Signal monitor

FUNCTIONAL BLOCK DIAGRAM

Figure 1. AD9640 Functional Block Diagram

Rev. PrD

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However, no responsibility is assumed by Analog Devices for its use, nor for any

infringements of patents or other rights of third parties that may result from its use.

Specifications subject to change without notice. No license is granted by implication

or otherwise under any patent or patent rights of Analog Devices. Trademarks and

registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.326.8703

www.analog.com

AD9640

Preliminary Technical Data

TABLE OF CONTENTS

General Description......................................................................... 4

Gain Switching............................................................................ 25

SIGNAL Monitor............................................................................ 27

Peak Detector Mode (Mode Bits 01) ....................................... 27

RMS/MS Magnitude Mode (Mode Bits 00)............................ 27

Threshold Crossing Mode (Mode Bits 1x).............................. 28

Additional Control Bits ............................................................. 28

DC Correction............................................................................ 29

Signal monitor SPORT OUTPUT............................................ 29

Built-In Self-Test (BIST) and Output test ................................... 30

Built in self test (BIST)............................................................... 30

output test modes....................................................................... 30

Channel/Chip Synchronization.................................................... 31

Serial Port Interface (SPI).............................................................. 32

Configuration Using the SPI..................................................... 32

Hardware Interface..................................................................... 32

Configuration WITHOUT the SPI.......................................... 33

Memory Map .............................................................................. 33

SPI Accessible Features.............................................................. 33

External memory MaP................................................................... 35

memory map register description............................................ 38

Applications..................................................................................... 39

Design Guidelines ...................................................................... 39

AD9640 Evaluation Board and Software..................................... 40

Outline Dimensions....................................................................... 41

Ordering Guide .......................................................................... 41

Product Highlights....................................................................... 4

Specifications..................................................................................... 5

ADC DC Specifications............................................................... 5

ADC AC Specifications ............................................................... 6

Digital specifications.................................................................... 7

switching specifications............................................................... 8

Absolute Maximum Ratings............................................................ 9

Thermal Characteristics .............................................................. 9

ESD Caution.................................................................................. 9

Pin Configuration and Function Descriptions........................... 10

Equivalent circuits .......................................................................... 13

Typical Performance Characteristics ........................................... 14

Timing Diagrams............................................................................ 15

Terminology .................................................................................... 16

Theory of Operation ...................................................................... 17

ADC Architecture ...................................................................... 17

Analog Input Considerations.................................................... 17

Voltage Reference ....................................................................... 19

Clock Input Considerations...................................................... 20

Power Dissipation and Standby Mode..................................... 22

Digital Outputs ........................................................................... 22

Timing.......................................................................................... 23

ADC OVERRANGE and GaIN control ...................................... 24

Fast detect overview................................................................... 24

ADC Fast Magnitude ................................................................. 24

ADC overrange (OVR).............................................................. 25

Rev. PrD | Page 2 of 41

Preliminary Technical Data

AD9640

REVISION HISTORY

12/06—Revision PrD:

9/06—Revision PrC:

8/06—Revision PrB: Preliminary Version

Rev. PrD | Page 3 of 41

AD9640

Preliminary Technical Data

GENERAL DESCRIPTION

14-bit output ports. These outputs can be set from 1.8V to

3.3V CMOS. Or 1.8V LVDS.

The AD9640 is a dual 14-Bit 150 MSPS ADC. The AD9640 is

designed to support communications applications where low

cost, small size, and versatility are desired.

Flexible power-down options allow significant power savings,

when desired.

The dual ADC core features a multistage differential pipelined

architecture with integrated output error correction logic. Each

ADC features wide bandwidth differential sample-and-hold

analog input amplifiers supporting a variety of user-selectable

input ranges. An integrated voltage reference eases design

considerations. A duty cycle stabilizer is provided to compen-

sate for variations in the ADC clock duty cycle, allowing the

converters to maintain excellent performance.

PRODUCT HIGHLIGHTS

•

Integrated dual 14-Bit 150 MSPS ADC.

•

Fast Over-range Detect and Signal monitor with Serial

Output

•

Signal monitor block with dedicate serial output mode.

The AD9640 has several functions which simply the AGC

function in the system receiver. The fast detect feature allows

fast overrange detection by outputting 4 bits of input level

information with very short latency. Additionally, the

programmable threshold detector allows monitoring of the

incoming signal power from the ADC’s 4 fast detect bits with

very low latency. If the input signal level exceeds the

programmable threshold, the decrement gain indicator will go

high. Because this threshold is set from the 4 MSB’s this allows

the user to quickly turn down the system gain to avoid an

overrange condition. The second AGC related function is the

Signal monitor. This block allows the user to monitor the

composite magnitude of the incoming signal which aids in

setting the gain to optimize the dynamic range of the overall

system.

Proprietary, differential input maintains excellent SNR

performance for input frequencies up to 450 MHz.

•

The AD9640 operates from a single 1.8 Volt supply and

features a separate digital output driver supply to

accommodate 1.8 V to 3.3 V logic families.

A standard serial port interface supports various product

features and functions, such as data formatting (offset

binary, twos complement, or gray coding), enabling the

clock DCS, power-down, and voltage reference mode.

•

The AD9640 is pin compatible with the AD9627, allowing

a simple migration from 12 to 14 Bits.

The ADC output data can be routed directly to the two external

Rev. PrD | Page 4 of 41

Preliminary Technical Data

AD9640

SPECIFICATIONS

ADC DC SPECIFICATIONS

AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, DCS

enabled, Fast Detect Outputs disabled, Signal Monitor disabled, unless otherwise noted.

Table 1.

AD9640BCPZ-80

Typ

AD9640BCPZ-105

AD9640BCPZ-125

AD9640BCPZ-150

Unit

Bits

Parameter

Temp

Min

Max

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

RESOLUTION

ACCURACY

Full

14

No Missing Codes

Offset Error

Gain Error

Full

Guaranteed

±±.3

Guaranteed

±±.3

Guaranteed

±±.3

Guaranteed

±±.3

±TBD

% FSR

LSB

±2.±

±1.ꢀ

Differential

Nonlinearity (DNL)¹

25°C

Full

±±.4

±2

±±.4

±1.ꢁ

±±.4

±2

±±.4

±2

LSB

Integral Nonlinearity

(INL)

±TBD

25°C

LSB

TEMPERATURE DRIFT

Offset Error

Full

±15

±ꢂ5

±15

±ꢂ5

±15

±ꢂ5

±15

±ꢂ5

ppm/°C

Gain Error

INTERNAL VOLTAGE

REFERENCE

Output Voltage Error

(1 V Mode)

Full

TBD

mV

Load Regulation @ 1.±

mA

INPUT REFERRED NOISE

VREF = 1.± V

25°C

Full

TBD

2

TBD

2

TBD

2

TBD

2

LSB rms

V p-p

ANALOG INPUT

Input Span, VREF = 1.±

V

Input Capacitance²

VREF INPUT RESISTANCE

POWER SUPPLIES

Supply Voltage

Full

ꢁ

6

ꢁ

6

pF

ꢁ

6

ꢁ

6

kΩ

1.ꢀ

1.ꢁ

3.3

1.ꢂ

3.6

1.ꢀ

1.ꢁ

3.3

1.ꢂ

3.6

AVDD, DVDD

Full

1.ꢀ

1.ꢁ

3.3

1.ꢂ

3.6

1.ꢀ

1.ꢁ

3.3

1.ꢂ

3.6

V

DRVDD (CMOS

Mode)

Supply Current

IAVDD

21ꢂ

2ꢂ

2ꢂ2

3ꢀ

Full

363

45

3ꢁ4

4ꢀ.5

53.3

TBD

mA

IDVDD

mA

3±

3ꢂ

IDRVDD (3.3V)

IDRVDD (1.ꢁV)

PSRR

4ꢀ

mA

TBD

±±.±1

TBD

±±.±1

TBD

±±.±1

mA

±±.±1

% FSR

POWER CONSUMPTION

DC Input

TBD

Full

TBD

mW

Sine Wave Input

(DRVDD=1.ꢁV)

546

ꢀ21

Sine Wave Input

(DRVDD=3.3V)

Full

ꢁꢂ±

ꢂ53

mW

Standby Power³

Full

TBD

mW

TBD

Powerdown Power

¹Measured with a low input frequency, full-scale sine wave, with approximately 5 pF loading on each output bit.

²Input capacitance refers to the effective capacitance between one differential input pin and AGND. Refer to Figure x for the equivalent analog input structure.

³Standby power is measured with a dc input, the CLK pins inactive (set to AVDD or AGND).

Rev. PrD | Page 5 of 41

AD9640

Preliminary Technical Data

ADC AC SPECIFICATIONS

AVDD = 1.8 V, DVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, DCS

Enabled, Fast Detect Outputs disabled, Signal Monitor disabled, unless otherwise noted.

Table 2.

AD9640BCPZ-80

AD9640BCPZ-105

AD9640BCPZ-125

AD9640BCPZ-150

Parameter

Temp

Unit

Min

Typ

ꢀ2.±

ꢀ1.ꢂ

Max

Min

Typ

ꢀ1.ꢂ

Max

Min

Typ

ꢀ1.ꢂ

ꢀ1.ꢀ

Max

Min

Typ

ꢀ1.ꢂ

ꢀ1.ꢀ

Max

SIGNAL-TO-NOISE-RATIO (SNR)

f_IN= 2.4 MHz

25°C

Full

dB

f_IN= ꢀ± MHz

25°C

Full

TBD

f_IN= 1±± MHz

f_IN= 1ꢀ± MHz

25°C

ꢀ1.6

6ꢂ.ꢂ

ꢀ1.6

ꢀ±.ꢂ

ꢀ1.6

ꢀ±.ꢁ

ꢀ1.6

ꢀ±.ꢁ

SIGNAL-TO-NOISE-AND

DISTORTION (SINAD)

ꢀ1.1

ꢀ1.5

ꢀ1.1

ꢀ±.ꢁ

ꢀ1.1

ꢀ±.6

ꢀ1.1

ꢀ±.6

f_IN= 2.4 MHz

25°C

Full

dB

f_IN= ꢀ± MHz

25°C

Full

TBD

ꢀ±.5

6ꢁ.±

ꢀ±.6

6ꢂ.ꢂ

ꢀ±.6

6ꢂ.ꢁ

ꢀ±.6

6ꢂ.ꢁ

f_IN= 1±± MHz

f_IN= 1ꢀ± MHz

25°C

EFFECTIVE NUMBER OF BITS

(ENOB)

25°C

11.ꢀ

11.6

11.5

11.ꢀ

11.6

11.5

11.ꢀ

11.6

11.5

11.ꢀ

11.6

11.5

Bits

f_IN= 2.4 MHz

f_IN= ꢀ± MHz

f_IN= 1±± MHz

f_IN= 1ꢀ± MHz

WORST SECOND OR THIRD

HARMONIC

25°C

Full

ꢂ±

ꢁ5

ꢂ±

ꢁ5

ꢂ±

ꢁ5

ꢂ±

ꢁ5

dBc

f_IN= 2.4 MHz

25°C

Full

f_IN= ꢀ± MHz

25°C

ꢁ5

ꢁ4

ꢁ5

ꢁ3

f_IN= 1±± MHz

f_IN= 1ꢀ± MHz

ꢁ3.4

SPURIOUS-FREE DYNAMIC RANGE

(SFDR)

25°C

Full

ꢂ±

ꢁ5

ꢂ±

ꢁ5

ꢂ±

ꢁ5

ꢂ±

ꢁ5

dBc

f_IN= 2.4 MHz

25°C

Full

f_IN= ꢀ± MHz

25°C

ꢁ5

ꢁ4

ꢁ5

ꢁ3

ꢁ±

f_IN= 1±± MHz

ꢁ3.4

f_IN= 1ꢀ± MHz

TWO TONE SFDR

25°C

TBD

dBc

f_IN= 3± MHz, 31 MHz (−ꢀ dBFS )

f_IN= 1ꢀ± MHz, 1ꢀ1 MHz (−ꢀ

dBFS )

Full

ꢂ5

dB

CROSSTALK

25°C

65±

MHz

ANALOG INPUT BANDWIDTH

MATCHING CHARACTERISTIC

Offset Error

TBD

25°C

TBD

%FSR

Gain Error

¹Measured with a low input frequency, full-scale sine wave, with approximately 5 pF loading on each output bit.

²Input capacitance refers to the effective capacitance between one differential input pin and AGND. Refer to Figure x for the equivalent analog input structure.

³Standby power is measured with a dc input, the CLK pin inactive (set to AVDD or AGND).

Rev. PrD | Page 6 of 41

Preliminary Technical Data

AD9640

DIGITAL SPECIFICATIONS

AVDD = 1.8 V, DVDD = 1.8V, DRVDD = 1.8 V, maximum sample rate, −1.0 dBFS differential input, 1.0 V internal reference, DCS

enabled, unless otherwise noted.

Table 3.

Parameter

Temp

AD9640BCPZ-80

Min Typ Max

AD9640BCPZ-105

AD9640BCPZ-125

AD9640BCPZ-150

Unit

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

DIFFERENTIAL CLOCK INPUTS (CLK+,

CLK-)

Logic Compliance

CMOS/LVDS/LVPECL

Internal Common-Mode Bias

Differential Input Voltage

Full

1.2

6

1.2

6

1.2

6

V

±.2

6

±.2

Vp-p

V

AVDD-

±.3

AVDD+

1.5

AVDD-

±.3

AVDD+

1.5

AVDD-

±.3

AVDD+

1.5

AVDD-

±.3

AVDD+

1.5

Input Voltage Range

Full

1.1V

AVDD

1.1V

AVDD

1.1V

AVDD

1.1V

AVDD

Input Common-Mode Range

High Level Input Voltage

Low Level Input Voltage

High Level Input Current

Low Level Input Current

Input Capacitance

V

TBD

V

±.ꢁ

Full

±.ꢁ

V

−1±

+1±

−1±

+1±

−1±

+1±

−1±

+1±

μA

pF

ΚΩ

TBD

1±

TBD

1±

TBD

1±

TBD

1±

Full

ꢁ

12

ꢁ

12

ꢁ

12

ꢁ

12

Input Resistance

LOGIC INPUTS (CSB, SCLK/DCS, OE,

PWDN)

High Level Input Voltage

Low Level Input Voltage

High Level Input Current

Low Level Input Current

Input Resistance

Full

TBD

V

±.ꢁ

V

−1±

+1±

−1±

+1±

−1±

+1±

−1±

+1±

μA

kΩ

pF

TBD

Input Capacitance

LOGIC INPUTS (SDIO/DFS)

High Level Input Voltage

Low Level Input Voltage

High Level Input Current

Low Level Input Current

Input Resistance

Full

1.2

V

±.ꢁ

V

−1±

+1±

−1±

+1±

−1±

+1±

−1±

+1±

μA

kΩ

pF

TBD

Input Capacitance

DIGITAL OUTPUTS

DRVDD = 3.3 V

3.2ꢂ

3.25

3.2ꢂ

3.25

High Level Output Voltage

(I_OH= 5± μA)

Full

3.2ꢂ

3.25

3.2ꢂ

3.25

V

High Level Output Voltage

(I_OH= ±.5 mA)

±.2

Low Level Output Voltage (I_OL

= 1.6 mA)

±.2

±.±5

Low Level Output Voltage (I_OL

= 5± μA)

±.±5

DRVDD = 1.ꢁ V

1.ꢀꢂ

1.ꢀ5

1.ꢀꢂ

1.ꢀ5

High Level Output Voltage

(I_OH= 5± μA)

Full

1.ꢀꢂ

1.ꢀ5

1.ꢀꢂ

1.ꢀ5

V

High Level Output Voltage

(I_OH= ±.5 mA)

±.2

Low Level Output Voltage (I_OL

= 1.6 mA)

±.2

±.±5

Low Level Output Voltage (I_OL

= 5± μA)

±.±5

Rev. PrD | Page ꢀ of 41

AD9640

Preliminary Technical Data

SWITCHING SPECIFICATIONS

Table 4.

Parameter

Temp

AD9640BCPZ-80

AD9640BCPZ-105

AD9640BCPZ-125

AD9640BCPZ-150

Unit

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

Min

Typ

Max

CLOCK INPUT PARAMETERS

Maximum Conversion Rate

Minimum Conversion Rate

Full

ꢁ±

1±5

125

15±

MSPS

ns

1±

CLK Period(t_CLK

CLK Pulse Width High¹(t_CLKH

CLK Pulse Width Low¹(t_CLKL

CLK Pulse Width High²(t_CLKH

CLK Pulse Width Low(t_CLKL

)

12.5

TBD

ꢂ.5

ꢁ

6.66

TBD

)

t_CLK/2

TBD

t_CLK/2

TBD

t_CLK/2

ns

)

ns

)

ns

DATA OUTPUT PARAMETERS

Data Propagation Delay

Full

TBD

ns

3

(t_PD)

DCO Propagation Delay

(t_DCO

)

Setup Time (t_S)

Full

ꢁ.5

12

ꢁ.5

12

ꢁ.5

12

ꢁ.5

12

ns

Hold Time (t_H)

ns

Pipeline Delay (Latency)

Aperture Delay (t_A)

Cycles

ns

TBD

±.1

TBD

±.1

TBD

±.1

TBD

±.1

Aperture Uncertainty (Jitter,

t_J)

ps rms

Wake-Up Time⁴

Full

TBD

ms

OUT-OF-RANGE RECOVERY

TIME

Parameter (Conditions)

Min

Typ

Max

Unit

RESET

TIMING REQUIREMENTS

t_RESLRESET

SYNC TIMING REQUIREMENTS

TBD

ns

Width Low

t_SS

TBD

ns

SYNC to ↑CLK Setup Time

SYNCto ↑CLK Hold Time

t_HS

SPI TIMING REQUIREMENTS

t_DS

t_DH

t_CLK

t_S

Set-up time between the data and the rising edge of SCLK

Hold time between the data and the rising edge of SCLK

Period of the SCLK

5

ns

5

4±

Set-up time between CSB and SCLK

TBD

t_H

Hold time between CSB and SCLK

t_HI

t_LO

Minimum period that SCLK should be in a logic high state

Minimum period that SCLK should be in a logic low state

¹With duty cycle stabilizer (DCS) enabled.

²With duty cycle stabilizer (DCS) disabled.

³Output propagation delay is measured from CLK 5±% transition to DATA 5±% transition, with 5 pF load.

⁴Wake-up time is dependant on the value of the decoupling capacitors.

Rev. PrD | Page ꢁ of 41

Preliminary Technical Data

AD9640

ABSOLUTE MAXIMUM RATINGS

Table 5.

Parameter

Stresses above those listed under the Absolute Maximum

Rating

Ratings may cause permanent damage to the device. This is a

stress rating only; functional operation of the device at these or

any other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

ELECTRICAL

AVDD, DVDD to AGND

DRVDD to DRGND

AGND to DRGND

VIN+A/B, VIN-A/B to AGND

CSB to AGND

−±.3 V to +2.± V

−±.3 V to +3.ꢂ V

−±.3 V to +±.3 V

−±.3 V to AVDD + ±.2 V

−±.3 V to +3.ꢂV

THERMAL CHARACTERISTICS

D±A/B through D13A/B to DRGND

FD±A/B through FD3A/B to DRGND

DCOA/B to DRGND

VREF to AGND

−±.3 V to DRVDD + ±.3 V

−±.3 V to AVDD + ±.3 V

−±.3 V to AVDD + ±.2 V

The exposed paddle must be soldered to the ground plane for

the LFCSP package. Soldering the exposed paddle to the

customer board increases the reliability of the solder joints,

maximizing the thermal capability of the package.

SENSE to AGND

ENVIRONMENTAL

Operating Temperature Range

(Ambient)

Maximum Junction Temperature

Under Bias

Table 6. Thermal Resistance

Package Type

−4±°C to +ꢁ5°C

15±°C

θ_JA

θ_JC

Unit

64 lead LFCSP ꢂ mm sq.

(CP-64-3)

24

TBD

°C/W

Typical θ_JAand θ_JCare specified for a 4-layer board in still air.

Airflow increases heat dissipation effectively reducing θ_JA. In

addition, metal in direct contact with the package leads from

metal traces, and through holes, ground, and power planes,

reduces the θ_JA.

Storage Temperature Range (Ambient) −65°C to +15±°C

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4±±± V readily accumulate on

the human body and test equipment and can discharge without detection. Although this product features

proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy

electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance

degradation or loss of functionality.

Rev. PrD | Page ꢂ of 41

AD9640

Preliminary Technical Data

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

Table 7. LFCSP Parallel CMOS Pin Configuration (Top View)

Table 8. Pin Function Descriptions (Parallel CMOS Mode)

Pin No.

Mnemonic

Type

Function

2±, 64

1, 21

24, 5ꢀ

36, 45, 46

±

DRGND

DRVDD

DVDD

AVDD

Gnd

Digital Output Ground

Supply

Gnd

Digital Output Driver Supply (1.ꢁV to 3.3V)

Digital Power Supply (1.ꢁV Nominal)

Analog Power Supply (1.ꢁV Nominal)

AGND

Analog Ground (Pin ± is the exposed thermal pad on the bottom of the package)

Rev. PrD | Page 1± of 41

Preliminary Technical Data

AD9640

Pin No.

Mnemonic

Type

Function

ADC INPUTS

3ꢀ

3ꢁ

44

43

3ꢂ

4±

42

41

4ꢂ

VIN+A

VIN-A

VIN+B

VIN−B

VREF

SENSE

RBIAS

CML

Input

I/O

Input

Output

Input

Differential Analog Input Pin (+) for Channel A.

Differential Analog Input Pin (−) for Channel A.

Differential Analog Input Pin (+) for Channel B.

Differential Analog Input Pin (−) for Channel B.

Voltage Reference Input/Output.

Voltage Reference Mode Select (See Table x for details)

External Reference Bias Resistor

Common Mode Level Bias Output for Analog Inputs

CLK+

ADC Master Clock – True (ADC Clock can be driven using single ended CMOS – See

Figure x.x for recommended connection)

5±

CLK-

Input

ADC Master Clock - Complement (ADC Clock can be driven using single ended

CMOS – See Figure x.x for recommended connection)

ADC Fast Detect Outputs

2ꢂ

3±

31

32

53

54

55

56

FD±A

FD1A

FD2A

FD3A

FD±B

FD1B

FD2B

FD3B

Output

Channel A Fast Detect Indicator (See Table x for full detials)

Channel B Fast Detect Indicator (See Table x for full detials)

Digital INPUTS

52

SYNC

Input

Digital Synchronization Pin(Slave Mode Only)

Channel A CMOS output data

Digital OUTPUTS

12, 13, 14,

15, 16, 1ꢀ,

1ꢁ, 1ꢂ, 22,

23, 25, 26,

2ꢀ, 2ꢁ

D±A-D13A

Output

5ꢁ, 5ꢂ, 6±,

61, 62, 63,

2, 3, 4, 5, 6,

ꢀ, ꢁ, ꢂ

D±B-D13B

Output

Channel B CMOS output data

11

1±

DCOA

DCOB

Output

Channel A Data Clock Output

Channel B Data Clock Output

SPI CONTROL

4ꢁ

Input

SPI Serial Clock/Data Format Select Pin in External Pin Mode

SCLK/DFS

4ꢀ

51

SDIO/DCS

CSB

I/O

Input

SPI Serial Data I/O/Duty Cycle Stabilizer in External Pin Mode

SPI Chip Select (Active Low)

Serial Port

33

SMI SDO/OEB

I/O

Signal monitor Serial Data Output/Output Enable Input (Active Low) in External Pin

Mode

35

34

SMI SDFS

Output

I/O

Signal monitor Serial Data Frame Sync

SMI SCLK/PDWN

Signal monitor Serial Clock Output/Power Down Input in External Pin Mode

Rev. PrD | Page 11 of 41

AD9640

Preliminary Technical Data

Table 9. LFCSP LVDS Pin Configuration (Top View)

Rev. PrD | Page 12 of 41

Preliminary Technical Data

EQUIVALENT CIRCUITS

AD9640

VIN

1kꢀ

SCLK/DFS

30kꢀ

Figure 2. Analog Input Circuit

AVDD

Figure 6. Equivalent SCLK/DFS Input Circuit

1.2V

1kΩ

10kΩ

SENSE

CLK+

CLK–

Figure 3. Equivalent Clock lInput Circuit

Figure7. Equivalent SENSE Circuit

AVDD

26kΩ

1kΩ

CSB

Figure 4. Digital Output

Figure 8. Equivalent CSB Input Circuit

AVDD

DRVDD

VREF

1kΩ

SDIO/DCS

6kΩ

Figure 9. Equivalent VREF Circuit

Figure5x. Equivalent SDIO/DCS Input Circuit

Rev. PrD | Page 13 of 41

AD9640

Preliminary Technical Data

TYPICAL PERFORMANCE CHARACTERISTICS

AVDD = 1.8 V; DVDD =1.8V; DRVDD = 1.8 V; Sample Rate = 150 MSPS, DCS enabled, 1 V internal reference; 2 V p-p differential input;

VIN = -1.0 dBFS; 64k sample; T_A= 25°C, unless otherwise noted.

Rev. PrD | Page 14 of 41

Preliminary Technical Data

TIMING DIAGRAMS

AD9640

N + 2

N + 1

N + 3

N

N + 4

N + 8

t_A

N + 5

N + 7

N + 6

t_CLK

CLK+

CLK–

t_PD

N – 12

DATA

DCO

N – 13

t_S

N – 11

N – 10

N – 9

t_DCO

N – 8

N – 7

t_CLK

N – 6

N – 5

N – 4

t_H

Figure18. Data and Fast Detect Output Timing

Figure 39. Reset Timing Requirements

Figure 20. SYNC Input Timing

Rev. PrD | Page 15 of 41

AD9640

Preliminary Technical Data

TERMINOLOGY

two samples per cycle.

Crosstalk

Coupling onto one channel being driven by a (−0.5 dBFS) signal

when the adjacent interfering channel is driven by a full-scale

signal. Measurement includes all spurs resulting from both

direct coupling and mixing components.

Out-of-Range Recovery Time

Out-of-range recovery time is the time it takes for the analog-

to-digital converter (ADC) to reacquire the analog input after a

transient from 10% above positive full scale to 10% above

negative full scale, or from 10% below negative full scale to 10%

below positive full scale.

IF Sampling (Undersampling)

Due to the effects of aliasing, an ADC is not necessarily limited

to Nyquist sampling. Frequencies above Nyquist are aliased and

appear in the first Nyquist zone (dc to Sample Rate/2). Care

must be taken to limit the bandwidth of the sampled signal so

that it does not overlap Nyquist zones and alias onto itself. IF

sampling performance is limited by the bandwidth of the input

SHA (sample-and-hold amplifier) and clock jitter. (Jitter adds

more noise at higher input frequencies.)

Signal-to-Noise Ratio (SNR)

The ratio of the rms value of the measured input signal to the

rms sum of all other spectral components within the pro-

grammed DDC filter bandwidth, excluding the first six

harmonics and dc. The value for SNR is expressed in

decibels (dB).

Two-Tone IMD Rejection

Nyquist Sampling (Oversampling)

The ratio of the rms value of either input tone to the rms value

of the worst third-order intermodulation product; reported

in dBc.ADC Equivalent Circuits

Oversampling occurs when the frequency components of the

analog input signal are below the Nyquist frequency (F_clock/2),

and requires that the analog input frequency be sampled at least

Rev. PrD | Page 16 of 41

Preliminary Technical Data

THEORY OF OPERATION

AD9640

sample capacitors and settling within one-half of a clock cycle.

A small resistor in series with each input can help reduce the

peak transient current required from the output stage of the

driving source. A shunt capacitor can be placed across the

inputs to provide dynamic charging currents. This passive

network creates a low-pass filter at the ADC’s input; therefore,

the precise values are dependant upon the application.

The AD9640 dual ADC design may be used for diversity

reception of signals, where the ADCs are operating identically

on the same carrier but from two separate antennae. The ADCs

can also be operated with independent analog inputs. The user

can sample any fs/2 frequency segment from dc to 100 MHz

using appropriate low-pass or band-pass filtering at the ADC

inputs with little loss in ADC performance. Operation to 200

MHz analog input is permitted, but at the expense of increased

ADC distortion.

In IF undersampling applications, any shunt capacitors should

be reduced. In combination with the driving source impedance,

they would limit the input bandwidth. See the application notes

AN-742 and AN-827, and the Analog Dialogue article

“Transformer-Coupled Front-End for Wideband A/D Converters”

for more information on this subject. In general, the precise

values are dependent on the application.

In non-diversity applications, the AD9640 can be used as a

baseband receiver where one ADC is used for I input data and

the other used for Q input data.

Synchronizaton capability is provided to allow synchronized

timing between multiple channels or multiple devices.

Programming and control of the AD9640 is accomplished using

a 3-bit SPI compatible serial interface.

ADC ARCHITECTURE

The AD9640 architecture consists of a dual front-end sample

and hold amplifier (SHA) followed by a pipelined switched

capacitor ADC. The quantized outputs from each stage are

combined into a final 14-bit result in the digital correction

logic. The pipelined architecture permits the first stage to

operate on a new input sample, while the remaining stages

operate on preceding samples. Sampling occurs on the rising

edge of the clock.

Figure21. Switched-Capacitor SHA Input

For best dynamic performance, the source impedances driving

VIN+ and VIN– should be matched.

Each stage of the pipeline, excluding the last, consists of a low

resolution flash ADC connected to a switched capacitor DAC

and interstage residue amplifier (MDAC). The residue amplifier

magnifies the difference between the reconstructed DAC output

and the flash input for the next stage in the pipeline. One bit of

redundancy is used in each stage to facilitate digital correction

of flash errors. The last stage simply consists of a flash ADC.

An internal differential reference buffer creates positive and

negative reference voltages that define the input span of the

ADC core. The span of the ADC core is set by the buffer to be

2X VREF.

Input Common Mode

The input stage of each channel contains a differential SHA that

can be ac- or dc-coupled in differential or single-ended modes.

The output-staging block aligns the data, carries out the error

correction, and passes the data to the output buffers. The output

buffers are powered from a separate supply, allowing

The analog inputs of the AD9640 are not internally dc-biased.

In ac-coupled applications, the user must provide this bias

externally. Setting the device so that V_CM= 0.5 × AVDD is

recommended for optimum performance, but the device

functions over a wider range with reasonable performance (see

Figure x). An on-board common-mode voltage reference is

included in the design and is available from the CML pin.

Optimum performance is achieved when the common-mode

voltage of the analog input is set by the CML pin voltage

(typically 0.55 × AVDD).

adjustment of the output voltage swing. During power-down,

the output buffers go into a high impedance state.

ANALOG INPUT CONSIDERATIONS

The analog input to the AD9640 is a differential switched

capacitor SHA that has been designed for optimum

performance while processing a differential input signal.

Differential Input Configurations

Optimum performance is achieved while driving the AD9640

in a differential input configuration. For baseband applications,

the AD8138 differential driver provides excellent performance

and a flexible interface to the ADC. The output common-mode

The clock signal alternatively switches the SHA between sample

mode and hold mode (see x). When the SHA is switched into

sample mode, the signal source must be capable of charging the

Rev. PrD | Page 1ꢀ of 41

AD9640

Preliminary Technical Data

voltage of the AD8352 is easily set with the CML pin of the

AD9640 (see Figure 4), and the driver can be configured in a

Sallen-Key filter topology to provide band limiting of the input

signal.

Ω

499

AVDD

VIN+

R

1V p-p

Ω

49.9

Ω

499

C

AD8138

AD9640

μF

0.1

523

–

VIN

CML

Figure 6. Differential Double Balun Input Configuration

Ω

499

Figure 4. Differential Input Configuration Using the AD8138

For baseband applications where SNR is a key parameter,

differential transformer coupling is the recommended input

configuration. An example is shown in Figure 5. The CML

voltage can be connected to the center tap of the transformer’s

secondary winding to bias the analog input.

The signal characteristics must be considered when selecting a

transformer. Most RF transformers saturate at frequencies

below a few MHz, and excessive signal power can also cause

core saturation, which leads to distortion.

Figure 7. Differential Input Configuration Using the AD8352

R

An alternative to using a transformer coupled input at

frequencies in the second Nyquist zone is to use the AD8352

differential driver. An example is shown in Figure 7. See the

AD8352 datsheet for more information.

VIN+

C

Ω

49.9

2V p-p

AD9640

R

VIN

–

In any configuration, the value of the shunt capacitor, C, is

dependent on the input frequency and source impedance and

may need to be reduced or removed. Table 1 displays

recommended values to set the RC network. However, these

values will be dependant on the input signal and should only be

used as a starting guide.

CML

μF

0.1

Figure 5. Differential Transformer-Coupled Configuration

Table 1 Example RC Network

At input frequencies in the second Nyquist zone and above, the

noise performance of most amplifiers is not adequate to achieve

the true SNR performance of the AD9640. For applications

where SNR is a key parameter, differential double balun

coupling is the recommended input configuration. An example

is shown in Figure 6.

Frequency Range

R series

(Ω, each)

C differential

MHz

0-70

70-200

200-300

>

(pF)

15

5

33

15

Open

Single-Ended Input Configuration

A single-ended input can provide adequate performance in

cost-sensitive applications. In this configuration, SFDR and

distortion performance degrade due to the large input

common-mode swing. If the source impedances on each input

are matched, there should be little effect on SNR performance.

Rev. PrD | Page 1ꢁ of 41

Preliminary Technical Data

AD9640

Figure 8 details a typical single-ended input configuration.

AVDD

10µF

R

1kꢀ

VIN+

0.1µF

1kꢀ

AVDD

2V p-p

49.9ꢀ

ADC

AD9640

C

1kꢀ

R

VIN–

10µF

Figure 8. Single-Ended Input Configuration

Table 2. Reference Configuration Summary

Resulting Differential

Selected Mode

SENSE Voltage

AVDD

VREF

Resulting VREF (V)

Span (V p-p)

2 × External Reference

1.±

External Reference

Internal Fixed Reference

Programmable Reference

N/A

±.5

±.2 V to VREF

2 × VREF

R2

R1

⎛

⎝

⎞

⎟

⎠

(See Figure 1±)

0.5 × 1 +

⎜

Internal Fixed Reference

AGND to ±.2 V

1.±

2.±

VOLTAGE REFERENCE

VIN+A/VIN+B

VIN-A/VIN-B

A stable and accurate voltage reference is built into the AD9640.

The input range can be adjusted by varying the reference

voltage applied to the AD9640, using either the internal

reference or an externally applied reference voltage. The input

span of the ADC tracks reference voltage changes linearly. The

various reference modes are summarized in the next few

sections. The Reference Decoupling section describes the best

practices PCB layout of the reference.

ADC

CORE

VREF

0.1uF

1.0uF

SELECT

LOGIC

Internal Reference Connection

SENSE

A comparator within the AD9640 detects the potential at the

SENSE pin and configures the reference into four possible

states, which are summarized in Table x. If SENSE is grounded,

the reference amplifier switch is connected to the internal

resistor divider (see Figure 9), setting VREF to 1 V. Connecting

the SENSE pin to VREF switches the reference amplifier output

to the SENSE pin, completing the loop and providing a 0.5 V

reference output. If a resistor divider is connected external to

the chip as shown in Figure 10, the switch again sets to the

SENSE pin. This puts the reference amplifier in a noninverting

mode with the VREF output defined as

0.5V

AD9640

Figure 9. Internal Reference Configuration

R2

R1

⎛

⎝

⎞

⎟

⎠

VREF = ±.5× 1+

⎜

The input range of the ADC always equals twice the voltage at

the reference pin for either an internal or an external reference.

Rev. PrD | Page 1ꢂ of 41

AD9640

Preliminary Technical Data

disabled, allowing the use of an external reference. An internal

reference buffer loads the external reference with an equivalent

TBD kΩ load. The internal buffer generates the positive and

negative full-scale references for the ADC core. Therefore, the

external reference must be limited to a maximum of 1 V.

VIN+A/VIN+B

VIN-A/VIN-B

ADC

CORE

CLOCK INPUT CONSIDERATIONS

VREF

For optimum performance, the AD9640 sample clock inputs

(CLK+ and CLK-) should be clocked with a differential signal.

The signal is typically ac-coupled into the CLK+ and CLK- pins

via a transformer or capacitors. These pins are biased internally

(See Figure 13) and require no external bias.

0.

1

uF

1.

0

uF

SELECT

LOGI

C

R2

SENSE

R1

0.5V

AVDD

AD9640

Figure 10. Programmable Reference Configuration

1.2V

If the internal reference of the AD9640 is used to drive multiple

converters to improve gain matching, the loading of the

CLK-

CLK+

reference by the other converters must be considered. Figure 11

depicts how the internal reference voltage is affected by loading.

2pF

Figure

Figure 13.Equivalent Clock Input Circuit

Clock Input Options

The AD9640 has a very flexible clock input structure. The clock

input can be a CMOS, LVDS, LVPECL, or sine wave signal.

Regardless of the type of signal being used, the jitter of the clock

source is of the most concern, as described in the Jitter

Considerations section.

Figure 11. VREF Accuracy vs. Load

External Reference Operation

Figure 14 shows one preferred method for clocking the AD9640

(at clock rates to 150MSPS). A low jitter clock source is

converted from single-ended to differential signal using an RF

transformer. The back-to-back Schottky diodes across the

transformer secondary limit clock excursions into the AD9640

to approximately 0.8 Vp-p differential. This helps prevent the

large voltage swings of the clock from feeding through to other

portions of the AD9640 while preserving the fast rise and fall

times of the signal, which are critical to a low jitter

performance.

The use of an external reference may be necessary to enhance

the gain accuracy of the ADC or improve thermal drift

characteristics. Figure 12 shows the typical drift characteristics

of the internal reference in both 1 V and 0.5 V modes.

MIN-CIRCUITS

T

ADT1–1W , 1:1Z

0.1µF

CLK

XFMR

CLOCK

INPUT

100kꢀ

ADC

AD9640

50kꢀ

0.1µF

~CLK

0.1µF

Y

SCHOTTK

DIODES:

Figure 12. Typical VREF Drift

HMS2812

When the SENSE pin is tied to AVDD, the internal reference is

Rev. PrD | Page 2± of 41

Preliminary Technical Data

AD9640

Figure 14. Transformer Coupled Differential Clock(up to 150MSPS)

VCC

0.1µF

OPTIONAL

100ꢀ

If a low jitter clock source is not available, another option is to

ac-couple a differential PECL signal to the sample clock input

pins as shown in Figure 15. The AD9510/AD9511/AD9512/

AD9513/AD9514/AD9515 family of clock drivers offers

excellent jitter performance.

0.1µF

ꢀ

1k

AD9510/1/2/3/4/5

CMOS DRIVER

CLOCK

INPUT

CLK

ꢀ

1k

50kꢀ

ADC

AD9640

~CLK

0.1µF

Figure 18 Single-ended 3.3V CMOS Sample Clock (up to 150MSPS)

0.1µF

CLOCK

INPUT

CLK

Input Clock Divider

ADC

AD9640

AD9510/1/2/3/4/5

CL

100kꢀ

The AD9640 contains an input clock divider with the ability to

divide the input clock by integer values between 1 and 8. If a

divide ratio other than 1 is selected the duty cycle stabilizer will

be automatically enabled.

0.1µF

I

R

PE DR VE

~ CLOCK

INPUT

~CLK

240kꢀ

50kꢀ

Figure 15. Differential PECL Sample Clock (up to 150MSPS)

The AD9640 clock divider can be synchronized using the

external SYNC input. Register 0x100 bits bits 1 and 2 allow the

clock divider to be re-synchronized on every SYNC signal or

only on the first SYNC signal after the register is written. A

valid SYNC causes the clock divider to reset to its initial state.

This synchronization feature allows multiple parts to have their

clock dividers aligned to guarantee simultaneous input

sampling.

A third option is to ac-couple a differential LVDS signal to the

sample clock input pins as shown in Figure 16. The

AD9510/AD9511/AD9512/ AD9513/AD9514/AD9515 family of

clock drivers offers excellent jitter performance.

0.1µF

CLOCK

INPUT

CLK

100kꢀ

ADC

AD9640

AD9510/1/2/3/4/5

0.1µF L

0.1µF

VDS DRIVER

Clock Duty Cycle

~ CLOCK

INPUT

~CLK

50kꢀ

Typical high speed ADCs use both clock edges to generate a

variety of internal timing signals, and as a result may be

sensitive to clock duty cycle. Commonly, a 5% tolerance is

required on the clock duty cycle to maintain dynamic

performance

characteristics. The AD9640 contains a duty cycle stabilizer

(DCS) that retimes the nonsampling, or falling, edge, providing

an internal clock signal with a nominal 50% duty cycle. This

allows the user to provide a wide range of clock input duty

cycles without affecting the performance of the AD9640. Noise

and distortion performance are nearly flat for a wide range of

duty cycles with the DCS on, as shown in Figure x.

50kꢀ

Figure 16 Differential LVDS Sample Clock (up to 150MSPS)

In some applications it may acceptable to drive the sample clock

inputs with a single ended CMOS signal. In such applications,

CLK+ should be directly driven from a CMOS gate, while the

CLK- pin should be bypassed to ground with a 0.1uF capacitor

in parallel with a 39 kΩ resistor (see Figure 17). CLK+ may be

directly driven from a CMOS gate. Although the CLK+ input

circuit supply is AVDD (1.8 V), this input is designed to

withstand input voltages up to 3.6V, making the selection of the

drive logic voltage very flexible.

The duty cycle stabilizer uses a delay-locked loop (DLL) to

create the nonsampling edge. As a result, any changes to the

sampling frequency require approximately TBD clock cycles to

allow the DLL to acquire and lock to the new rate.

VCC

OPTIONAL

100ꢀ

0.1µF

ꢀ

1k

CLOCK

INPUT

AD9510/1/2/3/4/5

CMOS DRIVER

CLK

50kꢀ

ꢀ

1k

ADC

AD9640

Jitter Considerations

High speed, high resolution ADCs are sensitive to the quality of

the clock input. The degradation in SNR at a given input

frequency (f_INPUT) due to jitter (t_J) can be calculated by:

~CLK

0.1µF

kꢀ

39

Figure 17. Single-ended 1.8V CMOS Sample Clock (up to 150MSPS)

SNR = −20log

[

2πf_INPUT×t_J

]

In the equation, the rms aperture jitter represents the root-

mean square of all jitter sources, which include the clock input,

analog input signal, and ADC aperture jitter specification. IF

undersampling applications are particularly sensitive to jitter, as

Rev. PrD | Page 21 of 41

AD9640

Preliminary Technical Data

illustrated in Figure 19.

Figure 20. Power vs. Clock Frequency@ 30 MHz

By asserting the PDWN mode (either through the SPI port or

by asserting the PDWN pin high), the AD9640 is placed in

power-down mode. In this state, the ADC typically dissipates

TBD mW. During power-down, the output drivers are placed in

a high impedance state. Asserting the PDWN pin low returns

the AD9640 to its normal operational mode. This pin is both

1.8V and 3.3V tolerant.

Figure 19. SNR vs. Input Frequency and Jitter

The clock input should be treated as an analog signal in cases

where aperture jitter may affect the dynamic range of the

AD9640. Power supplies for clock drivers should be separated

from the ADC output driver supplies to avoid modulating the

clock signal with digital noise. Low jitter, crystal-controlled

oscillators make the best clock sources. If the clock is generated

from another type of source (by gating, dividing, or other

methods), it should be retimed by the original clock at the last

step.

Low power dissipation in power-down mode is achieved by

shutting down the reference, reference buffer, biasing networks,

and clock. Internal capacitors are discharged when entering

power-down mode and then must be recharged when returning

to normal operation. As a result, the wake-up time is related to

the time spent in power-down mode and shorter power-down

cycles result in proportionally shorter wake-up times. It takes

approximately TBD sec to fully discharge the internal reference

buffer decoupling capacitors and TBD ms to restore full

operation.

Refer to the AN-501 Application Note and the AN-756

Application Note for more in-depth information about jitter

performance as it relates to ADCs. See www.analog.com.

POWER DISSIPATION AND STANDBY MODE

As shown in Figure 20, the power dissipated by the AD9640 is

proportional to its sample rate. In CMOS output mode, the

digital power dissipation is determined primarily by the

strength of the digital drivers and the load on each output bit.

The maximum DRVDD current (I_DRVDD) can be calculated as:

When using the SPI port interface, the user can place the ADC

in power-down or standby modes. Standby mode allows the

user to keep the internal reference circuitry powered when

faster wake-up times are required. See the SPI Register Map

Description section for more details.

I_DRVDD= V_DRVDD×C_LOAD×f_CLK×N

where N is the number of output bits, 14 in the case of the

AD9640. This maximum current occurs when every output bit

switches on every clock cycle, that is, a full-scale square wave at

the Nyquist frequency, f_CLK/2. In practice, the DRVDD current

is established by the average number of output bits switching,

which is determined by the sample rate and the characteristics

of the analog input signal. Reducing the capacitive load

presented to the output drivers can minimize digital power

consumption. The data in Figure 20 was taken with the same

operating conditions as the Typical Performance Characteristics

with a 5 pF load on each output driver.

DIGITAL OUTPUTS

The AD9640 output drivers can be configured to interface with

1.8 V to 3.3 V logic families by matching DRVDD to the digital

supply of the interfaced logic.

In CMOS output mode, the output drivers are sized to provide

sufficient output current to drive a wide variety of logic

families. However, large drive currents tend to cause current

glitches on the supplies that may affect converter performance.

Applications requiring the ADC to drive large capacitive loads

or large fan-outs may require external buffers or latches.

The output data format can be selected for either offset binary

or twos complement by setting the CLK/DFS pin when

operating in the external pin mode (see Table 3). As detailed in

the memory map register description section the data format

can be selected for either offset binary, twos complement, or

Rev. PrD | Page 22 of 41

Preliminary Technical Data

AD9640

Gray code when using the SPI control.

Table 3. CLK/DFS Mode Selection (external pin mode)

Voltage at pin

AGND (default)

AVDD

SCLK/DFS

Binary

SDIO/DCS

DCS Disabled

DCS Enabled

Twos Complement

Digital Output Enable Function (OEB)

The AD9640 has a flexible three-state ability for the digital

output pins. The three-state mode can be enabled using the

OEB pin or through the SPI interface. If the OEB pin is low, the

output data drivers are enabled. If the OEB pin is high, the

output data drivers are placed in a high impedance state. It is

not intended for rapid access to the data bus. Note that OEB is

referenced to the digital supplies (DRVDD) and should not

exceed that supply voltage.

Figure 21. OR Relation to Input Voltage and Output Data

TIMING

The AD9640 provides latched data with a pipeline delay of

twelve clock cycles. Data outputs are available one propagation

delay (t_PD) after the rising edge of the clock signal.

When using the SPI interface each channel’s data and fast detect

outputs can be independently three-stated by using the Output

Enable Bar bit in register 0x14.

The length of the output data lines and loads placed on them

should be minimized to reduce transients within the AD9640.

These transients can degrade the converter’s dynamic performance.

The AD9640 also provides data clock output (DCO) intended for

capturing the data in an external register. The data outputs are

valid on the rising edge of DCO. See Figure x for a graphical

timing description.

The lowest typical conversion rate of the AD9640 is 10 MSPS.

At clock rates below 10 MSPS, dynamic performance can

degrade.

Table 4. Output Data Format

Input (V)

Condition (V)

< –VREF – ±.5 LSB

= –VREF

Binary Output Mode

±± ±±±± ±±±± ±±±±

1± ±±±± ±±±± ±±±±

11 1111 1111 1111

Twos Complement Mode

1± ±±±± ±±±± ±±±±

±± ±±±± ±±±± ±±±±

±1 1111 1111 1111

OR

1

±

VIN+ – VIN–

= ±

= +VREF – 1.± LSB

> +VREF – ±.5 LSB

1

Rev. PrD | Page 23 of 41

AD9640

Preliminary Technical Data

ADC FAST MAGNITUDE

ADC OVERRANGE AND GAIN CONTROL

When the FD bits are configured to output the ADC fast

magnitude the information presented is the ADC level with

only a 1 clock cycle latency. Using the FD bits in this

configuration provides the earliest possible level indication

information. Since this information is provided from early in

the data path there is a significant uncertainty in the level

indicated. The nominal levels along with the uncertainty

indicated by the ADC fast magnitude are shown in table x.x.

It is desirable to have a mechanism to reliably determine when

the converter is about to be clipped. The standard overflow

indicator provides after the fact information which is of limited

usefulness. Therefore it is useful to have a programmable

threshold below full-scale that would allow time to reduce the

gain before the clip actually occurs. In addition, since input

signals can have significant slew rates, latency of this function is

a big concern. Highly pipelined converters can have significant

latency. A good compromise of this function is to use the

output bits from the first stage of the ADC for this function.

Latency for these output bits is very low, and overall resolution

is not highly significant. Peak input signals are typically

between full-scale and 6 to 10 dB below full-scale. A 3 or 4 bit

output should give more than adequate range and resolution for

this function.

Table xx. ADC Fast Magnitude Bits Nomimal Levels (Using

Mag[3:0])

Nominal Input

magnitude in

ADC_Fast_Mag[3:±] dB below FS

Nominal Input

magnitude

Uncertainty in dB

±±±±

±±±1

±±1±

±±11

±1±±

±1±1

±11±

±111

1±±±

-3±.14

-1ꢁ.±ꢀ

-12.±4

-ꢁ.52

-6.±2

-4.±ꢁ

-2.5

+12.±ꢀ to Min

+6.±3/-12.±ꢀ

+3.52/-6.±3

+2.5/-3.52

Via the SPI port, the user can provide a threshold above which a

fast over-range output would be active. As long as the signal is

below that threshold, the output should remain low. This pin

could also be programmed via the SPI port to function as a

traditional over-range pin for customers who currently use this

feature. In this mode, all 14 bits of the converter would be

examined in the traditional manner and the output would be

high for the condition normally defined as overflow. In either

mode, the sign of the data is not considered in the calculation of

the condition. The threshold detection responds identically to

positive and negative signals outside the desired range

(magnitude).

+1.ꢂ4/-2.5

+1.5ꢁ/-1.ꢂ4

+1.34/-1.5ꢁ

+1.16/-1.34

+±.2ꢁ/-±.ꢁꢁ

-1.16

-±.2ꢁ

When fast detect modes 001, 010, or 011 are selected a subset of

the FD bits are available. Table xx shows the corresponding

ADC input levels when Fast Magnitude[2:0] is selected using

001.

Table xx. ADC Fast Magnitude Bits Nomimal Levels (Using

Mag[2:0])

Nominal Input

magnitude in

ADC_Fast_Mag[2:±] dB below FS

FAST DETECT OVERVIEW

Nominal Input

magnitude

Uncertainty in dB

The AD9640 contains circuitry to facilitate fast over-range

detection allowing very flexible external gain control

implementations. Each ADC has four Fast Detect (FD) bits that

are utilized to output information about the current state of the

ADC input level. The FD bit function is programmable

allowing range information to be output from several points in

the internal data path. These bits can also be set up to indicate

the presence of overrange or underrange conditions according

to programmable threshold levels. Table X.x below shows the 6

configurations available for the Fast Detect bits. These

configurations are selecting by setting bits 3:1 in the register at

SPI address 0x104.

±±±

±±1

±1±

±11

1±±

1±1

11±

111

-3±.14

-1ꢁ.±ꢀ

-12.±4

-ꢁ.52

-6.±2

-4.±ꢁ

-2.5

+12.±ꢀ to Min

+6.±3/-12.±ꢀ

+3.52/-6.±3

+2.5/-3.52

+1.ꢂ4/-2.5

+1.5ꢁ/-1.ꢂ4

+1.34/-1.5ꢁ

+1.16/-1.34

-1.16

When ADC Fast Magnitude[2:1] is selected the LSB is not

provided. The Input ranges for this mode are shown in Table x.

Table xx. Fast Detect Bit Configuration Settings

Table xx. ADC Fast Magnitude Bits Nomimal Levels (Using

Mag[2:1])

Nominal Input

magnitude in

ADC_Fast_Mag[2:1] dB below FS

Fast Detect Mode

Select - Register

1±4h<3:1>

Information Presented on

FD Bits[3:±]

Nominal Input

magnitude

Uncertainty in dB

±±±

±±1

±1±

±11

1±±

1±1

ADC Fast Magnitude[3:±]

ADC Fast Magnitude[2:±], OVR

ADC Fast Magnitude[2:1], OVR, F_LT

ADC Fast Magnitude[2:1], C_UT, F_LT

OVR, C_UT, F_UT, F_LT

±±

±1

1±

11

-22.14

-1±.1±

-5.±±

+1±.1 to Min

+4.±ꢁ/-ꢀ.ꢂꢀ

+2.5/-3.52

+1.4ꢁ/-2.6

-1.4ꢁ

OVR, F_UT, IG, DG

Rev. PrD | Page 24 of 41

Preliminary Technical Data

AD9640

is a 13 bit threshold register that is compared with the

ADC OVERRANGE (OVR)

magnitude at the output of the ADC. This comparison is

subject to the ADC clock latency but allows a finer, more

accurate comparison. The fine threshold magnitude is defined

by equation x.x.

The ADC Overrange bit becomes active when an overrange is

detected on the input of the ADC. The overrange condition is

determined at the output of the ADC pipline and is therefore

subject to the TBD ADC clock cycle latency. So an overrange at

the input would be indicated by this bit TBD clock cycles after it

occurred.

dBFS = 20 log (threshold mag/2^13)

GAIN SWITCHING

Fine Lower Threshold (F_LT)

The AD9640 includes circuitry that is useful in applications

where either large dynamic ranges exist or where gain ranging

converters are employed. This circuitry allows digital thresholds

to be set such that an upper and a lower threshold can be

programmed. Fast detect modes 2 through 7 support various

combinations of the gain switching options.

The Fine Lower Threshold bit will be asserted if the input

magnitude is less than value programmed in the Fine Lower

Threshold Register located at addresses 0x108 and 0x109. The

fine lower threshold register is a 13 bit register that is compared

with the magnitude at the output of the ADC. This comparison

is delayed by the ADC clock latency but provides an accurate

comparison. The fine threshold magnitude is defined by

equation x.x.

One such use of this may be to detect when an ADC is about to

reach full scale with a particular input condition. The results

would be to provide a flag that could be used to quickly insert

an attenuator that would prevent ADC overdrive.

dBFS = 20 log (threshold mag/2^13)

Coarse Upper Threshold (C_UT)

Increment Gain (IG) and Decrement Gain (DG)

The coarse upper threshold bit is asserted if the input level

present on the ADC Fast Magnitude bits is greater than the level

programmed in the coarse upper threshold register at address

0x105 bits [2:0]. This value is compared with the ADC Fast

Magnitude Bits [2:0]. The coarse upper threshold levels are

shown in Table x.x. This bit remains asserted for a minimum of

2 ADC clock cycles or until the signal drops below the

threshold level.

The Increment Gain and decrement gain outputs are intended

to be used together to provide information to enable external

gain control. The Decrement Gain output works identically to

the Coarse Upper Threshold output. This bit is asserted when

the input magnitude is greater than the three bit value in the

Coarse Upper Threshold Register. The Increment Gain output

is similar to the Fine Lower Threshold bit except that it will be

asserted only if the input magnitude is less than value

programmed in the Fine Lower Threshold Register for greater

than the 16 bit Dwell Time value located at addresses 0x10A

and 0x10B. The dwell time is set in units of ADC input clock

cycles ranging from 1 to 65535. The fine lower threshold

register is a 13 bit register that is compared with the magnitude

at the output of the ADC. This comparison is subject to the

ADC clock latency but allows a finer, more accurate

Table xx. Fast Magnitude Nominal Threshold Levels

C_UT active when

Coarse Upper

Threshold Register

[2:±]

signal magnitude

in dB below FS is

greater than

±±±

±±1

±1±

±11

1±±

1±1

11±

111

TBD

comparison. The fine threshold magnitude is defined by

equation x.x.

The decrement gain output works off the ADC fast detect bits

providing a fast indication of potential overrange conditions.

The increment gain uses the comparison at the output of the

ADC requiring the input magnitude to remain below an

accurate programmable level for a predefined period before

signaling external circuitry to increase the gain.

Fine Upper Threshold (F_UT)

The Fine Upper Threshold bit will be asserted if the input

magnitude exceeds the value programmed in the Fine Upper

Threshold Register located at addresses 0x106 and 0x107. This

The operation of the increment gain and decrement gain bits is

shown in Figure x.x.

Rev. PrD | Page 25 of 41

AD9640

Preliminary Technical Data

Counter Restarts

"Low"

"High"

Upper Threshold

Lower Threshold

Dwell Time

Time

Figure 22. Threshold Settings for IG and DG

Rev. PrD | Page 26 of 41

Preliminary Technical Data

SIGNAL MONITOR

AD9640

level holding register is set to the current ADC input signal

magnitude. This comparison continues until the monitor

The Signal monitoring block serves to characterize the signal

being digitized by the ADC. It operates in one to three modes

to compute the RMS Input Magnitude, Peak Magnitude, and/or

the number of samples that the Magnitude crosses a particular

threshold. Together these functions can be used to gain insight

into the signal characteristics and can be used to estimate the

Peak/Average ratio or even the shape of the CCDF curve (peak

to average ratio) of the input signal. This information can be

used to drive an AGC loop and to optimize the range of the

ADC in the presence of real world signals.

period timer reaches a count of 1.

When the monitor period timer reaches a count of 1, the 13 bit

value in the peak level holding register is transferred to a

holding register, which can be read through the SPI port or

output through the SPORT serial interface. The monitor period

timer is reloaded with the value in the SMPR, and the

countdown is started. Also, the first input sample’s magnitude is

updated in the peak level holding register, and the comparison

and update procedure, as explained above, continues.

The signal monitor result values can be obtained from the part

by either reading back internal registers at addresses 0x116 to

0x11B using the SPI port or by using the signal monitor SPORT

output. The output contents of the SPI accessible signal monitor

registers is set via the 2 power-monitor mode bits of the signal

monitor control register. Both ADC channels must be

configured for the same signal monitor mode. Separate SPI

accessible 20 bit Signal monitor Value (PMV) output registers

are provided for each ADC channel. Any combination of the

signal monitor functions can also be output to the user via a

serial SPORT interface. These outputs are enabled using the

Peak Power Output Enable, RMS Magnitude Output Enable,

and Threshold Crossing Output Enable bits in the Signal

monitor SPORT Control Register.

Figure 23 is a block diagram of the peak detector logic. The

PMV contains the absolute magnitude of the peak detected by

the peak detector logic.

TO

FROM

MEMORY

MAP

INTERRUPT

CONTROLLER

POWER MONITOR

PERIOD REGISTER

DOWN

COUNTER

IS COUNT = 1?

LOAD

TO

MEMORY

MAP

FROM

INPUT

PORTS

CLEAR

MAGNITUDE

STORAGE

REGISTER

POWER MONITOR

HOLDING

REGISTER

LOAD

COMPARE

A>B

For each of the signal monitor measurements a programmable

Signal Monitor Period Register (SMPR) controls the duration

of the measurement. This time period is programmed as the

number of input clock cycles in a 24-bit ADC monitor period

register located at addresses 0x113, 0x114, and 0x115. This

register can be programmed with a period from 128 samples to

16.78 (2^24) million samples.

Figure 23. ADC Input Peak Detector Block Diagram

RMS/MS MAGNITUDE MODE (MODE BITS 00)

In this mode, the RMS or MS magnitude of the input port

signal is integrated (by adding an accumulator) over a

programmable time period (given by SMPR) to give the RMS or

MS magnitude of the input signal. This mode is set by

programming Logic 0 in the signal monitor mode bits of the

signal monitor control register or by setting the RMS

Magnitude Output Enable bit in the Signal monitor SPORT

Control Register. The 24-bit SMPR, representing the period

over which integration is performed, must be programmed

before activating this mode.

Since the DC offset of the ADC can be significantly larger than

the signal of interest a simple DC correction circuit is included

as part of the signal monitor block to null the DC offset before

measuring the power.

PEAK DETECTOR MODE (MODE BITS 01)

The magnitude of the input port signal is monitored over a

programmable time period (given by SMPR) to give the peak

value detected. This function is enabled by programming a logic

1 in the power-monitor mode bits of the power-monitor control

register or by setting the Peak Power Output Enable bit in the

Signal monitor SPORT Control Register. The 24-bit SMPR must

be programmed before activating this mode.

After enabling this mode, the value in the SMPR is loaded into a

monitor period timer, and the countdown is started

immediately. Each input sample is converted to floating point

format and squared. It is then converted to 11 bit fixed point

format and is added to the contents of a 24-bit holding register,

thus performing an accumulation. The integration continues

until the monitor period timer reaches a count of 1.

After enabling this mode, the value in the SMPR is loaded into a

monitor period timer and the countdown is started. The

magnitude of the input signal is compared to the internal peak

level holding register, and the greater of the two is updated back

into the peak level holding register. The initial value of the peak

When the monitor period timer reaches a count of 1, the square

root of the value in the holding register is taken and transferred

to the power-monitor holding register (after some formatting),

which can be read through the SPI port or output through the

Rev. PrD | Page 2ꢀ of 41

AD9640

Preliminary Technical Data

SPORT serial port. The monitor period timer is reloaded with

the value in the SMPR, and the countdown is restarted. Also,

the first input sample signal power is updated in the holding

register, and the accumulation continues with the subsequent

input samples. Figure 24 illustrates the RMS magnitude

monitoring logic.

After entering this mode, the value in the SMPR is loaded into a

monitor period timer, and the countdown is started. The

magnitude of the input signal is compared to the upper

threshold register (programmed previously) on each input clock

cycle. If the input signal has magnitude greater than the upper

threshold register, then the internal count register is

incremented by 1. The initial value of the internal count register

is set to 0. This comparison and increment of the internal count

register continues until the monitor period timer reaches a

count of 1.

For RMS magnitude mode, the value in the PMV is a 20 bit

fixed point number. The equation shown below can be used to

determine the RMS magnitude in dBFS from the MAG value in

the register. Note that if the signal monitor period (SMP) is a

power of 2, the 2nd term in the equation goes to zero.

When the monitor period timer reaches a count of 1, the value

in the internal count register is transferred to the signal monitor

holding register, which can be read through the SPI port or

output through the SPORT serial port. The monitor period

timer is reloaded with the value in the SMPR, and the

countdown is started. The internal count register is also cleared

to a value of 0. Figure 25 illustrates the threshold crossing logic.

The value in the PMV is the number of samples that have a

magnitude greater than the threshold register.

MAG

SMP

⎛

⎜

⎝

⎞

⎟

⎠

⎡

⎢

⎣

⎤

⎥

⎦

RMS_Magnitude := 20⋅log

− 10⋅log

20

2

ceil log (SMP)

⎡

⎣

⎤

⎦

2

For MS magnitude mode, the value in the PMV is a 20 bit fixed

point number. The equation shown below can be used to

determine the MS magnitude in dBFS from the MAG value in

the register. Note that if the signal monitor period (SMP) is a

power of 2, the 2nd term in the equation goes to zero.

TO

FROM

MEMORY

MAP

INTERRUPT

CONTROLLER

POWER MONITOR

PERIOD REGISTER

DOWN

COUNTER

MAG

SMP

IS COUNT = 1?

⎛

⎜

⎝

⎞

⎟

⎠

⎡

⎢

⎣

⎤

⎥

⎦

MS_Magnitude := 10⋅log

− 10⋅log

20

2

ceil log (SMP)

⎡

⎣

⎤

⎦

2

LOAD

CLEAR

2

TO

MEMORY

MAP

FROM

INPUT

PORTS

LOAD

POWER MONITOR

HOLDING

A

COMPARE

A > B

COMPARE

A > B

REGISTER

FROM

MEMORY

MAP

B

UPPER

THRESHOLD

REGISTER

Figure 25. ADC Input Threshold Crossing Block Diagram

ADDITIONAL CONTROL BITS

For additional flexibility in the signal monitoring process, two

control bits are provided in the power-monitor control register.

They are the signal monitor enable bit and the complex power

bit.

Figure 24. ADC Input RMS Magnitude Monitoring Block Diagram

Signal monitor Enable Bit

THRESHOLD CROSSING MODE (MODE BITS 1X)

The signal monitor enable bit located in bit 0 or register 0x112

enables operation of the signal monitor block. If the signal

monitor function is not needed in a particular application then

this bit should be cleared to conserver power.

In this mode of operation, the magnitude of the input port

signal is monitored over a programmable time period (given by

SMPR) to count the number of times it crosses a certain

programmable threshold value. This mode is set by program-

ming Logic 1x (where x is a don’t care bit) in the power-monitor

mode bits of the signal monitor control register or by setting the

Threshold Crossing Output Enable bit in the Signal monitor

SPORT Control Register. Before activating this mode, the user

needs to program the 24-bit SMPR and the 13-bit upper

threshold register for each individual input port. The same

upper threshold register is used for both signal monitoring and

gain control (see the ADC Overrange and Gain Control

section).

Measure Complex Power Bit

When this bit is set the part assumes that Channel A is

digitizing the I data and Channel B is digitizing the Q data for a

complex input signal (or vice versa). In this mode the power

reported is the sqrt(I^2 + Q^2). This complex power

measurement result is presented in the Channel A signal

monitor value register if the signal monitor mode bits are set to

00. The channel B signal monitor will continue to compute the

channel B value.

Rev. PrD | Page 2ꢁ of 41

Preliminary Technical Data

AD9640

Setting bit 0 of register 0x10C enables the DC correction for use

in the Signal monitor calculations. The calculated DC

correction value can be added to the output data signal path by

setting bit 1 of register 0x10C.

DC CORRECTION

Since the DC offset of the ADC can be significantly larger than

the signal we are trying to measure a simple DC correction

circuit is included to null the DC offset before measuring the

power. The DC Correction circuit can also be switched into the

main signal path but this may not be appropriate if the ADC is

digitizing a time-varying signal with significant DC content

such as GSM.

SIGNAL MONITOR SPORT OUTPUT

The SPORT is a serial interface with three output pins, the SMI

SCLK (SPORT clock), SMI_SDFS (SPORT frame sync) and

SMI_SDO (SPORT data). The SPORT is the master, and drives

all three pins out of the chip.

DC Correction Bandwidth

The DC correction circuit is basically a HP filter with a

programmable BW ranging between 0.15Hz and 1.2kHz. The

BW is controlled by writing the 4-bit DC correction register

located in bits 5:2 at address 0x10C. Table xx shows the BW

values for each of the 16 possible programmed values.

SMI SCLK

The data and frame sync are driven on the positive edge of the

SMI SCLK. The SMI SCLK has three possible baud rates. They

are ½, ¼, or 1/8 the ADC clock rate, based on the SPORT

controls. The SMI SCLK can also be gated off when not sending

any data, based on the SMI SCLK sleep bit. Gating off the SMI

SCLK when it is not needed will reduce the coupling errors

back into the signal path if these prove to be a problem in the

system. This has the disadvantage of spreading the frequency

content of the clock so this can be left running to ease

frequency planning if desired.

Table xx. DC Correction Bandwidth Settings

DC Correction Factor

SMI SDFS

reg.1±C<5:2>

±±±±

Bandwidth (Hz)

121ꢁ.56

6±ꢂ.2ꢁ

3±4.64

152.32

ꢀ6.16

3ꢁ.±ꢁ

1ꢂ.±4

ꢂ.52

The SMI_SDFS is the Serial Data Frame Sync, and defines the

start of a frame. One SPORT frame includes data from both

datapaths. The data from Datapath A is sent just after the frame

sync, followed by data from Datapath B.

±±±1

±±1±

±±11

SMI SDO

±1±±

±1±1

The SMI_SDO is the serial data out of the block. The data is

sent MSB first on the next positive edge after the SMI_SDFS.

Each data output block includes one or more of RMS

magnitude, Peak level, and Threshold Crossing values from

both datapaths in the stated order. If enabled the data is sent

RMS first, followed by Peak, and Threshold as shown in Figure

x.

±11±

±111

1±±±

4.ꢀ6

1±±1

2.3ꢁ

1±1±

1.1ꢂ

1±11

±.6±

11±±

±.3±

11±1

±.15

111±

±.15

1111

±.15

DC Correction Readback

The current DC correction value can be read back in registers

0x10D and 0x10E for channel A and registers 0x10F and 0x110

for channel B. The DC correction value is a 14 bit value that

can span the entire input range of the ADC.

Figure 26. Signal monitor SPORT Output Timing (RMS, Peak, and Threshold

Enabled)

DC Correction Freeze

Setting the DC Correction Freeze bits freezes the DC correction

at its current state and continues to use the last updated value as

the DC correction value. Clearing this bit restarts the DC

correction and adds the currently calculated value to the data.

Figure 27. Signal monitor SPORT Output Timing (RMS and Threshold

Enabled)

DC Correction Enable Bits

Rev. PrD | Page 2ꢂ of 41

AD9640

Preliminary Technical Data

BUILT-IN SELF-TEST (BIST) AND OUTPUT TEST

sequence can be observed as it runs. The PN sequence can be

continued from its last value or start from the beginning based

on the value programmed in register 0x00E bit 2. The BIST

signature result will vary based on the channel configuration.

The AD9640 includes built-in test features to enable verification

of the integrity of each channel as well as to facilitate board level

debugging. A BIST (built-in self-test) feature is included which

verifies the integrity of the digital data path of the AD9640.

Various output test options are also provided to place

OUTPUT TEST MODES

predictable values on the outputs of the AD9640.

The output test options are shown in table x.x. When an output

test mode is enabled, the analog section of the ADC is

disconnected from the digital backend blocks and the test

pattern is run through the output formatting block. As

indicated in table x.x some of the test patterns are subject to

output formatting and some are not. The seed value for the PN

sequence tests can be forced if the PN reset bits are used to hold

the generator in reset mode by setting bits 4 or 5 of register

0x0D. These tests can be performed with or without an analog

signal, but do require an encode clock.

BUILT IN SELF TEST (BIST)

The BIST is a thorough test of the digital portion of the selected

AD9640 signal path. When enabled, the test runs from a user

selectable internal source (PN or sine) through the digital data

path starting at the ADC block output. The BIST sequence will

run for 256 cycles and stop. The BIST signature value for

channel A or B will be placed in registers 0x024 and 0x025. If

one channel is chosen, its BIST signature is written to the two

registers. If both channels are chosen, the two channels’ results

are XOR’ed and placed in the BIST signature register. The

outputs are not disconnected during this test, so the PN

Rev. PrD | Page 3± of 41

Preliminary Technical Data

AD9640

CHANNEL/CHIP SYNCHRONIZATION

The AD9640 has a SYNC input that allows the user flexible

synchronization options for syncing the internal blocks. The

sync feature is useful to guarantee synchronized operation

across multiple ADCs. The input clock divider and the signal

monitor block can be synchronized using the SYNC input. The

input clock divider can be enabled to sync on a single

occurrence of the sync signal or on every occurrence. The

signal monitor syncs on every SYNC input.

The SYNC input is internally synchronized to the sample clock,

however to ensure there is no timing uncertainty between

multiple parts the SYNC input signal should be synchronized to

the input clock signal. The SYNC input should be driven using

a single ended CMOS type signal.

Rev. PrD | Page 31 of 41

AD9640

Preliminary Technical Data

port to be used both to program the chip as well as read the

contents of the on-chip memory. If the instruction is a readback

operation, performing a readback causes the serial data input/

output (SDIO) pin to change direction from an input to an

output at the appropriate point in the serial frame.

SERIAL PORT INTERFACE (SPI)

The AD9640 serial port interface (SPI) allows the user to

configure the converter for specific functions or operations

through a structured register space provided inside the ADC.

This gives the user added flexibility and customization

depending on the application. Addresses are accessed via the

serial port and may be written to or read from via the port.

Memory is organized into bytes that can be further divided

down into fields, which are documented in the Memory Map

section. Detailed operational information can be found in the

Analog Devices user manual titled Interfacing to High Speed

ADCs via SPI at www.analog.com.

Data may be sent in MSB or in LSB first mode. MSB first is

default on power up and may be changed via the configuration

register. For more information about this and other features see

“Interfacing to High Speed ADCs via SPI” at www.analog.com.

Table xx. SPI Timing Diagram Specifications

Spec

Meaning

Name

CONFIGURATION USING THE SPI

t_DS

t_DH

t_CLK

t_S

Setup time between data and rising edge of SCLK

Hold time between data and rising edge of SCLK

Period of the clock

There are three pins that define the SPI of this ADC. They are

the SCLK/DFS, SDIO/DCS, and CSB pins (summarized inTable

x). The SCLK/DFS (serial clock) is used to synchronize the read

and write data presented from/to the ADC. The SDIO/DCS

(serial data input/output) is a dual purpose pin that allows data

to be sent and read from the internal ADC memory map

registers. The CSB (chip select bar) is an active low control that

enables or disables the read and write cycles.

Setup time between CSB and SCLK

Hold time between CSB and SCLK

t_H

t_HI

Minimum period that SCLK should be in a logic high

state

Table xx. Serial Port Interface Pins

t_LO

Minimum period that SCLK should be in a logic low

state

Function

SCLK

SCLK (Serial Clock) is the serial shift clock in. SCLK is

used to synchronize serial interface reads and writes.

SDIO (Serial Data Input/Output) is a dual purpose pin.

The typical role for this pin is an input and output

depending on the instruction being sent and the

relative position in the timing frame.

SDIO

HARDWARE INTERFACE

The pins described in Table xError! Reference source not

found. comprise the physical interface between the user’s

programming device and the serial port of the AD9640. All

serial pins are inputs, which should be tied to an external pull-

up or pull-down resistor (suggested value 10 kΩ).

CSB

CSB (Chip Select Bar) is active low controls that gates

the read and write cycles.

The falling edge of the CSB in conjunction with the rising edge

of the SCLK determines the start of the framing. An example of

the serial timing and its definitions can be found in Figure x

and Table x.

The SPI interface is flexible enough to be controlled by either

FPGAs or mirocontrollers. This provides the user the ability use

an alternate method to program the ADC other than a

dedicated SPI controller.

Other modes involving the CSB are available. The CSB can be

held low indefinitely which permanently enabling the device,

this is called streaming. The CSB may stall high between bytes

to allow for additional external timing. When CSB is tied high,

SPI functions are placed in a high impedance more. This mode

turns on any SPI pin secondary functions.

The SPI port should not be active during periods when the full

dynamic performance of the converter is required. Since the

SCLK, CSB and SDIO signals are typically asynchronous to the

ADC clock, noise from these signals can degrade the converter’s

performance. If the on board SPI Bus is utilized for other

devices it may be necessary to provide buffers between this bus

and the AD9640 in order to keep these signals from

transitioning at the converter inputs during critical sampling

periods.

During an instruction phase a 16bit instruction is transmitted.

Data follows the instruction phase and it’s length is determined

by the W0 and W1 bits. All data is composed of 8bit words. The

first bit of each individual byte of serial data indicates whether a

read or write command is issued. This allows the serial data

input/output (SDIO) pin to change direction from an input to

an output.

Some pins serve a dual function when the SPI interface is not

being used. When the pins are strapped to AVDD or ground

during device power on, they are associated with a specific

function. The TBD section describes the strappable functions

supported on the AD9640.

In addition to word length, the instruction phase determines if

the serial frame is a read or write operation, allowing the serial

Rev. PrD | Page 32 of 41

Preliminary Technical Data

AD9640

Memory Map Table.

CONFIGURATION WITHOUT THE SPI

Logic Levels

In applications that do not interface to the SPI control registers,

the SDIO/DCS, SCLK/DFS, MON SDO/OEB, and MON

SCLK/PDWN pins serve as stand alone CMOS compatible

control pins. When the device is powered up, it is assumed that

the user intends to use the pins as static control lines for the

duty cycle stabilizer, output data format, output enable, and

power down feature control. In this mode the CSB chip select

should be connected to AVDD, which will disable the serial

port interface.

An explanation of various registers follows: “bit is set” is

synonymous with “bit is set to Logic 1” or “writing Logic 1 for

the bit.” Similarly “clear a bit” is synonymous with “bit is set to

Logic 0” or “writing Logic 0 for the bit.”

Transfer Register Map

Addresses 0x08 to 0x18 are shadowed. Writes to these

addresses do not affect the part operation until a transfer

command is issued by writing a 0x01 to address 0xFF setting

the transfer bit. This allows these registers to be updated

internally simultaneously when the transfer bit is set. The

internal update takes place when the transfer bit is set and the

bit autoclears.

Table 5. Mode Selection

External

Voltage

Configuration

SDIO/DCS

AVDD (default)

AGND

Duty Cycle Stabilizer Enabled

Duty Cycle Stabilizer Disabled

Twos Complement Enabled

Offset Binary Enabled

Channel Specific Registers

SCLK/DFS

AVDD

AGND (default)

AVDD

Some channel setup functions such as the signal monitor

thresholds can be programmed differently for each channel. In

these cases channel address locations are internally duplicated

for each channel. These registers are designated in the

‘Parameter Name’ column of Table x as (local) registers. These

local registers can be accessed by setting the appropriate

Channel A or Channel B bits in register 0x05. If both bits are

set the subsequent write will affect both channels’ registers. In a

read cycle only Channel A or Channel B should be set to read

one of the two registers. If both bits are set during a SPI read

cycle the part returns the value for channel A. Registers

designated as (global) in the ‘Parameter Name’ column of Table

x affect the entire part or the channel features where

MON SDO/

OEB

Outputs in High Impedance

Outputs Enabled

AGND (default)

AVDD

MON SCLK/

PDWN

Chip in PowerDown/Standby

Normal Operation

AGND (default)

MEMORY MAP

Reading the Memory Map Table

Each row in the memory map table has eight bit locations. The

memory map is roughly divided into four sections: chip

configuration and ID register map (Address 0x00 to Address

0x05), ADC setup, control and test (Addresses 0x08 to Address

0x25), transfer register map (Address 0xFF), and digital feature

control (Address 0x100 to Address 0x11B).

independent settings are not allowed between the channels.

The settings in register 0x05 do not affect the global registers.

Starting from the right hand column, the memory map register

in Table x documents the default hex value for each hex address

shown. The column with the heading Bit 7 (MSB) is the start of

the default hex value given. For example, hex address 0x18,

reference select, has a hex default value of 0xC0. This means Bit

7 = 1, Bit 6 = 1, and the remaining bits are zeros. This setting is

the default reference selection setting. The default value uses a

2.0V peak to peak reference. For more information on this

function and others consult “Interfacing to High Speed ADCs via

SPI” at www.analog.com.

SPI ACCESSIBLE FEATURES

A brief description of all features accessible via the SPI follows.

They are described in great detail in the Analog Devices user

manual titled Interfacing to High Speed ADCs via SPI at

www.analog.com.

Modes: Allows the user to set either power-down or standby

mode.

Clock: Allows the user to access the DCS via the SPI.

Open Locations

Offset: Allows the user to digitally adjust the converter offset.

All address and bit locations that are not included in Table x are

currently not supported for this device. Unused bits of a valid

address location should be written with 0s. Writing to these

locations is required only when part of an address location is

open (for example, Address 0x18). If the entire address location

is open (for example, Address 0x13), then this address location

should not be written.

Test IO: Allows the user to set test modes to have known data

on output bits.

Output Mode: Allows the user to setup outputs.

Output phase: Allows user to set the output clock polarity.

Default Values

Output Delay: Allows user to vary the strength of the output

drivers.

Coming out of reset, critical registers are loaded with default

values. The default values for the registers are given in the

Vref:

Allows the user to set the reference voltage.

Rev. PrD | Page 33 of 41

AD9640

Preliminary Technical Data

Figure 28. Serial Port Interface Timing Diagram

Rev. PrD | Page 34 of 41

Preliminary Technical Data

AD9640

EXTERNAL MEMORY MAP

Table 6. Memory Map Register

Default Default

Addr. Parameter

(Hex) Name

Bit 7

(MSB)

Bit 0

(LSB)

Value

(Hex)

Notes/

Comments

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Chip Configuration Registers

±±

SPI Port

Configuration

±

LSB first

Soft reset

1

Soft reset

LSB first

±

±x1ꢁ

The nibbles

should be

mirrored so

that LSB- or

MSB-first

(global)

mode register

correctly

regardless of

shift mode.

±1

±2

Chip ID

(global)

ꢁ-bit Chip ID Bits ꢀ:±

(ADꢂ64± = ±x11), (default)

±x±F

Read

Only

Default is

unique chip

ID, different

for each

device. This is

a read-only

register.

Chip Grade

(global)

X

Speed Grade ID 4:3

±± = ꢁ± MSPS

X

Read

only

Speed Grade

ID used to

differentiate

devices.

±1 = 1±5 MSPS

1± = 125 MSPS

11 = 15± MSPS

Channel Index and Transfer Registers

±5

Channel Index

X

Data

Channel B

Data

Channel A

±x±3

Bits are set to

determine

which device

on chip

(default)

receives the

next write

command.

Applies to

local registers

FF

Device Update

X

Transfer

±x±±

Synchronousl

transfers data

from the

master shift

register to the

slave.

ADC Functions

±ꢁ

Power modes

External

Power

Internal power-down

mode

Determines

various

Down Pin

Function

(global)

generic

modes of chip

operation.

(local)

±±—normal operation

±1—full power-down

1±—standby

± = pdwn

1 = stndby

X

11—normal operation

±ꢂ

±B

Global clock

(global)

X

Duty cycle ±x±1

stabilize

(default)

Clock divide

(global)

X

Clock Divide Ratio

±±± = divide by 1

±±1 = divide by 2

±1± = divide by 3

±11 = divide by 4

1±± = divide by 5

1±1 = divide by 6

11± = divide by ꢀ

111 = divide by ꢁ

±x±±

Clock divide

values other

than ±±±

automatically

causes the

Duty Cycle

Stabilization

to become

active

Rev. PrD | Page 35 of 41

AD9640

Preliminary Technical Data

Default Default

Addr. Parameter

(Hex) Name

Bit 7

(MSB)

Bit 0

(LSB)

Value

(Hex)

Notes/

Comments

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

±D

Test Mode

(local)

X

Reset PN23

gen

Reset

PNꢂ gen

X

Output test mode

±±±—off (default)

±±1—midscale short

±1±—+positive FS

±11—−negative FS

±x±±

When set, the

test data is

placed on the

output pins in

place of

1±±—alternating checker board

1±1—PN 23 sequence

normal data.

11±—PN ꢂ sequence

111—one/zero word toggle

±E

Bist enable

(local)

X

Reset

BIST

Sequence

X

BIST

Enable

±x±±

1±

14

Offset adjust

(local)

Offset Adjust in LSBs from +31 to -32 (twos compliment format)

±x±±

Output Mode

Drive

Strength

Output

Type

Interleaved

CMOS

Output

Enable

Bar

X

Output

invert

(local)

±±—offset binary ±1—

twos complement

±1—greycode 11—

offset binary (local)

Configures the

outputs and

the format of

the data.

±—3.3V

CMOS or

ANSI LVDS

± = CMOS

1 = LVDS

(global)

(local)

1—1.ꢁV

CMOS or

Reduced

LVDS

(global)

15

Output Adjust

(global)

X

CMOS 3.3V Drive

Strength (±± is lowest

drive and 11 is highest

drive)

CMOS 1.ꢁ V Drive

Strength (±± is lowest

drive and 11 is highest

drive)

±x±2

Determines

CMOS output

drive strength

– Selecting

higher drive

strengths can

affect

converter

performance

16

Clock Phase

Control

Invert DCO

Clock

X

Input clock divider phase adjust

±±± = no delay

±x±±

On devices

that utilize

global clock

divide, allows

selection of

clock delays

into the

(global)

±±1 = 1 input clock cycle

±1± = 2 input clock cycles

±11 = 3 input clock cycles

1±± = 4 input clock cycles

1±1 = 5 input clock cycles

11± = 6 input clock cycles

dividerb.

1ꢁ

Vref Select

(global)

Reference Voltage

X

±x3±

Selection

±± = 1.25V pk-pk

±1 = 1.5V pk-pk

1± = 1.ꢀ5V pk-pk

11 = 2.±V pk-pk (default)

24

BIST Signature

lsb (local)

BIST Signature [ꢀ:±]

BIST Signature [15:ꢁ]

±x±±

Read Only

25

BIST Signature

msb (local)

1±±

Synch_Control

(global)

PM Sync

Enable

X

Clock

Divider

Sync

Master

Sync

Enable

Sync

Enable

Only

1±4

1±5

Fast Detect

Control (local)

X

Fast Detect Mode Select [2:±]

Enable

Fast

Detect

±x±±

Coarse Upper

X

Coarse Upper Threshold [2:±]

Threshold (local)

Rev. PrD | Page 36 of 41

Preliminary Technical Data

AD9640

Default Default

Addr. Parameter

(Hex) Name

Bit 7

(MSB)

Bit 0

(LSB)

Value

(Hex)

Notes/

Comments

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

1±6

1±ꢀ

1±ꢁ

1±ꢂ

1±A

1±B

1±C

Fine Upper

Threshold

Register ± (local)

Fine Upper Threshold [ꢀ:±]

±x±±

Fine Upper

Threshold

Register 1 (local)

X

Fine Upper Threshold [12:ꢁ]

Fine Lower

Threshold

Register ± (local)

Fine Lower Threshold [ꢀ:±]

Fine Lower

Threshold

Register 1 (local)

X

Fine Lower Threshold [12:ꢁ]

Increase Gain

Dwell Time

Register ± (local)

IncreaseGain Dwell Time [ꢀ:±]

In ADC Clock

Cycles

Increase Gain

Dwell Time

Register 1 (local)

IncreaseGain Dwell Time [15:ꢁ]

DC Correction Bandwidth [3:±]

In ADC Clock

Cycles

Signal monitor

DC Correction

Control (global)

X

DC

Correction

Freeze

DC

Correction Correction

for Signal

Path

for PM

Enable

1±D

1±E

1±F

11±

111

Signal monitor

DC Value

Channel A

Register ±

(global)

DC Value Channel A [ꢀ:±]

Read only

Signal monitor

DC Value

Channel A

Register 1

(global)

X

DC Value Channel A [13:ꢁ]

Signal monitor

DC Value

Channel B

Register ±

(global)

DC Value Channel B [ꢀ:±]

Signal monitor

DC Value

Channel B

Register 1

(global)

DC Value Channel A [13:ꢁ]

Signal monitor

SPORT Control

X

RMS

Magnitude

Output

Peak

Power

Output

Enable

Threshold

Crossing

Output

Enble

SPORT Clock Divide

±± = Undefined

±1 = divide by 2

1± = divide by 4

11 = divide by ꢁ

SPORT

SCLK

Sleep

SPORT

Enable

±x±4

±x±±

(global)

Enable

112

Signal monitor

Control (global)

Enable

Complex

Power

Calculation

Mode

X

MS Mode

± = RMS

1 = MS

Signal monitor Mode

Signal

monitor

Enable

±± = RMS/MS

Magnitude

±1 = Peak Power

1x = Threshold Count

113

114

115

116

Signal monitor

Period Register ±

(global)

Signal monitor Period [ꢀ:±]

Signal monitor Period [15:ꢁ]

Signal monitor Period [23:16]

±xꢁ±

±x±±

In ADC Clock

Cycles

Signal monitor

Period Register 1

(global)

In ADC Clock

Cycles

Signal monitor

Period Register 2

(global)

In ADC Clock

Cycles

Signal monitor

Signal monitor Value Channel A [ꢀ:±]

Rev. PrD | Page 3ꢀ of 41

Read only

AD9640

Preliminary Technical Data

Default Default

Addr. Parameter

(Hex) Name

Bit 7

(MSB)

Bit 0

(LSB)

Value

(Hex)

Notes/

Comments

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Value Channel A

Register ±

(global)

11ꢀ

11ꢁ

11ꢂ

11A

11B

Signal monitor

Value Channel A

Register 1

Signal monitor Value Channel A [15:ꢁ]

Read only

(global)

Signal monitor

Value Channel A

Register 2

X

Signal monitor Value Channel A [1ꢂ:16]

(global)

Signal monitor

Value Channel B

Register ±

Signal monitor Value Channel B [ꢀ:±]

Signal monitor Value Channel B [15:ꢁ]

(global)

Signal monitor

Value Channel B

Register 1

(global)

Signal monitor

Value Channel B

Register 2

X

Signal monitor Value Channel B [1ꢂ:16]

(global)

MEMORY MAP REGISTER DESCRIPTION

Rev. PrD | Page 3ꢁ of 41

Preliminary Technical Data

AD9640

APPLICATIONS

To maximize the coverage and adhesion between the ADC and

PCB, overlay a silkscreen to partition the continuous plane on

the PCB into several uniform sections. This provides several tie

points between the two during the reflow process. Using one

continuous plane with no partitions only guarantees one tie

point between the ADC and PCB. See the evaluation board for a

PCB layout example. For detailed information on packaging

and the PCB layout of chip scale packages, see the AN-772

Application Note, “A Design and Manufacturing Guide for the

Lead Frame Chip Scale Package (LFCSP),” at www.analog.com.

DESIGN GUIDELINES

When designing the AD9640 into a system, it is recommended

that, before starting design and layout, the designer become

familiar with these guidelines, which discuss the special circuit

connections and layout requirements required for certain pins.

Power and Ground Recommendations

When connecting power to the AD9640, it is recommended

that two separate 1.8 V supplies be used: one supply should be

used for analog (AVDD) and digital (DVDD) and a separate

supply for the digital outputs (DRVDD). The AVDD and

DVDD supplies, while derived from the same source, should be

isolated with a ferrite bead or filter choke and separate

decoupling capacitors. The user can employ several different

decoupling capacitors to cover both high and low frequencies.

These should be located close to the point of entry at the PC

board level and close to the part’s pins with minimal trace

length.

CML

The CML pin should be decoupled to ground with a 0.1uF

capacitor, as shown in Figure 5.

RBIAS

The AD9640 requires the user to place a 10KΩ resistor between

the RBIAS pin and ground. This resister sets the master current

reference of the ADC core and should have at least a 1%

tolerance.

A single PC board ground plane should be sufficient when

using the AD9640. With proper decoupling and smart parti-

tioning of the PC board’s analog, digital, and clock sections,

optimum performance is easily achieved.

Reference Decoupling

The VREF pin should be externally decoupled to ground with a

low ESR 1.0uF capacitor in parallel with a 0.1uF ceramic low

ESR capacitor.

Exposed Paddle Thermal Heat Slug Recommendations

SPI Port

It is mandatory that the exposed paddle on the underside of the

ADC is connected to analog ground (AGND) to achieve the

best electrical and thermal performance of the AD9640. A

continuous exposed (no solder mask) copper plane on the PCB

should mate to the AD9640 exposed paddle, Pin 0. The copper

plane should have several vias to achieve the lowest possible

resistive thermal path for heat dissipation to flow through the

bottom of the PCB. These vias should be filled or plugged with

nonconductive epoxy.

The SPI port should not be active during periods when the full

dynamic performance of the converter is required. Since the

SCLK, CSB and SDIO signals are typically asynchronous to the

ADC clock, noise from these signals can degrade the converter’s

performance. If the on board SPI Bus is utilized for other

devices it may be necessary to provide buffers between this bus

and the AD9640 in order to keep these signals from

transitioning at the converter inputs during critical sampling

periods.

Rev. PrD | Page 3ꢂ of 41

AD9640

Preliminary Technical Data

AD9640 EVALUATION BOARD AND SOFTWARE

The AD9640 evaluation board kit contains a fully populated

AD9640 PCB, schematic diagrams, operating software, and a

comprehensive instruction manual.

Users can preview the evaluation board schematic, the software,

and the instruction manual on the product Web page of the

Analog Devices website.

Rev. PrD | Page 4± of 41

OUTLINE DIMENSIONS

0.30

0.25

0.18

9.00

BSC SQ

0.60 MAX

PIN 1

INDICATOR

64

49

1

48

PIN 1

INDICATOR

7.25

7.10 SQ

6.95

8.75

BSC SQ

TOP

VIEW

EXPOSED PAD

(BOTTOM VIEW)

0.50

0.40

0.30

33

16

17

32

0.25 MIN

7.50

REF

0.80 MAX

0.65 TYP

1.00

0.85

0.80

12° MAX

0.05 MAX

0.02 NOM

SEATING

PLANE

0.50 BSC

0.20 REF

COMPLIANT TO JEDEC STANDARDS MO-220-VMMD-4

Figure 29. 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

9mm x 9mm Body, Very Thin Quad

(CP-64-3)

Dimensions shown in millimeters

ORDERING GUIDE

Model

Temperature Range

Package Description

Package Option

CP-64-3

ADꢂ64±BCPZ-15±

ADꢂ64±BCPZ-125

ADꢂ64±BCPZ-1±5

ADꢂ64±BCPZ-ꢁ±

ADꢂ64±/PCB

−4±°C to +ꢁ5°C

64-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

Evaluation Board with ADꢂ64± and Software

©

registered trademarks are the property of their respective owners.

PR06547-0-12/06(PrA)

Rev. PrD | Page 41 of 41


型号：	AD9640BCPZ-150
厂家：	ADI
描述：	14-Bit, 80/105/125/150 MSPS, 1.8 V Dual Analog-to-Digital Converter 14位， 80/105/125/150 MSPS ， 1.8 V双通道模拟数字转换器转换器模数转换器
文件：	总41页 (文件大小：937K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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