AD9650USVZ-105EP [ADI]
16-Bit, 25 MSPS/65 MSPS/80 MSPS/105 MSPS, 1.8 V Dual Analog-to-Digital Converter (ADC);
| 型号： | AD9650USVZ-105EP |
| 厂家： | 
ADI |
| 描述： | 16-Bit, 25 MSPS/65 MSPS/80 MSPS/105 MSPS, 1.8 V Dual Analog-to-Digital Converter (ADC) 转换器 |
| 文件： | 总12页 (文件大小：222K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Dual 16-Bit, 105 MSPS, 1.8 V
Analog-to-Digital Converter
AD9650-EP
Data Sheet
FEATURES
FUNCTIONAL BLOCK DIAGRAM
SDIO/ SCLK/
Dual 16-bit ADC in enhanced package for extended
temperature range of −55°C to +85°C
1.8 V analog supply operation
AVDD
CSB
DRVDD
DCS
DFS
SPI
AD9650-EP
LVDS output
OR+
SNR: 80.5 dBFS at 30 MHz input and 105 MSPS data rate
SFDR: 93 dBc at 30 MHz input and 105 MSPS data rate
Low power: 328 mW per channel at 105 MSPS
Integer 1-to-8 input clock divider
PROGRAMMING DATA
CMOS/LVDS
D15+ (MSB)
TO
D0+ (LSB)
VIN+A
VIN–A
16
ADC
OUTPUT BUFFER
CLK+
CLK–
IF sampling frequencies up to 300 MHz
Analog input range of 2.7 V p-p
DIVIDE 1
TO 8
VREF
SENSE
DCO+
DCO–
Optional on-chip dither
DUTY CYCLE
STABILIZER
DCO
GENERATION
REF
SELECT
Integrated ADC sample-and-hold inputs
Differential analog inputs with 500 MHz bandwidth
ADC clock duty cycle stabilizer (DCS)
VCM
RBIAS
VIN–B
VIN+B
OR–
D15– (MSB)
TO
D0– (LSB)
16
CMOS/LVDS
OUTPUT BUFFER
ADC
APPLICATIONS
Radar
MULTICHIP
SYNC
Electronic warfare (EW) systems
Joint tactical radio system (JTRS) and other COMSEC
Industrial instrumentation
AGND
SYNC
PDWN
OEB
NOTES
X-ray, MRI, and ultrasound equipment
High speed pulse acquisition
Chemical and spectrum analysis
General-purpose software radios
1. PIN NAMES ARE FOR THE LVDS PIN CONFIGURATION ONLY.
Figure 1.
GENERAL DESCRIPTION
The AD9650-EP is a dual 16-bit, 105 MSPS analog-to-digital
converter (ADC) designed for digitizing high frequency, wide
dynamic range signals with input frequencies of up to 300 MHz.
Additional application and technical information can be found
in the AD9650 data sheet.
PRODUCT HIGHLIGHTS
The dual ADC core features a multistage differential pipelined
architecture with integrated output error correction logic. Each
ADC features wide bandwidth, differential sample-and-hold analog
input amplifiers, and a shared integrated voltage reference, which
eases design considerations. A duty cycle stabilizer (DCS) is pro-
vided to compensate for variations in the ADC clock duty cycle,
allowing the converters to maintain excellent performance.
1. On-chip dither option for improved SFDR performance
with low power analog input.
2. Proprietary differential input that maintains excellent SNR
performance for input frequencies up to 300 MHz.
3. Operation from a single 1.8 V supply with a separate digital
output driver supply that accommodates 1.8 V CMOS or
LVDS outputs.
The ADC output data can be routed directly to the two external
16-bit output ports or multiplexed on a single 16-bit bus. These
outputs can be set to either 1.8 V CMOS or LVDS.
4. Standard serial port interface (SPI) that supports various
product features and functions such as data formatting
(offset binary, twos complement, or Gray coding), enabling
the clock DCS, power-down, and test modes.
5. 12 mm × 12 mm, 80-lead TQFP with an exposed pad
(7.5 mm × 7.5 mm).
Flexible power-down options allow significant power savings,
when desired. Programming for setup and control is accomplished
using a 3-wire, SPI-compatible serial interface.
The AD9650-EP is available in an 80-lead TQFP and is specified
over the extended temperature range of −55°C to +85°C.
Rev. 0
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Tel: 781.329.4700
Technical Support
©2013 Analog Devices, Inc. All rights reserved.
www.analog.com
AD9650-EP
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Digital Specifications ....................................................................4
Switching Specifications ...............................................................6
Timing Specifications ...................................................................6
Absolute Maximum Ratings ............................................................8
Thermal Characteristics ...............................................................8
ESD Caution...................................................................................8
Pin Configuration and Function Descriptions..............................9
Outline Dimensions....................................................................... 11
Ordering Guide .......................................................................... 11
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
ADC DC Specifications............................................................... 3
ADC AC Specifications ............................................................... 4
REVISION HISTORY
5/13—Revision 0: Initial Version
Rev. 0 | Page 2 of 12
Data Sheet
AD9650-EP
SPECIFICATIONS
ADC DC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.35 V internal reference, DCS disabled,
unless otherwise noted.
Table 1.
Parameter
Temperature
Min
Typ
Max
Unit
RESOLUTION
Full
16
Bits
ACCURACY
No Missing Codes
Offset Error
Gain Error
Full
Full
Full
Full
25°C
Full
25°C
Guaranteed
0.4
0.4
0.7
2.5
+1.3
% FSR
% FSR
LSB
LSB
LSB
Differential Nonlinearity (DNL)1
−1
0.7
3
Integral Nonlinearity (INL)1
6
LSB
MATCHING CHARACTERISTIC
Offset Error
Gain Error
Full
Full
0.1
0.5
0.4
1.3
% FSR
% FSR
TEMPERATURE DRIFT
Offset Error
Gain Error
Full
Full
2
15
ppm/°C
ppm/°C
INTERNAL VOLTAGE REFERENCE
Output Voltage Error (1.35 V Mode)
Load Regulation at 1.0 mA
INPUT REFERRED NOISE
VREF = 1.35 V
Full
Full
7
10
14
mV
mV
25°C
1.5
LSB rms
ANALOG INPUT
Input Span, VREF = 1.35 V
Input Capacitance2
Input Common-Mode Voltage
REFERENCE INPUT RESISTANCE
POWER SUPPLIES
Supply Voltage
Full
Full
Full
Full
2.7
11
0.9
6
V p-p
pF
V
kΩ
AVDD
DRVDD
Supply Current1
Full
Full
1.7
1.7
1.8
1.8
1.9
1.9
V
V
IAVDD
Full
Full
Full
332
36
100
340
mA
mA
mA
IDRVDD (1.8 V CMOS)
IDRVDD (1.8 V LVDS)
POWER CONSUMPTION
DC Input
Full
656
675
mW
Sine Wave Input1 (DRVDD = 1.8 V)
CMOS Output Mode
LVDS Output Mode
Standby Power3
Full
Full
Full
Full
663
778
50
mW
mW
mW
mW
Power-Down Power
0.25
2.5
1 Measured with a low input frequency, full-scale sine wave, with approximately 5 pF loading on each output bit.
2 Input capacitance refers to the effective capacitance between one differential input pin and AGND.
3 Standby power is measured with a dc input and with the CLK+ and CLK− pins inactive (set to AVDD or AGND).
Rev. 0 | Page 3 of 12
AD9650-EP
Data Sheet
ADC AC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.35 V internal reference, DCS disabled,
unless otherwise noted.
Table 2.
Parameter1
Temperature
Min
78.4
77.9
Typ
Max
Unit
SIGNAL-TO-NOISE RATIO (SNR)
fIN = 30 MHz
25°C
Full
80.5
dBFS
dBFS
SIGNAL-TO-NOISE-AND-DISTORTION (SINAD)
fIN = 30 MHz
25°C
Full
80.2
dBFS
dBFS
EFFECTIVE NUMBER OF BITS (ENOB)
fIN = 30 MHz
25°C
13
Bits
WORST SECOND OR THIRD HARMONIC
fIN = 30 MHz
25°C
Full
−93
dBc
dBc
−87
−94
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
fIN = 30 MHz
25°C
Full
93
dBc
dBc
87
WORST OTHER (HARMONIC OR SPUR)
fIN = 30 MHz
25°C
Full
−101
dBc
dBc
CROSSTALK2
Full
−105
500
dBFS
MHz
ANALOG INPUT BANDWIDTH
25°C
1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions.
2 Crosstalk is measured with a 170 MHz tone at −1 dBFS on one channel and no input on the alternate channel.
DIGITAL SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.35 V internal reference, DCS enabled,
unless otherwise noted.
Table 3.
Parameter
Temperature
Min
Typ
Max
Unit
DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−)
Logic Compliance
CMOS/LVDS/LVPECL
0.9
Internal Common-Mode Bias
Differential Input Voltage
Input Voltage Range
Input Common-Mode Range
High Level Input Current
Low Level Input Current
Input Capacitance
Full
Full
Full
Full
Full
Full
Full
Full
V
0.3
AGND
0.9
−100
−100
3.6
AVDD
1.4
V p-p
V
V
+100
+100
µA
µA
pF
kΩ
9
10
Input Resistance
8
12
SYNC INPUT
Logic Compliance
Internal Bias
CMOS
0.9
Full
Full
Full
Full
Full
Full
Full
Full
V
Input Voltage Range
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Capacitance
AGND
1.2
AGND
−100
−100
AVDD
AVDD
0.6
V
V
V
+100
+100
µA
µA
pF
kΩ
1
16
Input Resistance
12
20
Rev. 0 | Page 4 of 12
Data Sheet
AD9650-EP
Parameter
Temperature
Min
Typ
Max
Unit
LOGIC INPUT (CSB)1
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Resistance
Full
Full
Full
Full
Full
Full
1.22
0
−10
40
2.1
0.6
+10
132
V
V
µA
µA
kΩ
pF
26
2
Input Capacitance
LOGIC INPUT (SCLK/DFS)2
High Level Input Voltage
Low Level Input Voltage
High Level Input Current (VIN = 1.8 V)
Low Level Input Current
Input Resistance
Full
Full
Full
Full
Full
Full
1.22
0
−92
−10
2.1
0.6
−135
+10
V
V
µA
µA
kΩ
pF
26
2
Input Capacitance
LOGIC INPUT/OUTPUT (SDIO/DCS)1
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Resistance
Full
Full
Full
Full
Full
Full
1.22
0
−10
38
2.1
0.6
+10
128
V
V
µA
µA
kΩ
pF
26
5
Input Capacitance
LOGIC INPUTS (OEB, PDWN)2
High Level Input Voltage
Low Level Input Voltage
High Level Input Current (VIN = 1.8 V)
Low Level Input Current
Input Resistance
Full
Full
Full
Full
Full
Full
1.22
0
−90
−10
2.1
0.6
−134
+10
V
V
µA
µA
kΩ
pF
26
5
Input Capacitance
DIGITAL OUTPUTS
CMOS Mode—DRVDD = 1.8 V
High Level Output Voltage
IOH = 50 µA
Full
Full
1.79
1.75
V
V
IOH = 0.5 mA
Low Level Output Voltage
IOL = 1.6 mA
IOL = 50 µA
Full
Full
0.2
0.05
V
V
LVDS Mode—DRVDD = 1.8 V
Differential Output Voltage (VOD)
ANSI Mode
Reduced Swing Mode
Output Offset Voltage (VOS)
ANSI Mode
Full
Full
290
160
345
200
400
230
mV
mV
Full
Full
1.15
1.15
1.25
1.25
1.35
1.35
V
V
Reduced Swing Mode
1 Pull up.
2 Pull down.
Rev. 0 | Page 5 of 12
AD9650-EP
Data Sheet
SWITCHING SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.35 V internal reference, DCS enabled,
unless otherwise noted.
Table 4.
Parameter
Temperature
Min
Typ
Max
Unit
CLOCK INPUT PARAMETERS
Input Clock Rate
Conversion Rate1
Full
640
MHz
DCS Enabled
DCS Disabled
Full
Full
Full
20
10
9.5
105
105
MSPS
MSPS
ns
CLK Period—Divide-by-1 Mode (tCLK
CLK Pulse Width High (tCH)
Divide-by-1 Mode, DCS Enabled
Divide-by-1 Mode, DCS Disabled
Divide-by-2 Mode Through Divide-by-8 Mode
Aperture Delay (tA)
Aperture Uncertainty (Jitter, tJ)
DATA OUTPUT PARAMETERS
CMOS Mode
)
Full
Full
Full
Full
Full
2.85
4.5
0.8
4.75
4.75
6.65
5.0
ns
ns
ns
ns
1.0
0.075
ps rms
Data Propagation Delay (tPD)
DCO Propagation Delay (tDCO
Full
Full
Full
2.8
3.5
3.1
−0.4
4.2
0
ns
ns
ns
2
)
)
DCO to Data Skew (tSKEW
LVDS Mode
)
−0.6
2.9
Data Propagation Delay (tPD)
DCO Propagation Delay (tDCO
Full
Full
Full
Full
3.7
3.9
4.5
+0.5
ns
ns
ns
Cycles
Cycles
µs
2
DCO to Data Skew (tSKEW
)
−0.1
+0.2
12
12/12.5
500
2
CMOS Mode Pipeline Delay (Latency)
LVDS Mode Pipeline Delay (Latency), Channel A/Channel B Full
Wake-Up Time3
Full
Full
Out-of-Range Recovery Time
Cycles
1 Conversion rate is the clock rate after the divider.
2 Additional DCO delay can be added by writing to Bit 0 through Bit 4 in SPI Register 0x17.
3 Wake-up time is defined as the time required to return to normal operation from power-down mode.
TIMING SPECIFICATIONS
Table 5.
Parameter
Description
Limit
Unit
SYNC TIMING REQUIREMENTS
tSSYNC
tHSYNC
SYNC to rising edge of CLK+ setup time
SYNC to rising edge of CLK+ hold time
0.3
0.4
ns typ
ns typ
SPI TIMING REQUIREMENTS
tDS
tDH
tCLK
tS
tH
tHIGH
tLOW
tEN_SDIO
Setup time between the data and the rising edge of SCLK
Hold time between the data and the rising edge of SCLK
Period of the SCLK
Setup time between CSB and SCLK
Hold time between CSB and SCLK
SCLK pulse width high
SCLK pulse width low
Time required for the SDIO pin to switch from an input to
an output relative to the SCLK falling edge
2
2
40
2
2
10
10
10
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
tDIS_SDIO
Time required for the SDIO pin to switch from an output to
an input relative to the SCLK rising edge
10
ns min
Rev. 0 | Page 6 of 12
Data Sheet
AD9650-EP
Timing Diagrams
N – 1
N + 4
tA
N + 5
N
N + 3
V
IN
N + 1
N + 2
tCH
tCLK
CLK+
CLK–
tDCO
DCOA/DCOB
tSKEW
CH A/CH B DATA
N – 13
N – 12
N – 11
N – 10
N – 9
N – 8
tPD
Figure 2. CMOS Default Output Mode Data Output Timing
N – 1
N + 4
tA
N + 5
N
N + 3
V
IN
N + 1
N + 2
tCH
tCLK
CLK+
CLK–
tDCO
DCOA/DCOB
tSKEW
tPD
CH A CH B CH A CH B CH A CH B CH A CH B CH A
N – 12 N – 12 N – 11 N – 11 N – 10 N – 10 N – 9 N – 9 N – 8
CH A/CH B DATA
Figure 3. CMOS Interleaved Output Mode Data Output Timing
N – 1
N + 4
tA
N + 5
N
N + 3
V
IN
N + 1
N + 2
tCH
tCLK
CLK+
CLK–
tDCO
DCO+/DCO–
tSKEW
tPD
CH A CH B CH A CH B CH A CH B CH A CH B CH A
N – 12 N – 12 N – 11 N – 11 N – 10 N – 10 N – 9 N – 9 N – 8
CH A/CH B DATA
Figure 4. LVDS Mode Data Output Timing
CLK+
SYNC
tSSYNC
tHSYNC
Figure 5. SYNC Input Timing Requirements
Rev. 0 | Page 7 of 12
AD9650-EP
Data Sheet
ABSOLUTE MAXIMUM RATINGS
THERMAL CHARACTERISTICS
Table 6.
The exposed pad on the underside of the TQFP package must
be soldered to the ground plane for the package. Soldering the
exposed pad to the PCB increases the reliability of the solder
joints and maximizes the thermal capability of the package.
Parameter
Electrical1
AVDD to AGND
DRVDD to AGND
Rating
−0.3 V to +2.0 V
−0.3 V to +2.0 V
VIN+A/VIN+B, VIN−A/VIN−B
to AGND
−0.3 V to AVDD + 0.2 V
Typical θJA is specified for a 4-layer PCB with a solid ground
plane. Airflow improves heat dissipation, which reduces θJA. In
addition, metal in direct contact with the package leads from metal
traces, through holes, ground, and power planes reduces θJA.
CLK+, CLK− to AGND
SYNC to AGND
VREF to AGND
SENSE to AGND
VCM to AGND
RBIAS to AGND
CSB to AGND
SCLK/DFS to AGND
SDIO/DCS to AGND
OEB
−0.3 V to AVDD + 0.2 V
−0.3 V to AVDD + 0.2 V
−0.3 V to AVDD + 0.2 V
−0.3 V to AVDD + 0.2 V
−0.3 V to AVDD + 0.2 V
−0.3 V to AVDD + 0.2 V
−0.3 V to DRVDD + 0.2 V
−0.3 V to DRVDD + 0.2 V
−0.3 V to DRVDD + 0.2 V
−0.3 V to DRVDD + 0.2 V
−0.3 V to DRVDD + 0.2 V
−0.3 V to DRVDD + 0.2 V
Table 7. Thermal Resistance
Airflow
Velocity (m/sec) θJA
1, 2, 4
1, 3, 4
Package Type
θJC
4.67
Unit
80-Lead TQFP_EP
0
22.48
°C/W
1 Per JEDEC JESD51-7, plus JEDEC JESD25-5 2S2P test board.
2 Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air).
3 Per MIL-STD-883, Method 1012.1.
4 Per JEDEC STD, a 7 × 7 via array should be used to achieve this value.
PDWN
D0+/D0− Through D15+/D15−
to AGND
ESD CAUTION
DCO+/DCO− to AGND
Environmental
Operating Temperature Range
(Ambient)
−0.3 V to DRVDD + 0.2 V
−55°C to +85°C
Maximum Junction Temperature 150°C
Under Bias
Storage Temperature Range
(Ambient)
−65°C to +150°C
1 The inputs and outputs are rated to the supply voltage (AVDD + 0.2 V or
DRVDD + 0.2 V), but they should not exceed 2.1 V.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rev. 0 | Page 8 of 12
Data Sheet
AD9650-EP
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
DNC
DNC
CLK+
CLK–
SYNC
D0–
1
2
3
4
5
6
7
8
9
60 DNC
PIN 1
59 DNC
IDENTIFIER
58 PDWN
57 OEB
56 CSB
55 SCLK/DFS
54 SDIO/DCS
53 OR+
D0+
D1–
AD9650-EP
TOP VIEW
(Not to Scale)
D1+
52 OR–
D2– 10
D2+ 11
51 D15+
50 D15–
49 D14+
48 D14–
47 DRVDD
46 D13+
45 D13–
44 D12+
43 D12–
42 DNC
CONNECT EXPOSED PAD TO GROUND
DRVDD 12
D3– 13
D3+ 14
D4– 15
D4+ 16
D5– 17
D5+ 18
DNC 19
DNC 20
41 DNC
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
NOTES
1. DNC = DO NOT CONNECT.
2. THE EXPOSED THERMAL PAD ON THE BOTTOM OF THE PACKAGE
PROVIDES THE ANALOG GROUND FOR THE PART. THIS EXPOSED
PAD MUST BE CONNECTED TO GROUND FOR PROPER OPERATION.
Figure 6. Interleaved Parallel LVDS Pin Configuration (Top View)
Table 8. Pin Function Descriptions (Interleaved Parallel LVDS Mode)
Pin No.
Mnemonic
Type
Description
ADC Power Supplies
12, 25, 34, 47
63, 64, 67, 68,
73, 74, 77, 78
DRVDD
AVDD
Supply
Supply
Digital Output Driver Supply (1.8 V Nominal).
Analog Power Supply (1.8 V Nominal).
0
AGND,
Exposed Pad
Ground
The exposed thermal pad on the bottom of the package provides the analog ground
for the part. This exposed pad must be connected to ground for proper operation.
ADC Analog
65
66
76
75
69
70
72
71
VIN+A
VIN−A
VIN+B
VIN−B
VREF
SENSE
RBIAS
VCM
Input
Input
Input
Input
Differential Analog Input Pin (+) for Channel A.
Differential Analog Input Pin (−) for Channel A.
Differential Analog Input Pin (+) for Channel B.
Differential Analog Input Pin (−) for Channel B.
Input/output Voltage Reference Input/Output.
Input Voltage Reference Mode Select.
Input/output External Reference Bias Resistor.
Output
Input
Common-Mode Level Bias Output for Analog Inputs.
ADC Clock Input—True.
ADC Clock Input—Complement.
3
4
CLK+
CLK−
Input
Digital Input
5
SYNC
Input
Digital Synchronization Pin. Slave mode only.
Rev. 0 | Page 9 of 12
AD9650-EP
Data Sheet
Pin No.
Mnemonic
Type
Description
Digital Outputs
7
6
9
8
11
10
14
13
16
15
18
17
24
23
27
26
29
28
33
32
36
35
38
37
44
43
46
45
49
48
51
50
D0+
D0−
D1+
D1−
D2+
D2−
D3+
D3−
D4+
D4−
D5+
D5−
D6+
D6−
D7+
D7−
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Channel A/Channel B LVDS Output Data 0—True (LSB).
Channel A/Channel B LVDS Output Data 0—Complement (LSB).
Channel A/Channel B LVDS Output Data 1—True.
Channel A/Channel B LVDS Output Data 1—Complement.
Channel A/Channel B LVDS Output Data 2—True.
Channel A/Channel B LVDS Output Data 2—Complement.
Channel A/Channel B LVDS Output Data 3—True.
Channel A/Channel B LVDS Output Data 3—Complement.
Channel A/Channel B LVDS Output Data 4—True.
Channel A/Channel B LVDS Output Data 4—Complement.
Channel A/Channel B LVDS Output Data 5—True.
Channel A/Channel B LVDS Output Data 5—Complement.
Channel A/Channel B LVDS Output Data 6—True.
Channel A/Channel B LVDS Output Data 6—Complement.
Channel A/Channel B LVDS Output Data 7—True.
Channel A/Channel B LVDS Output Data 7—Complement.
Channel A/Channel B LVDS Output Data 8—True.
D8+
D8−
D9+
D9−
Channel A/Channel B LVDS Output Data 8—Complement.
Channel A/Channel B LVDS Output Data 9—True.
Channel A/Channel B LVDS Output Data 9—Complement.
Channel A/Channel B LVDS Output Data 10—True.
Channel A/Channel B LVDS Output Data 10—Complement.
Channel A/Channel B LVDS Output Data 11—True.
Channel A/Channel B LVDS Output Data 11—Complement.
Channel A/Channel B LVDS Output Data 12—True.
Channel A/Channel B LVDS Output Data 12—Complement.
Channel A/Channel B LVDS Output Data 13—True.
Channel A/Channel B LVDS Output Data 13—Complement.
Channel A/Channel B LVDS Output Data 14—True.
Channel A/Channel B LVDS Output Data 14—Complement.
Channel A/Channel B LVDS Output Data 15—True (MSB).
Channel A/Channel B LVDS Output Data 15—Complement (MSB).
Channel A/Channel B LVDS Overrange Output—True.
Channel A/Channel B LVDS Overrange Output—Complement.
Channel A/Channel B LVDS Data Clock Output—True.
Channel A/Channel B LVDS Data Clock Output—Complement.
D10+
D10−
D11+
D11−
D12+
D12−
D13+
D13−
D14+
D14−
D15+
D15−
OR+
OR−
DCO+
DCO−
53
52
31
30
SPI Control
55
54
56
SCLK/DFS
SDIO/DCS
CSB
Input
SPI Serial Clock/Data Format Select Pin in External Pin Mode.
Input/output SPI Serial Data I/O/Duty Cycle Stabilizer Pin in External Pin Mode.
Input
SPI Chip Select (Active Low).
ADC Configuration
57
58
OEB
PDWN
Input
Input
Output Enable Input (Active Low) in External Pin Mode.
Power-Down Input in External Pin Mode. In SPI mode, this input can be configured
as power-down or standby.
Do Not Connect
1, 2, 19, 20, 21, 22,
39, 40, 41, 42, 59,
60, 61, 62, 79, 80
DNC
N/A
Do Not Connect.
Rev. 0 | Page 10 of 12
Data Sheet
AD9650-EP
OUTLINE DIMENSIONS
12.10
12.00 SQ
11.90
1.20
MAX
0.75
0.60
0.45
80
61
61
80
1
1
60
60
1.00 REF
SEATING
PLANE
PIN 1
14.20
7.60
7.50 SQ
7.40
14.00 SQ
13.80
EXPOSED
PAD
1.05
1.00
0.95
0.20
0.15
0.09
TOP VIEW
(PINS DOWN)
BOTTOM VIEW
(PINS UP)
41
41
20
20
21
40
40
21
0.15
0.10
0.05
7°
3.5°
0°
0.27
0.22
0.17
VIEW A
0.08
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.50
BSC
LEAD PITCH
COPLANARITY
SECTION OF THIS DATA SHEET.
VIEW A
ROTATED 90° CCW
COMPLIANT TO JEDEC STANDARDS MS-026-ADD-HD
Figure 7. 80-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP]
12 mm × 12 mm (SV-80-6)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
Temperature Range
−55°C to +85°C
−55°C to +85°C
Package Description
Package Option
SV-80-6
SV-80-6
AD9650USVZ-105EP
AD9650USVZR7-105EP
80-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP]
80-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP]
1 Z = RoHS Compliant Part.
Rev. 0 | Page 11 of 12
AD9650-EP
NOTES
Data Sheet
©2013 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D11312-0-5/13(0)
Rev. 0 | Page 12 of 12
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