AD9910_07 [ADI]
1 GSPS, 14-Bit, 3.3 V CMOS Direct Digital Synthesizer; 1 GSPS ， 14位， 3.3 V CMOS直接数字频率合成器
| 型号： | AD9910_07 |
| 厂家： | 
ADI |
| 描述： | 1 GSPS, 14-Bit, 3.3 V CMOS Direct Digital Synthesizer |
| 文件： | 总60页 (文件大小：1163K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
1 GSPS, 14-Bit, 3.3 V CMOS
Direct Digital Synthesizer
AD9910
FEATURES
APPLICATIONS
Agile local oscillator (LO) frequency synthesis
Programmable clock generator
FM chirp source for radar and scanning systems
Test and measurement equipment
Acousto-optic device drivers
1 GSPS internal clock speed (up to 400 MHz analog output)
Integrated 1 GSPS, 14-bit DAC
32-bit tuning word
Phase noise ≤ −125 dBc/Hz @ 1 kHz offset (400 MHz carrier)
Excellent dynamic performance with
>80 dB narrow-band SFDR
Polar modulator
Serial input/output (I/O) control
Fast frequency hopping
Automatic linear or arbitrary frequency, phase, and
amplitude sweep capability
8 frequency and phase offset profiles
1.8 V and 3.3 V power supplies
Software and hardware controlled power-down
100-lead TQFP_EP package
Integrated 1024 word × 32-bit RAM
PLL REFCLK multiplier
Parallel datapath interface
Internal oscillator, can be driven by a single crystal
Phase modulation capability
Amplitude modulation capability
Multichip synchronization
FUNCTIONAL BLOCK DIAGRAM
AD9910
HIGH SPEED PARALLEL
DATA INTERFACE
LINEAR
RAMP
GENERATOR
1GSPS DDS CORE
14-BIT DAC
1024
ELEMENT
RAM
REFCLK
MULTIPLIER
TIMING AND CONTROL
SERIAL CONTROL
DATA PORT
Figure 1.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2007 Analog Devices, Inc. All rights reserved.
AD9910
TABLE OF CONTENTS
Features .............................................................................................. 1
External PLL Loop Filter Components............................... 25
PLL Lock Indication .................................................................. 26
Output Shift Keying (OSK)....................................................... 26
Manual OSK............................................................................ 26
Automatic OSK....................................................................... 26
Digital Ramp Generator (DRG)............................................... 27
DRG Overview ....................................................................... 27
DRG Slope Control................................................................ 29
DRG Limit Control................................................................ 29
DRG Accumulator Clear....................................................... 29
Normal Ramp Generation .................................................... 29
No-Dwell Ramp Generation................................................. 31
DROVER Pin.......................................................................... 31
RAM Control.............................................................................. 32
RAM Overview....................................................................... 32
Load/Retrieve RAM Operation............................................ 32
RAM Playback Operation (Waveform Generation).......... 32
RAM_SWP_OVR (RAM Sweep Over) Pin........................ 33
Overview of RAM Playback Modes .................................... 33
RAM Direct Switch Mode..................................................... 33
RAM Direct Switch Mode with Zero-Crossing ................. 34
RAM Ramp Up Mode ........................................................... 34
RAM Ramp Up Internal Profile Control Mode................. 34
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 3
General Description......................................................................... 4
Specifications..................................................................................... 5
Electrical Specifications............................................................... 5
Absolute Maximum Ratings............................................................ 8
Equivalent Circuits....................................................................... 8
ESD Caution.................................................................................. 8
Pin Configuration and Function Descriptions............................. 9
Typical Performance Characteristics ........................................... 12
Application Circuits ....................................................................... 15
Theory of Operation ...................................................................... 16
Single Tone Mode....................................................................... 16
RAM Modulation Mode............................................................ 17
Digital Ramp Modulation Mode.............................................. 18
Parallel Data Port Modulation Mode....................................... 19
Parallel Data Clock (PDCLK)............................................... 19
Transmit Enable (TxENABLE)............................................. 20
Mode Priority.............................................................................. 21
Functional Block Detail ................................................................. 22
DDS Core..................................................................................... 22
14-Bit DAC Output .................................................................... 22
Auxiliary DAC ........................................................................ 23
Inverse Sinc Filter ....................................................................... 23
Clock Input (REF_CLK)............................................................ 23
REF_CLK Overview .............................................................. 23
Crystal Driven REF_CLK ..................................................... 24
Direct Driven REF_CLK ....................................................... 24
Phase-Locked Loop (PLL) Multiplier.................................. 24
PLL Charge Pump.................................................................. 25
Internal Profile Control Continuous Waveform Timing
Diagram................................................................................... 37
RAM Bidirectional Ramp Mode.......................................... 37
RAM Continuous Bidirectional Ramp Mode .................... 38
RAM Continuous Recirculate Mode................................... 40
Additional Features ........................................................................ 41
Profiles ......................................................................................... 41
I/O_Update Pin .......................................................................... 41
Automatic I/O Update............................................................... 41
Rev. 0 | Page 2 of 60
AD9910
Power-Down Control .................................................................41
Synchronization of Multiple Devices............................................43
Serial Programming........................................................................46
Control Interface—Serial I/O....................................................46
General Serial I/O Operation....................................................46
Instruction Byte...........................................................................46
Instruction Byte Information Bit Map .................................46
Serial I/O Port Pin Descriptions ...............................................46
SCLK—Serial Clock................................................................46
Register Bit Descriptions............................................................53
Control Function Register 1 (CFR1)....................................53
Control Function Register 2 (CFR2)....................................55
Control Function Register 3 (CFR3)....................................56
Auxiliary DAC Control Register...........................................56
I/O Update Rate Register.......................................................57
Frequency Tuning Word Register (FTW) ...........................57
Phase Offset Word Register (POW).....................................57
Amplitude Scale Factor Register (ASF) ...............................57
Multichip Sync Register .........................................................58
Digital Ramp Limit Register..................................................58
Digital Ramp Step Size Register............................................58
Digital Ramp Rate Register ...................................................58
Profile Registers ......................................................................59
Outline Dimensions........................................................................60
Ordering Guide ...........................................................................60
CS
—Chip Select Bar...............................................................46
SDIO—Serial Data Input/Output.........................................46
SDO—Serial Data Out ...........................................................46
I/O_RESET—Input/Output Reset ........................................46
I/O_UPDATE—Input/Output Update ................................47
Serial I/O Timing Diagrams......................................................47
MSB/LSB Transfers .....................................................................47
Register Map and Bit Descriptions ...............................................48
REVISION HISTORY
5/07—Revision 0: Initial Version
Rev. 0 | Page 3 of 60
AD9910
GENERAL DESCRIPTION
The AD9910 is a direct digital synthesizer (DDS) featuring
an integrated 14-bit DAC and supporting sample rates up to
1 GSPS. The AD9910 employs an advanced, proprietary DDS
technology that provides a significant reduction in power con-
sumption without sacrificing performance. The DDS/DAC
combination forms a digitally programmable, high frequency,
analog output synthesizer capable of generating a frequency
agile sinusoidal waveform at frequencies up to 400 MHz.
The AD9910 is controlled by programming its internal control
registers via a serial I/O port. The AD9910 includes an integrated
static RAM to support various combinations of frequency, phase,
and/or amplitude modulation. The AD9910 also supports a user
defined, digitally controlled, digital ramp mode of operation. In
this mode, the frequency, phase, or amplitude can be varied
linearly over time. For more advanced modulation functions, a
high speed parallel data input port is included to enable direct
frequency, phase, amplitude, or polar modulation.
The user has access to the three signal control parameters that
control the DDS: frequency, phase, and amplitude. The DDS
provides fast frequency hopping and frequency tuning resolu-
tion with its 32-bit accumulator. With a 1 GSPS sample rate, the
tuning resolution is ~0.23 Hz. The DDS also enables fast phase
and amplitude switching capability.
The AD9910 is specified to operate over the extended industrial
temperature range (see the Absolute Maximum Ratings section
for details).
RAM_SWP_OVR
AD9910
2
SDIO
SCLK
RAM
8
AUX
DAC
8-BIT
DAC FSC
I/O_RESET
DDS
CS
DAC_RSET
OUTPUT
AMPLITUDE (A)
PHASE (θ)
FREQUENCY (ω)
SHIFT
OSK
A
KEYING
IOUT
IOUT
Acos (ωt+θ)
Asin (ωt+θ)
DAC
14-BIT
2
DRCTL
DATA
ROUTE
θ
INVERSE
SINC
FILTER
DIGITAL
RAMP
GENERATOR
DRHOLD
AND
ω
PARTITION
CONTROL
DROVER
CLOCK
3
REFCLK_OUT
PROFILE
PROGRAMMING
REGISTERS
÷2
SYSCLK
I/O_UPDATE
8
REF_CLK
REF_CLK
DAC FSC
INTERNAL CLOCK TIMING
AND CONTROL
16
2
PLL
PARALLEL
INPUT
XTAL_SEL
POWER
DOWN
CONTROL
MULTICHIP
TxENABLE
PDCLK
PARALLEL DATA
TIMING AND
CONTROL
SYNCHRONIZATION
2
2
Figure 2. Detailed Block Diagram
Rev. 0 | Page 4 of 60
AD9910
SPECIFICATIONS
ELECTRICAL SPECIFICATIONS
AVDD (1.8 V) and DVDD (1.8 V) = 1.8 V 5ꢀ, AVDD (3.3 V) = 3.3 V 5ꢀ, DVDD_I/O = 3.3 V 5ꢀ, T = 25ꢁC, RSET = 10 kΩ,
OUT = 20 mA, external reference clock frequency = 1000 MHz with REFCLK multiplier disabled, unless otherwise noted.
I
Table 1.
Parameter
Conditions/Comments
Min
Typ
Max
Unit
REF_CLK INPUT CHARACTERISTICS
Frequency Range
REFCLK Multiplier
Disabled
Enabled
Full temperature range
Full temperature range
25
3.2
1000
60
MHz
MHz
MHz
MHz
MHz
pF
Maximum REFCLK Input Divider Frequency
Minimum REFCLK Input Divider Frequency
External Crystal
Input Capacitance
Input Impedance
1500 1900
25
25
3
2.8
35
Differential
kΩ
Single-ended
1.4
kΩ
Duty Cycle
REFCLK multiplier disabled
REFCLK multiplier enabled
Single-ended
45
40
50
100
55
60
1000
2000
%
%
mV p-p
mV p-p
REF_CLK Input level
Differential
REFCLK MULTIPLIER VCO CHARACTERISTICS
VCO Gain (KV) @ Center Frequency
VCO range Setting 0
VCO range Setting 1
VCO range Setting 2
VCO range Setting 3
VCO range Setting 4
VCO range Setting 51
429
500
555
750
789
850
MHz/V
MHz/V
MHz/V
MHz/V
MHz/V
MHz/V
REFCLK_OUT CHARACTERISTICS
Maximum Capacitive Load
Maximum Frequency
DAC OUTPUT CHARACTERISTICS
Full-Scale Output Current
Gain Error
20
25
pF
MHz
8.6
−10
20
31.6
+10
2.3
mA
%FS
μA
Output Offset
Differential Nonlinearity
Integral Nonlinearity
Output Capacitance
0.8
1.5
5
LSB
LSB
pF
Residual Phase Noise
REFCLK Multiplier
@ 1 kHz offset, 20 MHz AOUT
Disabled
Enabled @ 20×
−152
−140
−140
dBc/Hz
dBc/Hz
dBc/Hz
V
Enabled @ 100×
Voltage Compliance Range
Wideband SFDR
−0.5
+0.5
See the Typical Performance
Characteristics section
Narrow-Band SFDR
50.1 MHz Analog Output
500 kHz
125 kHz
12.5 kHz
500 kHz
125 kHz
12.5 kHz
–87
–87
–96
–87
–87
–95
dBc
dBc
dBc
dBc
dBc
dBc
101.3 MHz Analog Output
Rev. 0 | Page 5 of 60
AD9910
Parameter
Conditions/Comments
500 kHz
125 kHz
12.5 kHz
500 kHz
125 kHz
12.5 kHz
500 kHz
125 kHz
Min
Typ
–87
–87
–91
–86
–86
–88
–84
–84
–85
Max
Unit
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
201.1 MHz Analog Output
301.1 MHz Analog Output
401.3 MHz Analog Output
12.5 kHz
SERIAL PORT TIMING CHARACTERISTICS
Maximum SCLK Frequency
Minimum SCLK Clock Pulse Width
70
2
Mbps
ns
ns
Low
High
4
4
Maximum SCLK Rise/Fall Time
ns
Minimum Data Setup Time to SCLK
Minimum Data Hold Time to SCLK
Maximum Data Valid Time in Read Mode
5
0
ns
ns
ns
11
I/O_UPDATE/PS0/PS1/PS2 TIMING
CHARACTERISTICS
Minimum Pulse Width
Minimum Setup Time to SYNC_CLK
Minimum Hold Time to SYNC_CLK
High
1
2
0
SYNC_CLK cycle
ns
ns
Tx_ENABLE and 16-BIT PARALLEL (DATA) BUS
TIMING
Maximum PDCLK Frequency
Tx_ENABLE/Data Setup Time (to PDCLK)
Tx_ENABLE/Data Hold Time (to PDCLK)
250
MHz
ns
ns
2
1
MISCELLANEOUS TIMING CHARACTERISTICS
Wake-Up Time2
1
8
ms
Fast Recovery
Full Sleep Mode
Minimum Reset Pulse Width High
SYSCLK cycles
ꢀs
SYSCLK cycles3
150
5
DATA LATENCY (PIPE_LINE DELAY)
Data Latency, Single Tone or using Profiles
Frequency, Phase, Amplitude-to-DAC Output
Matched latency enabled and OSK
enabled
Matched latency enabled and OSK
disabled
91
79
SYSCLK cycles
SYSCLK cycles
Frequency, Phase-to-DAC Output
Matched latency disabled
Matched latency disabled
79
47
SYSCLK cycles
SYSCLK cycles
Amplitude-to-DAC Output
Data Latency using RAM Mode
Frequency, Phase-to-DAC Output
Amplitude-to-DAC Output
Matched latency enabled/disabled
Matched latency enabled
Matched latency disabled
94
106
58
SYSCLK cycles
SYSCLK cycles
SYSCLK cycles
Data Latency, Sweep Mode
Frequency, Phase-to-DAC Output
Amplitude-to-DAC Output
Matched latency enabled/disabled
Matched latency enabled
Matched latency disabled
91
91
47
SYSCLK cycles
SYSCLK cycles
SYSCLK cycles
Data Latency, 16-Bit Input Modulation Mode
Frequency, Phase-to-DAC Output
Matched latency enabled
Matched latency disabled
103
91
SYSCLK cycles
SYSCLK cycles
Rev. 0 | Page 6 of 60
AD9910
Parameter
Conditions/Comments
Min
Typ
Max
Unit
CMOS LOGIC INPUTS
Logic 1 Voltage
2.0
V
Logic 0 Voltage
Logic 1 Current
Logic 0 Current
Input Capacitance
CMOS LOGIC OUTPUTS
Logic 1 Voltage
0.8
120
50
V
90
38
2
μA
μA
pF
1 mA load
2.8
V
V
Logic 0 Voltage
0.4
POWER SUPPLY CURRENT
IAVDD (1.8 V)
IAVDD (3.3 V)
IDVDD (1.8 V)
IDVDD (3.3 V)
110
29
222
11
mA
mA
mA
mA
TOTAL POWER CONSUMPTION
Single Tone Mode
Rapid Power-Down Mode
Full Sleep Mode
715
330
19
850
400
25
mW
mW
mW
1 The gain value for VCO range Setting 5 is measured at 1000 MHz.
2 Wake-up time refers to the recovery from analog power-down. The longest time required is for the Reference Clock Multiplier PLL to relock to the reference. The wake-
up time assumes there is no capacitor on DAC_BP and that the recommended PLL loop filter values are used.
3 SYSCLK cycle refers to the actual clock frequency used on-chip by the DDS. If the reference clock multiplier is used to multiply the external reference clock frequency,
the SYSCLK frequency is the external frequency multiplied by the reference clock multiplication factor. If the reference clock multiplier is not used, the SYSCLK
frequency is the same as the external reference clock frequency.
Rev. 0 | Page 7 of 60
AD9910
ABSOLUTE MAXIMUM RATINGS
Table 2.
EQUIVALENT CIRCUITS
DAC OUTPUTS
Parameter
Rating
AVDD
AVDD (1.8 V), DVDD (1.8 V) Supplies
AVDD (3.3 V), DVDD_I/O (3.3 V) Supplies
Digital Input Voltage
Digital Output Current
Storage Temperature Range
Operating Temperature Range
θJA
2 V
4 V
−0.7 V to +4 V
5 mA
−65°C to +150°C
−40°C to +85°C
22°C/W
IOUT
IOUT
MUST TERMINATE OUTPUTS TO AGND
FOR CURRENT FLOW. DO NOT EXCEED
THE OUTPUT VOLTAGE COMPLIANCE
RATING.
θJC
2.8°C/W
150°C
300°C
Maximum Junction Temperature
Lead Temperature (10 sec Soldering)
Figure 3. Equivalent Input Circuit
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
DIGITAL INPUTS
DVDD_I/O
INPUT
AVOID OVERDRIVING DIGITAL INPUTS.
FORWARD BIASING ESD DIODES MAY
COUPLE DIGITAL NOISE ONTO POWER
PINS.
Figure 4. Equivalent Output Circuit
ESD CAUTION
Rev. 0 | Page 8 of 60
AD9910
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
75
74
73
72
71
70
69
68
67
66
AVDD (3.3V)
AVDD (3.3V)
NC
PLL_LOOP_FILTER
AVDD (1.8V)
AGND
1
2
PIN 1
INDICATOR
3
AGND
NC
4
AGND
5
I/O_RESET
CS
AVDD (1.8V)
SYNC_IN+
6
7
SCLK
SYNC_IN–
8
SDO
SYNC_OUT+
SYNC_OUT–
9
SDIO
10
11
12
13
14
15
16
17
18
19
20
21
DVDD_I/O (3.3V)
65 DGND
64
DVDD_I/O (3.3V)
SYNC_SMP_ERR
DGND
AD9910
DVDD (1.8V)
TQFP-100 (E_PAD)
TOP VIEW
(Not to Scale)
63
DRHOLD
62 DRCTL
61
MASTER_RESET
DVDD_I/O (3.3V)
DROVER
60 OSK
59
DGND
DVDD (1.8V)
I/O_UPDATE
EXT_PWR_DWN
PLL_LOCK
58
57
56
DGND
DVDD (1.8V)
NC
DVDD_I/O (3.3V)
55 SYNC_CLK
DVDD_I/O (3.3V)
54
53
52
51
DGND 22
PROFILE0
DVDD (1.8V)
23
24
25
PROFILE1
PROFILE2
RAM_SWP_OVR
D15
DGND
NC = NO CONNECT
Figure 5. Pin Configuration
Rev. 0 | Page 9 of 60
AD9910
Table 3. Pin Function Descriptions
Pin No.
Mnemonic
I/O1 Description
Not Connected. Allow device pins to float.
1, 20, 72, 86, 87,
93, 97 to 100
NC
2
PLL_LOOP_FILTER
I
PLL Loop Filter Compensation Pin. See the External PLL Loop Filter Components section for
details.
3, 6, 89, 92
74 to 77, 83
17, 23, 30, 47,
57, 64
AVDD (1.8V)
AVDD (3.3V)
DVDD (1.8V)
Analog Core VDD, 1.8 V Analog Supplies.
Analog DAC VDD, 3.3 V Analog Supplies.
Digital Core VDD, 1.8 V Digital Supplies.
11, 15, 21, 28, 45,
56, 66
4, 5, 73, 78, 79,
82, 85, 88, 96
DVDD_I/O (3.3V)
AGND
Digital Input/Output VDD, 3.3 V Digital Supplies.
Analog Ground.
13, 16, 22, 29, 46,
51, 58, 65
DGND
Digital Ground.
7
SYNC_IN+
I
Synchronization Signal, Digital Input (Rising Edge Active). The synchronization signal from
the external master to synchronize internal subclocks. See the Synchronization of Multiple
Devices section for details.
8
SYNC_IN−
I
Synchronization Signal, Digital Input (Rising Edge Active). The synchronization signal from
the external master to synchronize internal subclocks. See the Synchronization of Multiple
Devices section for details.
9
SYNC_OUT+
SYNC_OUT−
O
O
Synchronization Signal, Digital Output (Rising Edge Active). The synchronization signal
from the internal device subclocks to synchronize external slave devices. See the
Synchronization of Multiple Devices section for details.
Synchronization Signal, Digital Output (Rising Edge Active). The synchronization signal
from the internal device subclocks to synchronize external slave devices. See the
Synchronization of Multiple Devices section for details.
10
12
14
18
SYNC_SMP_ERR
MASTER_RESET
EXT_PWR_DWN
O
I
Synchronization Sample Error, Digital Output (Active High). Sync sample error: a high on
this pin indicates that the AD9910 did not receive a valid sync signal on SYNC_IN+/SYNC_IN−.
Master Reset, Digital Input (Active High). Master reset: clears all memory elements and sets
registers to default values.
External Power-Down, Digital Input (Active High). A high level on this pin initiates the
currently programmed power-down mode. See the Power-Down Control section of this
document for further details. If unused, connect to ground.
I
19
24
PLL_LOCK
O
O
I
Clock Multiplier PLL Lock, Digital Output (Active High). A high on this pin indicates the
Clock Multiplier PLL has acquired lock to the reference clock input.
RAM Sweep Over, Digital Output (Active High). A high on this pin indicates the RAM sweep
profile has completed.
RAM_SWP_OVR
25 to 27, 31 to 39, D<15:0>
42 to 44, 48
Parallel Input Bus (Active High).
49, 50
40
F<1:0>
PDCLK
I
O
Modulation Format Pin. Digital input to determine the modulation format.
Parallel Data Clock. This is the digital output (clock). The parallel data clock provides a
timing signal for aligning data at the parallel inputs.
41
TxENABLE
I
I
Transmit Enable. Digital input (active high). In burst mode communications, a high on this
pin indicates new data for transmission. In continuous mode, this pin remains high.
Profile Select Pins. Digital inputs (active high). Use these pins to select one of eight
phase/frequency profiles for the DDS. Changing the state of one of these pins transfers the
current contents of all I/O buffers to the corresponding registers. State changes should be
set up on the SYNC_CLK pin.
52 to 54
PROFILE<2:0>
55
SYNC_CLK
O
Output Clock Divided-By-Four. A digital output (clock). Many of the digital inputs on the
chip, such as I/O_UPDATE and PROFILE<2:0> need to be set up on the rising edge of this
signal.
Rev. 0 | Page 10 of 60
AD9910
Pin No.
Mnemonic
I/O1 Description
59
I/O_UPDATE
I
Input/Output Update. Digital input (active high). A high on this pin transfers the contents
of the I/O buffers to the corresponding internal registers.
60
OSK
I
Output Shift Keying. Digital input (active high). When the OSK features are placed in either
manual or automatic mode, this pin controls the OSK function. In manual mode, it toggles
the multiplier between 0 (low) and the programmed amplitude scale factor (high). In
automatic mode, a low sweeps the amplitude down to zero, a high sweeps the amplitude
up to the amplitude scale factor.
61
62
DROVER
DRCTL
O
I
Digital Ramp Over. Digital output (active high). This pin switches to Logic 1 whenever the
digital ramp generator reaches its programmed upper or lower limit.
Digital Ramp Control. Digital input (active high). This pin controls the slope polarity of the
digital ramp generator. See the Digital Ramp Generator (DRG) section for more details. If
not using the digital ramp generator, connect this pin to Logic 0.
63
67
DRHOLD
SDIO
I
Digital Ramp Hold. Digital input (active high). This pin stalls the digital ramp generator in
its present state. See the Digital Ramp Generator (DRG) section for more details. If not
using digital ramp generator, connect this pin to Logic 0.
Serial Data Input/Output. Digital input/output (active high). This pin can be either uni-
directional or bidirectional (default), depending on the configuration settings. In bidirectional
serial port mode, this pin acts as the serial data input and output. In unidirectional mode,
it is an input only.
I/O
68
69
70
SDO
SCLK
CS
O
I
Serial Data Output. Digital output (active high). This pin is only active in unidirectional
serial data mode. In this mode, it functions as the output. In bidirectional mode, this pin is
not operational and should be left floating.
Serial Data Clock. Digital clock (rising edge on write, falling edge on read). This pin
provides the serial data clock for the control data path. Write operations to the AD9910 use
the rising edge. Readback operations from the AD9910 use the falling edge.
Chip Select. Digital input (active low). This pin allows the AD9910 to operate on a common
serial bus for the control data path. Bringing this pin low enables the AD9910 to detect
serial clock rising/falling edges. Bringing this pin high causes the AD9910 to ignore input
on the serial data pins.
I
71
I/O_RESET
I
Input/Output Reset. Digital input (active high). This pin can be used when a serial I/O
communication cycle fails (see the I/O_RESET—Input/Output Reset section for details).
When not used, connect this pin to ground.
80
81
84
90
IOUT
O
O
O
I
Open Source DAC Complementary Output Source. Analog output (current mode). Connect
through a 50 Ω resistor to AGND.
Open Source DAC Output Source. Analog output (current mode). Connect through a 50 Ω
resistor to AGND.
Analog Reference Pin. This pin programs the DAC output full-scale reference current.
Attach a 10 kΩ resistor to AGND.
Reference Clock Input. Analog input. When the internal oscillator is engaged, this pin can
be driven by either an external oscillator or connected to a crystal. See the REF_CLK
Overview section for more details.
IOUT
DAC_RSET
REF_CLK
91
94
95
REF_CLK
I
Reference Clock Input. Analog input. See the REF_CLK Overview section for more details.
Crystal Output. Analog output. See the REF_CLK Overview section for more details.
Crystal Select. Analog input (active high). Driving the XTAL_SEL pin high, the AVDD (1.8V)
enables the internal oscillator to be used with a crystal resonator. If unused, connect it to AGND.
REFCLK_OUT
XTAL_SEL
O
I
1 I = input, O = output.
Rev. 0 | Page 11 of 60
AD9910
TYPICAL PERFORMANCE CHARACTERISTICS
–50
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–55
SFDR WITHOUT PLL
–60
SFDR WITH PLL
–65
1
–70
–75
0
50
100
150
200
250
300
350
400
450
450
START 0Hz
50MHz/DIV
STOP 500MHz
FREQUENCY OUT (MHz)
Figure 6. Wideband SFDR vs. Output Frequency
(PLL with Reference Clock = 15.625 × 64)
Figure 9. Wideband SFDR at 10 MHz
–45
–50
–55
–60
–65
–70
–75
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
LOW SUPPLY
HIGH SUPPLY
1
0
50
100
150
200
250
300
350
400
START 0Hz
50MHz/DIV
STOP 500MHz
FREQUENCY OUT (MHz)
Figure 7. SFDR vs. Supply ( 5%)
Figure 10. Wideband SFDR at 204 MHz
–50
–55
–60
–65
–70
–75
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–40°C
+85°C
1
0
50
100
150
200
250
300
350
400
START 0Hz
50MHz/DIV
STOP 500MHz
FREQUENCY OUT (MHz)
Figure 8. SFDR vs. Temperature
Figure 11. Wideband SFDR at 403 MHz
Rev. 0 | Page 12 of 60
AD9910
0
–12
–24
–36
–48
–60
–72
–84
–96
–108
–120
0
–12
–24
–36
–48
–60
–72
–84
–96
–108
–120
1
1
CENTER 403.78MHz
2.5kHz/DIV
SPAN 25kHz
CENTER 10.32MHz
2.5kHz/DIV
SPAN 25kHz
Figure 12. Narrow-Band SFDR at 10.32 MHz
Figure 14. Narrow-Band SFDR at 403.78 MHz
–90
0
–12
–24
–36
–48
–60
–72
–84
–96
–108
–120
fOUT = 397.8MHz
–100
–110
–120
–130
–140
–150
–160
–170
fOUT = 201.1MHz
fOUT = 98.6MHz
1
fOUT = 20.1MHz
10
100
1k
10k
100k
1M
10M
100M
CENTER 204.36MHz
2.5kHz/DIV
SPAN 25kHz
FREQUENCY OFFSET (Hz)
Figure 13. Narrow-Band SFDR at 204.36 MHz
Figure 15. Residual Phase Noise Plot, 1 GHz Operation with PLL Disabled
Rev. 0 | Page 13 of 60
AD9910
–90
–100
–110
–120
–130
–140
–150
450
400
350
300
250
200
150
100
50
fOUT = 397.8MHz
DVDD 1.8V
fOUT = 201.1MHz
AVDD 1.8V
AVDD 3.3V
DVDD 3.3V
fOUT = 20.1MHz
fOUT = 98.6MHz
1M 10M
FREQUENCY OFFSET (Hz)
–160
10
0
400
100
1k
10k
100k
100M
500
600
700
800
900
1000
SYSTEM CLOCK FREQUENCY (MHz)
Figure 16. Residual Phase Noise,
Figure 18. Power Dissipation vs. System Clock (PLL Enabled)
1 GHz Operation Using a 50 MHz Reference Clock with 20× PLL Multiplier
450
DVDD 1.8V
400
350
300
250
200
150
100
50
AVDD 1.8V
AVDD 3.3V
DVDD 3.3V
0
100
200
300
400
500
600
700
800
900 1000
SYSTEM CLOCK FREQUENCY (MHz)
Figure 17. Power Dissipation vs. System Clock (PLL Disabled)
Rev. 0 | Page 14 of 60
AD9910
APPLICATION CIRCUITS
AD9510, AD9511, ADF4106
÷
÷
CHARGE
PUMP
LOOP
FILTER
PHASE
COMPARATOR
VCO
REFERENCE
REF CLK
AD9910
LPF
Figure 19. DDS in PLL Feedback Locking to Reference Offering Fine Frequency and Delay Adjust Tuning
AD9510
CLOCK DISTRIBUTOR
CLOCK
SOURCE
WITH
DELAY EQUALIZATION
REF_CLK
AD9510
SYNCHRONIZATION
DELAY EQUALIZATION
SYNC_OUT
C1
S1AD9910
DATA
A1
FPGA
(MASTER)
SYNC_CLK
C2
DATA
S2AD9910
A2
FPGA
(SLAVE 1)
SYNC_CLK
CENTRAL
CONTROL
C3
S3AD9910
DATA
A3
FPGA
(SLAVE 2)
SYNC_CLK
C4
DATA
S4AD9910
A4
FPGA
(SLAVE 3)
SYNC_CLK
A_END
Figure 20. Synchronizing Multiple Devices to Increase Channel Capacity Using the AD9510 as a Clock Distributor for the Reference and Synchronization Clock
PROGRAMMABLE 1 TO 32
DIVIDER AND DELAY ADJUST
CLOCK OUTPUT
SELECTION(S)
AD9515
LVPECL
LVDS
CMOS
CH 2
AD9514
AD9513
AD9512
AD9910
n
LPF
REF CLK
n = DEPENDANT ON PRODUCT SELECTION.
Figure 21. Clock Generation Circuit Using the AD951x Series of Clock Distribution Chips
Rev. 0 | Page 15 of 60
AD9910
THEORY OF OPERATION
The AD9910 has four modes of operation:
A separate output shift keying (OSK) function is also available.
This function employs a separate digital linear ramp generator
that only affects the amplitude parameter of the DDS. The OSK
function has priority over the other data sources that can drive
the DDS amplitude parameter. As such, no other data source
can drive the DDS amplitude when the OSK function is enabled.
•
•
•
•
Single tone
RAM modulation
Digital ramp modulation
Parallel data port modulation
The modes relate to the data source used to supply the DDS
with its signal control parameters: frequency, phase, or ampli-
tude. The partitioning of the data into different combinations
of frequency, phase, and amplitude is handled automatically
based on the mode and/or specific control bits.
Although the various modes (including the OSK function) are
described independently, they can be enabled simultaneously.
This provides an unprecedented level of flexibility for generating
complex modulation schemes. However, to avoid multiple data
sources from driving the same DDS signal control parameter,
the device has a built-in priority protocol (see Table 5 in the
Mode Priority section).
In single tone mode, the DDS signal control parameters come
directly from the programming registers associated with the
serial I/O port. In RAM modulation mode, the DDS signal
control parameters are stored in the internal RAM and played
back upon command. In digital ramp modulation mode, the
DDS signal control parameters are delivered by a digital ramp
generator. In parallel data port modulation mode, the DDS
signal control parameters are driven directly into the parallel port.
SINGLE TONE MODE
In single tone mode, the DDS signal control parameters are
supplied directly from the programming registers. A profile is
an independent register that contains the DDS signal control
parameters. Eight profile registers are available.
Each profile is independently accessible. Use the three external
profile pins (PROFILE<2:0>) to select the desired profile. A
change in the state of the profile pins with the next rising edge
on SYNC_CLK updates the DDS with the parameters specified
by the selected profile.
The various modulation modes generally operate on only one of
the DDS signal control parameters (two in the case of the polar
modulation format). The unmodulated DDS signal control
parameters are stored in their appropriate programming
registers and automatically route to the DDS based on the
selected mode.
RAM_SWP_OVR
AD9910
2
SDIO
SCLK
RAM
8
AUX
DAC
8-BIT
DAC FSC
I/O_RESET
DDS
CS
DAC_RSET
OUTPUT
AMPLITUDE (A)
SHIFT
OSK
A
IOUT
IOUT
KEYING
Acos (ωt+θ)
Asin (ωt+θ)
DAC
14-BIT
PHASE (θ)
2
DRCTL
DRHOLD
DROVER
DATA
ROUTE
θ
INVERSE
SINC
FILTER
DIGITAL
RAMP
GENERATOR
FREQUENCY (ω)
AND
ω
PARTITION
CONTROL
CLOCK
3
REFCLK_OUT
PROFILE
PROGRAMMING
REGISTERS
÷2
SYSCLK
I/O_UPDATE
8
REF_CLK
REF_CLK
DAC FSC
INTERNAL CLOCK TIMING
AND CONTROL
16
2
PLL
PARALLEL
INPUT
XTAL_SEL
POWER
DOWN
CONTROL
MULTICHIP
TxENABLE
PDCLK
PARALLEL DATA
TIMING AND
CONTROL
SYNCHRONIZATION
2
2
Figure 22. Single Tone Mode
Rev. 0 | Page 16 of 60
AD9910
The selection of the specific DDS signal control parameters that
serve as the destination for the RAM samples is also programmable
through eight independent RAM profile registers. Select a par-
ticular profile using the three external profile pins (PROFILE<2:0>).
A change in the state of the profile pins with the next rising
edge on SYNC_CLK activates the selected RAM profile.
RAM MODULATION MODE
The RAM modulation mode (see Figure 23) is activated via the
RAM enable bit and assertion of the I/O_UPDATE pin (or a
profile change). In this mode, the modulated DDS signal
control parameters are supplied directly from RAM.
The RAM consists of 32-bit words and is 1024 words deep.
Coupled with a sophisticated internal state machine, the RAM
provides a very flexible method for generating arbitrary, time
dependent waveforms. A programmable timer controls the rate
at which words are extracted from the RAM for delivery to the
DDS. Thus, the programmable timer establishes a sample rate at
which 32-bit samples are supplied to the DDS.
In RAM modulation mode, the ability to generate a time
dependent amplitude, phase, or frequency signal enables
modulation of any one of the parameters controlling the DDS
carrier signal. Furthermore, a polar modulation format is
available that partitions each RAM sample into a magnitude
and phase component; 16 bits allocated to phase and 14 bits
allocated to magnitude.
RAM_SWP_OVR
AD9910
2
SDIO
SCLK
RAM
AUX
DAC
8-BIT
8
DAC FSC
I/O_RESET
DDS
CS
DAC_RSET
OUTPUT
AMPLITUDE (A)
SHIFT
OSK
A
IOUT
IOUT
KEYING
Acos (ωt+θ)
Asin (ωt+θ)
DAC
14-BIT
PHASE (θ)
2
DRCTL
DATA
ROUTE
θ
INVERSE
SINC
FILTER
DIGITAL
RAMP
GENERATOR
FREQUENCY (ω)
DRHOLD
AND
ω
PARTITION
CONTROL
DROVER
CLOCK
3
REFCLK_OUT
PROFILE
PROGRAMMING
REGISTERS
÷2
SYSCLK
I/O_UPDATE
8
REF_CLK
REF_CLK
DAC FSC
INTERNAL CLOCK TIMING
AND CONTROL
16
2
PLL
PARALLEL
INPUT
XTAL_SEL
POWER
DOWN
CONTROL
MULTICHIP
TxENABLE
PDCLK
PARALLEL DATA
TIMING AND
CONTROL
SYNCHRONIZATION
2
2
Figure 23. RAM Modulation Mode
Rev. 0 | Page 17 of 60
AD9910
The ramp is digitally generated with 32-bit output resolution.
The 32-bit output of the DRG can be programmed to represent
frequency, phase, or amplitude. When programmed to represent
frequency, all 32 bits are used. However, when programmed to
represent phase or amplitude, only the 16 MSBs or 14 MSBs,
respectively, are used.
DIGITAL RAMP MODULATION MODE
In digital ramp modulation mode (Figure 24), the modulated
DDS signal control parameter is supplied directly from the
digital ramp generator (DRG). The ramp generation parameters
are controlled through the serial I/O port.
The ramp generation parameters allow the user to control both
the rising and falling slopes of the ramp. The upper and lower
boundaries of the ramp, the step size and step rate of the rising
portion of the ramp, and the step size and step rate of the falling
portion of the ramp are all programmable.
The ramp direction (rising or falling) is externally controlled by
the DRCTL pin. An additional pin (DRHOLD) allows the user
to suspend the ramp generator in its present state.
RAM_SWP_OVR
AD9910
2
SDIO
SCLK
RAM
8
AUX
DAC
8-BIT
DAC FSC
I/O_RESET
DDS
CS
DAC_RSET
OUTPUT
AMPLITUDE (A)
PHASE (θ)
FREQUENCY (ω)
SHIFT
OSK
A
KEYING
IOUT
IOUT
Acos (ωt+θ)
Asin (ωt+θ)
DAC
14-BIT
2
DRCTL
DATA
ROUTE
θ
INVERSE
SINC
FILTER
DIGITAL
RAMP
GENERATOR
DRHOLD
AND
ω
PARTITION
CONTROL
DROVER
CLOCK
3
REFCLK_OUT
PROFILE
PROGRAMMING
REGISTERS
÷2
SYSCLK
I/O_UPDATE
8
REF_CLK
REF_CLK
DAC FSC
INTERNAL CLOCK TIMING
AND CONTROL
16
2
PLL
PARALLEL
INPUT
XTAL_SEL
POWER
DOWN
CONTROL
MULTICHIP
TxENABLE
PDCLK
PARALLEL DATA
TIMING AND
CONTROL
SYNCHRONIZATION
2
2
Figure 24. Digital Ramp Modulation Mode
Rev. 0 | Page 18 of 60
AD9910
the user to apply a weighting factor to the 16-bit data-word. In
the default state (0), the 16-bit data-word and the 32-bit word in
the FTW register are LSB aligned. Each increment in the value
of the FM gain word shifts the 16-bit data-word to the left
relative to the 32-bit word in the FTW register, increasing the
influence of the 16-bit data-word on the frequency defined by
the FTW register by a factor of two. The FM gain word effectively
controls the frequency range spanned by the data-word.
PARALLEL DATA PORT MODULATION MODE
In parallel data port modulation mode (Figure 25), the
modulated DDS signal control parameter(s) are supplied
directly from the 18-bit parallel data port.
The data port is partitioned into two sections. The 16 MSBs
make up a 16-bit data-word (D<15:0> pins) and the 2 LSBs
make up a 2-bit destination word (F<1:0> pins). The destination
word defines how the 16-bit data-word is applied to the DDS
signal control parameters. Table 4 defines the relationship
between the destination bits, the partitioning of the 16-bit
data-word, and the destination of the data (in terms of the
DDS signal control parameters). Formatting of the 16-bit
data-word is unsigned binary, regardless of the destination.
Parallel Data Clock (PDCLK)
The AD9910 generates a clock signal on the PDCLK pin that
runs at ¼ of the DAC sample rate (the sample rate of the par-
allel data port). PDCLK serves as a data clock for the parallel
port. By default, each rising edge of PDCLK is used to latch the
18 bits of user-supplied data into the data port. The edge polarity
can be changed through the PDCLK invert bit. Furthermore,
the PDCLK output signal can be switched off using the PDCLK
enable bit. However, even though the output signal is switched
off, it continues to operate internally using the internal PDCLK
timing to capture the data at the parallel port. Note that PDCLK
is Logic 0 when disabled.
When the destination bits indicate that the data-word is
destined as a DDS frequency parameter, the 16-bit data-word
serves as an offset to the 32-bit frequency tuning word in the
FTW register. This means that the 16-bit data-word must
somehow be properly aligned with the 32-bit frequency
parameter. This is accomplished by means of the 4-bit FM gain
word in the programming registers. The FM gain word allows
RAM_SWP_OVR
AD9910
2
SDIO
SCLK
RAM
AUX
DAC
8-BIT
8
DAC FSC
I/O_RESET
DDS
CS
DAC_RSET
OUTPUT
AMPLITUDE (A)
SHIFT
OSK
A
IOUT
IOUT
KEYING
Acos (ωt+θ)
Asin (ωt+θ)
DAC
14-BIT
PHASE (θ)
2
DRCTL
DATA
ROUTE
θ
INVERSE
SINC
FILTER
DIGITAL
RAMP
GENERATOR
FREQUENCY (ω)
DRHOLD
AND
ω
PARTITION
CONTROL
DROVER
CLOCK
3
REFCLK_OUT
PROFILE
PROGRAMMING
REGISTERS
÷2
SYSCLK
I/O_UPDATE
8
REF_CLK
REF_CLK
DAC FSC
INTERNAL CLOCK TIMING
AND CONTROL
16
2
PLL
PARALLEL
INPUT
XTAL_SEL
POWER
DOWN
CONTROL
MULTICHIP
TxENABLE
PDCLK
PARALLEL DATA
TIMING AND
CONTROL
SYNCHRONIZATION
2
2
Figure 25. Parallel Data Port Modulation Mode
Rev. 0 | Page 19 of 60
AD9910
Table 4. Parallel Port Destination Bits
F<1:0> D<15:0> Parameter(s)
Comments
00
D<15:2> 14-bit amplitude
parameter (unsigned
integer)
Amplitude scales from 0 to 1 − 2−14. D<1:0> are not used.
Phase offset ranges from 0 to 2π(1 − 2−16) radians.
01
10
D<15:0> 16-bit phase parameter
(unsigned integer)
D<15:0> 32-bit frequency
parameter (unsigned
integer)
The alignment of the 16-bit data-word with the 32-bit frequency parameter is controlled
by a 4-bit FM gain word in the programming registers.
11
D<15:8> 8-bit amplitude
(unsigned integer)
The MSB of the data-word amplitude aligns with the MSB of the DDS 14-bit amplitude
parameter. The 6 LSBs of the DDS amplitude parameter are assigned from Bits<5:0> of the
ASF register. The resulting 14-bit word scales the amplitude from 0 to 1 − 2−14
.
D<7:0>
8-bit phase (unsigned
integer)
The MSB of the data-word phase aligns with the MSB of the 16-bit phase parameter of
the DDS. The 8 LSBs of the DDS phase parameter are assigned from Bits<7:0> of the POW
register. The resulting 16-bit word offsets the phase from 0 to 2π(1 − 2−16) radians.
Transmit Enable (TxENABLE)
Alternatively, instead of operating the TxENABLE pin as a gate,
it can be driven with a clock signal operating at the parallel port
data rate. When driven by a clock signal, the transition from the
false to true state must meet the required setup and hold time
on each cycle to ensure proper operation. The TxENABLE and
PDCLK timing is shown in Figure 26.
The AD9910 also accepts a user generated signal applied to the
TxENABLE pin that acts as a gate for the user supplied data. By
default, TxENABLE is considered true for Logic 1 and false for
Logic 0. However, the logical behavior of this pin can be reversed
using the TxENABLE invert bit. When TxENABLE is true, the
device latches data into the device on the expected edge of PDCLK
(based on the PDCLK invert bit). When TxENABLE is false,
even though the PDCLK may continue to operate, the device
ignores the data supplied to the port. Furthermore, when the
TxENABLE pin is held false, then the device internally clears
the 18-bit data-words, or it retains the last value present on the
data port prior to TxENABLE switching to the false state (based
on the setting of the data assembler hold last value bit).
TRUE
TxENABLE
(BURST)
FALSE
TxENABLE
(CLOCK)
tDS
tDH
PDCLK
tDH
tDS
PARALLEL
DATA PORT
WORD
1
WORD
WORD
WORD WORD
N–4
WORD
N
2
3
4
Figure 26. PDCLK and TxENABLE Timing Diagram
Rev. 0 | Page 20 of 60
AD9910
drive the same DDS signal control parameter. To avoid con-
MODE PRIORITY
tention, the AD9910 has a built-in priority system. Table 5
summarizes the priority for each of the DDS signal control
parameters. The rows of the table list data sources for a particular
DDS signal control parameter in descending order of precedence.
For example, if both the RAM and the parallel port are enabled
and both are programmed for frequency as the destination,
then the DDS frequency parameter is driven by the RAM and
not the parallel data port.
The three different modulation modes generate frequency,
phase, and/or amplitude data destined for the DDS signal
control parameters. In addition, the OSK function generates
amplitude data destined for the DDS. Each of these functions is
independently invoked using the appropriate control bit via the
serial I/O port.
The ability to independently activate each of these functions
makes it possible to have multiple data sources attempting to
Table 5. Data Source Priority
DDS Signal Control Parameters
Phase
Frequency
Conditions
Amplitude
Conditions
Priority
Data Source
Data Source
Conditions
Data Source
Highest
Priority
RAM
RAM enabled and
data destination is
frequency
RAM
RAM enabled and
data destination is
phase or polar
OSK generator
OSK enabled (auto
mode)
DRG
DRG enabled and
data destination is
frequency
Parallel data port
enabled and data
destination is
frequency
DRG
DRG enabled and
data destination is
phase
Parallel data port
enabled and data
destination is
phase
ASF register
RAM
OSK enabled
(manual mode)
Parallel data
port + FTW
register
Parallel data port
RAM enabled and
data destination is
amplitude or polar
FTW register
RAM enabled and
data destination is
phase, amplitude
or polar
Parallel data port
concatenated with
the POW register
LSBs
Parallel data port
enabled and data
destination is polar
DRG
DRG enabled and
data destination is
amplitude
FTW in active
single tone
profile register
DRG enabled and
data destination is
phase or amplitude
POW register
RAM enabled and
destination is
frequency or
amplitude
Parallel data port
Parallel data port
enabled and data
destination is
amplitude
FTW in active
single tone
profile register
Parallel data port
enabled and data
destination is
phase, amplitude
or polar
POW in active
single tone profile
register
DRG enabled and
data destination is
frequency or
Parallel data port
concatenated with
the ASF register
LSBs
Parallel data port
enabled and data
destination is
polar
amplitude
FTW in active
single tone
profile register
None
POW in active
single tone profile
register
Parallel data port
enabled and data
destination is
frequency or
ASF in active single Enable amplitude
tone profile
scale from Single
Tone Profiles Bit
CFR2<24> set
register
amplitude
Lowest
Priority
POW in active
single tone profile
register
None
No amplitude
scaling
None
Rev. 0 | Page 21 of 60
AD9910
FUNCTIONAL BLOCK DETAIL
POW
⎛
⎜
⎝
⎞
⎟
⎠
DDS CORE
2π
216
The direct digital synthesizer (DDS) block generates a reference
signal (sine or cosine based on the selected DDS sine output
bit). The parameters of the reference signal (frequency, phase,
and amplitude) are applied to the DDS at its frequency, phase
offset, and amplitude control inputs, as shown in Figure 27.
Δθ =
POW
⎛
⎜
⎝
⎞
⎟
⎠
360
216
where the upper quantity is for the phase offset expressed as
radian units and the lower quantity as degrees. To find the
POW value necessary to develop an arbitrary Δθ, solve the
above equation for POW and round the result (in a manner
similar to that described for finding an arbitrary FTW in the
previous paragraphs).
DDS SIGNAL CONTROL PARAMETERS
14
AMPLITUDE
CONTROL
PHASE
16
OFFSET
CONTROL
MSB ALIGNED
32-BIT
The relative amplitude of the DDS signal can be digitally scaled
(relative to full scale) by means of a 14-bit amplitude scale
factor (ASF). The amplitude scale value is applied at the output
of the angle-to-amplitude conversion block internal to the DDS
core. The amplitude scale is given by
14
ACCUMULATOR
32
16
ANGLE
TO
19
(MSBs)
14
14
TO DAC
32
32
32 19
AMPLITUDE
CONVERSION
(SINE OR
COSINE)
FREQUENCY
CONTROL
D Q
R
DDS_CLK
ACCUMULATOR
RESET
ASF
214
Figure 27. DDS Block Diagram
Amplitude Scale =
(3)
ASF
⎛
⎜
⎝
⎞
⎟
⎠
20log
214
The output frequency (fOUT) of the AD9910 is controlled by the
frequency tuning word (FTW) at the frequency control input to
the DDS. The relationship between fOUT, FTW, and fSYSCLK is
given by
where the upper quantity is amplitude expressed as a fraction of
full scale and the lower quantity is expressed in decibels relative
to full scale. To find the ASF value necessary for a particular
scale factor, solve Equation 3 for ASF and round the result (in a
manner similar to that described for finding an arbitrary FTW
in the previous paragraphs).
FTW
⎛
⎜
⎝
⎞
⎟
⎠
fOUT
=
f
(1)
SYSCLK
232
where FTW is a 32-bit integer ranging in value from 0 to
2,147,483,647 (231 − 1), which represents the lower half of the
When the AD9910 is programmed to modulate any of the DDS
signal control parameters, the maximum modulation sample
rate is ¼ fSYSCLK. This means that the modulation signal exhibits
images about multiples of ¼ fSYSCLK. The impact of these images
must be considered when using the device as a modulator.
full 32-bit range. This range constitutes frequencies from dc to
Nyquist (that is, ½ fSYSCLK).
The FTW required to generate a desired value of fOUT is found
by solving Equation 1 for FTW as given in Equation 2
14-BIT DAC OUTPUT
⎛
⎜
⎝
⎞
⎟
⎛
⎜
⎜
⎝
⎞
⎟
⎟
⎠
fOUT
fSYSCLK
32
⎜
FTW = round 2
(2)
⎟
⎠
The AD9910 incorporates an integrated 14-bit, current output
DAC. The output current is delivered as a balanced signal using
two outputs. The use of balanced outputs reduces the potential
amount of common-mode noise present at the DAC output,
offering the advantage of an increased signal-to-noise ratio. An
external resistor (RSET) connected between the DAC_RSET pin
and AGND establishes the reference current. The full-scale
output current of the DAC (IOUT) is produced as a scaled version
of the reference current (see the Auxiliary DAC section). The
recommended value of RSET is 10 kΩ.
where the round(x) function rounds the argument (the value of
x) to the nearest integer. This is required because the FTW is
constrained to be an integer value. For example, for fOUT
41 MHz and fSYSCLK = 122.88 MHz, then FTW = 1,433,053,867
(0x556AAAAB).
=
Programming an FTW greater than 231 produces an aliased
image that appears at a frequency given by
FTW
⎛
⎝
⎞
⎟
⎠
(for FTW ≥ 231)
Attention should be paid to the load termination to keep the output
voltage within the specified compliance range; voltages developed
beyond this range cause excessive distortion and can damage the
DAC output circuitry.
fOUT = 1−
f
⎜
SYSCLK
232
The relative phase of the DDS signal can be digitally controlled
by means of a 16-bit phase offset word (POW). The phase offset
is applied prior to the angle-to-amplitude conversion block
internal to the DDS core. The relative phase offset (Δθ) is given by
Rev. 0 | Page 22 of 60
AD9910
1
0
Auxiliary DAC
An 8-bit auxiliary DAC controls the full-scale output current of
the main DAC (IOUT). An 8-bit code word stored in the
appropriate register map location sets IOUT according to the
following equation:
SINC
–1
–2
–3
–4
86.4
RSET
CODE
96
⎛
⎜
⎝
⎞
⎟
⎠
IOUT
=
1+
INVERSE
SINC
where RSET is the value of the RSET resistor (in ohms) and CODE
is the 8-bit value supplied to the auxiliary DAC (default is 127).
For example, with RSET = 10,000 and CODE = 127, then IOUT
20.07 mA.
=
0
0.1
0.2
0.3
0.4
0.5
FREQUENCY RELATIVE TO DAC SAMPLE RATE
INVERSE SINC FILTER
Figure 28. Sinc and Inverse Sinc Responses
The sampled carrier data stream is the input to the digital-to-
analog converter (DAC) integrated onto the AD9910. The
DAC output spectrum is shaped by the characteristic sin(x)/x
(or sinc) envelope, due to the intrinsic zero-order hold effect
associated with DAC generated signals. The sinc enveloped can
be compensated for because its shape is well known. This
envelope restoration function is provided by the inverse sinc
filter preceding the DAC. The inverse sinc filter is implemented as
a digital FIR filter. It has a response characteristic that very
nearly matches the inverse of the sinc envelope. The response of
the inverse sinc filter is shown in Figure 28 (with the sinc
envelope for comparison).
–2.8
–2.9
–3.0
–3.1
COMPENSATED RESPONSE
The inverse sinc filter is enabled using a bit in the register map.
The filter tap coefficients are given in Table 6. The filter
operates by predistorting the data prior to its arrival at the DAC
in such a way as to compensate for the sinc envelope that
otherwise distorts the spectrum.
0
0.1
0.2
0.3
0.4
0.5
FREQUENCY RELATIVE TO DAC SAMPLE RATE
Figure 29. DAC Response with Inverse Sinc Compensation
CLOCK INPUT (REF_CLK)
REF_CLK Overview
When the inverse sinc filter is enabled, it introduces an ~3.0 dB
insertion loss. The inverse sinc compensation is effective for
output frequencies up to approximately 40ꢀ of
the DAC sample rate.
The AD9910 supports a number of options for producing the
internal SYSCLK signal (that is, the DAC sample clock) via the
REF_CLK input pins. The REF_CLK input can be driven
directly from a differential or single-ended source, or it can
accept a crystal connected across the two input pins. There is
also an internal phase-locked loop (PLL) multiplier that can be
independently enabled. A block diagram of the REF_CLK
functionality is shown in Figure 30. The various input configu-
rations are controlled by means of the XTAL_SEL pin and
control bits in the CFR3 register. Figure 30 also shows how the
CFR3 control bits are associated with specific functional blocks.
Table 6. Inverse Sinc Filter Tap Coefficients
Tap No.
Tap Value
1, 7
−35
2, 6
+134
3, 5
−562
4
+6729
In Figure 28, the sinc envelope introduces a frequency
dependent attenuation that can be as much as 4 dB at the
Nyquist frequency (½ of the DAC sample rate). Without the
inverse sinc filter, the DAC output suffers from the frequency
dependent droop of the sinc envelope. The inverse sinc filter
effectively flattens the droop to within 0.05 dB as shown in
Figure 29, showing the corrected sinc response with the inverse
sinc filter enabled.
Rev. 0 | Page 23 of 60
AD9910
XTAL_SEL
95
PLL_LOOP_FILTER
2
Direct Driven REF_CLK
DRV0
When driving the REF_CLK inputs directly from a signal
source either single-ended or differential signals can be used.
With a differential signal source, the REF_CLK pins are driven
with complementary signals and ac-coupled with 0.1 μF
capacitors. With a single-ended signal source, either a single-
ended to differential conversion can be employed or the
REF_CLK input can be driven single-ended directly. In either
case, 0.1 μF capacitors are used to ac couple both REF_CLK
pins to avoid disturbing the internal dc bias voltage of ~1.35 V.
See Figure 32 for more details.
CFR3
<31:30>
2
PLL ENABLE
94
REFCLK_OUT
CFR3
<8>
REFCLK
INPUT
SELECT
LOGIC
ENABLE PLL_LOOP_FILTER
1
0
1
0
IN
OUT
PLL
CHARGE
PUMP DIVIDE
VCO
SYSCLK
90
91
REF_CLK
REF_CLK
SELECT
3
2
7
I
N
CFR3
<7:1>
VCO
CFR3
<26:24>
CP
The REF_CLK input resistance is ~2.5 kΩ differential (~1.2 kΩ
single-ended). Most signal sources have relatively low output
impedances. The REF_CLK input resistance is relatively high,
therefore, its effect on the termination impedance is negligible
and can usually be chosen to be the same as the output
impedance of the signal source. The bottom two examples in
Figure 32 assume a signal source with a 50 Ω output impedance.
CFR3
<21:19>
1
0
÷2
INPUT DIVIDER
RESETB
INPUT DIVIDER BYPASS
CFR3<15>
CFR3<14>
Figure 30. REF_CLK Block Diagram
0.1µF
The PLL enable bit is used to choose between the PLL path or
the direct input path. When the direct input path is selected, the
REF_CLK pins must be driven by an external signal source
(single-ended or differential). Input frequencies up to 2 GHz are
supported. For input frequencies greater than 1 GHz, the input
divider must be enabled for proper operation of the device.
90 REF_CLK
PECL,
LVPECL,
DIFFERENTIAL SOURCE,
DIFFERENTIAL INPUT.
OR
TERMINATION
0.1µF
LVDS
DRIVER
91
REF_CLK
0.1µF
BALUN
When the PLL is enabled, a buffered clock signal is available at
the REFCLK_OUT pin. This clock signal is the same frequency
as the REF_CLK input. This is especially useful when a crystal
is connected, because it gives the user a replica of the crystal
clock for driving other external devices. The REFCLK_OUT
buffer is controlled by two bits as listed in Table 7.
(1:1)
90
91
REF_CLK
REF_CLK
SINGLE-ENDED SOURCE,
DIFFERENTIAL INPUT.
50Ω
0.1µF
0.1µF
0.1µF
90
91
REF_CLK
REF_CLK
Table 7. REFCLK_OUT Buffer Control
SINGLE-ENDED SOURCE,
SINGLE-ENDED INPUT.
50Ω
CFR3<31:30>
REFCLK_OUT Buffer
00
01
10
11
Disabled (tristate)
Low output current
Medium output current
High output current
Figure 32. Direct Connection Diagram
Phase-Locked Loop (PLL) Multiplier
Crystal Driven REF_CLK
An internal phase-locked loop (PLL) provides users of the
AD9910 the option to use a reference clock frequency that is
significantly lower than the system clock frequency. The PLL
supports a wide range of programmable frequency multiplica-
tion factors (12× to 127×) as well as a programmable charge
pump current and external loop filter components (connected
via the PLL_LOOP_FILTER pin). These features add an extra
layer of flexibility to the PLL, allowing optimization of phase
noise performance and flexibility in frequency plan develop-
ment. The PLL is also equipped with a PLL_LOCK pin.
When using a crystal at the REF_CLK input, the resonant
frequency should be approximately 25 MHz. Figure 31 shows
the recommended circuit configuration.
90
91
REF_CLK
REF_CLK
XTAL
39pF
39pF
The PLL output frequency range (fSYSCLK) is constrained to the
range of 420 MHz ≤ fSYSCLK ≤ 1 GHz by the internal VCO. In
addition, the user must program the VCO to one of six operating
Figure 31. Crystal Connection Diagram
Rev. 0 | Page 24 of 60
AD9910
ranges such that fSYSCLK falls within the specified range. Figure 33
and Figure 34 summarize these VCO ranges.
FLOW = 820
VCO5
VCO4
VCO3
VCO2
VCO1
VCO0
FHIGH = 1150
FLOW = 700
FHIGH = 950
Figure 33 shows the boundaries of the VCO frequency ranges
over the full range of temperature and supply voltage variation
for all devices from the available population. The implication is
that multiple devices chosen at random from the population and
operated under widely varying conditions may require different
values to be programmed into CFR3<26:24> to operate at the
same frequency. For example, Part A chosen randomly from the
population, operating in an ambient temperature of −10ꢁC with
a system clock frequency of 900 MHz may require CFR3<26:24>
to be set to 100b. Whereas Part B chosen randomly from the
population, operating in an ambient temperature of 90ꢁC with a
system clock frequency of 900 MHz may require CFR3<26:24>
to be set to 101b. If a frequency plan is chosen such that the
system clock frequency operates within one set of boundaries
(as shown in Figure 33), the required value in CFR3<26:24> is
consistent from part to part.
FLOW = 600
FHIGH = 880
FLOW = 500
FHIGH = 700
FLOW = 420
FHIGH = 590
FLOW = 370
FHIGH = 510
335
435
535
635
735
835
935 1035 1135
(MHz)
Figure 34. Typical VCO Ranges
Table 8. VCO Range Bit Settings
VCO SEL BITS (CFR3<26:24>)
VCO Range
VCO0
VCO1
VCO2
VCO3
VCO4
VCO5
PLL Bypassed
PLL Bypassed
000
001
010
011
100
101
110
111
Figure 34 shows the boundaries of the VCO frequency ranges
over the full range of temperature and supply voltage variation
for an individual device selected from the population. Figure 34
shows that the VCO frequency ranges for a single device always
overlap when operated over the full range of conditions.
In conclusion, if a user wants to retain a single default value for
CFR3<26:24>, a frequency that falls into one of the ranges
found in Figure 33 should be selected. Additionally, for any
given individual device the VCO frequency ranges overlap,
meaning that any given device exhibits no gaps in its frequency
coverage across VCO ranges over the full range of conditions.
PLL Charge Pump
The charge pump current (ICP) is programmable to provide the
user with additional flexibility to optimize the PLL performance.
Table 9 lists the bit settings vs. the nominal charge pump
current.
FLOW = 920
VCO5
Table 9. PLL Charge Pump Current
FHIGH = 1030
ICP (CFR3<21:19>)
Charge Pump Current (ICP in μA)
FLOW = 760
FHIGH = 875
VCO4
VCO3
VCO2
VCO1
VCO0
000
001
010
011
100
101
110
111
212
237
262
287
312
337
363
387
FLOW = 650
FHIGH = 790
FLOW = 530
FHIGH = 615
FLOW = 455
FHIGH = 530
FLOW = 400
FHIGH = 460
External PLL Loop Filter Components
395
495
595
695
795
895
995
The PLL_LOOP_FILTER pin provides a connection interface to
attach the external loop filter components. The ability to use
custom loop filter components gives the user more flexibility to
optimize the PLL performance. The PLL and external loop filter
components are shown in Figure 35.
(MHz)
Figure 33. VCO Ranges Including Atypical Wafer Process Skew
Rev. 0 | Page 25 of 60
AD9910
AVDD
amplitude data generated by the OSK block has priority over
any other functional block that is programmed to deliver
amplitude data to the DDS. Hence, the OSK data source, when
enabled, overrides all other amplitude data sources.
C1
R1
C2
OSK
60
PLL_LOOP_FILTER
2
OSK ENABLE
AUTO OSK ENABLE
REFCLK PLL
PFD
PLL IN
MANUAL OSK EXTERNAL
LOAD ARR AT I/O_UPDATE
CP
VCO
PLL OUT
TO DDS
14
÷N
OSK
AMPLITUDE
CONTROL
PARAMETER
16
14
2
AMPLITUDE RAMP RATE
(ASF<31:16>)
CONTROLLER
Figure 35. REFCLK PLL External Loop Filter
AMPLITUDE SCALE FACTOR
(ASF<15:2>)
In the prevailing literature, this configuration yields a third-
order, Type II PLL. To calculate the loop filter component
values, begin with the feedback divider value (N), the gain of
the phase detector (KD), and the gain of the VCO (KV) based on
the programmed VCO SEL bit settings (see Table 1 for KV). The
loop filter component values depend on the desired open-loop
bandwidth (fOL) and phase margin (φ), as follows:
AMPLITUDE STEP SIZE
(ASF<1:0>)
DDS CLOCK
Figure 36. OSK Block Diagram
The operation of the OSK function is governed by four control
register bits, the external OSK pin, and the entire 32 bits of the
ASF register. The primary control for the OSK block is the OSK
enable bit. When the OSK function is disabled, the OSK input
controls are ignored and the internal clocks shut down.
⎛
⎜
⎜
⎝
⎞
⎟
⎟
⎠
πNfOL
KDKV
1
R1 =
C1 =
1+
(4)
(5)
sin
( )
φ
KDKV tan
φ
2
2N
(
πfOL
)
When the OSK function is enabled, automatic and manual
operation is selected using the select auto OSK bit.
⎛
⎞
⎟
⎟
⎠
KDKV
1− sin
φ
⎜
⎜
⎝
C2 =
(6)
2
N
(
2πfOL
)
cos
(φ)
Manual OSK
where:
In manual mode, output amplitude is varied by successive write
operations to the amplitude scale factor portion of the ASF
register. The rate at which amplitude changes can be applied to
the output signal is limited by the speed of the serial I/O port.
In manual mode, the OSK pin functionality depends on the
state of the manual OSK external bit. When the OSK pin is
Logic 0, the output amplitude is forced to zero; otherwise, the
output amplitude is set by the amplitude scale factor value.
KD is equal to the programmed value of ICP.
KV is taken from Table 1.
Ensure that proper units are used for the variables in Equation 4
through Equation 6. ICP must be in amps, not ꢂA as appears in
Table 9; KV must be in Hz/V, not MHz/V as listed in Table 1; the
loop bandwidth (fOL) must be in Hz; the phase margin (φ) must
be in radians.
Automatic OSK
For example, suppose the PLL is programmed such that
I
CP = 287 ꢂA, KV = 625 MHz/V, and N = 25. If the desired loop
In automatic mode, the OSK function automatically generates a
linear amplitude vs. time profile (or amplitude ramp). The
amplitude ramp is controlled via three parameters: the maximum
amplitude scale factor, the amplitude step size, and the time interval
between steps. The amplitude ramp parameters reside in the 32-bit
ASF register and are programmed via the serial I/O port. The time
interval between amplitude steps is set via the 16-bit amplitude
ramp rate portion of the ASF register (Bits<31:16>). The maximum
amplitude scale factor is set via the 14-bit amplitude scale factor in
the ASF register (Bits<15:2>). The amplitude step size is set via the
2-bit amplitude step size portion of the ASF register (Bits<1:0>).
Additionally, the direction of the ramp (positive or negative slope)
is controlled by the external OSK pin.
bandwidth and phase margin are 50 kHz and 45ꢁ, respectively,
then the loop filter component values are R1 = 52.85 Ω, C1 =
145.4 nF, and C2 = 30.11 nF.
PLL LOCK INDICATION
When the PLL is in use, the PLL_LOCK pin provides an active
high indication that the PLL has locked to the REFCLK input
signal. When the PLL is bypassed the PLL_LOCK pin defaults
to Logic 0.
OUTPUT SHIFT KEYING (OSK)
The OSK function (Figure 36) allows the user to control the
output signal amplitude of the DDS. Both a manual and an
automatic mode are available under program control. The
Rev. 0 | Page 26 of 60
AD9910
The step interval is controlled by a 16-bit programmable timer
that is clocked at a rate of ¼ fSYSCLK. The period of the timer sets
the time interval between amplitude steps. The step time interval
(Δt) is given by
DIGITAL RAMP GENERATOR (DRG)
DRG Overview
To sweep phase, frequency, or amplitude from a defined start
point to a defined endpoint, a completely digital, digital ramp
generator is included in the AD9910. The DRG makes use of
nine control register bits, three external pins, two 64-bit
registers, and one 32-bit register (see Figure 37).
4M
Δt =
fSYSCLK
where M is the 16-bit number stored in the amplitude ramp rate
(ARR) portion of the ASF register. For example, if fSYSCLK
=
750 MHz and M = 23218 (0x5AB2), then Δt ≈ 123.8293 ꢂs.
62
61
63
The output of the OSK function is a 14-bit unsigned data bus
that controls the amplitude parameter of the DDS (as long as
the OSK enable bit is set). When the OSK pin is set, the OSK
output value starts at 0 (zero) and increments by the pro-
grammed amplitude step size until it reaches the programmed
maximum amplitude value. When the OSK pin is cleared, the
OSK output starts at its present value and decrements by the
programmed amplitude step size until it reaches 0 (zero).
DIGITAL RAMP ENABLE
2
2
DIGITAL RAMP DESTINATION
DIGITAL RAMP NO-DWELL
DROVER PIN ACTIVE
LOAD LRR AT I/O_UPDATE
TO DDS
DIGITAL
RAMP
GENERATOR
CLEAR DIGITAL
RAMP ACCUMULATOR
AUTOCLEAR DIGITAL
RAMP ACCUMULATOR
32
SIGNAL
CONTROL
PARAMETER
The OSK output does not necessarily attain the maximum
amplitude value if the OSK pin is switched to Logic 0 before the
maximum value is reached. Nor does the OSK output necessarily
reach a value of zero if the OSK pin is switched to Logic 1
before the zero value is reached.
64
64
32
DIGITAL RAMP LIMIT REGISTER
DIGITAL RAMP STEP REGISTER
DIGITAL RAMP RATE REGISTER
The OSK output is initialized to 0 (zero) at power-up and reset
whenever the OSK enable bit or the select auto OSK bit is cleared.
DDS CLOCK
Figure 37. Digital Ramp Block Diagram
The amplitude step size of the OSK output is set by the amplitude
step size bits in the ASF register according to Table 10. The step
size refers to the LSB weight of the 14-bit OSK output. Regardless
of the programmed step size, the OSK output does not exceed
the maximum amplitude value programmed into the ASF
register.
The primary control for the DRG is the digital ramp enable bit.
When disabled, the other DRG input controls are ignored and the
internal clocks are shut down to conserve power.
The output of the DRG is a 32-bit unsigned data bus that can be
routed to any one of the three DDS signal control parameters, as
controlled by the two digital ramp destination bits in Control
Function Register 2 according to Table 11. The 32-bit output
bus is MSB-aligned with the 32-bit frequency parameter, the
16-bit phase parameter, or the 14-bit amplitude parameter, as
defined by the destination bits. When the destination is phase
or amplitude, the unused LSBs are ignored.
Table 10. OSK Amplitude Step Size
ASF<1:0>
Amplitude Step Size
00
01
10
11
1
2
4
8
As mentioned previously, a 16-bit programmable timer controls the
step interval. Normally, this timer is loaded with the programmed
timing value whenever the timer expires, initiating a new timing
cycle. However, there are three events that can cause reloading of
the timer to have its timing value reloaded prior to the timer
expiring. One such event is when the select auto OSK bit is
transitioned from cleared to set followed by an I/O update. A
second such event is a change of state in the OSK pin. The third is
dependent on the status of the Load ARR @ I/O Update bit. If this
bit is cleared, then no action occurs, otherwise, when the
I/O_UPDATE pin is asserted (or a profile change occurs), the timer
is reset to its initial starting point.
Table 11. Digital Ramp Destination
Digital Ramp
Destination Bits
CFR2<21:20>
DDS signal
Control
Parameter
Bits Assigned to
DDS Parameter
00
01
1x1
Frequency
Phase
Amplitude
31:0
31:16
31:18
1 x = don’t care.
The ramp characteristics of the DRG are fully programmable. This
includes the upper and lower ramp limits, and independent control
of the step size and step rate for both the positive and negative slope
characteristics of the ramp. A detailed block diagram of the DRG
appears in Figure 38.
Rev. 0 | Page 27 of 60
AD9910
The direction of the ramping function is controlled by the
DRCTL pin. A Logic 0 on this pin causes the DRG to ramp
with a negative slope, whereas a Logic 1 causes the DRG to
ramp with a positive slope.
The DRG also supports a hold feature controlled via the DRHOLD
pin. When this pin is Logic 1, the DRG is stalled at its last state,
otherwise, the DRG operates normally.
The DDS signal control parameters that are not the destination of
the DRG are taken from the active profile.
DIGITAL RAMP ACCUMULATOR
32
32
0
1
DECREMENT STEP SIZE
INCREMENT STEP SIZE
32
32
TO DDS
32
32
SIGNAL
D
Q
LIMIT CONTROL
32
CONTROL
PARAMETER
62
DRCTL
32
R
UPPER
LIMIT
LOWER
LIMIT
16
16
0
1
NEGATIVE SLOPE RATE
POSITIVE SLOPE RATE
16
2
NO-DWELL
CONTROL
NO DWELL
ACCUMULATOR
RESET
CONTROL
LOGIC
CLEAR DIGITAL RAMP ACCUMULATOR
AUTOCLEAR DIGITAL RAMP ACC
PRESET
LOAD
.
LOAD
CONTROL
LOGIC
LOAD LRR AT I/O_UPDATE
Q
DIGITAL
RAMP
TIMER
63
DRHOLD
DDS CLOCK
Figure 38. Digital Ramp Generator Detail
Rev. 0 | Page 28 of 60
AD9910
As described previously, the step interval is controlled by a 16-bit
programmable timer. There are three events that can cause this
timer to be reloaded prior to its expiration. One event is when the
digital ramp enable bit transitions from cleared to set followed by
an I/O update. A second event is a change of state in the DRCTL
pin. The third event is enabled using the Load LRR @ I/O Update
bit (see details in the Register Map and Bit Descriptions section).
DRG Slope Control
The heart of the DRG is a 32-bit accumulator clocked by a
programmable timer. The time base for the timer is the DDS
clock, which operates at ¼ fSYSCLK. The timer establishes
the interval between successive updates of the accumulator.
The positive (+Δt) and negative (−Δt) slope step intervals are
independently programmable as given by
DRG Limit Control
4P
+ Δt =
The ramp accumulator is followed by limit control logic that
enforces an upper and lower boundary on the output of the ramp
generator. Under no circumstances does the output of the DRG
exceed the programmed limit values while the DRG is enabled. The
limits are set through the 64-bit digital ramp limit register. Note
that the upper limit value must be greater than the lower limit value
to ensure normal operation.
fSYSCLK
4N
−Δt =
fSYSCLK
where P and N are the two 16-bit values stored in the 32-bit digital
ramp rate register and control the step interval. N defines the step
interval of the negative slope portion of the ramp. P defines the step
interval of the positive slope portion of the ramp. The step size of
the positive and negative slope portions of the ramp are controlled
by the 64-bit digital ramp step size register.
DRG Accumulator Clear
The ramp accumulator can be cleared (that is, reset to 0) under
program control. When the ramp accumulator is cleared, it forces
the DRG output to the lower limit programmed into the digital
ramp limit register.
The negative step size is programmed as a magnitude value (that is,
an unsigned integer). The relationship between the step size
(positive or negative) values and real units of frequency, phase,
or amplitude depend on the digital ramp destination bits. The
actual frequency, phase, or amplitude step size can be calculated
using the following equations with M representing either N or P
(for −Δt and +Δt, respectively):
With the limit control block imbedded in the feedback path of the
accumulator, resetting the accumulator is equivalent to presetting it
to the lower limit value.
Normal Ramp Generation
Normal ramp generation implies that both no-dwell bits are
cleared (see the No-Dwell Ramp Generation section for details).
In Figure 39, a sample ramp waveform is depicted with the
required control signals. The top trace is the DRG output. The
next trace down is the status of the DROVER output pin
(assuming that the DROVER pin active bit is set). The
remaining traces are control bits and control pins. The pertinent
ramp parameters are also identified (upper and lower limits
plus step size and Δt for the positive and negative slopes). Along
the bottom, circled numbers identify specific events. These
events are referred to by number (Event 1 and so on) in the
following paragraphs.
M
⎛
⎜
⎝
⎞
⎟
⎠
FrequencyStep =
f
SYSCLK
232
πM
⎛
⎜
⎝
⎞
PhaseStep =
PhaseStep =
(radians)
(degrees)
⎟
215
⎠
45M
⎛
⎜
⎝
⎞
⎟
⎠
213
M
⎛
⎞
⎟
⎠
AmplitudeStep =
I
⎜
FS
218
⎝
Note that the frequency units are the same as those used to
represent fSYSCLK, and the amplitude units are the same as those
used to represent IFS (the full-scale output current of the DAC).
In this particular example, the positive and negative slopes of
the ramp are different to demonstrate the flexibility of the DRG.
The parameters of both slopes can be programmed to make the
positive and negative slopes the same.
The phase and amplitude step size equations yield the average
step size. Due to quantization effects, the actual step size may
vary between the nearest destination LSB above and below the
calculated average.
Rev. 0 | Page 29 of 60
AD9910
P DDS CLOCK CYCLES
N DDS CLOCK CYCLES
NEGATIVE
1 DDS CLOCK CYCLE
STEP SIZE
POSITIVE
STEP SIZE
+Δ
t
–Δt
UPPER LIMIT
DRG OUTPUT
DROVER
LOWER LIMIT
DIGITAL RAMP ENABLE
DRCTL
DRHOLD
CLEAR DIGITAL
RAMP ACCUMULATOR
AUTOCLEAR DIGITAL
RAMP ACCUMULATOR
I/O_UPDATE
1
2
3
4
5
6
7
8
9
11
13
10
12
Figure 39. Normal Ramp Generation
Event 1—The digital ramp enable bit is set, which has no affect
on the DRG because the bit is not effective until an I/O update.
Event 8—The clear digital ramp accumulator bit is set, which
has no affect on the DRG because the bit is not effective until an
I/O update.
Event 2—An I/O update registers the enable bit. If DRCTL = 1
is in effect at this time (gray portion of DRCTL trace), then the
DRG output immediately begins a positive slope (gray portion
of DRG output trace). Otherwise, if DRCTL = 0, the DRG
output is initialized to the lower limit.
Event 9—An I/O update registers that the clear digital ramp
accumulator bit is set, resetting the ramp accumulator and
forcing the DRG output to the programmed lower limit. The
DRG output remains at the lower limit until the clear condition
is removed.
Event 3—DRCTL transitions to a Logic 1 to initiate a positive
slope at the DRG output. In this example, the DRCTL pin is
held long enough to cause the DRG to reach its programmed
upper limit. The DRG remains at the upper limit until the ramp
accumulator is cleared, DRCTL = 0, or the upper limit is
reprogrammed to a higher value. In the last case, the DRG
immediately resumes its previous positive slope profile.
Event 10—The clear digital ramp accumulator bit is cleared,
which has no affect on the DRG because the bit is not effective
until an I/O update.
Event 11—An I/O update registers that the clear digital ramp
accumulator bit is cleared, releasing the ramp accumulator and
the previous positive slope profile restarts.
Event 4—DRCTL transitions to a Logic 0 to initiate a negative
slope at the DRG output. In this example, the DRCTL pin is
held long enough to cause the DRG to reach its programmed
lower limit. The DRG remains at the lower limit until DRCTL = 1,
or the lower limit is reprogrammed to a lower value. In the
latter case, the DRG immediately resumes its previous negative
slope profile.
Event 12—The autoclear digital ramp accumulator bit is set,
which has no affect on the DRG because the bit is not effective
until an I/O update.
Event 13—An I/O update registers that the autoclear digital
ramp accumulator bit is set, resetting the ramp accumulator.
However, with an automatic clear, the ramp accumulator is only
held reset for a single DDS clock cycle. This forces the DRG
output to the lower limit, but the ramp accumulator is
immediately made available for normal operation. In this
example, the DRCTL pin remains a Logic 1, so the DRG output
restarts the previous positive ramp profile.
Event 5—DRCTL transitions to a Logic 1 for the second time,
initiating a second positive slope.
Event 6—The positive slope profile is interrupted by DRHOLD
transitioning to a Logic 1. This stalls the ramp accumulator and
freezes the DRG output at its last value.
Event 7—DRCTL transitions to a Logic 0, releasing the ramp
accumulator and reinstating the previous positive slope profile.
Rev. 0 | Page 30 of 60
AD9910
P DDS CLOCK CYCLES
No-Dwell Ramp Generation
The two no-dwell bits in Control Function Register 2 add to the
flexibility of the DRG capabilities. During normal ramp generation,
when the DRG output reaches the programmed upper or lower
limit, it simply remains at the limit until the operating parameters
dictate otherwise. However, during no-dwell operation, the DRG
output does not necessarily remain at the limit. For example, if the
digital ramp no-dwell high bit is set, when the DRG reaches the
upper limit it automatically (and immediately) snaps to the lower
limit (that is, it does not ramp back to the lower limit, it jumps to
the lower limit). Likewise, when the digital ramp no-dwell low bit
is set, when the DRG reaches the lower limit it automatically (and
immediately) snaps to the upper limit.
POSITIVE
STEP SIZE
+Δ
t
UPPER LIMIT
DRG OUTPUT
LOWER LIMIT
DROVER
DRCTL
1
2
3
4
5
6
7
8
Figure 40. No-Dwell High Ramp Generation
The circled numbers indicate specific events, which are explained
as follows:
During no-dwell operation, the DRCTL pin is monitored for state
transitions only, that is, the static logic level is immaterial.
Event 1—Indicates the instant that an I/O update registers that the
digital ramp enable bit has been set.
During no-dwell high operation, a positive transition of the
DRCTL pin initiates a positive slope ramp, which continues
uninterrupted (regardless of any further activity on the DRCTL
pin) until the upper limit is reached.
Event 2—DRCTL transitions to a Logic 1, initiating a positive
slope at the DRG output.
Event 3—DRCTL transition to a Logic 0, which has no effect on
the DRG output.
During no-dwell low operation, a negative transition of the DRCTL
pin initiates a negative slope ramp, which continues uninterrupted
(regardless of any further activity on the DRCTL pin) until the
lower limit is reached.
Event 4—Because the digital ramp no-dwell high bit is set, the
moment that the DRG output reaches the upper limit it immedi-
ately switches to the lower limit, where it remains until the next
Logic 0 to Logic 1 transition of DRCTL.
Setting both no-dwell bits invokes a continuous ramping mode
of operation. That is, the DRG output automatically oscillates
between the two limits using the programmed slope parameters.
Furthermore, the function of the DRCTL pin is slightly different.
Instead of controlling the initiation of the ramp sequence, it
only serves to change the direction of the ramp. That is, if the
DRG output is in the midst of a positive slope and DRCTL pin
transitions from Logic 1 to Logic 0, then the DRG immediately
switches to the negative slope parameters and resumes oscilla-
tion between the limits. Likewise, if the DRG output is in the
midst of a negative slope and the DRCTL pin transitions from
Logic 0 to Logic 1, the DRG immediately switches to the positive
slope parameters and resumes oscillation between the limits.
Event 5—DRCTL transitions from Logic 0 to Logic 1, which
restarts at positive slope ramp.
Event 6 and Event 7—DRCTL transitions are ignored until the
DRG output reaches the programmed upper limit.
Event 8—Because the digital ramp no-dwell high bit is set, the
moment that the DRG output reaches the upper limit it
immediately switches to the lower limit, where it remains until
the next Logic 0 to Logic 1 transition of DRCTL.
Operation with the digital ramp no-dwell low bit set (instead of the
digital ramp no-dwell high bit) is similar, except that the DRG
output ramps in the negative direction on a Logic 1 to Logic 0
transition of DRCTL and jumps to the upper limit upon reaching
the lower limit.
When both no-dwell bits are set, the DROVER signal produces a
positive pulse (two cycles of the DDS clock) each time the DRG
output reaches either of the programmed limits (assuming that the
DROVER pin active bit is set).
DROVER Pin
A no-dwell high DRG output waveform is shown in Figure 40.
The waveform diagram assumes that the digital ramp no-dwell
high bit is set and has been registered by an I/O update. The
status of the DROVER pin is also shown with the assumption
that the DROVER pin active bit has been set.
The DROVER pin provides an external signal to indicate the status
of the DRG. The functionality of this pin is controlled by the
DROVER pin active bit. When this bit is cleared (default), the
DROVER pin is always Logic 0 regardless of the status of the DRG.
When this bit is set, the DROVER pin logic level depends on the
status of the DRG. Specifically, when the DRG output is at either of
the programmed limits, the DROVER pin is Logic 1, otherwise, it is
Logic 0. In the special case of both no-dwell bits set, the DROVER
pin pulses positive for two DDS clock cycles each time the DRG
output reaches either of the programmed limits.
Rev. 0 | Page 31 of 60
AD9910
3. Write (or read) the address range specified by the selected
RAM profile via the serial port (see the Serial Programming
section for details). Figure 41 is a block diagram showing
the functional components used for RAM data load/retrieve
operation.
RAM CONTROL
RAM Overview
The AD9910 makes use of a 1024 × 32-bit RAM. The RAM has
two fundamental modes of operation: data entry/retrieve mode
and playback mode. Data entry/retrieve mode is active when
the RAM data is being loaded or read back via the serial I/O
port. Playback mode is active when the RAM contents are
routed to one of the internal data destinations.
During RAM load/retrieve operations, the state machine controls
an up/down counter to step through the required RAM loca-
tions. The counter synchronizes with the serial I/O port so that
the serial/parallel conversion of the 32-bit words is correctly
timed with the generation of the appropriate RAM address to
properly execute the desired read or write operation.
Depending on the specific playback mode, the user can
partition the RAM with up to eight independent time domain
waveforms. These waveforms drive the DDS signal control
parameters allowing for frequency, phase, amplitude, or polar
modulated signals.
10
WAVEFORM START ADDRESS
3
PROGRAMMING
REGISTERS
10
PROFILE
WAVEFORM END ADDRESS
UP/DOWN
COUNTER
RAM operations are enabled by setting the RAM enable bit in
Control Function Register 1; an I/O update (or a profile change)
is necessary to enact any change to the state of this bit.
2
SDIO
U/D
32
SERIAL
I/O
PORT
STATE
MACHINE
SCLK
Q
RAM
I/O_RESET
CS
Waveforms are generated using eight RAM profile registers that
are accessed via the three profile pins. Each profile contains the
following:
ADDRESS CLOCK
Figure 41. RAM Data Load/Retrieve Operation
•
•
•
•
•
•
10-bit waveform start address word
10-bit waveform end address word
16-bit address step rate control word
3-bit RAM mode control word
No-dwell high bit
The RAM profiles are completely independent; it is possible
to define overlapping address ranges. Doing so causes data
that has been written to overlapped address locations to be
overwritten by the most recent write operation.
Multiple waveforms can be loaded into RAM by treating them
as a single waveform, that is, a time-domain concatenation of all
the waveforms. This is done by programming one of the RAM
profiles with a start and end address spanning the entire range
of the concatenated waveforms. Then the single concatenated
waveform is written into RAM via the serial I/O port using the
same RAM profile that was programmed with the start and end
addresses. The RAM profiles must then be programmed with
the proper start and end addresses associated with each
individual waveform.
Zero-crossing bit
The user must ensure that the end address is greater than the
start address.
Each profile defines the number of samples and the sample rate
for a given waveform. In conjunction with an internal state
machine, the RAM contents are delivered to the appropriate
DDS signal control parameter(s) at the specified rate. Further-
more, the state machine can control the order in which samples
are extracted from RAM (forward/reverse), facilitating efficient
generation of time symmetric waveforms.
RAM Playback Operation (Waveform Generation)
When the RAM has been loaded with the desired waveform
data, it can then be used for waveform generation during
playback. RAM playback requires that RAM enable = 1. To
playback RAM data select the desired waveform using the
profile pins. The selected profile directs the internal state
machine by defining the RAM address range occupied by the
waveform, the rate at which samples are to be extracted from
the RAM (playback rate), the mode of operation, and whether
to use the no-dwell feature. Figure 42 is a block diagram
showing the functional components used for RAM playback
operation.
Load/Retrieve RAM Operation
It is strongly recommended that RAM enable = 0 when
performing RAM load/retrieve operations. Loading or
retrieving the contents of the RAM requires a three-step
process.
1. Program the RAM Profile<0:7> registers with the start and
end addresses that are to define the boundaries of each
independent waveform.
2. Drive the appropriate logic levels on the profile pins to
select the desired RAM profile.
Rev. 0 | Page 32 of 60
AD9910
The RAM playback destination bits affect specific DDS signal
control parameters. The parameters that are not affected by the
RAM playback destination bits are controlled by the FTW, POW,
and/or ASF registers.
WAVEFORM START ADDRESS
WAVEFORM END ADDRESS
ADDRESS RAMP RATE
RAM MODE
RAM
PROFILE
REGISTERS
3
PROFILE
10
3
NO DWELL
10
16
2
UP/DOWN
COUNTER
RAM_SWP_OVR (RAM Sweep Over) Pin
U/D
10
The RAM_SWP_OVR pin provides an active high external
signal that indicates the end of a playback sequence. The
operation of this pin varies with the RAM operating mode
as detailed in the following sections. When RAM enable = 0,
this pin is forced to a Logic 0.
32
TO DDS
STATE
MACHINE
SIGNAL
Q
RAM
CONTROL
PARAMETER
DDS CLOCK
Figure 42. RAM Playback Operation
Overview of RAM Playback Modes
During playback, the state machine uses an up/down counter to
step through the specified address locations. The clock rate of
this counter defines the playback rate; that is, the sample rate of
the generated waveform. The clocking of the counter is
controlled by a 16-bit programmable timer that is internal to
the state machine. This timer is clocked by the DDS clock and
its time interval is set by the 16-bit address step rate value
stored in the selected RAM profile register.
The RAM can operate in any one of five different playback modes:
•
•
•
•
•
Direct switch
Ramp up
Bidirectional ramp
Continuous bidirectional ramp
Continuous recirculate
The mode is selected via the 3-bit RAM mode control word
located in each of the RAM profile registers. Thus, the RAM
operating mode is profile dependent. The RAM profile mode
control bits are detailed in Table 13.
The address step rate value determines the playback rate. For
example, if M is the 16-bit value of the address step rate for a
specific RAM profile, then the playback rate for that profile is
given by
Table 13. RAM Operating Modes
fDDSCLOCK
fSYSCLK
4M
PlaybackRate =
=
RAM Profile
Mode Control Bits
M
RAM Operating Mode
Direct switch
The sample interval (Δt) associated with the playback rate, is
therefore given by
000, 101, 110, 111
001
010
011
100
Ramp up
Bidirectional ramp
Continuous bidirectional ramp
Continuous recirculate
1
4M
Δt =
=
PlaybackRate fSYSCLK
RAM data entry/retrieval via the I/O port takes precedence
over playback operation. An I/O operation targeting the RAM
during playback interrupts any waveform in progress.
RAM Direct Switch Mode
In direct switch mode, the RAM is not used as a waveform
generator. Instead, when a RAM profile is selected via the
PROFILE pins only a single 32-bit word is routed to the DDS to
be applied to the signal control parameter(s). This 32-bit word
is the data stored in the RAM at the location given by the 10-bit
waveform start address of the selected profile.
The 32-bit words output by the RAM during playback route to
the DDS signal control parameters according to two RAM
Playback Destination bits in Control Function Register 1. The
32-bit words are partitioned based on Table 12.
In direct switch mode, the RAM_SWP_OVR pin is always
Logic 0 and the no-dwell high bit is ignored.
Table 12. RAM Playback Destination
RAM Playback
Destination Bits
CFR1<30:29>
DDS Signal
Control
Parameter
Bits Assigned to
DDS Parameters
Direct switch mode enables up to eight-level FSK, PSK, or ASK
modulation; the type of modulation is determined by the RAM
playback destination bits (frequency for FSK, and so on). Each
RAM profile is associated with a specific value of frequency,
phase, or amplitude. Each unique waveform start address value
in each RAM profile allows access of the 32-bit word stored in
that particular RAM location. In this way, the profile pins
implement the shift-keying function, modulating the DDS
output as desired.
00
01
10
11
Frequency
Phase
Amplitude
31:0
31:16
31:18
Phase<31:16>
Polar (phase
and amplitude) Amplitude<15:2>
When the destination is phase, amplitude, or polar the unused
LSBs are ignored.
Rev. 0 | Page 33 of 60
AD9910
Note that two-level modulation can be accomplished by using
only one of the three profile pins to toggle between two
different parameter values. Likewise, four-level modulation can
be accomplished by using only two of the three profile pins.
There is no restriction on which profile pins are used.
Ramp Up Timing Diagram
A graphic representation of the ramp up mode appears in
Figure 43, showing both normal and no-dwell operation.
The two upper traces show the progression of the RAM address
from the waveform start address to the waveform end address
for the selected profile. The address value advances by one with
each timeout of the timer internal to the state machine. The
timer period (Δt) is determined by the address ramp rate value
for the selected profile. The two upper traces are differentiated
by the state of the no-dwell high bit.
RAM Direct Switch Mode with Zero-Crossing
The zero-crossing function (enabled with the zero-crossing bit)
is a special feature that is only available in RAM direct switch
mode. The zero-crossing function is only valid if the RAM
playback destination bits specify phase as the DDS signal
control parameter.
M DDS CLOCK CYCLES
Enabling zero-crossing causes the DDS to delay the application
of a new phase value until such time as the DDS phase
accumulator rolls over from full scale to zero (the point at
which the DDS phase accumulator represents a phase angle that
is at the 360ꢁ to 0ꢁ transition point). This can be a very
beneficial feature when the DDS is programmed to generate a
sine wave (using the select DDS sine output bit), because the
zero-crossing point of phase for a sine wave corresponds with
the zero-crossing point of amplitude.
Δ
t
WAVEFORM END ADDRESS
1
NO-DWELL
HIGH = 0
RAM ADDRESS
RAM ADDRESS
WAVEFORM START ADDRESS
WAVEFORM END ADDRESS
NO-DWELL
HIGH = 1
1
In the case of binary phase shift keying (BPSK), the zero-
crossing feature allows the AD9910 to perform the 180ꢁ phase
jumps associated with BPSK with only a minimal instantaneous
change in amplitude. This avoids the spectral splatter that
frequently accompanies BPSK modulation.
WAVEFORM START ADDRESS
RAM_SWP_OVER
I/O_UPDATE
1
2
3
Although the intent of the zero-crossing feature is for use with
the DDS sine output enabled, it can be used with a cosine
output. In this case, the phase values extracted from RAM are
registered at the DDS when the output amplitude is at its peak
positive value.
Figure 43. Ramp Up Timing Diagram
The circled numbers in Figure 43 indicate specific events
explained as follows:
Event 1—An I/O update or profile change occurs. This event
initializes the state machine to the waveform start address and
sets the RAM_SWP_OVR pin to Logic 0.
RAM Ramp Up Mode
In ramp up mode, upon assertion of an I/O update or a change
of profile, the RAM begins operating as a waveform generator
using the parameters programmed into the selected RAM
profile register. Data is extracted from RAM over the specified
address range and at the specified rate contained in the wave-
form start address, waveform end address, and address ramp
rate values of the selected RAM profile. The data is delivered
to the specified DDS signal control parameter(s) based on the
RAM playback destination bits.
Event 2—The state machine reaches the waveform end address
value for the selected profile. The RAM_SWP_OVR pin
switches to Logic 1. This marks the end of the waveform
generation sequence for normal operation.
Event 3—The state machine switches to the waveform start
address. This marks the end of the waveform generation
sequence for no-dwell operation.
The internal state machine begins extracting data from the
RAM at the waveform start address and continues to extract
data until it reaches the waveform end address. Upon reaching
this address, it either remains at the waveform end address or
returns to the waveform start address as defined by the no-dwell
high bit. Then the state machine halts and the RAM_SWP_OVR
pin goes high.
Changing profiles resets the RAM_SWP_OVR pin to Logic 0,
automatically terminates the current waveform, and initiates the
newly selected waveform.
RAM Ramp Up Internal Profile Control Mode
Ramp up internal profile control mode is invoked via the four
internal profile control bits (rather than through the RAM
profile mode control bits in the RAM profile registers).
Rev. 0 | Page 34 of 60
AD9910
Table 14. RAM Internal Profile Control Modes
Internal Profile
Control Description
Internal Profile Control Bits
Waveform Type
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Internal profile control disabled.
Burst
Burst
Burst
Burst
Burst
Burst
Burst
Continuous
Continuous
Continuous
Continuous
Continuous
Continuous
Continuous
Execute Profile 0, then Profile 1, then halt.
Execute Profile 0 to Profile 2, then halt.
Execute Profile 0 to Profile 3, then halt.
Execute Profile 0 to Profile 4, then halt.
Execute Profile 0 to Profile 5, then halt.
Execute Profile 0 to Profile 6, then halt.
Execute Profile 0 to Profile 7, then halt.
Execute Profile 0, then 1, continuously.
Execute Profile 0 to Profile 2, continuously.
Execute Profile 0 to Profile 3, continuously.
Execute Profile 0 to Profile 4, continuously.
Execute Profile 0 to Profile 5, continuously.
Execute Profile 0 to Profile 6, continuously.
Execute Profile 0 to Profile 7, continuously.
Invalid.
If any of the internal profile control bits are set, then the RAM
profile mode control bits of the RAM profile registers are
ignored. The no-dwell high bit is ignored in this mode. The
internal profile control mode is identical to ramp up mode,
except that profile switching is done automatically and
internally; the state of the PROFILE<2:0> pins is ignored.
Profiles cycle according to Table 14.
waveforms, the state machine automatically jumps to Profile 0
and continues the automatic waveform generation by sequentially
advancing through the profiles. This process continues indefi-
nitely until the internal profile control bits are reprogrammed
and an I/O update is asserted.
A burst waveform timing diagram is exemplified in Figure 44.
The diagram assumes that internal profile control bits in
Control Function Register 1 (CFR1) are programmed as 0010,
the start address in RAM Profile 1 is greater than the end address
in RAM Profile 0, and the start address in RAM Profile 2 is
greater than the end address in RAM Profile 1. However,
understand that the block of RAM associated with each profile
can be chosen arbitrarily based on the waveform start address
and waveform end address for each profile. Furthermore, the
example shows how different Δt values associated with each
profile might be utilized.
There are two types of waveform generation types available
under internal profile control; burst waveforms and continuous
waveforms. With both types, the state machine begins with the
waveform specified by the waveform start address, waveform
end address, and address ramp rate in Profile 0. After reaching
the waveform end address of Profile 0, the state machine
automatically advances to the next profile and initiates the
specified waveform as defined by the new profile parameters.
After the state machine reaches the waveform end address of
the new profile it advances to the next profile. This action
continues until the state machine reaches the waveform end
address of the last profile as governed by the internal profile
control bits in Register CFR1 per Table 14.
At this point, the next course of action depends on whether the
waveform type is burst or continuous. For burst waveforms, the
state machine halts operation after reaching the waveform end
address of the final profile. For continuous
Rev. 0 | Page 35 of 60
AD9910
RAM PROFILE
0
1
2
WAVEFORM END ADDRESS 2
WAVEFORM START ADDRESS 2
Δ
t2
1
WAVEFORM END ADDRESS 1
Δt1
RAM
ADDRESS
WAVEFORM START ADDRESS 1
WAVEFORM END ADDRESS 0
1
Δ
t0
1
WAVEFORM START ADDRESS 0
RAM_SWP_OVER
I/O_UPDATE
1
2
3
4
5
6
7
Figure 44. Internal Profile Control Timing Diagram (Burst)
and begins incrementing through the address range for RAM
Profile 1 at intervals of Δt1.
The gray bar across the top indicates the time interval over
which the designated profile is in effect. The circled numbers
indicate specific events as follows:
Event 4—The state machine reaches the waveform end address
of RAM Profile 1 and the RAM_SWP_OVR pin generates a
positive pulse spanning two DDS clock cycles.
Event 1—An I/O update registers the Internal Profile Control
bits (in Control Function Register 1) are as 0010. The
RAM_SWP_OVR pin is set to Logic 0. The state machine is
initialized to the waveform start address of RAM Profile 0 and
begins incrementing through the address range for RAM
Profile 0 at intervals of Δt0 (as specified by the address step rate
for RAM Profile 0).
Event 5—Having reached the waveform end address of RAM
Profile 1, the next expiration of the internal timer causes the
state machine to advance to RAM Profile 2. The state machine
initializes to the waveform start address of RAM Profile 2 and
begins incrementing through the address range for RAM
Profile 2 at intervals of Δt2.
Event 2—The state machine reaches the waveform end address
of RAM Profile 0 and the RAM_SWP_OVR pin generates a
positive pulse spanning two DDS clock cycles.
Event 6—The state machine reaches the waveform end address of
RAM Profile 2 and the RAM_SWP_OVR pin generates a positive
pulse spanning two DDS clock cycles.
Event 3—Having reached the waveform end address of RAM
Profile 0, the next expiration of the internal timer causes the
state machine to advance to RAM Profile 1. The state machine
is initialized to the waveform start address of RAM Profile 1
Event 7—Having reached the waveform end address of RAM
Profile 2, the next expiration of the internal timer causes the
state machine to halt and marks completion of the burst
waveform generation process.
Rev. 0 | Page 36 of 60
AD9910
0
1
0
1
0
2
RAM PROFILE
WAVEFORM END
ADDRESS 1
Δ
t1
1
WAVEFORM START
ADDRESS 1
RAM
ADDRESS
WAVEFORM END
ADDRESS 0
Δt0
1
WAVEFORM START
ADDRESS 0
RAM_SWP_OVER
I/O_UPDATE
1
2
3
4
5
6
7
8
9
10 11
Figure 45. Internal Profile Control Timing Diagram (Continuous)
Profile 0 and begins incrementing through the address range for
RAM Profile 0 at intervals of Δt0.
Internal Profile Control Continuous Waveform
Timing Diagram
An example of an internal profile control, continuous waveform
timing diagram is shown in Figure 45. The diagram assumes
that Internal Profile Control<20:17> is programmed as 1000. It
also assumes that the start address in RAM Profile 1 is greater
than the end address in RAM Profile 0.
Event 6 and Event 8—Same as Event 2 and Event 4, respectively.
Event 5 to Event 8—Repeat indefinitely until the internal profile
control bits are reprogrammed and an I/O update is asserted.
RAM Bidirectional Ramp Mode
The gray bar across the top indicates the time interval over
which the designated profile is in effect. The circled numbers
indicate specific events.
In bidirectional ramp mode, upon assertion of an I/O update,
the RAM begins operating as a waveform generator using the
parameters programmed only into RAM Profile 0 (unlike ramp
up mode, which uses all eight profiles). Data is extracted from
RAM over the specified address range and at the specified rate
contained in the waveform start address, waveform end address,
and address ramp rate values of the selected RAM profile. The
data is delivered to the specified DDS signal control
Event 1—An I/O update registers the fact that internal profile
control bits (in Control Function Register 1) are programmed
to 1000. The RAM_SWP_OVR pin is set to Logic 0. The state
machine is initialized to the waveform start address of RAM
Profile 0 and begins incrementing through the address range for
RAM Profile 0 at intervals of Δt0 (as specified by the address
step rate for RAM Profile 0).
parameter(s) based on the RAM playback destination bits.
The PROFILE<2:1> pins are ignored by the internal logic in
this mode. When a RAM profile programmed to operate in this
mode is selected, no other RAM profiles can be selected until
the active RAM profile is reprogrammed with a different RAM
operating mode. The no-dwell high bit is ignored in this mode.
Event 2—The state machine reaches the waveform end address
of RAM Profile 0 and the RAM_SWP_OVR pin generates a
positive pulse spanning two DDS clock cycles.
Event 3—Having reached the waveform end address of RAM
Profile 0, the next expiration of the internal timer causes the
state machine to advance to RAM Profile 1. The state machine
is initialized to the waveform start address of RAM Profile 1
and begins incrementing through the address range for RAM
Profile 1 at intervals of Δt1.
With the bidirectional ramp mode activated via an I/O update
or profile change, the internal state machine readies to extract
data from the RAM at the waveform start address. Data
extraction begins when PROFILE0 is Logic 1, which instructs
the state machine to begin incrementing through the address
range. As long as the PROFILE0 pin remains Logic 1, the state
machine continues to extract data until it reaches the waveform
end address. At this point, the state machine halts until the
PROFILE0 pin is Logic 0 instructing the state machine to begin
decrementing through the address range. As long as the
PROFILE0 pin is Logic 0, the state machine continues to extract
data until it reaches the waveform start address. At this point,
the state machine halts until the PROFILE0 pin is Logic 1.
Event 4—The state machine reaches the waveform end address
of RAM Profile 1 and the RAM_SWP_OVR pin generates a
positive pulse spanning two DDS clock cycles.
Event 5—Having reached the waveform end address of RAM
Profile 1, the next expiration of the internal timer causes the
state machine to jump back to RAM Profile 0. The state
machine initializes to the waveform start address of RAM
Rev. 0 | Page 37 of 60
AD9910
M DDS CLOCK CYCLES
Δ
t
Δt
WAVEFORM END ADDRESS
RAM ADRESS
1
WAVEFORM START ADDRESS
RAM_SWP_OVER
PROFILE0
I/O_UPDATE
1
2
3
4
5
6
7
8
Figure 46. Bidirectional Ramp Timing Diagram
If the PROFILE0 pin changes states before the state machine
reaches the programmed start or end address, the internal timer
is restarted and the direction of the address counter is reversed.
Event 6—PROFILE0 pin switches to Logic 0. The state machine
resets its internal timer and again reverses the direction of the RAM
address counter. The RAM_SWP_OVR state does not change.
Figure 46 is a graphic representation of the bidirectional ramp
mode. It shows the action of the state machine in response to
the PROFILE0 pin, and the response of the RAM_SWP_OVR pin.
Event 7—PROFILE0 pin remains at Logic 0 long enough for the
state machine to reach the waveform start address. There is no
change in the RAM_SWP_OVR state.
The RAM_SWP_OVR pin switches to Logic 1 when the state
machine reaches the waveform end address. It remains Logic 1
until the state machine reaches the waveform start address and
the PROFILE0 pin transitions from Logic 0 to Logic 1.
Event 8—PROFILE0 pin switches to Logic 1. The state machine
resets its internal timer and begins incrementing the RAM
address counter. The RAM_SWP_OVR pin switches to Logic 0
because both the waveform start address was reached and the
PROFILE0 pin transitioned from Logic 0 to Logic 1.
The circled numbers in Figure 46 indicate specific events as
follows:
RAM Continuous Bidirectional Ramp Mode
In continuous bidirectional ramp mode, upon assertion of an
I/O update or a change of profile, the RAM begins operating as
a waveform generator using the parameters programmed into
the RAM profile designated by the profile pins. Data is extracted
from RAM over the specified address range and at the specified
rate contained in the waveform start address, waveform end
address, and address ramp rate values of the selected RAM
profile. The data is delivered to the specified DDS signal control
parameter(s) based on the RAM playback destination bits. The
no-dwell high bit is ignored in this mode.
Event 1—An I/O update or profile change activates the RAM
bidirectional ramp mode. The state machine initializes to the
waveform start address and the RAM_SWP_OVR pin is set to
Logic 0.
Event 2—PROFILE0 pin switches to Logic 1. The state machine
begins incrementing the RAM address counter.
Event 3—PROFILE0 pin remains at Logic 1 long enough for
the state machine to reach the waveform end address. The
RAM_SWP_OVR pin switches to Logic 1 accordingly.
With the continuous bidirectional ramp mode activated via an
I/O update or profile change, the internal state machine begins
extracting data from the RAM at the waveform start address
and incrementing the address counter until it reaches the
waveform end address. At this point, the state machine
automatically reverses the direction of the address counter and
begins decrementing through the address range. Whenever one
of the terminal addresses is reached, the state machine reverses
the address counter; the process continues indefinitely.
Event 4—PROFILE0 pin switches to Logic 0. The state
machine begins decrementing the RAM address counter.
The RAM_SWP_OVR pin remains at Logic 1.
Event 5—PROFILE0 pin switches to Logic 1. The state machine
resets its internal timer and reverses the direction of the RAM
address counter (that is, it starts to increment). No change of
the RAM_SWP_OVR state because the waveform start address
has not yet been reached.
Rev. 0 | Page 38 of 60
AD9910
M DDS CLOCK CYCLES
Δ
t
Δt
WAVEFORM END ADDRESS
RAM ADRESS
1
WAVEFORM START ADDRESS
RAM_SWP_OVER
I/O_UPDATE
1
2
3
Figure 47. Continuous Bidirectional Ramp Timing Diagram
A change in state of the profile pins aborts the current waveform
and the newly selected RAM profile is used to initiate a new
waveform.
Event 1—An I/O update or profile change has activated the RAM
continuous bidirectional ramp mode. The state machine initializes
to the waveform start address. The RAM_SWP_OVR pin resets to
Logic 0. The state machine begins incrementing through the
specified address range.
The RAM_SWP_OVR pin switches to Logic 1 when the state
machine reaches the waveform end address, then returns to
Logic 0 at the waveform start address, toggling each time one
of these addresses is reached.
Event 2—The state machine reaches the waveform end address.
The RAM_SWP_OVR pin toggles to Logic 1.
A graphic representation of the continuous bidirectional ramp
mode is shown in Figure 47. The circled numbers indicate specific
events as follows:
Event 3—The state machine reaches the waveform start address.
The RAM_SWP_OVR pin toggles to Logic 0.
This action continues indefinitely until the next I/O update or
change in profile.
Rev. 0 | Page 39 of 60
AD9910
M DDS CLOCK CYCLES
Δ
t
WAVEFORM END ADDRESS
RAM ADRESS
1
WAVEFORM START ADDRESS
RAM_SWP_OVER
I/O_UPDATE
1
2
3
4
5
Figure 48. Continuous Recirculate Timing Diagram
RAM Continuous Recirculate Mode
Event 1—An I/O update or profile change occurs. This event
initializes the state machine to the waveform start address and
sets the RAM_SWP_OVR pin to Logic 0.
The continuous recirculate mode mimics the ramp up mode,
except that when the state machine reaches the waveform end
address, the next timeout of the internal timer causes the state
machine to jump to the waveform start address. The waveform
repeats until an I/O update or profile change.
Event 2—The state machine reaches the waveform end address
value for the selected profile. The RAM_SWP_OVR pin toggles
to Logic 1 for two DDS clock cycles.
The no-dwell high bit is ignored in this mode.
Event 3—The state machine switches to the waveform start
address and continues to increment the address counter.
A profile pin state change aborts the current waveform and the
newly selected RAM profile is used to initiate a new waveform.
Event 4—The state machine again reaches the waveform end
address value for the selected profile and the RAM_SWP_OVR
pin toggles to Logic 1 for two DDS clock cycles.
The RAM_SWP_OVR pin pulses high for two DDS clock cycles
when the state machine reaches the waveform end address.
Event 5—The state machine switches to the waveform start
address and continues to increment the address counter.
Continuous recirculate mode is graphically represented in
Figure 48. The circled numbers indicate specific events as
follows:
Event 4 and Event 5—These events repeat until an I/O update
or change in profile.
Rev. 0 | Page 40 of 60
AD9910
programmed into the I/O registers. A rising edge on I/O_UPDATE
initiates transfer of the register contents to the internal workings
of the device. Alternatively, the transfer of programmed data
from the programming registers to the internal hardware can
be accomplished by changing the state of the profile pins.
ADDITIONAL FEATURES
PROFILES
The AD9910 supports the use of profiles, which consist of a group
of eight registers containing pertinent operating parameters for
a particular operating mode. Profiles enable rapid switching
between parameter sets. Profile parameters are programmed via
the serial I/O port. Once programmed, a specific profile is
activated by means of three external pins (PROFILE<2:0>). A
particular profile is activated by providing the appropriate logic
levels to the profile control pins per Table 15.
AUTOMATIC I/O UPDATE
The AD9910 offers an option whereby the I/O update function
is asserted automatically rather than relying on an external signal
supplied by the user. This feature is enabled by setting the internal
I/O update active bit in Control Function Register 2 (CFR2).
When this feature is active, the I/O_UPDATE pin becomes
an output pin. It generates an active high pulse each time an
internal I/O update occurs. The duration of the pulse is
approximately 12 cycles of SYSCLK. This I/O update strobe
can be used to notify an external controller that the device
has generated an I/O update internally.
Table 15. Profile Control Pins
PROFILE<2:0>
Active Profile
000
001
010
011
100
101
110
111
0
1
2
3
4
5
6
7
The repetition rate of the internal I/O Update is programmed
via the serial I/O port. There are two parameters that control
the repetition rate. The first consists of the two I/O update rate
control bits in CFR2. The second is the 32-bit word in the I/O
update rate register that sets the range of an internal counter.
There are two different parameter sets that the eight profile
registers can control depending on the operating mode of the
device. When RAM enable = 0, the profile parameters follow
the single tone profile format detailed in the Register Map and
Bit Descriptions section. When RAM enable = 1, they follow
the RAM profile format.
The I/O update rate control bits establish a divide by 1, 2, 4, or 8
of a clock signal that runs at ¼ fSYSCLK. The output of the divider
clocks the aforementioned 32-bit internal counter. The
repetition rate of the I/O update is given by
fSYSCLK
fI /O _Update
=
As an example of the use of profiles, consider an application for
implementing basic two-tone frequency shift keying (FSK). FSK
uses the binary data in a serial bit stream to select between two
different frequencies: a mark frequency (Logic 1) and a space
frequency (Logic 0). To accommodate FSK, the device operates
in single tone mode. The register, Single Tone Profile 0, is
programmed with the appropriate frequency tuning word for a
space. The register, Single Tone Profile 1, is programmed with
the appropriate frequency tuning word for a mark. Then, with
the PROFILE1 and PROFILE2 pins tied to Logic 0, the
PROFILE0 pin is connected to the serial bit stream. In this way,
the logic state of the PROFILE0 pin causes the appropriate mark
and space frequencies to be generated in accordance with the
binary digits of the bit stream.
2A B
where A is the value of the 2-bit word comprising the I/O
update rate control bits and B is the value of the 32-bit word
stored in the I/O update rate register. The default value of A is 0
and the value of B is 0xFFFF. If B is programmed to 0x0003 or
less, the I/O_UPDATE pin no longer pulses, but assumes a
static Logic 1 state.
POWER-DOWN CONTROL
The AD9910 offers the ability to independently power down
four specific sections of the device. Power-down functionality
applies to the
•
•
•
•
Digital core
DAC
Auxiliary DAC
Input REFCLK clock circuitry
I/O_UPDATE PIN
By default, the I/O_UPDATE pin is an input that serves as a
strobe signal to allow synchronous update of the device
operating parameters. For example, frequency, phase and
amplitude control words for the DDS may be programmed via
the serial I/O Port. However, the serial I/O Port is an
asynchronous interface, so programming of the device
operating parameters via the I/O port is not synchronized with
the internal timing. With the I/O_UPDATE pin, the user can
synchronize the application of certain programmed operating
parameters with external circuitry when new parameters are
A power-down of the digital core disables the ability to update
the serial I/O port. However, the digital power-down bit can
still be cleared via the serial port to prevent the possibility of a
non-recoverable state.
Software power-down is controlled via four independent
power-down bits in Control Function Register 1 (CFR1).
Rev. 0 | Page 41 of 60
AD9910
Software control requires that the EXT_PWR_DWN pin be
forced to a Logic 0 state. In this case, setting the desired power-
down bits (via the serial I/O port) powers down the associated
functional block, whereas clearing the bits restores the function.
Based on the state of the external power-down control bit, the
EXT_PWR_DWN pin produces either a full power-down or a
fast recovery power-down. The fast recovery power-down mode
maintains power to the DAC bias circuitry and the PLL, VCO,
and input clock circuitry. Although the fast recovery power-
down does not conserve as much power as the full power-down,
it allows the device to awaken very quickly from the power-
down state.
Alternatively, all four functions can be simultaneously powered
down via external hardware control through the EXT_PWR_DWN
pin. When this pin is forced to Logic 1, all four circuit blocks are
powered down regardless of the state of the power-down bits.
That is, the independent power-down bits in CFR1 are ignored
and overridden when EXT_PWR_DWN is Logic 1.
Rev. 0 | Page 42 of 60
AD9910
SYNCHRONIZATION OF MULTIPLE DEVICES
The internal clocks of the AD9910 provide the timing for the
propagation of data along the baseband signal processing path.
These internal clocks are derived from the internal system clock
(SYSCLK) and are all submultiples of the SYSCLK frequency.
The logic state of all of these clocks in aggregate during any
given SYSCLK cycle defines a unique clock state. The clock state
advances with each cycle of SYSCLK, but the sequence of clock
states is periodic. By definition, multiple devices are synchronized
when their clock states match and they transition between states
simultaneously. Clock synchronization allows the user to asyn-
chronously program multiple devices but synchronously activate
the programming by applying a coincident I/O update to all
devices. It also allows multiple devices to operate in unison when
the parallel port is in use with either the QDUC or interpolating
DAC mode (see Figure 52).
The synchronization mechanism relies on the premise that the
REFCLK signal appearing at each device is edge aligned with all
others as a result of the external REFCLK distribution system
(see Figure 52).
The sync generator block is shown in Figure 50. It is activated
via the sync generator enable bit. It allows for one AD9910 in a
group to function as a master timing source with the remaining
devices slaved to the master.
9
PROGAMMABLE
÷16
÷N
D
Q
SYNC_OUT
SYSCLK
DELAY
10
LVDS
DRIVER
0
1
5
R
SYNC
GENERATOR
DELAY
SYNC
POLARITY
SYNC
GENERATOR
ENABLE
The function of the synchronization logic in the AD9910 is to
force the internal clock generator to a predefined state coincident
with an external synchronization signal applied to the SYNC_IN
pins. If all devices are forced to the same clock state in synchro-
nization with the same external signal, then the devices are, by
definition, synchronized. Figure 49 is a block diagram of the
synchronization function. The synchronization logic is divided
into two independent blocks; a sync generator and a sync receiver,
both of which use the local SYSCLK signal for internal timing.
Figure 50. Sync Generator Diagram
The sync generator produces a clock signal that appears at the
SYNC_OUT pins. This clock is delivered by an LVDS driver
and exhibits a 50ꢀ duty cycle. The clock has a fixed frequency
given by
fSYSCLK
16
fSYNC _ OUT
=
The clock at the SYNC_OUT pins synchronizes with either the
rising or falling edge of the internal SYSCLK signal as deter-
mined by the sync generator polarity bit. Because the SYNC_OUT
signal is synchronized with the internal SYSCLK of the master
device, the master device SYSCLK serves as the reference timing
source for all slave devices. The user can adjust the output delay
of the SYNC_OUT signal in steps of ~150 ps by programming
the 5-bit sync generator delay word via the serial I/O port. The
programmable output delay facilitates added edge timing
flexibility to the overall synchronization mechanism.
REF_CLK
INPUT
90
91
SYSCLK
REF_CLK
CIRCUITRY
5
9
SYNC
GENERATOR
SYNC_OUT
10
SYNC
RECEIVER
DELAY
SYNC
RECEIVER
ENABLE
The sync receiver block (shown in Figure 51) is activated via the
sync receiver enable bit. The sync receiver consists of three sub-
sections; the input delay and edge detection block, the internal
clock generator block, and the setup and hold validation block.
5
7
8
INPUT DELAY
SYNC_IN
AND EDGE
DETECTION
SYNC
RECEIVER
INTERNAL
CLOCKS
The clock generator block remains operational even if the sync
receiver is not enabled.
12
SETUP AND
HOLD VALIDATION
SYNC_SMP_ERR
6
4
SYNC STATE
SYNC
SYNC
TIMING
VALIDATION
DISABLE
PRESET VALUE VALIDATION
DELAY
Figure 49. Synchronization Circuit Block Diagram
Rev. 0 | Page 43 of 60
AD9910
CLOCK
STATE
SYNC STATE
PRESET VALUE
SYNC
RECEIVER
ENABLE
DELAYED SYNC-IN SIGNAL
6
SYNC
RECEIVER
DELAY
D1 Q1
D2 Q2
D3 Q3
D4 Q4
D5 Q5
D6 Q6
INTERNAL
CLOCKS
LVDS
RECEIVER
5
RISING EDGE
DETECTOR
AND
7
8
PROGAMMABLE
DELAY
SYNC_IN
LOAD
STROBE
GENERATOR
CLOCK
GENERATOR
SETUP AND HOLD
VALIDATION
12
SYNC_SMP_ERR
SYSCLK
4
SYNC
SYNC
VALIDATION
DELAY
SYNC PULSE
TIMING
VALIDATION
DISABLE
Figure 51. Sync Receiver Diagram
CLOCK DISTRIBUTION
AND
DELAY EQUALIZATION
CLOCK
SOURCE
EDGE
(FOR EXAMPLE AD951x)
ALIGNED
AT REF_CLK
INPUTS.
REF_CLK
DATA
AD9910
FPGA
MASTER DEVICE
NUMBER 1
SYNC SYNC
IN
OUT
EDGE
ALIGNED
AT SYN_IN
INPUTS.
REF_CLK
DATA
AD9910
FPGA
NUMBER 2
SYNC SYNC
IN
OUT
SYNCHRONIZATION
DISTRIBUTION AND
DELAY EQUALIZATION
(FOR EXAMPLE AD951x)
REF_CLK
DATA
AD9910
FPGA
NUMBER 3
SYNC SYNC
IN
OUT
Figure 52. Multichip Synchronization Example
The sync pulse presets the counter to a predefined state
(programmable via the 6-bit sync state preset value word in the
multichip sync register). The predefined state is only active for a
single SYSCLK cycle, after which the clock generator resumes
cycling through its state sequence at the SYSCLK rate. This
unique state presetting mechanism gives the user the flexibility
to synchronize devices with specific relative clock state offsets
(by assigning a different sync state preset value word to each
device).
The sync receiver accepts a periodic clock signal at the
SYNC_IN pins. This signal is assumed to originate from an
LVDS-compatible driver. The user can delay the SYNC_IN
signal in steps of ~150 ps by programming the 5-bit sync
receiver delay word in the multichip sync register. For the sake
of discussion, the signal at the output of the programmable
delay is referred to as the delayed sync-in signal.
The edge detection logic generates a sync pulse having a dura-
tion of one SYSCLK cycle with a repetition rate equal to the
frequency of the signal applied to the SYNC_IN pins. The sync
pulse is generated as a result of sampling the rising edge of the
delayed sync-in signal with the rising edge of the local SYSCLK.
The sync pulse is routed to the internal clock generator, which
behaves as a presettable counter clocked at the SYSCLK rate.
Multiple device synchronization is accomplished by providing
each AD9910 with a SYNC_IN signal that is edge aligned across
all the devices. If the SYNC_IN signal is edge aligned at all devices,
and all devices have the same sync receiver delay and sync state
preset value, then they all have matching clock states (that is, they
Rev. 0 | Page 44 of 60
AD9910
are synchronized). This concept is shown in Figure 52, in which
three AD9910s are synchronized with one device operating as a
master timing unit and the others as slave units.
The synchronization mechanism depends on the reliable gen-
eration of a sync pulse by the edge detection block in the sync
receiver. Generation of a valid sync pulse, however, requires
proper sampling of the rising edge of the delayed sync-in signal
with the rising edge of the local SYSCLK. If the edge timing of
these signals fails to meet the setup or hold time requirements
of the internal latches in the edge detection circuitry, then the
proper generation of the sync pulse is in jeopardy. The setup
and hold validation block (see Figure 53) gives the user a means
to validate that proper edge timing exists between the two
signals.
The master device must have its SYNC_IN pins included as part
of the synchronization distribution and delay equalization mecha-
nism in order for it to be synchronized with the slave units.
The synchronization mechanism begins with the clock
distribution and delay equalization block, which is used to
ensure that all devices receive an edge aligned REFCLK signal.
However, even though the REFCLK signal is edge aligned
among all devices, this alone does not guarantee that the clock
state of each internal clock generator is coordinated with the
others. This is the role of the Synchronization and Delay
Equalization block. This block accepts the SYNC_OUT signal
generated by the master device and redistributes it to the
SYNC_IN input of the slave units (as well as feeding it back to
the master). The goal of the redistributed SYNC_OUT signal
from the master device is to deliver an edge aligned SYNC_IN
signal to all of the sync receivers.
The setup and hold validation block can be disabled via the
sync timing validation disable bit in Control Function Register 2.
The validation block makes use of a user-specified time window
(programmable in increments of ~150 ps via the 4-bit sync
validation delay word in the multichip sync register). The setup
validation and hold validation circuits use latches identical to
those in the rising edge detector and strobe generator. The
programmable time window is used to skew the timing between
the rising edges of the local SYSCLK signal and the rising edges
of the delayed sync-in signal. If either the hold or setup
validation circuits fail to detect a valid edge sample, the
condition is indicated externally via the SYNC_SMP_ERR pin
(active high).
Assuming that all devices share the same REFCLK edge (due to
the clock distribution and delay equalization block), and all
devices share the same SYNC_IN edge (due to the synchroni-
zation and delay equalization block), then all devices should
generate an internal sync pulse in unison (assuming they all
have the same sync receiver delay value). With the further
stipulation that all devices have the same sync state preset value,
then the synchronized sync pulses cause all of the devices to
assume the same predefined clock state simultaneously. That is,
the internal clocks of all devices become fully synchronized.
The user must choose a sync validation delay value that is a
reasonable fraction of the SYSCLK period. For example, if the
SYSCLK frequency is 1 GHz (1 ns period), then a reasonable
value is 1 or 2 (150 ps or 300 ps). Choosing too large a value can
cause the SYNC_SMP_ERR pin to generate false error signals.
Choosing too small a value may cause instability.
SYNC RECEIVER
RISING EDGE
DETECTOR
AND STROBE
GENERATOR
FROM
SYNC
RECEIVER
DELAY
TO
CLOCK
LOGIC
GENERATION
LOGIC
SYNC
PULSE
D
Q
SETUP AND HOLD VALIDATION
SETUP
VALIDATION
DELAY
D
Q
4
4
4
12
SYNC_SMP_ERR
SYNC VALIDATION
DELAY
D Q
SYSCLK
HOLD
VALIDATION
DELAY
SYNC TIMING VALIDATION DISABLE
Figure 53. Sync Timing Validation Block
Rev. 0 | Page 45 of 60
AD9910
SERIAL PROGRAMMING
the serial port buffer, and data is driven out on the falling edge
of SCLK.
CONTROL INTERFACE—SERIAL I/O
The AD9910 serial port is a flexible, synchronous serial commu-
nications port allowing easy interface to many industry-standard
microcontrollers and microprocessors. The serial I/O is compatible
with most synchronous transfer formats, including both the
Motorola 6905/11 SPI and Intel® 8051 SSR protocols.
INSTRUCTION BYTE
The instruction byte contains the following information as
shown in the instruction byte bit map.
Instruction Byte Information Bit Map
The interface allows read/write access to all registers that
configure the AD9910. MSB-first or LSB-first transfer formats
are supported. In addition, the serial interface port can be
configured as a single pin input/output (SDIO) allowing a two-
wire interface, or it can be configured as two unidirectional pins
for input/output (SDIO/SDO) enabling a 3-wire interface. Two
MSB
D7
LSB
D6
D5
D4
D3
D2
D1
D0
R/W
X
X
A4
A3
A2
A1
A0
W
R/ —Bit 7 of the instruction byte determines whether a read
or write data transfer occurs after the instruction byte write. Set
indicates read operation. Cleared indicates a write operation.
CS
optional pins (I/O_RESET and ) enable greater flexibility for
designing systems with the AD9910.
X, X—Bit 6 and Bit 5 of the instruction byte are don’t care.
GENERAL SERIAL I/O OPERATION
A4, A3, A2, A1, A0—Bit 4, Bit 3, Bit 2, Bit 1, and Bit 0 of the
instruction byte determine which register is accessed during the
data transfer portion of the communications cycle.
There are two phases to a serial communications cycle. The first
is the instruction phase to write the instruction byte into the
AD9910. The instruction byte contains the address of the
register to be accessed (see the Register Map and Bit Descriptions
section) and also defines whether the upcoming data transfer is
a write or read operation.
SERIAL I/O PORT PIN DESCRIPTIONS
SCLK—Serial Clock
The serial clock pin is used to synchronize data to and from the
AD9910 and to run the internal state machines.
For a write cycle, Phase 2 represents the data transfer between
the serial port controller to the serial port buffer. The number
of bytes transferred is a function of the register being accessed.
For example, when accessing the Control Function Register 2
(Address 0x01), Phase 2 requires that four bytes be transferred.
Each bit of data is registered on each corresponding rising edge
of SCLK. The serial port controller expects that all bytes of the
register be accessed, otherwise the serial port controller is put
out of sequence for the next communication cycle. However,
one way to write fewer bytes than required is to use the I/O_RESET
pin feature. The I/O_RESET pin function can be used to abort
an I/O operation and reset the pointer of the serial port con-
troller. After an I/O reset, the next byte is the instruction byte.
Note that every completed byte written prior to an I/O reset is
preserved in the serial port buffer. Partial bytes written are not
preserved. At the completion of any communication cycle, the
AD9910 serial port controller expects the next eight rising
SCLK edges to be the instruction byte for the next communi-
cation cycle.
CS
—Chip Select Bar
Active low input that allows more than one device on the same
serial communications line. The SDO and SDIO pins go to a
high impedance state when this input is high. If driven high
during any communications cycle, that cycle is suspended until
CS
CS
is reactivated low. Chip select ( ) can be tied low in
systems that maintain control of SCLK.
SDIO—Serial Data Input/Output
Data is always written into the AD9910 on this pin. However,
this pin can be used as a bidirectional data line. Bit 1 of CFR1
Register Address 0x00 controls the configuration of this pin.
The default is cleared, which configures the SDIO pin as
bidirectional.
SDO—Serial Data Out
Data is read from this pin for protocols that use separate lines
for transmitting and receiving data. In the case where the
AD9910 operates in a single bidirectional I/O mode, this pin
does not output data and is set to a high impedance state.
After a write cycle, the programmed data resides in the serial
port buffer and is inactive. I/O_UPDATE transfers data from
the serial port buffer to active registers. The I/O update can
either be sent after each communication cycle or when all serial
operations are complete. In addition, a change in profile pins
can initiate an I/O update.
I/O_RESET—Input/Output Reset
I/O_RESET synchronizes the I/O port state machines without
affecting the addressable registers contents. An active high
input on the I/O_RESET pin causes the current communication
cycle to abort. After I/O_RESET returns low (Logic 0), another
For a read cycle, Phase 2 is the same as the write cycle with the
following differences: Data is read from the active registers, not
Rev. 0 | Page 46 of 60
AD9910
communication cycle can begin, starting with the instruction
byte write.
MSB/LSB TRANSFERS
The AD9910 serial port can support both most significant bit
(MSB) first or least significant bit (LSB) first data formats. This
functionality is controlled by Bit 0 in Control Function
Register 1 (0x00). The default format is MSB first. If Bit 0 is set
high, the serial port is configured for LSB-first format. If LSB
first is active, all data, including the instruction byte, must
follow LSB-first convention. Note that the highest number
found in the bit range column for each register (see the Register
Map and Bit Descriptions section and Table 16) is the MSB and
the lowest number is the LSB for that register.
I/O_UPDATE—Input/Output Update
The I/O_UPDATE initiates the transfer of written data from
the I/O port buffer to active registers. I/O_UPDATE is active
on the rising edge and its pulse width must be greater than one
SYNC_CLK period. It is either an input or output pin depending
on the programming of the Internal I/O update active bit.
SERIAL I/O TIMING DIAGRAMS
The diagrams below provide basic examples of the timing
relationships between the various control signals of the serial
I/O port. Most of the bits in the register map are not transferred
to their internal destinations until assertion of an I/O update,
which is not included in the timing diagrams that follow.
INSTRUCTION CYCLE
CS
DATA TRANSFER CYCLE
SCLK
I
I
I
I
I
I
I
I
D
D
D
D
D
D
D
D
SDIO
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Figure 54. Serial Port Write Timing, Clock Stall Low
INSTRUCTION CYCLE
DATA TRANSFER CYCLE
CS
SCLK
SDIO
SDO
I
I
I
I
I
I
I
I
0
DON'T CARE
7
6
5
4
3
2
1
D
D
D
D
D
D
D
D
O0
O7
O6
O5
O4
O3
O2
O1
Figure 55. 3-Wire Serial Port Read Timing, Clock Stall Low
INSTRUCTION CYCLE
DATA TRANSFER CYCLE
CS
SCLK
SDIO
I
I
I
I
I
I
I
I
D
D
D
D
D
D
D
D
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
Figure 56. Serial Port Write Timing, Clock Stall High
INSTRUCTION CYCLE
DATA TRANSFER CYCLE
CS
SCLK
SDIO
I
I
I
I
I
I
I
I
D
D
D
D
D
D
D
D
O0
7
6
5
4
3
2
1
0
O7
O6
O5
O4
O3
O2
O1
Figure 57. 2-Wire Serial Port Read Timing, Clock Stall High
Rev. 0 | Page 47 of 60
AD9910
REGISTER MAP AND BIT DESCRIPTIONS
Table 16. Register Map
Register
Name
(Serial
Address)
Default
Value5
(Hex)
Bit Range
(Internal
Address)
Bit 7
(MSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Open
Bit 1
Bit 0 (LSB)
CFR1—
Control
Function
Register 1
(0x00)
31:24
RAM
Enable
RAM Playback
Destination
0x00
23:16
Manual
OSK
External
Inverse
Sinc Filter
Enable
Open
Internal Profile Control
Select DDS
Sine Output
0x00
0x00
0x00
0x00
Control
15:8
7:0
Load LRR Autoclear
@ I/O
Update
Autoclear
Phase
Accum.
Clear
Clear
Phase
Accum.
Load ARR
@ I/O
Update
OSK
Enable
Select Auto
OSK
Digital
Ramp
Accum.
Digital
Ramp
Accum.
Digital
Power-
Down
DAC
Power-
Down
REFCLK
Input
Power-
Aux DAC
Power-
Down
External
Power-
Down
Open
SDIO
Input Only
LSB First
Down
Control
CFR2—
Control
Function
Register 2
(0x01)
31:24
Open
DROVER
Pin Active
Enable
Amplitude
Scale from
Single Tone
Profiles
23:16
Internal
I/O
SYNC_CLK
Enable
Digital Ramp
Destination
Digital
Ramp
Digital
Ramp
Digital
Ramp
Read
Effective
0x40
Update
Active
Enable
No-Dwell
High
No-Dwell
Low
FTW
15:8
7:0
I/O Update Rate Control
Open
PDCLK
Enable
PDCLK
Invert
TxEnable
Invert
Open
0x08
0x20
Matched
Latency
Enable
Data
Sync
Sample
Parallel
Data Port
Enable
FM Gain
Assembler
Hold Last
Value
Error Mask
CFR3—
Control
Function
Register 3
(0x02)
31:24
23:16
15:8
DRV0<1:0>
Open
REFCLK
Open<5:3>
ICP<2:0>
VCO SEL<2:0>
Open
0x1F
0x3F
0x40
REFCLK
Input
Open
PLL Enable
Open
Input
Divider
Bypass
Divider
ResetB
7:0
N<6:0>
0x00
0x00
0x00
0x7F
0x7F
0xFF
0xFF
0xFF
0xFF
0x00
0x00
0x00
0x00
Auxiliary
DAC
Control
31:24
23:16
15:8
7:0
Open
Open
Open
(0x03)
FSC<7:0>
I/O Update
Rate (0x04)
31:24
23:16
15:8
7:0
I/O Update Rate<31:24>
I/O Update Rate<23:16>
I/O Update Rate<15:8>
I/O Update Rate<7:0>
FTW—
Frequency
Tuning
Word
31:24
23:16
15:8
7:0
Frequency Tuning Word<31:24>
Frequency Tuning Word<23:16>
Frequency Tuning Word<15:8>
Frequency Tuning Word<7:0>
(0x07)
Rev. 0 | Page 48 of 60
AD9910
Register
Name
(Serial
Default
Value5
(Hex)
0x00
0x00
Bit Range
(Internal
Address)
Bit 7
(MSB)
Address)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0 (LSB)
POW—
Phase Offset
Word (0x08)
15:8
7:0
Phase Offset Word<15:8>
Phase Offset Word<7:0>
ASF—
Amplitude
Scale
Factor
(0x09)
31:24
23:16
15:8
Amplitude Ramp Rate<15:8>
Amplitude Ramp Rate<7:0>
Amplitude Scale Factor<13:6>
0x00
0x00
0x00
0x00
0x00
7:0
Amplitude Scale Factor<5:0>
Sync Validation Delay<3:0>
Amplitude Step Size<1:0>
Multichip
31:24
Sync
Sync
Sync
Open
Sync (0x0A)
Receiver
Enable
Generator
Enable
Generator
Polarity
23:16
15:8
Sync State Preset Value<5:0>
Open
0x00
0x00
0x00
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
0x08
0xB5
0x00
0x00
0x00
0x00
0x00
0x00
N/A
N/A
N/A
N/A
N/A
Output Sync Generator Delay<4:0>
Input Sync Receiver Delay<4:0>
Open
Open
7:0
Digital
Ramp Limit
(0x0B)
63:56
55:48
47:40
39:32
31:24
23:16
15:8
Digital Ramp Upper Limit<31:24>
Digital Ramp Upper Limit<23:16>
Digital Ramp Upper Limit<15:8>
Digital Ramp Upper Limit<7:0>
Digital Ramp Lower Limit<31:24>
Digital Ramp Lower Limit<23:16>
Digital Ramp Lower Limit<15:8>
7:0
Digital Ramp Lower Limit<7:0>
Digital
Ramp Step
Size (0x0C)
63:56
55:48
47:40
39:32
31:24
23:16
15:8
Digital Ramp Decrement Step Size<31:24>
Digital Ramp Decrement Step Size<23:16>
Digital Ramp Decrement Step Size<15:8>
Digital Ramp Decrement Step Size<7:0>
Digital Ramp Increment Step Size<31:24>
Digital Ramp Increment Step Size<23:16>
Digital Ramp Increment Step Size<15:8>
Digital Ramp Increment Step Size<7:0>
Digital Ramp Negative Slope Rate <15:8>
Digital Ramp Negative Slope Rate<7:0>
Digital Ramp Positive Slope Rate<15:8>
Digital Ramp Positive Slope Rate<7:0>
7:0
Digital
Ramp Rate
(0x0D)
31:24
23:16
15:8
7:0
Single Tone 63:56
Open
Amplitude Scale Factor 0<13:8>
Profile 0
55:48
Amplitude Scale Factor 0<7:0>
Phase Offset Word 0<15:8>
Phase Offset Word 0<7:0>
(0x0E)
47:40
39:32
31:24
23:16
15:8
Frequency Tuning Word 0<31:24>
Frequency Tuning Word 0<23:16>
Frequency Tuning Word 0<15:8>
Frequency Tuning Word 0<7:0>
Open
7:0
RAM
Profile 0
(0x0E)
63:56
55:48
47:40
39:32
31:24
RAM Profile 0 Address Step Rate<15:8>
RAM Profile 0 Address Step Rate<7:0>
RAM Profile 0 Waveform End Address<9:2>
Open
RAM Profile 0 Waveform
End Address<1:0>
23:16
15:8
RAM Profile 0 Waveform Start Address<9:2>
Open
N/A
N/A
RAM Profile 0
Waveform Start
Address<1:0>
7:0
Open
No-Dwell
High
Open
Zero-
Crossing
RAM Profile 0 Mode Control<2:0>
N/A
Rev. 0 | Page 49 of 60
AD9910
Register
Name
(Serial
Default
Value5
Bit Range
(Internal
Address)
Bit 7
(MSB)
Address)
Bit 6
Open
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0 (LSB)
(Hex)
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Single Tone 63:56
Profile 1
(0x0F)
47:40
Amplitude Scale Factor 1<13:8>
55:48
Amplitude Scale Factor 1<7:0>
Phase Offset Word 1<15:8>
Phase Offset Word 1<7:0>
39:32
31:24
23:16
15:8
Frequency Tuning Word 1<31:24>
Frequency Tuning Word 1<23:16>
Frequency Tuning Word 1<15:8>
Frequency Tuning Word 1<7:0>
Open
7:0
RAM
Profile 1
(0x0F)
63:56
55:48
47:40
39:32
31:24
RAM Profile 1 Address Step Rate <15:8>
RAM Profile 1 Address Step Rate <7:0>
RAM Profile 1 Waveform End Address <9:2>
Open
RAM Profile 1
Waveform End
Address<1:0>
23:16
15:8
RAM Profile 1 Waveform Start Address<9:2>
Open
N/A
N/A
RAM Profile 1
Waveform Start
Address<1:0>
7:0
Open
No-Dwell
High
Open
Zero-
Crossing
RAM Profile 1 Model Control<2:0>
N/A
Single Tone 63:56
Open
Amplitude Scale Factor 2<13:8>
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Profile 2
(0x10)
47:40
55:48
Amplitude Scale Factor 2<7:0>
Phase Offset Word 2<15:8>
Phase Offset Word 2<7:0>
Frequency Tuning Word 2<31:24>
Frequency Tuning Word 2<23:16>
Frequency Tuning Word 2<15:8>
Frequency Tuning Word 2<7:0>
Open
39:32
31:24
23:16
15:8
7:0
RAM
Profile 2
(0x10)
63:56
55:48
47:40
39:32
31:24
RAM Profile 2 Address Step Rate<15:8>
RAM Profile 2 Address Step Rate<7:0>
RAM Profile 2 Waveform End Address<9:2>
Open
RAM Profile 2
Waveform End
Address<1:0>
23:16
15:8
RAM Profile 2 Waveform Start Address <9:2>
Open
N/A
N/A
RAM Profile 2
Waveform Start Address
<1:0>
7:0
Open
No-Dwell
High
Open
Zero-
Crossing
RAM Profile 2 Mode Control<2:0>
N/A
Single Tone 63:56
Open
Amplitude Scale Factor 3<13:8>
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Profile 3
(0x11)
47:40
55:48
Amplitude Scale Factor 3<7:0>
Phase Offset Word 3<15:8>
39:32
31:24
23:16
15:8
Phase Offset Word 3<7:0>
Frequency Tuning Word 3<31:24>
Frequency Tuning Word 3<23:16>
Frequency Tuning Word 3<15:8>
Frequency Tuning Word 3<7:0>
7:0
Rev. 0 | Page 50 of 60
AD9910
Register
Name
(Serial
Default
Value5
Bit Range
(Internal
Address)
Bit 7
(MSB)
Address)
Bit 6
Bit 5
Bit 4
Bit 3
Open
Bit 2
Bit 1
Bit 0 (LSB)
(Hex)
N/A
N/A
N/A
N/A
N/A
RAM
Profile 3
(0x11)
63:56
55:48
47:40
39:32
RAM Profile 3 Address Step Rate<15:8>
RAM Profile 3 Address Step Rate<7:0>
RAM Profile 3 Waveform End Address<9:2>
Open
RAM Profile 3 Waveform
End Address<1:0>
31:24
23:16
15:8
RAM Profile 3 Waveform Start Address<9:2>
Open
N/A
N/A
RAM Profile 3 Waveform
Start Address<1:0>
Open
No-Dwell
High
Open
Zero-
Crossing
N/A
7:0
RAM Profile 3 Mode Control<2:0>
Single Tone 63:56
Open
Amplitude Scale Factor 4<13:8>
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Profile 4
(0x12)
47:40
55:48
Amplitude Scale Factor 4<7:0>
Phase Offset Word 4<15:8>
Phase Offset Word 4<7:0>
Frequency Tuning Word 4<31:24>
Frequency Tuning Word 4<23:16>
Frequency Tuning Word 4<15:8>
Frequency Tuning Word 4<7:0>
Open
39:32
31:24
23:16
15:8
7:0
RAM
Profile 4
(0x12)
63:56
55:48
47:40
39:32
31:24
RAM Profile 4 Address Step Rate<15:8>
RAM Profile 4 Address Step Rate<7:0>
RAM Profile 4 Waveform End Address<9:2>
Open
RAM Profile 4
Waveform End
Address<1:0>
23:16
15:8
RAM Profile 4 Waveform Start Address<9:2>
Open
N/A
N/A
RAM Profile 4
Waveform Start
Address<1:0>
7:0
Open
No-Dwell
High
Open
Zero-
Crossing
RAM Profile 4 Mode Control<2:0>
N/A
Single Tone 63:56
Open
Amplitude Scale Factor 5<13:8>
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Profile 5
(0x13)
47:40
55:48
Amplitude Scale Factor 5<7:0>
Phase Offset Word 5<15:8>
Phase Offset Word 5<7:0>
Frequency Tuning Word 5<31:24>
Frequency Tuning Word 5<23:16>
Frequency Tuning Word 5<15:8>
Frequency Tuning Word 5<7:0>
Open
39:32
31:24
23:16
15:8
7:0
RAM
Profile 5
(0x13)
63:56
55:48
47:40
39:32
RAM Profile 5 Address Step Rate<15:8>
RAM Profile 5 Address Step Rate<7:0>
RAM Profile 5 Waveform End Address<9:2>
Open
RAM Profile 5 Waveform
End Address<1:0>
31:24
23:16
15:8
RAM Profile 5 Waveform Start Address <9:2>
Open
N/A
N/A
RAM Profile 5 Waveform
Start Address<1:0>
Open
No-Dwell
High
Open
Zero-
Crossing
RAM Profile 5 Mode Control<2:0>
N/A
7:0
Rev. 0 | Page 51 of 60
AD9910
Register
Name
(Serial
Default
Value5
Bit Range
(Internal
Address)
Bit 7
(MSB)
Address)
Bit 6
Open
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0 (LSB)
(Hex)
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Single Tone 63:56
Profile 6
(0x14)
47:40
Amplitude Scale Factor 6<13:8>
55:48
Amplitude Scale Factor 6<7:0>
Phase Offset Word 6<15:8>
Phase Offset Word 6<7:0>
39:32
31:24
23:16
15:8
Frequency Tuning Word 6<31:24>
Frequency Tuning Word 6<23:16>
Frequency Tuning Word 6<15:8>
Frequency Tuning Word 6<7:0>
Open
7:0
RAM
Profile 6
(0x14)
63:56>
55:48
47:40
39:32
31:24
RAM Profile 6 Address Step Rate<15:8>
RAM Profile 6 Address Step Rate<7:0>
RAM Profile 6 Waveform End Address<9:2>
Open
RAM Profile 6
Waveform End
Address<1:0>
23:16
15:8
RAM Profile 6 Waveform Start Address<9:2>
Open
N/A
N/A
AM Profile 6 Waveform
Start Address <1:0>
7:0
Open
No-Dwell
High
Open
Zero-
Crossing
RAM Profile 6 Mode Control<2:0>
N/A
Single Tone 63:56
Open
Amplitude Scale Factor 7<13:8>
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Profile 7
(0x15)
47:40
55:48
Amplitude Scale Factor 7<7:0>
Phase Offset Word 7<15:8>
Phase Offset Word 7<7:0>
Frequency Tuning Word 7<31:24>
Frequency Tuning Word 7<23:16>
Frequency Tuning Word 7<15:8>
Frequency Tuning Word 7<7:0>
Open
39:32
31:24
23:16
15:8
7:0
RAM
Profile 7
(0x15)
63:56
55:48
47:40
39:32
RAM Profile 7 Address Step Rate<15:8>
RAM Profile 7 Address Step Rate<7:0>
RAM Profile 7 Waveform End Address<9:2>
Open
RAM Profile 7 Waveform
End Address <1:0>
31:24
23:16
RAM Profile 7 Waveform Start Address<9:2>
Open
N/A
N/A
RAM Profile 7
Waveform Start Address
<1:0>
15:8
Open
No-Dwell
High
Open
Zero-
Crossing
RAM Profile 7 Mode Control<2:0>
N/A
N/A
7:0
RAM (0x16)
31:0
RAM[1023:0]<31:0>
5 N/A = not applicable.
Rev. 0 | Page 52 of 60
AD9910
REGISTER BIT DESCRIPTIONS
This section is organized in sequential order of the serial
The serial I/O port registers span an address range of 0 to 23
(0x00 to 0x16 in hexadecimal notation). This represents a total
of 24 registers. However, two of these registers are unused
yielding a total of 22 available registers. The unused registers are
Register 5 and Register 6 (0x05 and 0x06, respectively).
addresses of the registers. Each subheading includes the register
name and optional register mnemonic (in parentheses). Also
given is the serial address in hexadecimal format and the
number of bytes assigned to the register.
Following each subheading is a table containing the individual
bit descriptions for that particular register. The location of the
bit(s) in the register are indicated by a single number or a pair
of numbers separated by a colon. That is, a pair of numbers
(A:B) indicates a range of bits from the most significant (A) to
the least significant (B). For example, 5:2 implies Bit Position 5
down to Bit Position 2, inclusive, with Bit 0 identifying the LSB
of the register.
The number of bytes assigned to the registers varies from
register to register. That is, the registers are not of uniform
depth; each contains the number of bytes necessary for its
particular function. Additionally, the registers are assigned
names according to their functionality. In some cases, a register
is given a mnemonic descriptor. For example, the register at
Serial Address 0x00 is named Control Function Register 1 and
is assigned the mnemonic CFR1.
Unless otherwise stated, programmed bits are not transferred to
their internal destinations until the assertion of the I/O_UPDATE
pin or a profile change.
The following section provides a detailed description of each bit
in the AD9910 register map. Of course, for cases in which a
group of bits serve a specific function, the entire group is
considered as a binary word and described in aggregate.
Control Function Register 1 (CFR1)
Address 0x00; 4 bytes are assigned to this register.
Table 17. Bit Description for CFR1
Bit(s)
Descriptor
Explanation
31
RAM Enable
0 = disables RAM functionality (default).
1 = enables RAM functionality (required for both load/retrieve and playback operation).
See Table 12 for details; default is 002.
30:29
28:24
23
RAM Playback Destination
Not Available
Manual OSK External
Control
Ineffective unless Bits<9:8> = 102.
0 = OSK pin inoperative (default).
1 = OSK pin enabled for manual OSK control (see Output Shift Keying (OSK) section for
details).
22
Inverse Sinc Filter Enable
0 = Inverse sinc filter bypassed (default).
1 = Inverse sinc filter active.
21
Not Available
20:17
Internal Profile Control
Ineffective unless Bit 31 = 1. These bits are effective without the need for an I/O update.
See Table 14 for details. Default is 00002.
16
15
Select DDS Sine Output
Load LRR @ I/O Update
0 = cosine output of the DDS is selected (default).
1 = sine output of the DDS is selected.
Ineffective unless CFR2<19> = 1.
0 = normal operation of the digital ramp timer (default).
1 = digital ramp timer loaded any time I/O_UPDATE is asserted or a profile change occurs.
0 = normal operation of the DRG accumulator (default).
1 = the ramp accumulator is reset for one cycle of the DDS clock after which the
accumulator automatically resumes normal operation. As long as this bit remains set, the
ramp accumulator is momentarily reset each time an I/O update is asserted or a profile
change occurs. This bit is synchronized with either an I/O update or a profile change and
the next rising edge of SYNC_CLK.
14
Autoclear Digital Ramp
Accumulator
13
Autoclear Phase
Accumulator
0 = normal operation of the DDS phase accumulator (default).
1 = synchronously resets the DDS phase accumulator anytime I/O_UPDATE is asserted or a
profile change occurs.
Rev. 0 | Page 53 of 60
AD9910
Bit(s)
Descriptor
Explanation
12
Clear Digital Ramp
Accumulator
0 = normal operation of the DRG accumulator (default).
1 = asynchronous, static reset of the DRG accumulator. The ramp accumulator remains reset
as long as this bit remains set. This bit is synchronized with either an I/O update or a profile
change and the next rising edge of SYNC_CLK.
11
10
Clear Phase Accumulator
Load ARR @ I/O Update
0 = normal operation of the DDS phase accumulator (default).
1 = asynchronous, static reset of the DDS phase accumulator.
Ineffective unless Bits<9:8> = 112.
0 = normal operation of the OSK amplitude ramp rate timer (default).
1 = OSK amplitude ramp rate timer reloaded anytime I/O_UPDATE is asserted or a profile
change occurs.
9
8
7
OSK Enable
The Output Shift Keying Enable bit.
0 = OSK disabled (default).
1 = OSK enabled.
Ineffective unless Bit 9 = 1.
0 = manual OSK enabled (default).
1 = automatic OSK enabled.
This bit is effective without the need for an I/O update.
0 = clock signals to the digital core are active (default).
1 = clock signals to the digital core are disabled.
0 = DAC clock signals and bias circuits are active (default).
1 = DAC clock signals and bias circuits are disabled.
Select Auto OSK
Digital Power-Down
DAC Power-Down
6
5
REFCLK Input Power-Down This bit is effective without the need for an I/O update.
0 = REFCLK input circuits and PLL are active (default).
1 = REFCLK input circuits and PLL are disabled.
4
3
Auxiliary DAC Power-Down 0 = auxiliary DAC clock signals and bias circuits are active (default).
1 = auxiliary DAC clock signals and bias circuits are disabled.
External Power-Down
Control
0 = assertion of the EXTPWRDN pin effects full power-down (default).
1 = assertion of the EXTPWRDN pin effects fast recovery power-down.
2
1
Not Available
SDIO Input Only
0 = configures the SDIO pin for bidirectional operation; 2-wire serial programming
mode (default).
1 = configures the serial data I/O pin (SDIO) as an input only pin; 3-wire serial
programming mode.
0
LSB First
0 = configures the serial I/O port for MSB-first format (default)
1 = configures the serial I/O port for LSB-first format.
Rev. 0 | Page 54 of 60
AD9910
Control Function Register 2 (CFR2)
Address 0x01; 4 bytes are assigned to this register.
Table 18. Bit Descriptions for CFR2
Bit(s)
31:26
25
Descriptor
Explanation
Not Available
DROVER Pin Active
Enable Amplitude Scale
from Single Tone Profiles
Ineffective unless Bit 19 = 1. Refer to DROVER Pin section for details.
Ineffective if Bit 19 = 1 or CFR1<31> = 1 or CFR1<9> = 1.
0 = the amplitude scaler is bypassed and shut down for power conservation (default).
1 = the amplitude is scaled by the ASF from the active profile.
24
23
Internal I/O Update Active
This bit is effective without the need for an I/O update.
0 = serial I/O programming is synchronized with the external assertion of the
I/O_UPDATE pin, which is configured as an input pin (default).
1 = serial I/O programming is synchronized with an internally generated I/O update
signal (the internally generated signal appears at the I/O_UPDATE pin, which is
configured as an output pin).
22
SYNC_CLK Enable
0 = The SYNC_CLK pin is disabled; static Logic 0 output.
1 = the SYNC_CLK pin generates a clock signal at ¼ fSYSCLK; used for synchronization of the
serial I/O port (default).
21:20
19
Digital Ramp Destination
Digital Ramp Enable
See Table 11 for details. Default is 002. See Digital Ramp Generator (DRG) section for details.
0 = disables digital ramp generator functionality (default).
1 = enables digital ramp generator functionality.
18
17
16
Digital Ramp No-Dwell High See Digital Ramp Generator (DRG) section for details.
0 = disables no-dwell high functionality (default).
1 = enables no-dwell high functionality.
Digital Ramp No-Dwell Low See Digital Ramp Generator (DRG) section for details.
0 = disables no-dwell low functionality (default).
1 = enables no-dwell low functionality.
Read Effective FTW
0 = a serial I/O port read operation of the FTW register reports the contents of the FTW
register (default).
1 = a serial I/O port read operation of the FTW register reports the actual 32-bit word
appearing at the input to the DDS phase accumulator.
15:14
I/O Update Rate Control
Ineffective unless Bit 23 = 1. Sets the prescale ratio of the divider that clocks the auto I/O
update timer as follows:
00 = divide-by-1 (default).
01 = divide-by-2.
10 = divide-by-4.
11 = divide-by-8.
13:12
11
Not Available
PDCLK Enable
0 = the PDCLK pin is disabled and forced to a static Logic 0 state; the internal clock signal
continues to operate and provide timing to the data assembler.
1 = the internal PDCLK signal appears at the PDCLK pin (default).
10
9
PDCLK Invert
0 = normal PDCLK polarity; Q-data associated with Logic 1, I-data with Logic 0 (default).
1 = inverted PDCLK polarity.
0 = no inversion.
TxEnable Invert
1 = inversion.
8
7
Not Available
Matched Latency Enable
0 = simultaneous application of amplitude, phase, and frequency changes to the DDS
arrive at the output in the order listed (default).
1 = simultaneous application of amplitude, phase, and frequency changes to the DDS
arrive at the output simultaneously.
Rev. 0 | Page 55 of 60
AD9910
Bit(s)
Descriptor
Explanation
6
Data Assembler Hold Last
Value
Ineffective unless Bit 4 = 1.
0 = the data assembler of the parallel data port internally forces zeros on the data path
and ignores the signals on the D<15:0> and F<1:0> pins while the TxENABLE pin is
Logic 0 (default). This implies that the destination of the data at the parallel data port is
amplitude when TxENABLE is Logic 0.
1 = the data assembler of the parallel data port internally forces the last value received
on the D<15:0> and F<1:0> pins while the TxENABLE pin is Logic 1.
5
4
Sync Sample Error Mask
Parallel Data Port Enable
0 = enables the SYNC_SMP_ERR pin to indicate (active high) detection of a synchronization
pulse sampling error.
1 = the SYNC_SMP_ERR pin is forced to a static Logic 0 condition (default).
See the Parallel Data Port Modulation Mode section for more details.
0 = disables parallel data port modulation functionality (default).
1 = enables parallel data port modulation functionality.
3:0
FM Gain
See the Parallel Data Port Modulation Mode section for more details. Default is 00002.
Control Function Register 3 (CFR3)
Address 0x02; 4 bytes are assigned to this register.
Table 19. Bit Descriptions for CFR3
Bit(s)
31:30
29:27
26:24
23:22
21:19
18:16
15
Descriptor
Explanation
DRV0
Not Available
VCO SEL
Not Available
ICP
Not Available
Controls the REFCLK_OUT pin, (see Table 7 for details); default is 002.
Selects frequency band of the REFCLK PLL VCO, (see Table 8 for details); default is 1112.
Selects the charge pump current in the REFCLK PLL (see Table 9 for details); default is 1112.
REFCLK Input Divider
Bypass
0 = input divider is selected (default).
1 = input divider is bypassed.
14
REFCLK Input Divider
ResetB
0 = input divider is reset.
1 = input divider operates normally (default).
13:9
8
Not Available
PLL Enable
0 = REFCLK PLL bypassed (default).
1 = REFCLK PLL enabled.
7:1
0
N
This 7-bit number is divide modulus of the REFCLK PLL feedback divider; default is
00000002.
Not Available
Auxiliary DAC Control Register
Address 0x03; 4 bytes are assigned to this register.
Table 20. Bit Descriptions for DAC Control Register
Bit(s)
31:8
7:0
Descriptor
Not Available
FSC
Explanation
This 8-bit number controls the full-scale output current of the main DAC (see the Auxiliary
DAC section); default is 0xFF.
Rev. 0 | Page 56 of 60
AD9910
I/O Update Rate Register
Address 0x04, 4 bytes are assigned to this register. This register is effective without the need for an I/O update.
Table 21. Bit Descriptions for I/O Update Rate Register
Bit(s)
Descriptor
Explanation
31:0
I/O Update Rate
Ineffective unless CFR2<23> = 1. This 32-bit number controls the automatic I/O update
rate (see the Automatic I/O Update section for details). Default is 0xFFFFFFFF.
Frequency Tuning Word Register (FTW)
Address 0x07, 4 bytes are assigned to this register.
Table 22. Bit Descriptions for FTW Register
Bit(s)
Descriptor
Explanation
31:0
Frequency Tuning Word
32-bit frequency tuning word.
Phase Offset Word Register (POW)
Address 0x08, 2 bytes are assigned to this register.
Table 23. Bit Descriptions for POW Register
Bit(s)
Descriptor
Explanation
15:0
Phase Offset Word
16-bit phase offset word.
Amplitude Scale Factor Register (ASF)
Address 0x09, 4 bytes are assigned to this register.
Table 24. Bit Descriptions for ASF Register
Bit(s)
Descriptor
Explanation
31:16
Amplitude Ramp Rate
16-bit amplitude ramp rate value. Effective only if CFR1<9:8> = 112; see the Output Shift
Keying (OSK) section for details.
15:2
1:0
Amplitude Scale Factor
Amplitude Step Size
14-bit amplitude scale factor.
Effective only if CFR1<9:8> = 112; see the Output Shift Keying (OSK) section for details.
Rev. 0 | Page 57 of 60
AD9910
Multichip Sync Register
Address 0x0A, 4 bytes are assigned to this register.
Table 25. Multichip Sync Register
Bit(s)
Descriptor
Explanation
31:28
Sync Validation Delay
This 4-bit number sets the timing skew (in ~150 ps increments) between SYSCLK and the
delayed sync-in signal for the sync validation block in the sync receiver. Default is 00002.
27
26
25
Sync Receiver Enable
Sync Generator Enable
Sync Generator Polarity
0 = synchronization clock receiver disabled (default).
1 = synchronization clock receiver enabled.
0 = synchronization clock generator disabled (default).
1 = synchronization clock generator enabled.
0 = synchronization clock generator coincident with the rising edge of SYSCLK (default).
1 = synchronization clock generator coincident with the falling edge of SYSCLK.
24
Not Available
23:18
Sync State Preset Value
This 6-bit number is the state that the internal clock generator assumes when it receives a
sync pulse. Default is 0000002.
17:16
15:11
Not Available
Output Sync Generator
Delay
This 5-bit number sets the output delay (in ~150 ps increments) of the sync generator.
Default is 000002.
10:8
7:3
Not Available
Input Sync Receiver Delay
This 5-bit number sets the input delay (in ~150 ps increments) of the sync receiver. Default
is 000002.
2:0
Not Available
Digital Ramp Limit Register
Address 0x0B, 8 bytes are assigned to this register. This register is only effective if CFR2<19> = 1. See the Digital Ramp Generator (DRG)
section for details.
Table 26. Bit Descriptions for Digital Ramp Limit Register
Bit(s)
63:32
31:0
Descriptor
Explanation
Digital Ramp Upper Limit
Digital Ramp Lower Limit
32-bit digital ramp upper limit value.
32-bit digital ramp lower limit value.
Digital Ramp Step Size Register
Address 0x0C, 8 bytes are assigned to this register. This register is only effective if CFR2<19> = 1. See the Digital Ramp Generator (DRG)
section for details.
Table 27. Bit Descriptions for Digital Ramp Step Size Register
Bit(s)
Descriptor
Explanation
63:32
Digital Ramp Decrement
Step Size
32-bit digital ramp decrement step size value.
31:0
Digital Ramp Increment
Step Size
32-bit digital ramp increment step size value.
Digital Ramp Rate Register
Address 0x0D, 4 bytes are assigned to this register. This register is only effective if CFR2<19> = 1. See the Digital Ramp Generator (DRG)
section for details.
Table 28. Bit Descriptions for Digital Ramp Rate Register
Bit(s)
Descriptor
Explanation
31:16
Digital Ramp Negative
Slope Rate
16-bit digital ramp negative slope value that defines the time interval between decrement
values.
15:0
Digital Ramp Positive Slope 16-bit digital ramp positive slope value that defines the time interval between increment
Rate values.
Rev. 0 | Page 58 of 60
AD9910
Profile Registers
are in effect when CFR1<31> = 0, CFR2<19> = 0, and CFR2<4>
= 0. In normal operation, the active profile register is selected
using the external PROFILE<2:0> pins. However, in the specific
case when CFR1<31> = 1 and CFR1<20:17> ≠ 00002, the active
profile is selected automatically (see the RAM Ramp Up
Internal Profile Control Mode section).
There are eight consecutive serial I/O addresses (Address 0x0E
to Address 0x015) dedicated to device profiles. All eight profile
registers are either single tone profiles or RAM profiles. RAM
profiles are in effect when CFR1<31> = 1. Single tone profiles
Profile 0 to Profile 7—Single Tone Register
Address 0x0E to Address 0x15, 8 bytes are assigned to this register.
Table 29. Bit Descriptions for Profile 0 to Profile 7 Single Tone Register
Bit(s)
63:62
61:48
47:32
31:0
Descriptor
Explanation
Not Available
Amplitude Scale Factor
Phase Offset Word
Frequency Tuning Word
This 14-bit number controls the DDS output amplitude.
This 16-bit number controls the DDS phase offset.
This 32-bit number controls the DDS frequency.
Profile 0 to Profile 7—RAM Register
Address 0x0E to Address 0x15, 8 bytes are assigned to this register.
Table 30. Bit Descriptions for Profile 0 to Profile 7 RAM Register
Bit(s)
63:56
55:40
39:30
29:24
23:14
13:6
Descriptor
Explanation
Not Available
Address Step Rate
Waveform End Address
Not Available
Waveform Start Address
Not Available
16-bit address step rate value.
10-bit waveform end address.
10-bit waveform start address.
5
No-Dwell High
Effective only when the RAM mode is in ramp up.
0 = when the RAM state machine reaches the end address, it halts.
1 = when the RAM state machines reaches the end address, it jumps to the start address
and halts.
4
3
Not Available
Zero-Crossing
Effective only when in RAM mode, direct switch.
0 = zero-crossing function disabled.
1 = zero-crossing function enabled.
See Table 13 for details.
2:0
RAM Mode Control
Rev. 0 | Page 59 of 60
AD9910
OUTLINE DIMENSIONS
16.00 BSC SQ
1.20
MAX
0.75
0.60
0.45
14.00 BSC SQ
76
76
75
100
100
1
75
1
PIN 1
EXPOSED
PAD
5.00 SQ
TOP VIEW
(PINS DOWN)
0° MIN
1.05
1.00
0.95
0.20
0.09
7°
BOTTOM VIEW
(PINS UP)
51
51
25
25
26
50
50
26
3.5°
0°
0.08 MAX
COPLANARITY
0.50 BSC
LEAD PITCH
0.27
0.22
0.17
VIEW A
0.15
0.05
SEATING
PLANE
VIEW A
ROTATED 90° CCW
COMPLIANT TO JEDEC STANDARDS MS-026-AED-HD
[Note: Exposed Pad should be solder to ground]
Figure 58. 100-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP]
(SV-100-4)
Dimensions shown in millimeters
ORDERING GUIDE
Model
Temperature Range Package Description
Package Option
AD9910BSVZ1
–40°C to +85°C
–40°C to +85°C
100-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP]
100-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP]
Evaluation Board
SV-100-4
SV-100-4
AD9910BSVZ-REEL1
AD9910/PCBZ1
1 Z = RoHS Compliant Part.
©2007 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06479-0-5/07(0)
Rev. 0 | Page 60 of 60
相关型号：
AD9913BCPZ
PARALLEL, WORD INPUT LOADING, 10-BIT DAC, QCC32, 5 X 5 MM, ROHS COMPLIANT, MO-220VHHD-2, LFCSP-32
ROCHESTER
©2020 ICPDF网 联系我们和版权申明