ADA4937-2_15_技术文档

Ultralow Distortion

Differential ADC Driver

Data Sheet

ADA4937-1/ADA4937-2

FEATURES

FUNCTIONAL BLOCK DIAGRAMS

Extremely low harmonic distortion (HD)

−112 dBc HD2 @ 10 MHz

−84 dBc HD2 @ 70 MHz

−77 dBc HD2 @ 100 MHz

−102 dBc HD3 @ 10 MHz

−91 dBc HD3 @ 70 MHz

ADA4937-1

12 PD

–FB

+IN

–IN

1

2

3

4

11 –OUT

10 +OUT

+FB

9

V

OCM

−84 dBc HD3 @ 100 MHz

Low input voltage noise: 2.2 nV/√Hz

High speed

−3 dB bandwidth of 1.9 GHz, G = 1

Slew rate: 6000 V/µs, 25% to 75%

Fast overdrive recovery of 1 ns

0.5 mV typical offset voltage

Externally adjustable gain

Differential-to-differential or single-ended-to-differential

operation

Adjustable output common-mode voltage

Single-supply operation: 3.3 V to 5 V

Figure 1. ADA4937-1

–IN1

+FB1

1

18 +OUT1

17 V

2

3

4

5

6

OCM1

16 –V

15

14

+V

S2

S1

ADA4937-2

–V

+V

S1

–FB2

+IN2

PD2

13 –OUT2

APPLICATIONS

ADC drivers

Single-ended-to-differential converters

IF and baseband gain blocks

Differential buffers

Figure 2. ADA4937-2

–55

–60

HD2, V = 5.0V

S

HD3, V = 5.0V

HD2, V = 3.3V

HD3, V = 3.3V

Line drivers

S

–65

S

GENERAL DESCRIPTION

–70

The ADA4937-xis a low noise, ultralow distortion, high speed

differential amplifier. It is an ideal choice for driving high

performance ADCs with resolutions up to 16 bits from dc to

100 MHz. The adjustable level of the output common mode

allows the ADA4937-x to match the input of the ADC. The

internal common-mode feedback loop also provides exceptional

output balance as well as suppression of even-order harmonic

distortion products.

–75

–80

–85

–90

–95

–100

–105

–110

–115

With the ADA4937-x, differential gain configurations are easily

realized with a simple external feedback network of four resis-

tors that determine the closed-loop gain of the amplifier.

1

10

100

FREQUENCY (MHz)

Figure 3. Harmonic Distortion vs. Frequency

The ADA4937-x is available in a Pb-free, 3 mm × 3 mm, 16-lead

LFCSP (ADA4937-1, single) or a Pb-free, 4 mm × 4 mm, 24-lead

LFCSP (ADA4937-2, dual). The pinout has been optimized to

facilitate PCB layout and minimize distortion. The ADA4937-x

is specified to operate over the automotive (−40°C to +105°C)

temperature range and between 3.3 V and 5 V supplies.

The ADA4937-x is fabricated using Analog Devices, Inc., proprie-

tary silicon-germanium (SiGe), complementary bipolar process,

enabling it to achieve very low levels of distortion with an input

voltage noise of only 2.2 nV/√Hz. The low dc offset and excellent

dynamic performance of the ADA4937-x make it well-suited

for a wide variety of data acquisition and signal processing appli-

cations.

Rev. D

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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Technical Support

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IMPORTANT LINKS for the ADA4937-1_4937-2*

Last content update 08/29/2013 11:25 am

PARAMETRIC SELECTION TABLES

DESIGN TOOLS, MODELS, DRIVERS & SOFTWARE

ADI DiffAmpCalc™

Find Similar Products By Operating Parameters

High Speed Amplifiers Selection Table

ADA4937 SPICE Macro Model

DOCUMENTATION

PRODUCT RECOMMENDATIONS & REFERENCE DESIGNS

CN-0051: Driving the AD9233/9246/9254 ADCs in AC-Coupled

Baseband Applications

AN-1026: High Speed Differential ADC Driver Design Considerations

AN-0990: Terminating a Differential Amplifier in Single-Ended Input

Applications

AN-0992: Active Filter Evaluation Board for Differential Amplifiers

AN-282: Fundamentals of Sampled Data Systems

DESIGN COLLABORATION COMMUNITY

AN-649: Using the Analog Devices Active Filter Design Tool

AN-584: Using the AD813X Differential Amplifier

AN-589: Ways to Optimize the Performance of a Difference Amplifie

MT-218: Multiple Feedback Band-Pass Design Example

MT-076: Differential Driver Analysis

Collaborate Online with the ADI support team and other designers

about select ADI products.

Follow us on Twitter: www.twitter.com/ADI_News

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MT-075: Differential Drivers for High Speed ADCs Overview

Designing 1-ppm DAC Accuracy into Instrumentation Applications

Part 1

Designing 1-ppm DAC Accuracy into Instrumentation Applications

Part 2

DESIGN SUPPORT

Submit your support request here:

Linear and Data Converters

Embedded Processing and DSP

“Rules of the Road” for High-Speed Differential ADC Drivers

RF Source Booklet

FOR THE ADA4937-1

Telephone our Customer Interaction Centers toll free:

CN-0051: Driving the AD9233/9246/9254 ADCs in AC-Coupled

Americas:

Europe:

China:

1-800-262-5643

00800-266-822-82

4006-100-006

Baseband Applications

A Stress-Free Method for Choosing High-Speed Op Amps

India:

1800-419-0108

8-800-555-45-90

UG-132: Evaluation Board User Guide for the ADA492x-1 and

ADA493x-1 Family of Differential Amplifiers

Russia:

Ask The Application Engineer 36, Wideband A/D Converter Front-End

Design Considerations II: Amplifier-or Transformer Drive for the ADC?

Quality and Reliability

Lead(Pb)-Free Data

FOR THE ADA4937-2

UG-018: Evaluation Board for Dual High Speed Differential Amplifiers

SAMPLE & BUY

ADA4937-1

EVALUATION KITS & SYMBOLS & FOOTPRINTS

ADA4937-2

View the Evaluation Boards and Kits page for the ADA4937-1

View Price & Packaging

View the Evaluation Boards and Kits page for the ADA4937-2

Symbols and Footprints for the ADA4937-1

Request Evaluation Board

Request Samples

Check Inventory & Purchase

Symbols and Footprints for the ADA4937-2

Find Local Distributors

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Note: Dynamic changes to the content on this page (labeled 'Important Links') does not

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This content may be frequently modified.

ADA4937-1/ADA4937-2

Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

Analyzing an Application Circuit ............................................ 18

Setting the Closed-Loop Gain .................................................. 18

Estimating the Output Noise Voltage...................................... 18

Impact of Mismatches in the Feedback Networks................. 19

Applications....................................................................................... 1

General Description......................................................................... 1

Functional Block Diagrams............................................................. 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

5 V Operation ............................................................................... 3

3.3 V Operation ............................................................................ 5

Absolute Maximum Ratings............................................................ 7

Thermal Resistance ...................................................................... 7

ESD Caution.................................................................................. 7

Pin Configurations and Function Descriptions ........................... 8

Typical Performance Characteristics ............................................. 9

Test Circuits..................................................................................... 16

Terminology .................................................................................... 17

Theory of Operation ...................................................................... 18

Calculating the Input Impedance for an Application

Circuit .......................................................................................... 19

Input Common-Mode Voltage Range in Single-Supply

Applications ................................................................................ 20

Setting the Output Common-Mode Voltage .......................... 20

Power-Down Operation............................................................ 20

Layout, Grounding, and Bypassing.............................................. 22

High Performance ADC Driving ................................................. 23

3.3 V Operation.......................................................................... 25

Outline Dimensions....................................................................... 26

Ordering Guide .......................................................................... 26

REVISION HISTORY

8/13—Rev. C to Rev. D

11/07—Rev. 0 to Rev. A

Changes to Input Bias Current Parameter, Table 1...................... 3

Changes to Input Bias Current Parameter, Table 3...................... 5

Updated Outline Dimensions ....................................................... 26

Added the ADA4937-2......................................................Universal

Changes to Features ..........................................................................1

Changes to Specifications.................................................................3

Changes to Figure 4...........................................................................7

Changes to Typical Performance Characteristics..........................9

Inserted Figure 44........................................................................... 15

Added the Terminating a Single-Ended Input Section ............. 19

Changes to Table 10 and Table 11 ................................................ 21

Changes to Layout, Grounding, and Bypassing Section ........... 22

Inserted Figure 59, Figure 60, and Figure 61 .............................. 22

Updated Outline Dimensions....................................................... 26

Changes to Ordering Guide.......................................................... 26

3/10—Rev. B to Rev. C

Changes to Table 2, Power Supply Parameter............................... 4

Changes to Table 4, Power Supply Parameter............................... 6

Changes to Figure 43...................................................................... 15

Added the Power-Down Operation Section............................... 20

10/09—Rev. A to Rev. B

Changes to General Description Section ...................................... 1

Changes to Table 1............................................................................ 3

Changes to Operating Temperature Range Parameter, Table 2.. 4

Changes to Table 3............................................................................ 5

Changes to Figure 4.......................................................................... 7

Changes to Figure 5 and Figure 6................................................... 8

Added EP Row to Table 7 and EP Row to Table 8........................ 8

Added Figure 46, Figure 47, and Figure 48; Renumbered

Sequentially ..................................................................................... 15

Changes to Table 9.......................................................................... 18

Changes to Input Common-Mode Voltage Range in Single-

Supply Applications Section.......................................................... 20

Changes to Ordering Guide .......................................................... 26

5/07—Revision 0: Initial Version

Rev. D | Page 2 of 28

Data Sheet

ADA4937-1/ADA4937-2

SPECIFICATIONS

5 V OPERATION

T_A= 25°C, +V_S= 5 V, −V_S= 0 V, V _OCM= +V_S/2, R_T= 61.9 Ω, R_G= R_F= 200 Ω, G = +1, R_{L, dm}= 1 kΩ, unless otherwise noted. All specifica-

tions refer to single-ended input and differential outputs, unless otherwise noted.

±±_INto ±OUT Performance

Table 1.

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

DYNAMIC PERFORMANCE

−3 dB Small Signal Bandwidth

Bandwidth for 0.1 dB Flatness

Large Signal Bandwidth

Slew Rate

V_{OUT, dm}= 0.1 V p-p

V_{OUT, dm}= 2 V p-p

V_{OUT, dm}= 2 V p-p; 25% to 75%

V_{OUT, dm}= 2 V p-p

1900

200

1700

6000

7

MHz

V/µs

ns

Settling Time

Overdrive Recovery Time

NOISE/HARMONIC PERFORMANCE

Second Harmonic

V_IN= 0 V to 1.5 V step; G = 3.16

See Figure 51 for distortion test circuit

V_{OUT, dm}= 2 V p-p; 10 MHz

V_{OUT, dm}= 2 V p-p; 70 MHz

V_{OUT, dm}= 2 V p-p; 100 MHz

V_{OUT, dm}= 2 V p-p; 10 MHz

V_{OUT, dm}= 2 V p-p; 70 MHz

V_{OUT, dm}= 2 V p-p; 100 MHz

f₁= 70 MHz; f₂= 70.1 MHz; V_{OUT, dm}= 2 V p-p

f = 100 kHz

<1

ns

−112

−84

−77

−102

−91

−84

−91

2.2

dBc

nV/√Hz

pA/√Hz

dB

Third Harmonic

IMD

Voltage Noise (RTI)

Input Current Noise

Noise Figure

Crosstalk (ADA4937-2)

INPUT CHARACTERISTICS

Offset Voltage

f = 100 kHz

4

15

−72

G = 4; R_T= 136 Ω; R_F= 200 Ω; R_G= 37 Ω; f = 100 MHz

f = 100 MHz

dB

V_{OS, dm}= V_{OUT, dm}/2; V_DIN+= V_DIN−= 2.5 V

T_MINto T_MAXvariation

−2.5

−50

−2

0.5

1

−30

0.01

+0.5

6

3

1

+2.5

−10

+2

mV

µV/°C

µA

µA/°C

µA

MΩ

pF

Input Bias Current

T_MINto T_MAXvariation

Input Offset Current

Input Resistance

Differential

Common mode

Input Capacitance

Input Common-Mode Voltage

CMRR

0.3 to 3.0

−80

V

dB

∆V_{OUT, dm}/∆V_{IN, cm}; ∆V_{IN, cm}= 1 V

−69

0.9

OUTPUT CHARACTERISTICS

Output Voltage Swing

Linear Output Current

Output Balance Error

Maximum ∆V_OUT; single-ended output; R_F= R_G= 10 kΩ

Per amplifier; R_{L, dm}= 20 Ω; f = 10 MHz

∆V_{OUT, cm}/∆V_{OUT, dm}; ∆V_{OUT, dm}= 1 V; f = 10 MHz;

see Figure 50 for test circuit

4.1

V

mA

dB

70

−61

Rev. D | Page 3 of 28

ADA4937-1/ADA4937-2

Data Sheet

V_OCMto ±OUT Performance

Table 2.

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

V_OCMDYNAMIC PERFORMANCE

−3 dB Bandwidth

Slew Rate

Input Voltage Noise (RTI)

V_OCMINPUT CHARACTERISTICS

Input Voltage Range

Input Resistance

Input Offset Voltage

Input Bias Current

V_OCMCMRR

440

1150

7.5

MHz

V/µs

nV/√Hz

V_IN= 1.5 V to 3.5 V; 25% to 75%

f = 100 kHz

1.2

8

3.8

12

7.1

V

10

2

0.5

−75

0.98

kΩ

mV

µA

dB

V/V

V_{OS, cm}= V_{OUT, cm}; V_DIN+= V_DIN−= +V_S/2

ΔV_{OUT, dm}/ΔV_OCM; ΔV_OCM= 1 V

ΔV_{OUT, cm}/ΔV_OCM; ΔV_OCM= 1 V

−70

0.97

Gain

1.00

POWER SUPPLY

Operating Range

Quiescent Current per Amplifier

3.0

38.0

5.25

42.0

V

Enabled

39.5

17

0.3

mA

µA/°C

mA

dB

T_MINto T_MAXvariation

Powered down

ΔV_{OUT, dm}/ΔV_S; ΔV_S= 1 V

0.02

−70

0.5

Power Supply Rejection Ratio

POWER-DOWN (PD)

−90

PD Input Voltage

Powered down

Enabled

≤1

≥2

1

V

µs

ns

Turn-Off Time

Turn-On Time

200

PD Bias Current per Amplifier

Enabled

PD = 5 V

PD = 0 V

10

30

50

µA

°C

Powered Down

−300

−40

−200

−150

+105

OPERATING TEMPERATURE RANGE

Rev. D | Page 4 of 28

Data Sheet

ADA4937-1/ADA4937-2

3.3 V OPERATION

T_A= 25°C, +V_S= 3.3 V, −V_S= 0 V, V _OCM= +V_S/2, R_T= 61.9 Ω, R_G= R_F= 200 Ω, G = 1, R_{L, dm}= 1 kΩ, unless otherwise noted. All

specifications refer to single-ended input and differential outputs, unless otherwise noted.

±±_INto ±OUT Performance

Table 3.

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

DYNAMIC PERFORMANCE

−3 dB Small Signal Bandwidth

Bandwidth for 0.1 dB Flatness

Large Signal Bandwidth

Slew Rate

V_{OUT, dm}= 0.1 V p-p

V_{OUT, dm}= 2 V p-p

V_{OUT, dm}= 2 V p-p; 25% to 75%

V_{OUT, dm}= 2 V p-p

1800

200

1300

4000

7

MHz

V/µs

ns

Settling Time

Overdrive Recovery Time

NOISE/HARMONIC PERFORMANCE

Second Harmonic

V_IN= 0 V to 1.0 V step; G = 3.16

See Figure 51 for distortion test circuit

V_{OUT, dm}= 2 V p-p; 10 MHz

V_{OUT, dm}= 2 V p-p; 70 MHz

V_{OUT, dm}= 2 V p-p; 100 MHz

V_{OUT, dm}= 2 V p-p; 10 MHz

V_{OUT, dm}= 2 V p-p; 70 MHz

V_{OUT, dm}= 2 V p-p; 100 MHz

f₁= 70 MHz; f₂= 70.1 MHz; V_{OUT, dm}= 2 V p-p

f = 100 kHz

<1

ns

−113

−85

−77

−95

−77

−71

−87

2.2

dBc

nV/√Hz

pA/√Hz

dB

Third Harmonic

IMD

Voltage Noise (RTI)

Input Current Noise

Noise Figure

Crosstalk (ADA4937-2)

INPUT CHARACTERISTICS

Offset Voltage

f = 100 kHz

4

15

−72

G = 4; R_T= 136 Ω; R_F= 200 Ω; R_G= 37 Ω; f = 100 MHz

f = 100 MHz

dB

V_{OS, dm}= V_{OUT, dm}/2; V_DIN+= V_DIN−= +V_S/2

T_MINto T_MAXvariation

−2.5

−50

0.5

1

−30

0.01

6

3

1

+2.5

−10

mV

µV/°C

µA

µA/°C

MΩ

pF

Input Bias Current

Input Resistance

T_MINto T_MAXvariation

Differential

Common mode

Input Capacitance

Input Common-Mode Voltage

CMRR

0.3 to 1.2

−80

V

dB

∆V_{OUT, dm}/∆V_{IN, cm}; ∆V_{IN, cm}= 1 V

−67

0.8

OUTPUT CHARACTERISTICS

Output Voltage Swing

Linear Output Current

Output Balance Error

Maximum ∆V_OUT; single-ended output; R_F= R_G= 10 kΩ

Per amplifier; R_{L, dm}= 20 Ω; f = 10 MHz

∆V_{OUT, cm}/∆V_{OUT, dm}; ∆V_{OUT, dm}= 1 V; f = 10 MHz;

see Figure 50 for test circuit

2.5

V

mA

dB

47

−61

Rev. D | Page 5 of 28

ADA4937-1/ADA4937-2

Data Sheet

V_OCMto ±OUT Performance

Table 4.

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

V_OCMDYNAMIC PERFORMANCE

−3 dB Bandwidth

Slew Rate

Input Voltage Noise (RTI)

V_OCMINPUT CHARACTERISTICS

Input Voltage Range

Input Resistance

Input Offset Voltage

Input Bias Current

V_OCMCMRR

440

900

7.5

MHz

V/µs

nV/√Hz

V_IN= 0.9 V to 2.4 V; 25% to 75%

f = 100 kHz

1.2

2.1

7.1

V

10

2

0.5

−75

0.98

kΩ

mV

µA

dB

V/V

V_{OS, cm}= V_{OUT, cm}; V_DIN+= V_DIN−= 1.67 V

∆V_{OUT, dm}/∆V_OCM; ∆V_OCM= 1 V

∆V_{OUT, cm}/∆V_OCM; ∆V_OCM= 1 V

−70

0.97

Gain

1.00

POWER SUPPLY

Operating Range

Quiescent Current per Amplifier

3.0

36

5.25

40

V

Enabled

38

17

0.2

−90

mA

µA/°C

mA

dB

T_MINto T_MAXvariation

Powered down

∆V_{OUT, dm}/∆V_S; ∆V_S= 1 V

0.02

−70

0.5

Power Supply Rejection Ratio

POWER-DOWN (PD)

PD Input Voltage

Powered down

Enabled

≤1

≥2

1

V

µs

ns

Turn-Off Time

Turn-On Time

200

PD Bias Current per Amplifier

Enabled

PD = 3.3 V

PD = 0 V

10

20

30

µA

°C

Powered Down

−200

−40

−120

−100

+105

OPERATING TEMPERATURE RANGE

Rev. D | Page 6 of 28

Data Sheet

ADA4937-1/ADA4937-2

ABSOLUTE MAXIMUM RATINGS

The power dissipated in the package (P_D) is the sum of the

quiescent power dissipation and the power dissipated in the

package due to the load drive. The quiescent power is the voltage

between the supply pins (V_S) times the quiescent current (I_S).

The power dissipated due to the load drive depends upon the

particular application. The power due to load drive is calculated

by multiplying the load current by the associated voltage drop

across the device. RMS voltages and currents must be used in

these calculations.

Table 5.

Parameter

Rating

Supply Voltage

5.5 V

Power Dissipation

See Figure 4

−65°C to +125°C

−40°C to +105°C

300°C

Storage Temperature Range

Operating Temperature Range

Lead Temperature (Soldering, 10 sec)

Junction Temperature

150°C

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

Airflow increases heat dissipation, effectively reducing θ_JA. In

addition, more metal directly in contact with the package

leads/exposed pad from metal traces, through holes, ground,

and power planes reduces θ_JA.

Figure 4 shows the maximum safe power dissipation in the

package vs. the ambient temperature for the ADA4937-1 single

16-lead LFCSP (95°C/W), and the ADA4937-2 dual 24-lead

LFCSP (67°C/W) on a JEDEC standard 4-layer board.

3.5

THERMAL RESISTANCE

θ_JAis specified for the device (including exposed pad) soldered

to a high thermal conductivity 2s2p circuit board, as described

in EIA/JESD51-7.

3.0

2.5

Table 6. Thermal Resistance

Package Type

ADA4937-2

θ_JA

95

67

Unit

°C/W

2.0

16-Lead LFCSP (Exposed Pad)

24-Lead LFCSP (Exposed Pad)

1.5

ADA4937-1

1.0

Maximum Power ±issipation

The maximum safe power dissipation in the ADA4937-x packages

is limited by the associated rise in junction temperature (T_J) on

the die. At approximately 150°C, which is the glass transition

temperature, the plastic changes its properties. Even temporarily

exceeding this temperature limit can change the stresses that the

package exerts on the die, permanently shifting the parametric

performance of the ADA4937-x. Exceeding a junction

0.5

0

–40 –30 –20 –10

0

10 20 30 40 50 60 70 80 90 100 110

AMBIENT TEMPERATURE (°C)

Figure 4. Maximum Power Dissipation vs. Temperature, 4-Layer Board

ESD CAUTION

temperature of 150°C for an extended period can result in

changes in the silicon devices, potentially causing failure.

Rev. D | Page 7 of 28

ADA4937-1/ADA4937-2

Data Sheet

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

PIN 1

INDICATOR

PIN 1

INDICATOR

–IN1

+FB1

1

2

3

4

5

6

18 +OUT1

17 V

12 PD

–FB

+IN

–IN

1

2

3

4

OCM1

11 –OUT

10 +OUT

ADA4937-1

TOP VIEW

(Not to Scale)

16 –V

+V

ADA4937-2

TOP VIEW

(Not to Scale)

S2

S1

–V

15

14

+V

S1

–FB2

+IN2

PD2

+FB

9 V

OCM

13 –OUT2

NOTES

1. EXPOSED PADDLE. THE EXPOSED PAD IS NOT

ELECTRICALLY CONNECTED TO THE DEVICE. IT IS

TYPICALLY SOLDERED TO GROUND OR A POWER

PLANE ON THE PCB THAT IS THERMALLY CONDUCTIVE.

NOTES

1. EXPOSED PADDLE. THE EXPOSED PAD IS NOT

ELECTRICALLY CONNECTED TO THE DEVICE. IT IS

TYPICALLY SOLDERED TO GROUND OR A POWER

PLANE ON THE PCB THAT IS THERMALLY CONDUCTIVE.

Figure 5. ADA4937-1 Pin Configuration

Figure 6. ADA4937-2 Pin Configuration

Table 7. ADA4937-1 Pin Function Descriptions

Table 8. ADA4937-2 Pin Function Descriptions

Pin No. Mnemonic Description

Pin No.

Mnemonic

Description

1

−FB

Negative Output for Feedback

Component Connection.

Positive Input Summing Node.

Negative Input Summing Node.

Positive Output for Feedback

Component Connection.

Positive Supply Voltage.

Output Common-Mode Voltage.

Positive Output for Load Connection.

Negative Output for Load Connection.

Power-Down Pin.

1

2

3, 4

5

6

7

8

9, 10

11

12

−IN1

+FB1

+V_S1

−FB2

+IN2

−IN2

+FB2

+V_S2

V_OCM2

+OUT2

−OUT2

PD2

Negative Input Summing Node 1.

Positive Output Feedback Pin 1.

Positive Supply Voltage 1.

Negative Output Feedback Pin 2.

Positive Input Summing Node 2.

Negative Input Summing Node 2.

Positive Output Feedback Pin 2.

Positive Supply Voltage 2.

Output Common-Mode Voltage 2.

Positive Output 2.

2

3

4

+IN

−IN

+FB

5 to 8

9

10

11

12

+V_S

V_OCM

+OUT

−OUT

PD

13

14

Negative Output 2.

Power-Down Pin 2.

13 to 16 −V_S

EP

Negative Supply Voltage.

Exposed Paddle. The exposed pad is not

electrically connected to the device. It is

typically soldered to ground or a power

plane on the PCB that is thermally

conductive.

15, 16

17

18

19

20

−V_S2

Negative Supply Voltage 2.

Output Common-Mode Voltage 1.

Positive Output 1.

Negative Output 1.

Power-Down Pin 1.

V_OCM1

+OUT1

−OUT1

PD1

21, 22

23

24

−V_S1

−FB1

+IN1

Negative Supply Voltage 1.

Negative Output Feedback Pin 1.

Positive Input Summing Node 1.

EP

Exposed Paddle. The exposed pad is

not electrically connected to the

device. It is typically soldered to

ground or a power plane on the PCB

that is thermally conductive.

Rev. D | Page 8 of 28

Data Sheet

ADA4937-1/ADA4937-2

TYPICAL PERFORMANCE CHARACTERISTICS

T_A= 25°C, +V_S= 5 V, −V_S= 0 V, V _{OUT, dm}= 2 V p-p, V_OCM= +V_S/2, R_T= 61.9 Ω, R_G= R_F= 200 Ω, G = 1, R_{L, dm}= 1 kΩ, unless otherwise

noted. Refer to Figure 49 for the test setup circuit.

6

3

0

–3

–6

–9

–12

–15

–3

–6

–9

–12

–15

G = +1, R = 200Ω

F

G = +2, R = 402Ω

F

G = +5, R = 402Ω

F

1

10

100

FREQUENCY (MHz)

1000

1

10

100

FREQUENCY (MHz)

1000

Figure 7. Small Signal Frequency Response for Various Gains,

V_{OUT, dm}= 100 mV p-p

Figure 10. Large Signal Frequency Response for Various Gains

6

V

= 3.3V

= 5.0V

V

= 3.3V

= 5.0V

S

3

0

3

0

–3

–6

–9

–12

–15

–12

–15

1

10

100

1000

1

10

100

1000

FREQUENCY (MHz)

Figure 11. Large Signal Frequency Response for Various Supplies

Figure 8. Small Signal Frequency Response for Various Supplies,

V_{OUT, dm}= 100 mV p-p

6

+105°C

+25°C

–40°C

3

0

–3

0

–3

–6

–9

–12

1

10

100

1000

1

10

100

1000

FREQUENCY (MHz)

Figure 9. Small Signal Frequency Response for Various Temperatures,

V_{OUT, dm}= 100 mV p-p

Figure 12. Large Signal Frequency Response for Various Temperatures

Rev. D | Page 9 of 28

ADA4937-1/ADA4937-2

Data Sheet

6

3

R

= 1kΩ

= 100Ω

= 200Ω

R

= 1kΩ

= 100Ω

= 200Ω

L

3

0

–3

–6

–9

–3

–6

–9

1

10

100

1000

1

10

100

1000

FREQUENCY (MHz)

Figure 13. Small Signal Frequency Response for Various Loads,

V_{OUT, dm}= 100 mV p-p

Figure 16. Large Signal Frequency Response for Various Loads

6

3

6

3

0

–3

–6

–9

–12

–3

–6

–9

–12

V

= 3.3V, G = +1, R = 200Ω

F

V

= 3.3V, G = +1, R = 200Ω

F

S

= 3.3V, G = +2, R = 402Ω

F

= 3.3V, G = +5, R = 402Ω

F

–15

1

10

100

FREQUENCY (MHz)

1000

1

10

100

FREQUENCY (MHz)

1000

Figure 17. Large Signal Frequency Response for Various Gains, V_S= 3.3 V

Figure 14. Small Signal Frequency Response for Various Gains,

V_S= 3.3 V, V_{OUT, dm}= 100 mV p-p

6

3

0

–3

–6

–9

–3

–6

–9

–12

–15

G = +1, R = 348Ω

F

G = +2, R = 348Ω

F

G = +5, R = 348Ω

F

–15

1

10

100

1000

1

10

100

FREQUENCY (MHz)

1000

FREQUENCY (MHz)

Figure 15. Small Signal Frequency Response for Various Gains,

_{OUT, dm}= 100 mV p-p, R_F= 348 Ω

Figure 18. Large Signal Frequency Response for Various Gains, R_F= 348 Ω

V

Rev. D | Page 10 of 28

Data Sheet

ADA4937-1/ADA4937-2

3

–50

–60

HD2, G = +1, R = 200Ω

V

= 1.0V

= 2.5V

= 3.9V

F

OCM

HD3, G = +1, R = 200Ω

V

F

OCM

HD2, G = +2, R = 402Ω

F

HD3, G = +2, R = 402Ω

0

–3

F

–70

–80

–90

–6

–100

–110

–120

–9

–12

1

10

100

1000

1

10

100

FREQUENCY (MHz)

Figure 19. Small Signal Frequency Response

for Various V_OCM

Figure 22. Harmonic Distortion vs. Frequency and Gain

–50

HD2, R = 1kΩ

L

1.5

1.4

1.3

1.2

1.1

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

HD3, R = 1kΩ

L

R

= 1kΩ, ADA4937-1

= 100Ω, ADA4937-1

= 1kΩ, ADA4937-2

= 100Ω, ADA4937-2

L

HD2, R = 200Ω

–60

–70

L

HD3, R = 200Ω

L

–80

–90

–100

–110

–120

–0.1

–0.2

–0.3

–0.4

–0.5

1

10

FREQUENCY (MHz)

100

1

10

100

1000

FREQUENCY (MHz)

Figure 23. Harmonic Distortion vs. Frequency and Load

Figure 20. 0.1 dB Flatness Response for Various Loads

–50

HD2, V = 3.3V

S

–55

–60

HD3, V = 3.3V

HD2, V = 5.0V

S

–60

–70

HD2, V = 5.0V

S

HD3, V = 5.0V

S

HD3, V = 5.0V

HD2, V = 3.3V

S

–65

HD3, V = 3.3V

S

–70

–80

–75

–80

–90

–85

–100

–110

–120

–130

–90

–95

–100

–105

–110

–115

–1

0

1

2

3

4

5

6

7

1

10

100

V

(V)

OUT

FREQUENCY (MHz)

Figure 24. Harmonic Distortion vs. V_OUTand Supply Voltage

Figure 21. Harmonic Distortion vs. Frequency and Supply Voltage

Rev. D | Page 11 of 28

ADA4937-1/ADA4937-2

Data Sheet

–30

0

–20

HD2, f = 10MHz

HD3, f = 10MHz

HD2, f = 75MHz

HD3, f = 75MHz

–40

–50

–60

–70

–40

–60

–80

–90

–80

–100

–110

–120

–100

–120

1.0

1.5

2.0

2.5

3.0

3.5

4.0

69.4

69.6

69.8

70.0

70.2

70.4

70.6

V

(V)

FREQUENCY (MHz)

OCM

Figure 25. Harmonic Distortion vs. V_OCMand Frequency

Figure 28. 70 MHz Intermodulation Distortion

–30

–40

–50

–60

–70

–40

–50

–60

–70

–80

–90

–100

HD2, f = 30MHz

HD3, f = 30MHz

HD2, f = 75MHz

HD3, f = 75MHz

R

= 200Ω

L

1

10

100

1000

1.1

1.2

1.3

1.4

1.5

1.6

(V)

1.7

1.8

1.9

2.0

FREQUENCY (MHz)

V

OCM

Figure 29. CMRR vs. Frequency

Figure 26. Harmonic Distortion vs. V_OCMand Frequency, V_S= 3.3 V

–10

–20

–30

–40

–50

–60

–50

HD2, 1V p-p

HD3, 1V p-p

HD2, 2V p-p

R

= 200Ω

L

–60

HD3, 2V p-p

–70

–80

–90

–100

–110

–120

–130

1

10

100

1000

1

10

100

FREQUENCY (MHz)

Figure 27. Harmonic Distortion vs. Frequency and V_OUT, V_S= 3.3 V

Figure 30. Output Balance vs. Frequency

Rev. D | Page 12 of 28

Data Sheet

ADA4937-1/ADA4937-2

–30

V

28

26

24

22

20

18

16

14

12

10

PSRR, V = 3.3V

G = +1

G = +2

G = +4

OUT, dm

S

V

PSRR, V = 5.0V

S

OUT, dm

–40

–50

–60

–70

–80

–90

–100

1

10

100

1000

10

100

FREQUENCY (MHz)

Figure 31. PSRR vs. Frequency, R_L= 200 Ω

Figure 34. Noise Figure vs. Frequency

0

5

4

3

2

1

0

S11

S22

–5

–10

–15

–20

–25

–30

–35

–40

–45

–50

–55

–60

–65

V

× 3.16

IN

V

OUT, dm

–1

–2

–3

–4

–5

1

10

100

1000

TIME (4ns/DIV)

FREQUENCY (MHz)

Figure 32. Return Loss (S11, S22) vs. Frequency

Figure 35. Overdrive Recovery Time (Pulse Input)

5

4

–55

–60

SFDR, R = 1kΩ

L

V

× 3

IN

OUT, dm

SFDR, R = 200Ω

L

–65

3

–70

2

–75

1

–80

–85

0

–90

–1

–2

–3

–4

–5

–95

–100

–105

–110

–115

+V = +2.5V

S

–V = –2.5V

S

0

100

200

300

400

500

600

1

10

FREQUENCY (MHz)

100

TIME (ns)

Figure 33. Spurious-Free Dynamic Range vs. Frequency and Load

Figure 36. Overdrive Amplitude Characteristics (Triangle Wave Input)

Rev. D | Page 13 of 28

ADA4937-1/ADA4937-2

Data Sheet

60

55

50

45

40

35

60

55

50

45

40

35

30

25

20

15

10

5

+105°C

+55°C

+25°C

0°C

30

+25°C

+105°C

25

+55°C

20

0°C

15

–40°C

10

5

0

1.0

0

1.0

1.1

1.2

1.3

1.4

1.5

1.6

1.7

1.8

1.9

2.0

1.1

1.2

1.3

1.4

1.5

1.6

1.7

1.8

1.9

2.0

POWER-DOWN VOLTAGE (V)

PD

for Various Temperatures, V_S= 3.3 V

Figure 37. Supply Current vs.

for Various Temperatures

Figure 40. Supply Current vs.

0.20

3.5

3.0

+V = +2.5V

S

V

= 4V p-p

= 2V p-p

OUT, dm

–V = –2.5V

S

OUT, dm

0.15

0.10

0.05

0

V

= 0V

V = 0V

OCM

2.5

2.0

1.5

1.0

0.5

0

–0.5

–1.0

–1.5

–2.0

–2.5

–3.0

–3.5

–0.05

–0.10

–0.15

–0.20

TIME (1ns/DIV)

Figure 41. Large Signal Pulse Response

Figure 38. Small Signal Pulse Response

4.00

3.75

3.50

3.25

3.00

2.75

2.50

2.25

2.00

1.75

1.50

1.25

1.00

2.60

2.58

2.56

2.54

2.52

2.50

2.48

2.46

2.44

2.42

2.40

V

= +5V

S

V

= +5V

S

G = 1

R

= 1kΩ

L, dm

R

= 1kΩ

L, dm

TIME (2ns/DIV)

Figure 42. Large Signal V_OCMPulse Response

Figure 39. Small Signal V_OCMPulse Response

Rev. D | Page 14 of 28

Data Sheet

ADA4937-1/ADA4937-2

10

9

8

7

6

5

4

3

2

1

0

10

G = 1

POWER-DOWN PULSE

1

OUTPUT

0.1

0.01

–1.0

–0.5

0

0.5

1.0

1.5

2.0

2.5

0.1

1

10

100

1k

TIME (ms)

FREQUENCY (MHz)

PD

Figure 46. Closed-Loop Output Impedance

Figure 43.

Response vs. Time

2

1

1.0

–40

–50

–60

V

IN

INPUT2, OUTPUT1

0.5

0.1

–70

SETTLING ERROR

–80

0

–0.1

–90

–100

–110

–120

–130

–140

INPUT1, OUTPUT2

–1

–2

–0.5

–1.0

0.3

1

10

FREQUENCY (MHz)

100

1000

TIME (1ns/DIV)

Figure 44. Crosstalk vs. Frequency for ADA4937-2

Figure 47. 0.1% Settling Time

100

10

1

70

50

PHASE

60

50

0

GAIN

–50

–100

–150

–200

–250

–300

40

30

20

10

0

–10

–20

10

100

1k

10k

100k

1M

10M

1

10

100

1k

10k 100k 1M 10M 100M 1G 10G

FREQUENCY (Hz)

Figure 45. Voltage Spectral Noise Density, RTI

Figure 48. Open-Loop Gain and Phase vs. Frequency

Rev. D | Page 15 of 28

ADA4937-1/ADA4937-2

TEST CIRCUITS

Data Sheet

200Ω

5V

50Ω

200Ω

V

IN

OCM

61.9Ω

ADA4937

1kΩ

200Ω

27.5Ω

200Ω

Figure 49. Equivalent Basic Test Circuit

200Ω

5V

50Ω

200Ω

50Ω

V

IN

OCM

61.9Ω

ADA4937

200Ω

50Ω

27.5Ω

200Ω

Figure 50. Test Circuit for Output Balance

200Ω

5V

0.1µF

412Ω

50Ω

200Ω

FILTER

61.9Ω

V

IN

OCM

ADA4937

0.1µF

200Ω

412Ω

27.5Ω

200Ω

Figure 51. Test Circuit for Distortion Measurements

Rev. D | Page 16 of 28

Data Sheet

ADA4937-1/ADA4937-2

TERMINOLOGY

–FB

Common-Mode Voltage

Common-mode voltage refers to the average of two node

voltages. The output common-mode voltage is defined as

R

F

R

G

+IN

–OUT

+D

IN

V

R

V

OUT, dm

OCM

L, dm

ADA4937

V

_{OUT, cm}= (V_+OUT+ V_−OUT)/2

–D

IN

–IN

+OUT

R

G

R

F

Output Balance

+FB

Output balance is a measure of how close the differential signals

are to being equal in amplitude and opposite in phase. Output

balance is most easily determined by placing a well-matched

resistor divider between the differential voltage nodes and

comparing the magnitude of the signal at the midpoint of the

divider with the magnitude of the differential signal (see Figure

50). By this definition, output balance is the magnitude of the

output common-mode voltage divided by the magnitude of the

output differential mode voltage.

Figure 52. Circuit Definitions

Differential Voltage

Differential voltage refers to the difference between two node

voltages. For example, the output differential voltage (or

equivalently, output differential-mode voltage) is defined as

V

_{OUT, dm}= (V_+OUT− V_−OUT)

where V_+OUTand V_−OUTrefer to the voltages at the +OUT and

−OUT terminals with respect to a common reference.

V_{OUT, cm}

Output Balance Error =

V_{OUT, dm}

Rev. D | Page 17 of 28

ADA4937-1/ADA4937-2

Data Sheet

THEORY OF OPERATION

The ADA4937-x differs from conventional op amps in that it

has two outputs whose voltages move in opposite directions.

Like an op amp, it relies on open-loop gain and negative feed-

back to force these outputs to the desired voltages. The ADA4937-

x behaves much like a standard voltage feedback op amp, which

makes it easier to perform single-ended-to-differential conversions,

common-mode level shifting, and amplifications of differential

signals. Also like an op amp, the ADA4937-x has high input

impedance and low output impedance.

SETTING THE CLOSED-LOOP GAIN

The differential-mode gain of the circuit in Figure 52 can be

determined by

V_{OUT, dm}

R_F

R_G

=

V_{IN, dm}

This assumes that the input resistors (R_G) and feedback resistors

(R_F) on each side are equal.

Two feedback loops control the differential and common-mode

output voltages. The differential feedback loop, set with external

resistors, controls only the differential output voltage. The

common-mode feedback loop controls only the common-mode

output voltage. This architecture makes it easy to set the output

common-mode level to any arbitrary value. It is forced, by

internal common-mode feedback, to be equal to the voltage

applied to the V_OCMinput without affecting the differential

output voltage.

ESTIMATING THE OUTPUT NOISE VOLTAGE

The differential output noise of the ADA4937-x can be esti-

mated using the noise model in Figure 53. The input-referred

noise voltage density, v_nIN, is modeled as a differential input, and

the noise currents, i_nIN−and i_nIN+, appear between each input and

ground. The noise currents are assumed to be equal and produce

a voltage across the parallel combination of the gain and feedback

resistances. v_{n, cm}is the noise voltage density at the V_OCMpin. Each

of the four resistors contributes (4kTR_x)^1/2.

The ADA4937-x architecture results in outputs that are highly

balanced over a wide frequency range without requiring tightly

matched external components. The common-mode feedback

loop forces the signal component of the output common-mode

voltage to zero. This results in nearly perfectly balanced differential

outputs that are identical in amplitude and are exactly 180° apart

in phase.

Table 9 summarizes the input noise sources, the multiplication

factors, and the output-referred noise density terms.

V

nRG1

nRF1

R

F1

G1

i_nIN+

+

V

nIN

V

nOD

i_nIN–

ADA4937

ANALYZING AN APPLICATION CIRCUIT

V

OCM

The ADA4937-x uses open-loop gain and negative feedback to

force its differential and common-mode output voltages in such

a way as to minimize the differential and common-mode error

voltages. The differential error voltage is defined as the voltage

between the differential inputs labeled +IN and −IN (see

Figure 52). For most purposes, this voltage can be assumed

to be zero. Similarly, the difference between the actual output

common-mode voltage and the voltage applied to V_OCMcan

also be assumed to be zero. Starting from these two assumptions,

any application circuit can be analyzed.

V

nCM

R

F2

G2

V

nRG2

nRF2

Figure 53. ADA4937-x Noise Model

Table 9. Output Noise Voltage Density Calculations

Input Noise

Voltage Density

Output

Multiplication Factor

Output Noise

Voltage Density Term

Input Noise Contribution

Differential Input

Inverting Input

Noninverting Input

V_OCMInput

Gain Resistor R_G1

Gain Resistor R_G2

Feedback Resistor R_F1

Feedback Resistor R_F2

Input Noise Term

v_nIN

i_nIN−

i_nIN+

v_{n, cm}

v_nRG1

v_nRG2

v_nRF1

v_nRF2

v_nIN

G_N

v_nO1= G_N(v_nIN)

v_nO2= G_N[i_nIN−× (R_G2||R_F2)]

v_nO3= G_N[i_nIN+× (R_G1||R_F1)]

i_nIN−× (R_G2||R_F2)

i_nIN+× (R_G1||R_F1)

v_{n, cm}

(4kTR_G1)^1/2

(4kTR_G2)^1/2

(4kTR_F1)^1/2

(4kTR_F2)^1/2

G_N(β₁− β₂)

G_N(1 − β₁)

G_N(1 − β₂)

1

v_nO4= G_N(β₁− β₂)(v_{n, cm})

v_nO5= G_N(1 − β₁)(4kTR_G1)^1/2

v_nO6= G_N(1 − β₂)(4kTR_G2)^1/2

v_nO7= (4kTR_F1)^1/2

v_nO8= (4kTR_F2)^1/2

Rev. D | Page 18 of 28

Data Sheet

ADA4937-1/ADA4937-2

R

F

Similar to the case of a conventional op amp, the output noise

voltage densities can be estimated by multiplying the input-

referred terms at +IN and −IN by the appropriate output factor,

ADA4937

+V

S

R

G

+IN

+D

–D

IN

where:

2

V

OCM

V

OUT, dm

G_N



is the circuit noise gain.

IN

–IN



β₁ β₂

R_G1



G

R

F

R_G2

β₁

and β₂

are the feedback factors.

R_F1 R_G1

R_F2 R_G2

Figure 54. ADA4937-x Configured for Balanced (Differential) Inputs

For an unbalanced, single-ended input signal (see Figure 55),

the input impedance is

When R_F1/R_G1= R_F2/R_G2, then β1 = β2 = β, and the noise gain

becomes

1

β

R_F

R_G









G_N



1

R_G

R_F

R_G R_F





R_{IN, cm}



Note that the output noise from V_OCMgoes to zero in this case.

The total differential output noise density, v_nOD, is the root-sum-

square of the individual output noise terms.

1 





2 









R

F

+V

S

8

v_nOD



v²

R



G

S

nOi

i1

R

V

OCM

T

V

ADA4937

OUT, dm

IMPACT OF MISMATCHES IN THE FEEDBACK

NETWORKS

R

G

R

T

S

As previously mentioned in the Setting the Closed-Loop Gain

section), even if the external feedback networks (R_F/R_G) are

mismatched, the internal common-mode feedback loop still

forces the outputs to remain balanced. The amplitudes of the

signals at each output remain equal and 180° out of phase. The

input-to-output differential mode gain varies proportionately to

the feedback mismatch, but the output balance is unaffected.

R

F

Figure 55. ADA4937-x Configured for Unbalanced (Single-Ended) Input

The input impedance of the circuit is effectively higher than it

would be for a conventional op amp connected as an inverter

because a fraction of the differential output voltage appears at

the inputs as a common-mode signal, partially bootstrapping

the voltage across the Input Gain Resistor R_G.

As well as causing a noise contribution from V_OCM, ratio matching

errors in the external resistors result in a degradation of the

ability of the circuit to reject input common-mode signals, much

the same as for a four-resistor difference amplifier made from

a conventional op amp.

Terminating a Single-Ended Input

This section explains how to properly terminate a single-ended

input to the ADA4937-x. Using a simple example with an input

source of 2 V and a source resistor of 50 Ω, four simple steps

must be followed.

In addition, if the dc levels of the input and output common-

mode voltages are different, matching errors result in a small

differential-mode output offset voltage. When G = 1, with a

ground referenced input signal and the output common-mode

level set to 2.5 V, an output offset of as much as 25 mV (1%

of the difference in common-mode levels) can result if 1% toler-

ance resistors are used. Resistors of 1% tolerance result in a

worst-case input CMRR of approximately 40 dB, a worst-case

differential-mode output offset of 25 mV due to 2.5 V level

shift, and no significant degradation in output balance error.

1. The input impedance must be calculated using the formula

















R_G

R_F

200

2  (200  200)









R_IN



 267 ꢀ

1 













2  (R_G R_F)





R

F

R

267Ω

200Ω

+V

IN

S

R

S

R

G

CALCULATING THE INPUT IMPEDANCE FOR AN

APPLICATION CIRCUIT

50Ω

200Ω

V

2V

S

V

OCM

ADA4937

R

V

O

L

The effective input impedance of a circuit depends on whether

the amplifier is being driven by a single-ended or differential

signal source. For balanced differential input signals, as shown

in Figure 54, the input impedance (R_{IN, dm}) between the inputs

(+D_INand −D_IN) is simply R_{IN, dm}= 2 × R_G.

R

G

200Ω

–V

S

R

F

200Ω

Figure 56. Single-Ended Input Impedance R_IN

Rev. D | Page 19 of 28

ADA4937-1/ADA4937-2

Data Sheet

R

F

2. For the source termination to be 50 Ω, the termination

resistor (R_T) is calculated using R_T||R_IN= 50 Ω, which

makes R_Tequal to 61.9 Ω.

+V

S

R

S

G

R

F

50Ω

200Ω

R

61.9Ω

T

200Ω

+V

V

2V

S

50Ω

V

OCM

ADA4937

R

V

O

L

S

R

G

R

S

G

200Ω

R

TS

27.4Ω

50Ω

200Ω

R

61.9Ω

T

V

S

V

OCM

ADA4937

–V

S

R

V

O

2V

L

R

F

R

G

200Ω

Figure 60. Complete Single-Ended-to-Differential System

–V

S

INPUT COMMON-MODE VOLTAGE RANGE IN

SINGLE-SUPPLY APPLICATIONS

R

F

200Ω

Figure 57. Adding Termination Resistor R_T

The ADA4937-x is optimized for level-shifting ground-referenced

input signals. As such, the center of the input common-mode

range is shifted approximately 1 V down from midsupply. For

5 V single-supply operation, the input common-mode range at

the summing nodes of the amplifier is 0.3 V to 3.0 V, and 0.3 V

to 1.2 V with a 3.3 V supply. To avoid clipping at the outputs,

the voltage swing at the +IN and −IN terminals must be confined

to these ranges.

3. To compensate for the imbalance of the gain resistors,

a correction resistor (R_TS) is added in series with the

inverting Input Gain Resistor R_G. R_TSis equal to the

Thevenin equivalent of the Source Resistance R_S||R_T.

R

S

TH

50Ω

R

61.9Ω

27.4Ω

T

V

S

2V

TH

1.1V

SETTING THE OUTPUT COMMON-MODE VOLTAGE

The V_OCMpin of the ADA4937-x is internally biased at a voltage

approximately equal to the midsupply point, [(+V_S) + (−V_S)]/2.

Relying on this internal bias results in an output common-mode

voltage that is within about 100 mV of the expected value.

Figure 58. Calculating Thevenin Equivalent

R_TS= R_TH= R_S||R_T= 27.4 Ω. Note that V_THis not equal to V_S/2,

which would be the case if the termination were not affected by

the amplifier circuit.

In cases where more accurate control of the output common-

mode level is required, it is recommended that an external source,

or resistor divider (10 kΩ or greater resistors), be used. The

output common-mode offset listed in Table 2 and Table 4 assumes

that the V_OCMinput is driven by a low impedance voltage source.

R

F

200Ω

+V

S

R

TH

G

27.4Ω

200Ω

V

TH

1.1V

V

O

V

OCM

ADA4937

R

0.97V

L

It is also possible to connect the V_OCMinput to a common-mode

level (CML) output of an ADC. However, care must be taken to

ensure that the output has sufficient drive capability. The input

impedance of the V_OCMpin is approximately 10 kΩ. If multiple

ADA4937-x devices share one reference output, it is recommended

that a buffer be used.

R

G

200Ω

R

TS

27.4Ω

–V

S

R

F

200Ω

Figure 59. Balancing Gain Resistor R_G

Table 10 and Table 11 list several common gain settings, asso-

ciated resistor values, input impedances, and output noise density

values for both balanced and unbalanced input configurations.

4. The feedback resistor is calculated to adjust the output

voltage.

a. To make the output voltage V_OUT= 1 V, R_Fmust be

calculated using the following formula:

POWER-DOWN OPERATION

The ADA4937-x power-down pin features an internal 25 kꢀ

pull-up resistor to the positive supply (+V_S). This ensures that,

with the power-down pin left unconnected (floating), the

ADA4937-x turns on. Applying a voltage of ≤1 V turns the

ADA4937-x off.













V_OUT (R_G R_TS)

1  (200  27.4)









R_F



207 ꢀ

V_TH

1.1





b. To make V_O= V_S= 2 V to recover the loss due to the

input termination, R_Fshould be













V_OUT (R_G R_TS)

2  (200  27.4)









R_F



 414 ꢀ

V_TH

1.1





Rev. D | Page 20 of 28

Data Sheet

ADA4937-1/ADA4937-2

Table 10. Differential Ground-Referenced Input, DC-Coupled, 1 kΩ Load; See Figure 54

Nominal Gain (dB)

R_F(Ω)

R_G(Ω) R_{IN, dm}(Ω) Differential Output Noise Density (nV/√Hz)

0

6

10

14

200

402

200

127

80.6

400

254

161

5.8

9.6

12.1

16.2

Table 11. Single-Ended Ground-Referenced Input, DC-Coupled, R_S= 50 Ω, R_L= 1 kΩ; See Figure 55

Nominal Gain (dB)

R_F(Ω) R_G1(Ω)

R_T(Ω) R_{IN, cm}(Ω)

R_G2(Ω)¹

226

228

155

Differential Output Noise Density (nV/√Hz)

0

6

10

14

200

402

200

127

80.6

61.9

60.4

66.5

76.8

267

301

205

138

5.5

8.6

10.1

12.2

111

¹R_G2= R_G1+ (R_S||R_T)

Rev. D | Page 21 of 28

ADA4937-1/ADA4937-2

Data Sheet

LAYOUT, GROUNDING, AND BYPASSING

As a high speed device, the ADA4937-x is sensitive to the

PCB environment in which it operates. Realizing its superior

performance requires attention to the details of high speed

PCB design. This section shows a detailed example of how

the design issues of the ADA4937-1 were addressed.

Bypass the power supply pins as close to the device as possible

and directly to a nearby ground plane. Use high frequency ceramic

chip capacitors. It is recommended that two parallel bypass capaci-

tors (1000 pF and 0.1 μF) be used for each supply with the 1000 pF

capacitor placed closer to the device; further away, provide low

frequency bypassing using 10 μF tantalum capacitors from each

supply to ground.

The first requirement is a solid ground plane that covers as

much of the board area around the ADA4937-1 as possible.

However, the area near the feedback resistors (R_F), input gain

resistors (R_G), and the input summing nodes (Pin 2 and Pin 3)

should be cleared of all ground and power planes (see Figure 61).

Clearing the ground and power planes minimizes any stray capa-

citance at these nodes and prevents peaking of the response of

the amplifier at high frequencies.

Signal routing should be short and direct to avoid parasitic

effects. Wherever complementary signals exist, provide a sym-

metrical layout to maximize balanced performance. When

routing differential signals over a long distance, keep PCB

traces close together and twist any differential wiring to mini-

mize loop area. Doing this reduces radiated energy and makes

the circuit less susceptible to interference.

The thermal resistance, θ_JA, is specified for the device, including

the exposed pad, soldered to a high thermal conductivity 4-layer

circuit board, as described in EIA/JESD 51-7.

1.30

0.80

1.30 0.80

Figure 62. Recommended PCB Thermal Attach Pad Dimensions (mm)

Figure 61. Ground and Power Plane Voiding in Vicinity of R_Fand R_G

1.30

TOP METAL

GROUND PLANE

0.30

PLATED

VIA HOLE

POWER PLANE

BOTTOM METAL

Figure 63. Cross-Section of 4-layer PCB Showing Thermal Via Connection to Buried Ground Plane (Dimensions in mm)

Rev. D | Page 22 of 28

Data Sheet

ADA4937-1/ADA4937-2

HIGH PERFORMANCE ADC DRIVING

The ADA4937-x is ideally suited for broadband IF applications.

The circuit in Figure 64 shows a front-end connection for an

ADA4937-1 driving an AD9445, 14-bit, 105 MSPS ADC. The

AD9445 achieves its optimum performance when driven dif-

ferentially. The ADA4937-x eliminates the need for a transformer

to drive the ADC and performs a single-ended-to-differential

conversion and buffering of the driving signal.

The signal generator has a symmetric, ground-referenced bipolar

output. The V_OCMpin of the ADA4937-x remains unconnected

allowing the internal divider to set the output common-mode

voltage at midsupply; one half of the common-mode voltage is

fed back to the summing nodes, biasing −IN and +IN at 1.25 V. For

a common-mode voltage of 2.5 V, each ADA4937-x output swings

between 2.0 V and 3.0 V, providing a 2 V p-p differential output.

The ADA4937-x is configured with a single 5 V supply and unity

gain for a single-ended input to differential output. The 61.9 Ω

termination resistor, in parallel with the single-ended input imped-

ance of 267 Ω, provides a 50 Ω termination for the source. The

additional 26 Ω (226 Ω total) at the inverting input balances the

parallel impedance of the 50 Ω source and the termination resistor

driving the noninverting input.

The output of the amplifier is ac-coupled to the ADC through a

second-order, low-pass filter with a cutoff frequency of 100 MHz.

This reduces the noise bandwidth of the amplifier and isolates

the driver outputs from the ADC inputs.

The AD9445 is configured for a 2 V p-p full-scale input by

connecting the SENSE pin to AGND, as shown in Figure 64.

5V (A) 3.3V (A) 3.3V (D)

200Ω

5V

AVDD2 AVDD1 DRVDD

30nH

0.1µF

200Ω

50Ω

VIN–

47pF

VIN+

AD9445

+

BUFFER T/H

24.3Ω

V

61.9Ω

OCM

ADA4937-1

14

ADC

SIGNAL

GENERATOR

30nH

226Ω

CLOCK/

TIMING

REF

200Ω

AGND

SENSE

Figure 64. Driving an AD9445, 14-Bit, 105 MSPS ADC

Rev. D | Page 23 of 28

ADA4937-1/ADA4937-2

Data Sheet

The circuit in Figure 66 shows a simplified front-end connection

for an ADA4937-1 driving an AD9246, 14-bit, 125 MSPS ADC.

The AD9246 achieves its optimum performance when driven

differentially. The ADA4937-x performs the single-ended-to-

differential conversion, eliminating the need for a transformer

to drive the ADC.

The AD9246 is set for a 2 V p-p full-scale input by connecting

the SENSE pin to AGND. The inputs of the AD9246 are biased

at 1 V by connecting the CML output, as shown in Figure 66.

The circuit was tested with a −1 dBFS signal at various frequencies.

Figure 65 shows a plot of the second- and third-order harmonic

distortion (HD2/HD3) vs. frequency.

The ADA4937-x is configured with a single 5 V supply and a

gain of ~2 V/V for a single-ended input to differential output.

The 76.8 Ω termination resistor, in parallel with the single-ended

input impedance of 137 Ω, provides a 50 Ω ac termination for the

source. The additional 30 Ω (120 Ω total) at the inverting input

balances the parallel ac impedance of the 50 Ω source and the

termination resistor driving the noninverting input.

–75

G = +2

–80

HD3

–85

HD2

–90

The signal generator has a symmetric, ground-referenced bipolar

output. The V_OCMpin of the ADA4937-x remains unconnected;

therefore, the internal pull-ups set the output common-mode

voltage to midsupply. A portion of this is fed back to the summing

nodes, biasing −IN and +IN at 0.55 V. For a common-mode vol-

tage of 2.5 V, each ADA4937-x output swings between 2.0 V and

3.0 V, providing a 2 V p-p differential output.

–95

–100

0

20

40

60

80

100

120

FREQUENCY (MHz)

Figure 65. HD2/HD3 for Combination of ADA4937-x and AD9246 ADC

The output is ac-coupled to a single-pole, low-pass filter. This

reduces the noise bandwidth of the amplifier and provides some

level of isolation from the switched capacitor inputs of the ADC.

200Ω

1.8V

5V

76.8Ω

10µF

50Ω

33Ω

10pF

90Ω

AVDD DRVDD

VIN–

+

200Ω

D13 TO

V

IN

AD9246

D0

ADA4937-1

10µF

90Ω

VIN+

AGND SENSE CML

33Ω

10µF

50Ω

76.8Ω

200Ω

Figure 66. Driving an AD9246, 14-Bit, 125 MSPS ADC

Rev. D | Page 24 of 28

Data Sheet

ADA4937-1/ADA4937-2

59 Ω termination resistor, in parallel with the single-ended input

impedance of 306 Ω, provides a 50 Ω termination for the source.

The additional 26 Ω (226 Ω total) at the inverting input balances

the parallel impedance of the 50 Ω source and the termination

resistor that drives the noninverting input. The signal generator

has a symmetric, ground-referenced bipolar output. The V_OCMpin

is connected to the CML output of the AD9230, and sets the out-

put common mode of the ADA4937-x at 1.4 V. One third of the

output common-mode voltage of the amplifier is fed back to the

summing nodes, biasing −IN and +IN at ~0.5 V. For a common-

mode voltage of 1.4 V, each ADA4937-x output swings between

1.09 V and 1.71 V, providing a 1.25 V p-p differential output.

3.3 V OPERATION

The ADA4937-x provides excellent performance in 3.3 V

single-supply applications. Significant power savings can be

realized when the ADA4937-x is used in combination with

a low voltage ADC.

The circuit in Figure 67 is an example of the ADA4937-1

driving an AD9230, 12-bit, 250 MSPS ADC that is specified

to operate with a single 1.8 V supply. The performance of the

ADC is optimized when it is driven differentially, making the

best use of the signal swing available within the 1.8 V supply.

The ADA4937-x performs the single-ended-to-differential

conversion, common-mode level-shifting, and buffering of

the driving signal.

A third-order, 125 MHz, low-pass filter between the ADA4937-x

and the AD9230 reduces the noise bandwidth of the amplifier

and isolates the driver outputs from the ADC inputs.

The ADA4937-x is configured with a single 3.3 V supply and a

gain of 2 V/V for a single-ended input to differential output. The

453Ω

1.8V

3.3V

56nH

50Ω

33Ω

200Ω

AVDD DRVDD

+

VIN–

V

D11 TO

D0

59Ω

OCM

V

AD9230

10pF

30pF

ADA4937-1

IN

VIN+

AGND

CML

33Ω

56nH

226Ω

453Ω

Figure 67. Driving an AD9230, 12-Bit, 250 MSPS ADC

Rev. D | Page 25 of 28

ADA4937-1/ADA4937-2

OUTLINE DIMENSIONS

Data Sheet

0.50

0.40

0.30

3.00

BSC SQ

0.60 MAX

PIN 1

INDICATOR

*

1.45

13

16

1

0.45

1.30 SQ

1.15

12

PIN 1

INDICATOR

2.75

BSC SQ

TOP

VIEW

EXPOSED

PAD

4

9

0.50

BSC

8

5

0.25 MIN

1.50 REF

0.80 MAX

12° MAX

0.65 TYP

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

1.00

0.85

0.80

0.05 MAX

0.02 NOM

SECTION OF THIS DATA SHEET.

SEATING

PLANE

0.30

0.23

0.18

0.20 REF

*

COMPLIANT TO JEDEC STANDARDS MO-220-VEED-2

EXCEPT FOR EXPOSED PAD DIMENSION.

Figure 68. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

3 mm × 3 mm Body, Very Thin Quad

(CP-16-2)

Dimensions shown in millimeters

4.10

4.00 SQ

0.60 MAX

2.50 REF

3.90

0.60 MAX

PIN 1

INDICATOR

19

24

18

13

1

0.50

BSC

PIN 1

INDICATOR

2.25

2.10 SQ

1.95

3.75 BSC

SQ

EXP OSED

PAD

6

12

7

0.50

0.40

0.30

0.25 MIN

BOTTOM VIEW

TOP VIEW

0.80 MAX

0.65 TYP

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

12° MAX

1.00

0.85

0.80

0.05 MAX

0.02 NOM

SECTION OF THIS DATA SHEET.

COPLANARITY

0.08

0.20 REF

0.30

0.23

0.18

SEATING

PLANE

COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-2

Figure 69. 24-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

4 mm × 4 mm Body, Very Thin Quad

(CP-24-1)

Dimensions shown in millimeters

ORDERING GUIDE

Model¹

Temperature Range

−40°C to +105°C

Package Description

16-Lead LFCSP_VQ

24-Lead LFCSP_VQ

Evaluation Board

Package Option

CP-16-2

CP-24-1

Ordering Quantity

Branding

H1S

ADA4937-1YCPZ-R2

ADA4937-1YCPZ-RL

ADA4937-1YCPZ-R7

ADA4937-2YCPZ-R2

ADA4937-2YCPZ-RL

ADA4937-2YCPZ-R7

ADA4937-1YCP-EBZ

ADA4937-2YCP-EBZ

250

5,000

1,500

250

5,000

1,500

H1S

CP-24-1

Evaluation Board

¹Z = RoHS Compliant Part.

Rev. D | Page 26 of 28

Data Sheet

NOTES

ADA4937-1/ADA4937-2

Rev. D | Page 27 of 28

ADA4937-1/ADA4937-2

NOTES

Data Sheet

registered trademarks are the property of their respective owners.

D06591-0-8/13(D)

Rev. D | Page 28 of 28


型号：	ADA4937-2_15
厂家：	ADI
描述：	Ultralow Distortion Differential ADC Driver
文件：	总29页 (文件大小：959K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADA4937-2_15 [ADI]

相关型号：

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ADA4938-1YCPZ-RL

ADA4938-1_06

ADA4938-1_07

ADA4938-1_15

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