ADG3242BRJ-REEL7 [ADI]
2.5 V/3.3 V, 2-Bit, Common Control Level Translator Bus Switch; 2.5 V / 3.3 V ， 2位，普通的控制电平转换器总线开关
| 型号： | ADG3242BRJ-REEL7 |
| 厂家： | 
ADI |
| 描述： | 2.5 V/3.3 V, 2-Bit, Common Control Level Translator Bus Switch |
| 文件： | 总12页 (文件大小：247K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
2.5 V/3.3 V, 2-Bit, Common Control
Level Translator Bus Switch
ADG3242
FEATURES
FUNCTIONAL BLOCK DIAGRAM
225 ps Propagation Delay through the Switch
4.5 ⍀ Switch Connection between Ports
Data Rate 1.5 Gbps
B0
A0
2.5 V/3.3 V Supply Operation
Selectable Level Shifting/Translation
Level Translation
B1
A1
3.3 V to 2.5 V
BE
3.3 V to 1.8 V
2.5 V to 1.8 V
Small Signal Bandwidth 710 MHz
8-Lead SOT-23 Package
APPLICATIONS
3.3 V to 2.5 V Voltage Translation
3.3 V to 1.8 V Voltage Translation
2.5 V to 1.8 V Voltage Translation
Bus Switching
Bus Isolation
Hot Swap
Hot Plug
Analog Switch Applications
GENERAL DESCRIPTION
PRODUCT HIGHLIGHTS
The ADG3242 is a 2.5 V or 3.3 V, 2-bit, 2-port common-
control digital switch. It is designed on a low voltage CMOS
process, which provides low power dissipation yet gives high
switching speed and very low on resistance. This allows the inputs
to be connected to the outputs without additional propagation
delay or generating additional ground bounce noise.
1. 3.3 V or 2.5 V supply operation.
2. Extremely low propagation delay through switch.
3. 4.5 Ω switches connect inputs to outputs.
4. Level/voltage translation.
5. Tiny SOT-23 package.
These switches are enabled by means of a common bus enable
(BE) input signal. This digital switch allows a bidirectional
signal to be switched when ON. In the OFF condition, signal
levels up to the supplies are blocked.
This device is ideal for applications requiring level translation.
When operated from a 3.3 V supply, level translation from 3.3 V
inputs to 2.5 V outputs is allowed. Similarly, if the device is
operated from a 2.5 V supply and 2.5 V inputs are applied, the
device will translate the outputs to 1.8 V. In addition, a level
translating select pin (SEL) is included. When SEL is low, VCC
is reduced internally, allowing for level translation between 3.3
V inputs and 1.8 V outputs. This makes the device suitable for
applications requiring level translation between different supplies,
such as converter to DSP/microcontroller interfacing.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
www.analog.com
© 2003 Analog Devices, Inc. All rights reserved.
(VCC = 2.3 V to 3.6 V, GND = 0 V, all specifications TMIN to TMAX, unless
ADG3242–SPECIFICATIONS1 otherwise noted.)
B Version
Typ2
Parameter
Symbol
Conditions
Min
Max
Unit
DC ELECTRICAL CHARACTERISTICS
Input High Voltage
VINH
VINH
VINL
VINL
II
VCC = 2.7 V to 3.6 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
VCC = 2.3 V to 2.7 V
2.0
1.7
V
V
V
V
µA
µA
µA
V
V
V
Input Low Voltage
0.8
0.7
1
1
1
2.9
2.1
2.1
Input Leakage Current
0.01
0.01
0.01
2.5
1.8
1.8
OFF State Leakage Current
ON State Leakage Current
Maximum Pass Voltage
IOZ
0 ≤ A, B ≤ VCC
0 ≤ A, B ≤ VCC
VA/VB = VCC = SEL = 3.3 V, IO = –5 µA
VA/VB = VCC = SEL = 2.5 V, IO= –5 µA
VA/VB = VCC = 3.3 V, SEL = 0 V, IO = –5 µA
VP
2.0
1.5
1.5
CAPACITANCE3
A Port Off Capacitance
B Port Off Capacitance
A, B Port On Capacitance
Control Input Capacitance
CA OFF
f = 1 MHz
f = 1 MHz
3.5
3.5
7
pF
pF
pF
pF
C
B OFF
CA, CB ON f = 1 MHz
CIN
f = 1 MHz
4
SWITCHING CHARACTERISTICS3
Propagation Delay A to B or B to A, tPD
4
tPHL, tPLH
CL = 50 pF, VCC = SEL = 3 V
0.225 ns
Propagation Delay Matching5
Bus Enable Time BE to A or B6
Bus Disable Time BE to A or B6
Bus Enable Time BE to A or B6
Bus Disable Time BE to A or B6
Bus Enable Time BE to A or B6
Bus Disable Time BE to A or B6
Maximum Data Rate
5
ps
tPZH, tPZL
tPHZ, tPLZ
tPZH, tPZL
tPHZ, tPLZ
tPZH, tPZL
tPHZ, tPLZ
VCC = 3.0 V to 3.6 V; SEL = VCC
VCC = 3.0 V to 3.6 V; SEL = VCC
VCC = 3.0 V to 3.6 V; SEL = 0 V
VCC = 3.0 V to 3.6 V; SEL = 0 V
VCC = 2.3 V to 2.7 V; SEL = VCC
VCC = 2.3 V to 2.7 V; SEL = VCC
VCC = SEL = 3.3 V; VA/VB = 2 V
VCC = SEL = 3.3 V; VA/VB = 2 V
1
1
1
1
1
1
3.2
3
3
2.5
3
2.5
1.5
45
4.6
4
ns
ns
4
ns
3.8
4
ns
ns
3.4
ns
Gbps
ps p-p
Channel Jitter
DIGITAL SWITCH
On Resistance
RON
VCC = 3 V, SEL = VCC, VA = 0 V, IBA = 8 mA
VCC = 3 V, SEL = VCC, VA = 1.7 V, IBA = 8 mA
VCC = 2.3 V, SEL = VCC, VA = 0 V, IBA = 8 mA
4.5
12
5
9
5
12
0.1
0.1
8
28
9
18
8
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
V
CC = 2.3 V, SEL = VCC, VA = 1 V, IBA = 8 mA
VCC = 3 V, SEL = 0 V, VA = 0 V, IBA = 8 mA
VCC = 3 V, SEL = 0 V, VA = 1 V, IBA = 8 mA
VCC = 3 V, SEL = VCC, VA = 0 V, IA = 8 mA
VCC = 3 V, SEL = 0 V, VA = 0 V, IA = 8 mA
On Resistance Matching
⌬RON
0.5
0.5
POWER REQUIREMENTS
VCC
Quiescent Power Supply Current
2.3
3.6
1
0.2
8
V
ICC
Digital Inputs = 0 V or VCC; SEL = VCC
Digital Inputs = 0 V or VCC ; SEL = 0 V
VCC = 3.6 V, BE = 3.0 V; SEL = VCC
0.01
0.1
0.15
µA
mA
µA
Increase in ICC per Input7
NOTES
⌬ICC
1Temperature range is as follows: B Version: –40°C to +85°C.
2Typical values are at 25°C, unless otherwise stated.
3Guaranteed by design, not subject to production test.
4The digital switch contributes no propagation delay other than the RC delay of the typical RON of the switch and the load capacitance when driven by an ideal voltage
source. Since the time constant is much smaller than the rise/fall times of typical driving signals, it adds very little propagation delay to the system. Propagation delay
of the digital switch when used in a system is determined by the driving circuit on the driving side of the switch and its interaction with the load on the driven side.
5Propagation delay matching between channels is calculated from the on resistance matching and load capacitance of 50 pF.
6See Timing Measurement Information section.
7This current applies to the control pin BE only. The A and B ports contribute no significant ac or dc currents as they transition.
Specifications subject to change without notice.
–2–
REV. 0
ADG3242
ABSOLUTE MAXIMUM RATINGS*
(TA = 25°C, unless otherwise noted.)
PIN CONFIGURATION
8-Lead SOT-23
VCC to GND . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to +4.6 V
Digital Inputs to GND . . . . . . . . . . . . . . . . . –0.5 V to +4.6 V
DC Input Voltage . . . . . . . . . . . . . . . . . . . . . –0.5 V to +4.6 V
DC Output Current . . . . . . . . . . . . . . . . . 25 mA per Channel
Operating Temperature Range
1
2
3
4
BE
8
7
6
5
V
CC
ADG3242
SEL
A0
A1
TOP VIEW
(Not to Scale)
B0
B1
GND
Industrial (B Version) . . . . . . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
PIN FUNCTION DESCRIPTIONS
JA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 206°C/Ω
Pin No.
Mnemonic
Description
Lead Temperature, Soldering (10 sec) . . . . . . . . . . . . . 300°C
IR Reflow, Peak Temperature (<20 sec) . . . . . . . . . . . . 235°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability. Only one absolute
maximum rating may be applied at any one time.
1
2
3
4
5
6
7
8
BE
A0
A1
GND
B1
B0
SEL
VCC
Bus Enable (Active Low)
Port A0, Input or Output
Port A1, Input or Output
Ground Reference
Port B1, Input or Output
Port B0, Input or Output
Level Translation Select
Positive Power Supply Voltage
Table I. Truth Table
BE SEL* Function
L
L
H
L
A0 = B0, A1 = B1, 3.3 V to 1.8 V
Level Shifting
A0 = B0, A1 = B1, 3.3 V to 2.5 V/2.5 V to 1.8 V
Level Shifting
Disconnect
H
X
*SEL = 0 V only when VDD = 3.3 V 10%.
ORDERING GUIDE
Model
Temperature Range
Package Description
Package
Branding
ADG3242BRJ-R2
ADG3242BRJ-REEL
ADG3242BRJ-REEL7
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
SOT-23 (Small Outline Transistor)
SOT-23 (Small Outline Transistor)
SOT-23 (Small Outline Transistor)
RJ-8
RJ-8
RJ-8
SCA
SCA
SCA
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
ADG3242 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.
REV. 0
–3–
ADG3242
TERMINOLOGY
VCC
GND
VINH
VINL
II
Positive Power Supply Voltage.
Ground (0 V) Reference.
Minimum Input Voltage for Logic 1.
Maximum Input Voltage for Logic 0.
Input Leakage Current at the Control Inputs.
IOZ
IOL
OFF State Leakage Current. It is the maximum leakage current at the switch pin in the OFF state.
ON State Leakage Current. It is the maximum leakage current at the switch pin in the ON state.
VP
Maximum Pass Voltage. The maximum pass voltage relates to the clamped output voltage of an NMOS device when
the switch input voltage is equal to the supply voltage.
RON
Ohmic Resistance Offered by a Switch in the ON State. It is measured at a given voltage by forcing a specified
amount of current through the switch.
⌬RON
ON Resistance Match between any two channels, i.e., RON max to RON min.
OFF Switch Capacitance.
ON Switch Capacitance.
C
C
X OFF
X ON
CIN
ICC
Control Input Capacitance. This consists of BE and SEL.
Quiescent Power Supply Current. This current represents the leakage current between the VCC and ground pins.
It is measured when all control inputs are at a logic high or low level and the switches are OFF.
⌬ICC
Extra power supply current component for the EN control input when the input is not driven at the supplies.
t
t
t
PLH, tPHL
PZH, tPZL
PHZ, tPLZ
Data Propagation Delay through the Switch in the ON State. Propagation delay is related to the RC time constant
RON × CL, where CL is the load capacitance.
Bus Enable Times. These are the times taken to cross the VT voltage at the switch output when the switch turns on
in response to the control signal, BE.
Bus Disable Times. These are the times taken to place the switch in the high impedance OFF state in response to
the control signal. They are measured as the time taken for the output voltage to change by V⌬ from the original
quiescent level, with reference to the logic level transition at the control input. (Refer to Figure 3 for enable and
disable times.)
Max Data Rate Maximum Rate at which Data Can Be Passed through the Switch.
Channel Jitter
Peak-to-Peak Value of the Sum of the Deterministic and Random Jitter of the Switch Channel.
–4–
REV. 0
Typical Performance Characteristics–ADG3242
40
35
30
25
40
40
35
30
25
20
15
10
5
V
= 3V
V
= 3V
CC
CC
T
= 25؇C
T
= 25؇C
V
= 2.3V
A
35
30
25
20
15
10
5
A
CC
T
= 25؇C
A
SEL = 0V
SEL = V
CC
SEL = V
CC
V
= 3.3V
= 3.6V
V
= 3.3V
V
= 2.5V
= 2.7V
CC
CC
CC
20
15
10
5
V
V
CC
CC
V
= 3.6V
CC
0
0
0
0
0.5
1.0
1.5
2.0
2.5
3.0
0
0.5
1.0
1.5
2.0
)
2.5
3.0
3.5
0
0.5
1.0
1.5
2.0
/V (V
2.5
3.0 3.5
V
/V (V)
V
/V (V
A
B
V
)
A
B
A
B
TPC 2. On Resistance vs.
Input Voltage
TPC 1. On Resistance vs.
Input Voltage
TPC 3. On Resistance vs.
Input Voltage
15
10
5
3.0
2.5
20
15
10
5
V
= 3.6V
T
= 25؇C
CC
V
= 3.3V
A
V
= 2.5V
CC
CC
SEL = V
CC
= –5A
SEL = V
SEL = V
CC
CC
I
O
2.0
1.5
V
= 3.3V
CC
؉85؇C
V
= 3V
CC
؉85؇C
1.0
0.5
0
؊40؇C
؉25؇C
؉25؇C
؊40؇C
0
0
0
0.5
1.0
1.5
2.0 2.5
/V (V)
3.0 3.5
1.0
/V (V)
2.0
0
0.5
1.5
0
0.5
V
1.0
1.2
V
V
A
B
/V (V)
A
B
A
B
TPC 5. On Resistance vs. Input
Voltage for Different Temperatures
TPC 6. Pass Voltage vs. VCC
TPC 4. On Resistance vs. Input
Voltage for Different Temperatures
2.5
2.5
500
450
400
350
300
250
200
150
100
50
T
= 25؇C
A
T
= 25؇C
T = 25؇C
A
A
V
= 2.7V
= 2.5V
V
= 3.6V
CC
CC
SEL = V
SEL = 0V
= –5A
CC
= –5A
2.0
1.5
1.0
0.5
2.0
1.5
1.0
0.5
I
I
O
O
V
= SEL = 3.3V
CC
V
CC
V
= 3.3V
CC
= 3V
V
= 3.3V
CC
V
= 2.3V
V
CC
CC
SEL = 0V
V
= SEL = 2.5V
CC
0
0
0
0
0.5
1.0
1.5
/V (V)
2.0
2.5
3.0
0
0.5
1.0
1.5
2.0
/V (V)
2.5
3.0 3.5
0
5
10 15 20 25 30 35 40 45 50
ENABLE FREQUENCY (MHz)
V
V
A
B
A
B
TPC 7. Pass Voltage vs. VCC
TPC 8. Pass Voltage vs. VCC
TPC 9. ICC vs. Enable Frequency
REV. 0
–5–
ADG3242
3.0
3.0
2.5
2.0
1.5
0
–0.2
–0.4
–0.6
–0.8
–1.0
–1.2
T
= 25؇C
T
V
= 25؇C
= V
CC
T
= 25؇C
A
A
A
V
= 0V
SEL = V
A
A
CC
V
= 2.5V
CC
2.5
2.0
1.5
1.0
ON OFF
= 1nF
BE = 0
BE = 0
C
L
V
= SEL = 3.3V
CC
V
= 3.3V; SEL = 0V
CC
V
= SEL = 3.3V
CC
V
= 3.3V
CC
1.0
V
= SEL = 2.5V
CC
0.5
0
0.5
0
V
= 3.3V; SEL = 0V
CC
V
= SEL = 2.5V
CC
0
0.02
0.04
0.06
(A)
0.08
0.10
–0.10 –0.08
–0.06
–0.04
I (A)
O
–0.02
0
0
0.5
1.0
1.5
2.0
2.5
3.0
I
O
V
/V (V)
A
B
TPC 10. Output Low Characteristic
TPC 11. Output High Characteristic
TPC 12. Charge Injection vs.
Source Voltage
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
2
1
0
T
V
= 25؇C
A
T
V
= 25؇C
A
= 3.3V/2.5V
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
CC
= 3.3V/2.5V
CC
SEL =V
CC
= 0dBm
SEL = V
V
N/W ANALYZER
R
0
CC
V
IN
N/W ANALYZER:
= 0dBm
IN
–1
–2
–3
R
= R = 50⍀
L
S
= R = 50⍀
L
S
T
V
= 25؇C
–4
–5
–6
–7
–8
A
= 3.3V/2.5V
CC
SEL = V
V
N/W ANALYZER:
R
CC
= 0dBm
IN
= R = 50⍀
L
S
0.03 0.1
1.0
10
100
1000
0.03 0.1
1.0
10
100
1000
0.1
1
10
100
1000
FREQUENCY (MHz)
FREQUENCY (MHz)
FREQUENCY (MHz)
TPC 13. Bandwidth vs. Frequency
TPC 14. Crosstalk vs. Frequency
TPC 15. Off Isolation vs. Frequency
4.0
100
4.0
V
= SEL = 3.3V
= 1.5V p-p
CC
ENABLE
DISABLE
V
= SEL = 3.3V
CC
90
80
70
60
50
40
30
20
10
0
V
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
IN
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
20dB ATTENUATION
ENABLE
DISABLE
V
= SEL = 2.5V
CC
ENABLE
DISABLE
V
= 3.3V, SEL = 0V
CC
–40
–20
0
20
40
60
80
0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9
DATA RATE (Gbps)
–40
–20
0
20
40
60
80
TEMPERATURE (؇C)
TEMPERATURE (؇C)
TPC 16. Enable/Disable Time
vs. Temperature
TPC 17. Enable/Disable Time
vs. Temperature
TPC 18. Jitter vs. Data Rate;
PRBS 31
–6–
REV. 0
ADG3242
100
95
90
85
80
75
V
= SEL = 3.3V
= 1.5V p-p
CC
V
IN
20dB ATTENUATION
70
65
60
55
50
V
= 2.5V
V
= 3.3V
20dB
ATTENUATION
CC
SEL = 2.5V
= 1.5V p-p
20dB
ATTENUATION
CC
SEL = 3.3V
= 1.5V p-p
20mV/DIV
200ps/DIV
50mV/DIV
200ps/DIV
V
V
T
= 25؇C
T = 25؇C
IN
IN
A
A
% EYE WIDTH = ((CLOCK PERIOD –
JITTER p-p)/CLOCK PERIOD)
؋
100% 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9
DATA RATE (Gbps)
TPC 20. Eye Pattern; 1.5 Gbps,
CC = 3.3 V, PRBS 31
TPC 21. Eye Pattern; 1.244 Gbps,
VCC = 2.5 V, PRBS 31
TPC 19. Eye Width vs. Data
Rate; PRBS 31
V
REV. 0
–7–
ADG3242
TIMING MEASUREMENT INFORMATION
For the following load circuit and waveforms, the notation that
is used is VIN and VOUT where
VIN = VA and VOUT = VB or VIN = VB and VOUT = VA
V
V
IH
CC
2
؋
V CC
CONTROL
INPUT BE
SW1
V
T
0V
GND
tPLH
tPLH
R
L
V
V
H
T
V
V
OUT
IN
V
PULSE
GENERATOR
OUT
DUT
V
L
R
R
C
L
L
T
Figure 2. Propagation Delay
NOTES
PULSE GENERATOR FOR ALL PULSES: tR Յ 2.5ns, tF Յ 2.5ns,
FREQUENCY Յ 10MHz.
C
INCLUDES BOARD, STRAY, AND LOAD CAPACITANCES.
L
R
IS THE TERMINATION RESISTOR, SHOULD BE EQUAL TO Z
T
OUT
OF THE PULSE GENERATOR.
Figure 1. Load Circuit
Test Conditions
Symbol
VCC = 3.3 V ؎ 0.3 V (SEL = VCC
)
VCC = 2.5 V ؎ 0.2 V (SEL = VCC
)
VCC = 3.3 V ؎ 0.3 V (SEL = 0 V) Unit
RL
V⌬
CL
VT
500
300
50
500
150
30
500
150
30
Ω
mV
pF
V
1.5
0.9
0.9
DISABLE
ENABLE
V
INH
V
CONTROL INPUT BE
T
Table II. Switch Position
0V
tPZL
tPLZ
Test
S1
V
CC
V
CC
V
OUT
tPLZ, tPZL
tPHZ, tPZH
2 × VCC
GND
V
V
= 0V
= V
T
IN
V
V
+V
⌬
L
L
SW1 @ 2V
CC
tPZH
tPHZ
V
V
H
H
V
OUT
V
–V
V
IN
CC
⌬
T
SW1 @ GND
0V
0V
Figure 3. Enable and Disable Times
–8–
REV. 0
ADG3242
BUS SWITCH APPLICATIONS
2.5 V to 1.8 V Translation
Mixed Voltage Operation, Level Translation
When VCC is 2.5 V (SEL = 2.5 V) and the input signal range is
0 V to VCC, the maximum output signal will, as before, be clamped
to within a voltage threshold below the VCC supply. In this case,
the output will be limited to approximately 1.8 V, as shown
in Figure 8.
Bus switches can provide an ideal solution for interfacing
between mixed voltage systems. The ADG3242 is suitable for
applications where voltage translation from 3.3 V technology to
a lower voltage technology is needed. This device can translate
from 3.3 V to 1.8 V, from 2.5 V to 1.8 V, or bidirectionally
from 3.3 V directly to 2.5 V.
2.5V
Figure 4 shows a block diagram of a typical application in which
a user needs to interface between a 3.3 V ADC and a 2.5 V
microprocessor. The microprocessor may not have 3.3 V toler-
ant inputs, therefore placing the ADG3242 between the two
devices allows the devices to communicate easily. The bus
switch directly connects the two blocks, therefore introducing
minimal propagation delay, timing skew, or noise.
ADG3242
2.5V
1.8V
Figure 7. 2.5 V to 1.8 V Voltage Translation, SEL = 2.5 VCC
3.3V
3.3V
2.5V
V
OUT
2.5V SUPPLY
SEL = 2.5V
2.5V
1.8V
3.3V ADC
MICROPROCESSOR
Figure 4. Level Translation between a 3.3 V ADC
and a 2.5 V Microprocessor
V
IN
0V
SWITCH
INPUT
2.5V
3.3 V to 2.5 V Translation
When VCC is 3.3 V (SEL = 3.3 V) and the input signal range is
0 V to VCC, the maximum output signal will be clamped to
within a voltage threshold below the VCC supply. In this case,
the output will be limited to 2.5 V, as shown in Figure 6. This
device can be used for translation from 2.5 V to 3.3 V devices
and also between two 3.3 V devices.
Figure 8. 2.5 V to 1.8 V Voltage Translation, SEL = VCC
3.3 V to 1.8 V Translation
The ADG3242 offers the option of interfacing between a 3.3 V
device and a 1.8 V device. This is possible through use of the
SEL pin. The SEL pin is an active low control pin. SEL acti-
vates internal circuitry in the ADG3242 that allows voltage
translation between 3.3 V devices and 1.8 V devices.
3.3V
When VCC is 3.3 V and the input signal range is 0 V to VCC, the
maximum output signal will be clamped to 1.8 V, as shown in
Figure 9. To do this, the SEL pin must be tied to Logic 0. If
3.3V
2.5V
2.5V
2.5V
ADG3242
SEL is unused, it should be tied directly to VCC
.
3.3V
Figure 5. 3.3 V to 2.5 V Voltage Translation, SEL = VCC
3.3V
ADG3242
1.8V
V
OUT
3.3V SUPPLY
SEL = 3.3V
2.5V
Figure 9. 3.3 V to 1.8 V Voltage Translation, SEL = 0 V
V
IN
V
OUT
3.3V SUPPLY
SEL = 0V
0V
SWITCH
INPUT
3.3V
1.8V
Figure 6. 3.3 V to 2.5 V Voltage Translation, SEL = VCC
V
IN
0V
SWITCH
INPUT
3.3V
Figure 10. 3.3 V to 1.8 V Voltage Translation, SEL = 0 V
REV. 0
–9–
ADG3242
Bus Isolation
There are many systems, such as docking stations, PCI boards
for servers, and line cards for telecommunications switches, that
require the ability to handle hot swapping. If the bus can be
isolated prior to insertion or removal, there is more control over
the hot swap event. This isolation can be achieved using bus
switches. The bus switches are positioned on the hot swap card
between the connector and the devices. During hot swap, the
ground pin of the hot swap card must connect to the ground pin
of the backplane before any other signal or power pins.
A common requirement of bus architectures is low capacitance
loading of the bus. Such systems require bus bridge devices that
extend the number of loads on the bus without exceeding the
specifications. Because the ADG3242 is designed specifically for
applications that do not need drive yet require simple logic
functions, it solves this requirement. The device isolates access
to the bus, thus minimizing capacitance loading.
LOAD A
LOAD C
Analog Switching
Bus switches can be used in many analog switching applications,
for example, video graphics. Bus switches can have lower on
resistance, smaller ON and OFF channel capacitance, and thus
improved frequency performance than their analog counterparts.
The bus switch channel itself, consisting solely of an NMOS
switch, limits the operating voltage (see TPC 1 for a typical
plot), but in many cases, this does not present an issue.
BUS/
BACKPLANE
LOAD B
LOAD D
BUS SWITCH
LOCATION
Figure 11. Location of Bus Switched in a Bus
Isolation Application
High Impedance during Power-Up/Power-Down
To ensure the high impedance state during power-up or power-
down, BE should be tied to VCC through a pull-up resistor; the
minimum value of the resistor is determined by the current-
sinking capability of the driver.
Hot Plug and Hot Swap Isolation
The ADG3242 is suitable for hot swap and hot plug applications.
The output signal of the ADG3242 is limited to a voltage that is
below the VCC supply, as shown in Figures 6, 8, and 10. Therefore
the switch acts like a buffer to take the impact from hot insertion,
protecting vital and expensive chipsets from damage.
In hot plug applications, the system cannot be shut down when
new hardware is being added. To overcome this, a bus switch can
be positioned on the backplane between the bus devices and the
hot plug connectors. The bus switch is turned off during hot plug.
Figure 12 shows a typical example of this type of application.
PLUG-IN
CARD I/O
CARD (1)
CPU
RAM
PLUG-IN
CARD I/O
CARD (2)
Figure 12. ADG3242 in a Hot Plug Application
–10–
REV. 0
ADG3242
OUTLINE DIMENSIONS
8-Lead Small Outline Transistor Package [SOT-23]
(RJ-8)
Dimensions shown in millimeters
2.90 BSC
8
1
7
2
6
3
5
4
1.60 BSC
PIN 1
2.80 BSC
0.65 BSC
1.95
BSC
1.30
1.15
0.90
1.45 MAX
0.22
0.08
0.60
0.45
0.30
8؇
4؇
0؇
0.38
0.22
0.15 MAX
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-178BA
REV. 0
–11–
–12–
相关型号：
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