ADG3257BRQ [ADI]
High Speed, 3.3 V/5 V Quad 2:1 Mux/Demux (4-Bit, 1 of 2) Bus Switch; 高速， 3.3 V / 5 V四路2 ： 1复用器/解复用器（ 4位， 1 2 ）总线开关
| 型号： | ADG3257BRQ |
| 厂家： | 
ADI |
| 描述： | High Speed, 3.3 V/5 V Quad 2:1 Mux/Demux (4-Bit, 1 of 2) Bus Switch |
| 文件： | 总8页 (文件大小：170K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
High Speed, 3.3 V/5 V Quad 2:1 Mux/Demux
(4-Bit, 1 of 2) Bus Switch
a
ADG3257
FEATURES
FUNCTIONAL BLOCK DIAGRAM
100 ps Propagation Delay through the Switch
2 ⍀ Switches Connect Inputs to Outputs
Data Rates up to 933 Mbps
1B
1B
1
1A
2
Single 3.3 V/5 V Supply Operation
Level Translation Operation
Ultralow Quiescent Supply Current (1 nA Typical)
3.5 ns Switching
2B
1
2A
3A
4A
2B
2
1
2
1
3B
3B
4B
Standard ‘3257 Type Pinout
APPLICATIONS
4B
2
Bus Switching
Bus Isolation
Level Translation
Memory Switching/Interleaving
LOGIC
BE
S
GENERAL DESCRIPTION
PRODUCT HIGHLIGHTS
The ADG3257 is a CMOS bus switch comprised of four 2:1
multiplexers/demultiplexers with high impedance outputs. The
device is manufactured on a CMOS process. This provides low
power dissipation yet high switching speed and very low ON
resistance, allowing the inputs to be connected to the outputs
without adding propagation delay or generating additional ground
bounce noise.
1. 0.1 ns propagation delay through switch
2. 2 Ω switches connect inputs to outputs
3. Bidirectional operation
4. Ultralow power dissipation
5. 16-lead QSOP package
The ADG3257 operates from a single 3.3 V/5 V supply. The
control logic for each switch is shown in Table I. These switches
are bidirectional when ON. In the OFF condition, signal levels are
blocked up to the supplies.
This bus switch is suited to both switching and level translation
applications. It may be used in applications requiring level
translation from 3.3 V to 2.5 V when powered from 3.3 V.
Additionally, with a diode connected in series with 5 V VDD
,
the ADG3257 may also be used in applications requiring 5 V
to 3.3 V level translation.
Table I. Truth Table
BE
S
Function
H
L
L
X
L
H
DISABLE
A = B1
A = B2
REV. C
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
www.analog.com
© 2003 Analog Devices, Inc. All rights reserved.
ADG3257–SPECIFICATIONS1
(VCC = 5.0 V ؎ 10%, GND = 0 V. All specifications TMIN to TMAX, unless otherwise noted.)
B Version
Parameter
Symbol
Conditions2
Min
Typ3 Max Unit
DC ELECTRICAL CHARACTERISTICS
Input High Voltage
Input Low Voltage
VINH
VINL
II
IOZ
IOZ
VP
2.4
–0.3
V
V
µA
µA
µA
V
+0.8
1
1
1
4.4
Input Leakage Current
0
0
0
Յ
Յ
Յ
VIN
A, B
A, B
Յ
Յ
Յ
5.5 V
VCC
VCC
0.01
0.01
0.01
OFF State Leakage Current
ON State Leakage Current
Max Pass Voltage4
VIN = VCC = 5 V, IO = –5 µA
3.9
4.2
CAPACITANCE4
A Port OFF Capacitance
B Port OFF Capacitance
A, B Port ON Capacitance
Control Input Capacitance
CA OFF
CB OFF
CA, CB ON f = 1 MHz
f = 1 MHz
f = 1 MHz
7
5
11
4
pF
pF
pF
pF
CIN
f = 1 MHz
SWITCHING CHARACTERISTICS4
Propagation Delay A to B or B to A tPD
Propagation Delay Matching6
Bus Enable Time BE to A or B
Bus Disable Time BE to A or B
Bus Select Time S to A or B
Enable
5
tPHL, tPLH
VA = 0 V, CL = 50 pF
VA = 0 V, CL = 50 pF
CL = 50 pF, RL = 500 Ω
CL = 50 pF, RL = 500 Ω
0.10 ns
0.0075 0.035 ns
t
PZH, tPZL
1
1
5
3.5
7.5
7
ns
ns
tPHZ, tPLZ
tSEL_EN
tSEL_DIS
CL = 50 pF, RL = 500 Ω
CL = 50 pF, RL = 500 Ω
VA = 2 V p-p
8
5
12
8
ns
ns
Disable
Max Data Rate
933
Mbps
DIGITAL SWITCH
ON Resistance
RON
VA = 0 V
IO = 48 mA, 15 mA, 8 mA, TA = 25°C
IO = 48 mA, 15 mA, 8 mA
VA = 2.4 V
2
3
4
Ω
Ω
IO = 48 mA, 15 mA, 8 mA, TA = 25°C
IO = 48 mA, 15 mA, 8 mA
VA = 0 V
48 mA, 15 mA, 8 mA, TA = 25°C
VA = 0 V, 48 mA, 15 mA, 8 mA
3
5
6
Ω
Ω
ON Resistance Matching
∆RON
0.15
0.35
0.7
Ω
Ω
POWER REQUIREMENTS
VCC
3.0
5.5
1
V
µA
Quiescent Power Supply Current
ICC
∆ICC
Digital Inputs = 0 V or VCC
VCC = 5.5 V, One Input at 3.0 V;
Others at VCC or GND
0.001
Increase in ICC per Input7
200
µA
NOTES
1Temperature range is as follows: B Version: –40°C to +85°C.
2See Test Circuits and Waveforms.
3All typical values are at TA = 25°C, unless otherwise noted.
4Guaranteed by design, not subject to production test.
5The digital switch contributes no propagation delay other than the RC delay of the typical RON of the switch and the load capacitance when driven by an ideal voltage
source. Since the time constant is much smaller than the rise/fall times of typical driving signals, it adds very little propagation delay to the system. Propagation delay
of the digital switch when used in a system is determined by the driving circuit on the driving side of the switch and its interaction with the load on the driven side.
6Propagation delay matching between channels is calculated from ON resistance matching of worst-case channel combinations and load capacitance.
7This current applies to the control pins only and represents the current required to switch internal capacitance at the specified frequency. The A and B ports
contribute no significant ac or dc currents as they transition. This parameter is guaranteed by design, not subject to production test.
Specifications subject to change without notice.
–2–
REV. C
ADG3257
SPECIFICATIONS1 (VCC = 3.3 V ؎ 10%, GND = 0 V. All specifications TMIN to TMAX, unless otherwise noted.)
B Version
Parameter
Symbol
Conditions2
Min
Typ3 Max
Unit
DC ELECTRICAL CHARACTERISTICS
Input High Voltage
Input Low Voltage
VINH
VINL
II
IOZ
IOZ
VP
2.0
–0.3
V
V
µA
µA
µA
V
+0.8
1
1
1
2.8
Input Leakage Current
0
0
0
Յ
Յ
Յ
V
A, B
A, B
IN Յ 3.6 V
0.01
0.01
0.01
OFF State Leakage Current
ON State Leakage Current
Max Pass Voltage4
Յ
VCC
VCC
Յ
VIN = VCC = 3.3 V, IO = –5 µA
2.3
2.6
CAPACITANCE4
A Port OFF Capacitance
B Port OFF Capacitance
A, B Port ON Capacitance
Control Input Capacitance
CA OFF
CB OFF
CA, CB ON f = 1 MHz
f = 1 MHz
f = 1 MHz
7
5
11
4
pF
pF
pF
pF
CIN
f = 1 MHz
SWITCHING CHARACTERISTICS4
Propagation Delay A to B or B to A tPD
Propagation Delay Matching6
Bus Enable Time BE to A or B
Bus Disable Time BE to A or B
Bus Select Time S to A or B
Enable
5
tPHL, tPLH
VA = 0 V, CL = 50 pF
VA = 0 V, CL = 50 pF
CL = 50 pF, RL = 500 Ω
CL = 50 pF, RL = 500 Ω
0.10
0.01 0.04
ns
ns
ns
ns
tPZH, tPZL
tPHZ, tPLZ
1
1
5.5
4.5
9
8.5
tSEL_EN
tSEL_DIS
CL = 50 pF, RL = 500 Ω
CL = 50 pF, RL = 500 Ω
VA = 2 Vp-p
8
6
933
12
9
ns
ns
Mbps
Disable
Max Data Rate
DIGITAL SWITCH
ON Resistance
RON
VA = 0 V
IO = 15 mA, 8 mA, TA = 25°C
2
4
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
4.5
16.5
18
14
17
VA = 1.7 V, IO = 15 mA, TA = 25°C
VA = 1.7 V, IO = 8 mA, TA = 25°C
8
7
ON Resistance Matching
∆RON
VA = 0 V, 15 mA, 8 mA, TA = 25°C
VA = 0 V, 15 mA, 8 mA
0.2
0.4
0.8
POWER REQUIREMENTS
VCC
3.0
5.5
V
Quiescent Power Supply Current
ICC
∆ICC
Digital Inputs = 0 V or VCC
VCC = 3.3 V, One Input at 3.0 V;
Others at VCC or GND
0.001 1
µA
Increase in ICC per Input7
200
µA
NOTES
1Temperature range is as follows: B Version: –40°C to +85°C.
2See Test Circuits and Waveforms.
3All typical values are at TA = 25°C, unless otherwise noted.
4Guaranteed by design, not subject to production test.
5The digital switch contributes no propagation delay other than the RC delay of the typical RON of the switch and the load capacitance when driven by an ideal voltage
source. Since the time constant is much smaller than the rise/fall times of typical driving signals, it adds very little propagation delay to the system. Propagation delay
of the digital switch when used in a system is determined by the driving circuit on the driving side of the switch and its interaction with the load on the driven side.
6Propagation delay matching between channels is calculated from ON resistance matching of worst-case channel combinations and load capacitance.
7This current applies to the control pins only and represents the current required to switch internal capacitance at the specified frequency. The A and B ports
contribute no significant ac or dc currents as they transition. This parameter is guaranteed by design, not subject to production test.
Specifications subject to change without notice.
–3–
REV. C
ADG3257
ABSOLUTE MAXIMUM RATINGS*
PIN CONFIGURATION
(TA = 25°C, unless otherwise noted.)
VCC to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V
Digital Inputs to GND . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V
DC Input Voltage . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V
DC Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA
Operating Temperature Range
Industrial (B Version) . . . . . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
QSOP Package
V
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
S
CC
1B
BE
1
2
4B
1B
1
4B
ADG3257
1A
2
TOP VIEW
2B
4A
3B
1
2
(Not to Scale)
2B
1
3B
2A
2
3A
GND
θ
JA Thermal Impedance . . . . . . . . . . . . . . . . . . 149.97°C/W
Lead Temperature, Soldering (10 sec) . . . . . . . . . . . . 300°C
IR Reflow, Peak Temperature (<20 sec) . . . . . . . . . . . 235°C
PIN FUNCTION DESCRIPTIONS
Stresses above those listed under Absolute Maximum Ratings may cause perma-
*
nent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability. Only one absolute
maximum rating may be applied at any one time.
Mnemonic
Description
BE
S
Ax
Bx
Output Enable (Active Low)
Port Select
Port A, Inputs or Outputs
Port B, Inputs or Outputs
ORDERING GUIDE
Model
Temperature Range
Package Descriptions
Package Option
RQ-16
ADG3257BRQ
–40°C to +85°C
RQ = 0.15" Quarter Size Outline Package (QSOP)
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the ADG3257 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
–4–
REV. C
Typical Performance Characteristics–ADG3257
20
16
12
20
16
12
20
V
= 5V
T
= 25 C
T
= 25 C
CC
A
A
15
10
5
V
= 3.0V
CC
V
CC
= 5.0V
8
4
0
8
4
0
V
= 2.7V
CC
+85 C
V
= 4.5V
CC
+25 C
V
= 3.3V
CC
V
= 5.5V
CC
–40 C
0
0
0.5
1.0
1.5
VA/VB – V
2.0
2.5
3.0
0
1
2
3
4
5
0
1
2
3
4
5
VA/VB – V
VA/VB – V
TPC 2. ON Resistance vs. Input
Voltage
TPC 3. ON Resistance vs. Input
Voltage for Different Temperatures
TPC 1. ON Resistance vs. Input
Voltage
20
10m
5
V = 5.5V
CC
T
= 25؇C
T
= 25؇C
V
= 3V
A
A
CC
1m
100
10
1
4
3
2
1
0
15
10
5
V
= 5V
CC
V
= 5.0V
CC
+85 C
V
= 4.5V
CC
+25 C
V
= 3V
CC
100n
10n
–40 C
0
0
0.5
1.0
1.5
VA/VB – V
2.0
2.5
3.0
0
1
2
3
4
5
0.1
1
10
100
1000
10000
INPUT VOLTAGE – V
FREQUENCY – kHz
TPC 6. Max Pass Voltage
TPC 4. ON Resistance vs. Input
TPC 5. ICC vs. Enable Frequency
Voltage for Different Temperatures
3.6
V
= 3.6V
T
= 25؇C
CC
A
3
2
1
0
V
= 3.3V
CC
V
= 3.0V
CC
40mV/DIV
267ps/DIV
V
V
= 5V
= 2V p-p
622MBPS
20dB ATTENUATION
= 25؇C
40mV/DIV
180ps/DIV
V
= 5V
= 2V p-p
933MBPS
20dB ATTENUATION
= 25؇C
CC
CC
T
T
A
V
A
IN
IN
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
INPUT VOLTAGE – V
TPC 7. Max Pass Voltage
TPC 8. 622 Mbps Eye Diagram
TPC 9. 933 Mbps Eye Diagram
–5–
REV. C
ADG3257
2
؋
V APPLICATIONS
CC
V
CC
S1
R
Mixed Voltage Operation, Level Translation
Bus switches can be used to provide a solution for mixed voltage
systems where interfacing bidirectionally between 5 V and 3 V
devices is required. To interface between 5 V and 3.3 V buses,
an external diode is placed in series with the 5 V power supply
as shown in Figure 4.
OPEN
GND
L
V
V
OUT
IN
1
PULSE
D.U.T.
GENERATOR
3
2
R
C
L
R
T
L
V
= 5V
CC
NOTES
1
PULSE GENERATOR FOR ALL PULSES: tF < 2.5ns, tR < 2.5ns.
2
3
C
R
= INCLUDES BOARD, STRAY, AND LOAD CAPACITANCES.
IS THE TERMINATION RESISTOR; SHOULD BE EQUAL TO Z
L
T
OUT
BE
OF THE PULSE GENERATOR.
Figure 1. Load Circuit
3.3V CPU/DSP/
MICROPROCESSOR/
MEMORY
5V MEMORY
5V I/O
V
IH
SWITCH INPUT
OUTPUT
V
T
3.3V TO 5V
0V
tPHL
tPLH
V
OH
3.3V TO 3.3V
V
T
V
OL
Figure 4. Level Translation Between 5 V and 3.3 V Devices
Figure 2. Propagation Delay
The diode drops the internal gate voltage down to 4.3 V.
The bus switch limits the voltage present on the output to
ENABLE
DISABLE
V
IH
V
CONTROL INPUTS
T
VCC – external diode drop = VTH
.
0V
Therefore, assuming a diode drop of 0.7 V and a VTH of 1 V,
the output voltage would be limited to 3.3 V with a logic high.
tPZL
tPLZ
V
CC
V
OUTPUT
CC
V
T
S1 @ 2V
CC
V
V
OL
+ ⌬V
– ⌬V
OL
V
OUT
LOW
5V SUPPLY
tPHZ
tPZH
3.3V
V
OH
OUTPUT
V
OH
V
T
S1 @ 2V
CC
0V
0V
Figure 3. Select, Enable, and Disable Times
V
IN
0V SWITCH INPUT 5V
Table II. Switch S1 Condition
Figure 5. Input Voltage to Output Voltage
Test
S1
Similarly, the device could be used to translate bidirectionally
between 3.3 V to 2.5 V systems. In this case, there is no need
for an external diode. The internal VTH drop is 1 V, so with a
VCC = 3.3 V the bus switch will limit the output voltage to
VCC – 1 V = 2.3 V.
tPLH, tPHL
tPLZ, tPZL
tPHZ, tPZH
tSEL
OPEN
2 × VCC
GND
OPEN
Table III. Test Conditions
Symbol VCC = 5 V ؎10% VCC = 3.3 V ؎10%
Unit
RL
V∆
CL
500
300
50
500
300
50
Ω
mV
pF
–6–
REV. C
ADG3257
3.3V
V
OUT
SDRAM #1
SDRAM #2
3.3V SUPPLY
2.5V
3.3V
2.5V
2.5V
2.5V
ADG3257
SDRAM #7
SDRAM #8
V
IN
0V
3.3V
SWITCH INPUT
LOGIC
Figure 6. 3.3 V to 2.5 V Level Translation Using the
ADG3257 Bus Switch
Memory Switching
S
BE
This quad bus switch may be used to allow switching between
different memory banks, thus allowing additional memory and
decreasing capacitive loading. Figure 7 illustrates the ADG3257
in such an application.
Figure 7. Allows Additional Memory Modules without
Added Drive or Delay
REV. C
–7–
ADG3257
OUTLINE DIMENSIONS
16-Lead Shrink Small Outline Package [QSOP]
(RQ-16)
Dimensions shown in inches
0.193
BSC
16
1
9
8
0.154
BSC
0.236
BSC
PIN 1
0.069
0.053
0.065
0.049
8؇
0؇
0.010
0.004
COPLANARITY
0.004
0.012
0.008
0.025
BSC
0.050
0.016
SEATING
PLANE
0.010
0.006
COMPLIANT TO JEDEC STANDARDS MO-137AB
Revision History
Location
Page
4/03—Data Sheet changed from REV. B to REV. C.
Updated Publication Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4/03—Data Sheet changed from REV. A to REV. B.
Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
06/02—Data Sheet changed from REV. 0 to REV. A.
Edits to FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
–8–
REV. C
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