ADG5409BRUZ-REEL7 [ADI]
High Voltage Latch-Up Proof, 4-/8-Channel Multiplexers; 高电压闩锁防，4 / 8通道多路复用器
| 型号： | ADG5409BRUZ-REEL7 |
| 厂家： | 
ADI |
| 描述： | High Voltage Latch-Up Proof, 4-/8-Channel Multiplexers |
| 文件： | 总24页 (文件大小：384K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
High Voltage Latch-Up Proof,
4-/8-Channel Multiplexers
Data Sheet
ADG5408/ADG5409
FEATURES
FUNCTIONAL BLOCK DIAGRAMS
Latch-up proof
ADG5408
ADG5409
8 kV human body model (HBM) ESD rating
Low on resistance (13.5 Ω)
9 V to 22 V dual-supply operation
9 V to 40 V single-supply operation
48 V supply maximum ratings
S1
S1A
S4A
DA
DB
D
S1B
S4B
Fully specified at 15 V, 20 V, +12 V, and +36 V
V
SS to VDD analog signal range
S8
APPLICATIONS
1-OF-8
DECODER
1-OF-4
DECODER
Relay replacement
Automatic test equipment
Data acquisition
A0 A1 A2 EN
A0 A1 EN
Figure 1.
Instrumentation
Avionics
Audio and video switching
Communication systems
GENERAL DESCRIPTION
The ADG5408/ADG5409 do not have VL pins; rather, the logic
power supply is generated internally by an on-chip voltage
generator.
The ADG5408/ADG5409 are monolithic CMOS analog multi-
plexers comprising eight single channels and four differential
channels, respectively. The ADG5408 switches one of eight
inputs to a common output, as determined by the 3-bit binary
address lines, A0, A1, and A2. The ADG5409 switches one of
four differential inputs to a common differential output, as
determined by the 2-bit binary address lines, A0 and A1.
PRODUCT HIGHLIGHTS
1. Trench isolation guards against latch-up. A dielectric trench
separates the P and N channel transistors thereby preventing
latch-up even under severe overvoltage conditions.
An EN input on both devices enables or disables the device.
When EN is disabled, all channels switch off. The on-resistance
profile is very flat over the full analog input range, which ensures
good linearity and low distortion when switching audio signals.
High switching speed also makes the parts suitable for video
signal switching.
2. Low RON
.
3. Dual-supply operation. For applications where the analog
signal is bipolar, the ADG5408/ADG5409 can be operated
from dual supplies up to 22 V.
4. Single-supply operation. For applications where the analog
signal is unipolar, the ADG5408/ADG5409 can be operated
from a single rail power supply up to 40 V.
Each switch conducts equally well in both directions when on,
and each switch has an input signal range that extends to the
power supplies. In the off condition, signal levels up to the
supplies are blocked.
5. 3 V logic compatible digital inputs: VINH = 2.0 V, VINL = 0.8 V.
6. No VL logic power supply required.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rightsof third parties that may result fromits use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks andregisteredtrademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2010–2012 Analog Devices, Inc. All rights reserved.
ADG5408/ADG5409
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Absolute Maximum Ratings ............................................................9
ESD Caution...................................................................................9
Pin Configurations and Function Descriptions......................... 10
Typical Performance Characteristics ........................................... 12
Test Circuits..................................................................................... 16
Terminology.................................................................................... 18
Trench Isolation.............................................................................. 19
Applications Information .............................................................. 20
Outline Dimensions....................................................................... 21
Ordering Guide .......................................................................... 22
Applications....................................................................................... 1
Functional Block Diagrams............................................................. 1
General Description ......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ........................................................................... 2
Specifications..................................................................................... 3
15 V Dual Supply ....................................................................... 3
20 V Dual Supply ....................................................................... 4
12 V Single Supply........................................................................ 5
36 V Single Supply........................................................................ 6
Continuous Current per Channel, Sx or D............................... 8
REVISION HISTORY
5/12—Rev. A to Rev. B
Removed Automotive Information (Throughout)....................... 1
Changes to Ordering Guide .......................................................... 22
Deleted Automotive Products Section......................................... 22
6/11—Rev. 0 to Rev. A
Change to Features Section ............................................................. 1
Change to ISS Parameter, Table 2..................................................... 5
Changes to Figure 3........................................................................ 10
Changes to Figure 5........................................................................ 11
Updated Outline Dimensions....................................................... 21
Changes to Ordering Guide .......................................................... 21
Added Automotive Products Section........................................... 21
7/10—Revision 0: Initial Version
Rev. B | Page 2 of 24
Data Sheet
ADG5408/ADG5409
SPECIFICATIONS
15 V DUAL SUPPLY
VDD = +15 V 10%, VSS = −15 V 10%, GND = 0 V, unless otherwise noted.
Table 1.
Parameter
25°C −40°C to +85°C −40°C to +125°C Unit
Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
VDD to VSS
22
V
13.5
15
0.3
Ω typ
Ω max
Ω typ
VS = 10 V, IS = −10 mA; see Figure 26
VDD = +13.5 V, VSS = −13.5 V
VS = 10 V, IS = −10 mA
18
On-Resistance Match Between
Channels, ∆RON
0.8
1.8
2.2
1.3
2.6
1.4
3
Ω max
Ω typ
Ω max
On-Resistance Flatness, RFLAT (ON)
VS = 10 V, IS = −10 mA
LEAKAGE CURRENTS
VDD = +16.5 V, VSS = −16.5 V
Source Off Leakage, IS (Off)
0.05
nA typ
nA max
nA typ
nA max
nA typ
nA max
VS = 10 V, VD =
10 V; see Figure 29
0.25
0.1
0.4
0.1
0.4
1
4
4
7
Drain Off Leakage, ID (Off)
Channel On Leakage, ID (On), IS (On)
DIGITAL INPUTS
VS = 10 V, VD =
10 V; see Figure 29
30
30
VS = VD = 10 V; see Figure 25
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINL or IINH
2.0
0.8
V min
V max
µA typ
µA max
pF typ
0.002
3
VIN = VGND or VDD
0.1
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS1
Transition Time, tTRANSITION
170
217
140
175
130
161
ns typ
ns max
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
RL = 300 Ω, CL = 35 pF
VS = 10 V; see Figure 32
RL = 300 Ω, CL = 35 pF
VS = 10 V; see Figure 34
RL = 300 Ω, CL = 35 pF
VS = 10 V; see Figure 34
RL = 300 Ω, CL = 35 pF
VS1 = VS2 = 10 V; see Figure 33
258
213
183
292
242
198
16
tON (EN)
tOFF (EN)
Break-Before-Make Time Delay, tD 50
Charge Injection, QINJ
115
VS = 0 V, RS = 0 Ω, CL = 1 nF;
see Figure 35
Off Isolation
−60
−60
0.01
dB typ
dB typ
% typ
RL = 50 Ω, CL = 5 pF, f = 1 MHz; see
Figure 28
RL = 50 Ω, CL = 5 pF, f = 1 MHz; see
Figure 27
RL = 1 kΩ, 15 V p-p, f = 20 Hz to 20 kHz;
see Figure 30
Channel-to-Channel Crosstalk
Total Harmonic Distortion + Noise
−3 dB Bandwidth
ADG5408
ADG5409
RL = 50 Ω, CL = 5 pF; see Figure 31
50
87
0.9
MHz typ
MHz typ
dB typ
Insertion Loss
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
Figure 31
CS (Off)
15
pF typ
VS = 0 V, f = 1 MHz
CD (Off)
ADG5408
ADG5409
102
50
pF typ
pF typ
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
Rev. B | Page 3 of 24
ADG5408/ADG5409
Data Sheet
Parameter
CD (On), CS (On)
ADG5408
25°C −40°C to +85°C −40°C to +125°C Unit
Test Conditions/Comments
133
81
pF typ
pF typ
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
ADG5409
POWER REQUIREMENTS
IDD
VDD = +16.5 V, VSS = −16.5 V
Digital inputs = 0 V or VDD
45
55
0.001
µA typ
µA max
µA typ
µA max
70
1
ISS
Digital inputs = 0 V or VDD
VDD/VSS
9/ 22
V min/V max GND = 0 V
1 Guaranteed by design; not subject to production test.
20 V DUAL SUPPLY
VDD = +20 V 10%, VSS = −20 V 10%, GND = 0 V, unless otherwise noted.
Table 2.
Parameter
25°C −40°C to +85°C −40°C to +125°C Unit
Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
VDD to VSS
21
V
12.5
14
0.3
Ω typ
Ω max
Ω typ
VS = 15 V, IS = −10 mA; see Figure 26
VDD = +18 V, VSS = −18 V
VS = 15 V, IS = −10 mA
17
On-Resistance Match Between
Channels, ∆RON
0.8
2.3
2.7
1.3
3.1
1.4
3.5
Ω max
Ω typ
Ω max
On-Resistance Flatness, RFLAT (ON)
VS = 15 V, IS = −10 mA
VDD = +22 V, VSS = −22 V
LEAKAGE CURRENTS
Source Off Leakage, IS (Off)
0.1
0.25
0.15
0.4
0.15
0.4
nA typ
nA max
nA typ
nA max
nA typ
nA max
VS = 15 V, VD =
15 V; see Figure 29
1
4
4
7
Drain Off Leakage, ID (Off)
VS = 15 V, VD =
15 V; see Figure 29
30
30
Channel On Leakage, ID (On), IS (On)
VS = VD = 15 V; see Figure 25
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINL or IINH
2.0
0.8
V min
V max
µA typ
µA max
pF typ
0.002
3
VIN = VGND or VDD
0.1
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS1
Transition Time, tTRANSITION
160
207
140
165
133
153
ns typ
ns max
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
RL = 300 Ω, CL = 35 pF
VS = 10 V; see Figure 32
RL = 300 Ω, CL = 35 pF
VS = 10 V; see Figure 34
RL = 300 Ω, CL = 35 pF
VS = 10 V; see Figure 34
RL = 300 Ω, CL = 35 pF
VS1 = VS2 = 10 V; see Figure 33
VS = 0 V, RS = 0 Ω, CL = 1 nF; see
Figure 35
RL = 50 Ω, CL = 5 pF, f = 1 MHz; see
Figure 28
237
194
174
262
218
189
11
tON (EN)
tOFF (EN)
Break-Before-Make Time Delay, tD 38
Charge Injection, QINJ
Off Isolation
155
−60
−60
dB typ
dB typ
Channel-to-Channel Crosstalk
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
see Figure 27
Rev. B | Page 4 of 24
Data Sheet
ADG5408/ADG5409
Parameter
25°C −40°C to +85°C −40°C to +125°C Unit
Test Conditions/Comments
Total Harmonic Distortion + Noise
0.012
% typ
RL = 1 kΩ, 20 V p-p, f = 20 Hz to 20 kHz;
see Figure 30
−3 dB Bandwidth
ADG5408
ADG5409
RL = 50 Ω, CL = 5 pF; see Figure 31
50
88
0.8
MHz typ
MHz typ
dB typ
Insertion Loss
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
see Figure 31
CS (Off)
CD (Off)
17
pF typ
VS = 0 V, f = 1 MHz
ADG5408
ADG5409
98
48
pF typ
pF typ
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
CD (On), CS (On)
ADG5408
ADG5409
128
80
pF typ
pF typ
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
POWER REQUIREMENTS
IDD
VDD = +22 V, VSS = −22 V
Digital inputs = 0 V or VDD
50
70
0.001
µA typ
µA max
µA typ
µA max
110
1
ISS
Digital inputs = 0 V or VDD
VDD/VSS
9/ 22
V min/V max GND = 0 V
1 Guaranteed by design; not subject to production test.
12 V SINGLE SUPPLY
VDD = 12 V 10%, VSS = 0 V, GND = 0 V, unless otherwise noted.
Table 3.
Parameter
25°C −40°C to +85°C −40°C to +125°C Unit
Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
0 V to VDD
42
V
26
Ω typ
VS = 0 V to 10 V, IS = −10 mA; see
Figure 26
VDD = 10.8 V, VSS = 0 V
30
0.3
36
Ω max
Ω typ
On-Resistance Match Between
Channels, ∆RON
VS = 0 V to 10 V, IS = −10 mA
1
5.5
6.5
1.5
8
1.6
12
Ω max
Ω typ
Ω max
On-Resistance Flatness, RFLAT (ON)
VS = 0 V to 10 V, IS = −10 mA
VDD = 13.2 V, VSS = 0 V
LEAKAGE CURRENTS
Source Off Leakage, IS (Off)
0.02
nA typ
VS = 1 V/10 V, VD = 10 V/1 V; see
Figure 29
0.25
0.05
1
7
nA max
nA typ
Drain Off Leakage, ID (Off)
VS = 1 V/10 V, VD = 10 V/1 V; see
Figure 29
0.4
0.05
0.4
4
4
30
30
nA max
nA typ
nA max
Channel On Leakage, ID (On), IS (On)
VS = VD = 1 V/10 V; see Figure 25
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINL or IINH
2.0
0.8
V min
V max
µA typ
µA max
pF typ
0.002
3
VIN = VGND or VDD
0.1
Digital Input Capacitance, CIN
Rev. B | Page 5 of 24
ADG5408/ADG5409
Data Sheet
Parameter
25°C −40°C to +85°C −40°C to +125°C Unit
Test Conditions/Comments
DYNAMIC CHARACTERISTICS1
Transition Time, tTRANSITION
230
321
215
276
134
161
ns typ
RL = 300 Ω, CL = 35 pF
VS = 8 V; see Figure 32
RL = 300 Ω, CL = 35 pF
VS = 8 V; see Figure 34
RL = 300 Ω, CL = 35 pF
VS = 8 V; see Figure 34
RL = 300 Ω, CL = 35 pF
VS1 = VS2 = 8 V; see Figure 33
388
345
187
430
397
209
55
ns max
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
tON (EN)
tOFF (EN)
Break-Before-Make Time Delay, tD 118
Charge Injection, QINJ
45
VS = 6 V, RS = 0 Ω, CL = 1 nF; see
Figure 35
Off Isolation
−60
−60
0.1
dB typ
dB typ
% typ
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
see Figure 28
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
see Figure 27
RL = 1 kΩ, 6 V p-p, f = 20 Hz to 20 kHz;
see Figure 30
Channel-to-Channel Crosstalk
Total Harmonic Distortion + Noise
−3 dB Bandwidth
ADG5408
ADG5409
RL = 50 Ω, CL = 5 pF; see Figure 31
35
74
−1.8
MHz typ
MHz typ
dB typ
Insertion Loss
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
see Figure 31
CS (Off)
CD (Off)
22
pF typ
VS = 6 V, f = 1 MHz
ADG5408
ADG5409
119
59
pF typ
pF typ
VS = 6 V, f = 1 MHz
VS = 6 V, f = 1 MHz
CD (On), CS (On)
ADG5408
ADG5409
146
86
pF typ
pF typ
VS = 6 V, f = 1 MHz
VS = 6 V, f = 1 MHz
VDD = 13.2 V
POWER REQUIREMENTS
IDD
40
50
µA typ
µA max
Digital inputs = 0 V or VDD
65
VDD
9/40
V min/V max GND = 0 V, VSS = 0 V
1 Guaranteed by design; not subject to production test.
36 V SINGLE SUPPLY
VDD = 36 V 10%, VSS = 0 V, GND = 0 V, unless otherwise noted.
Table 4.
Parameter
25°C −40°C to +85°C −40°C to +125°C Unit
Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
0 V to VDD
23
V
14.5
Ω typ
VS = 0 V to 30 V, IS = −10 mA; see
Figure 26
VDD = 32.4 V, VSS = 0 V
16
0.3
19
Ω max
Ω typ
On-Resistance Match Between
Channels, ∆RON
VS = 0 V to 30 V, IS = −10 mA
0.8
3.5
4.3
1.3
5.5
1.4
6.5
Ω max
Ω typ
Ω max
On-Resistance Flatness, RFLAT (ON)
VS = 0 V to 30 V, IS = −10 mA
VDD =39.6 V, VSS = 0 V
LEAKAGE CURRENTS
Source Off Leakage, IS (Off)
0.1
nA typ
VS = 1 V/30 V, VD = 30 V/1 V; see
Figure 29
0.25
1
7
nA max
Rev. B | Page 6 of 24
Data Sheet
ADG5408/ADG5409
Parameter
25°C −40°C to +85°C −40°C to +125°C Unit
Test Conditions/Comments
Drain Off Leakage, ID (Off)
0.15
nA typ
VS = 1 V/30 V, VD = 30 V/1 V; see
Figure 29
0.4
0.15
0.4
4
4
30
30
nA max
nA typ
nA max
Channel On Leakage, ID (On), IS (On)
VS = VD = 1 V/30 V; see Figure 25
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINL or IINH
2.0
0.8
V min
V max
µA typ
µA max
pF typ
0.002
3
VIN = VGND or VDD
0.1
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS1
Transition Time, tTRANSITION
187
242
160
195
147
184
ns typ
ns max
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
RL = 300 Ω, CL = 35 pF
VS = 18 V; see Figure 32
RL = 300 Ω, CL = 35 pF
VS = 18 V; see Figure 34
RL = 300 Ω, CL = 35 pF
VS = 18 V; see Figure 34
RL = 300 Ω, CL = 35 pF
VS1 = VS2 = 18 V; see Figure 33
257
219
184
281
237
190
17
tON (EN)
tOFF (EN)
Break-Before-Make Time Delay, tD 53
Charge Injection, QINJ
150
VS = 18 V, RS = 0 Ω, CL = 1 nF;
see Figure 35
Off Isolation
−60
−60
0.4
dB typ
dB typ
% typ
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
see Figure 28
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
see Figure 27
RL = 1 kΩ, 18 V p-p, f = 20 Hz to 20 kHz;
see Figure 30
Channel-to-Channel Crosstalk
Total Harmonic Distortion + Noise
−3 dB Bandwidth
ADG5408
ADG5409
RL = 50 Ω, CL = 5 pF; see Figure 31
45
76
−1
MHz typ
MHz typ
dB typ
Insertion Loss
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
see Figure 31
CS (Off)
CD (Off)
18
pF typ
VS = 18 V, f = 1 MHz
ADG5408
ADG5409
120
60
pF typ
pF typ
VS = 18 V, f = 1 MHz
VS = 18 V, f = 1 MHz
CD (On), CS (On)
ADG5408
ADG5409
137
80
pF typ
pF typ
VS = 18 V, f = 1 MHz
VS = 18 V, f = 1 MHz
VDD = 39.6 V
POWER REQUIREMENTS
IDD
80
µA typ
Digital inputs = 0 V or VDD
100
130
µA max
VDD
9/40
V min/V max GND = 0 V, VSS = 0 V
1 Guaranteed by design; not subject to production test.
Rev. B | Page 7 of 24
ADG5408/ADG5409
Data Sheet
CONTINUOUS CURRENT PER CHANNEL, Sx OR D
Table 5. ADG5408
Parameter
25°C
85°C
125°C
Unit
CONTINUOUS CURRENT, Sx OR D
VDD = +15 V, VSS = −15 V
TSSOP (θJA = 112.6°C/W)
LFCSP (θJA = 30.4°C/W)
VDD = +20 V, VSS = −20 V
TSSOP (θJA = 112.6°C/W)
LFCSP (θJA = 30.4°C/W)
VDD = 12 V, VSS = 0 V
100
170
44
54
16
16
mA maximum
mA maximum
106
178
45
55
16
16
mA maximum
mA maximum
TSSOP (θJA = 112.6°C/W)
LFCSP (θJA = 30.4°C/W)
VDD = 36 V, VSS = 0 V
81
140
39
51
15
16
mA maximum
mA maximum
TSSOP (θJA = 112.6°C/W)
LFCSP (θJA = 30.4°C/W)
104
175
44
55
16
16
mA maximum
mA maximum
Table 6. ADG5409
Parameter
25°C
85°C
125°C
Unit
CONTINUOUS CURRENT, Sx OR D
VDD = +15 V, VSS = −15 V
TSSOP (θJA = 112.6°C/W)
LFCSP (θJA = 30.4°C/W)
VDD = +20 V, VSS = −20 V
TSSOP (θJA = 112.6°C/W)
LFCSP (θJA = 30.4°C/W)
VDD = 12 V, VSS = 0 V
75
130
37
49
15
16
mA maximum
mA maximum
79
136
38
50
15
16
mA maximum
mA maximum
TSSOP (θJA = 112.6°C/W)
LFCSP (θJA = 30.4°C/W)
VDD = 36 V, VSS = 0 V
60
105
32
44
14
16
mA maximum
mA maximum
TSSOP (θJA = 112.6°C/W)
LFCSP (θJA = 30.4°C/W)
78
133
38
50
15
16
mA maximum
mA maximum
Rev. B | Page 8 of 24
Data Sheet
ADG5408/ADG5409
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Table 7.
Parameter
Rating
VDD to VSS
48 V
−0.3 V to +48 V
+0.3 V to −48 V
VSS − 0.3 V to VDD + 0.3 V or
30 mA, whichever occurs first
VDD to GND
VSS to GND
Analog Inputs1
Digital Inputs1
VSS − 0.3 V to VDD + 0.3 V or
30 mA, whichever occurs first
Only one absolute maximum rating can be applied at any
one time.
Peak Current, Sx or D Pins
ADG5408
ESD CAUTION
370 mA (pulsed at 1 ms, 10%
duty cycle maximum)
ADG5409
275 mA (pulsed at 1 ms, 10%
duty cycle maximum)
Continuous Current, Sx or D2
Temperature Range
Operating
Storage
Junction Temperature
Thermal Impedance, θJA
Data + 15%
−40°C to +125°C
−65°C to +150°C
150°C
16-Lead TSSOP (4-Layer
Board)
16-Lead LFCSP (4-Layer
Board)
112.6°C/W
30.4°C/W
Reflow Soldering Peak
Temperature, Pb Free
260(+0/−5)°C
1 Overvoltages at the Ax, EN, Sx, and D pins are clamped by internal diodes.
Limit current to the maximum ratings given.
2 See Table 5.
Rev. B | Page 9 of 24
ADG5408/ADG5409
Data Sheet
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
A0
EN
A1
A2
V
GND
SS
V
1
2
3
4
12 GND
SS
S1
V
ADG5408
TOP VIEW
(Not to Scale)
ADG5408
TOP VIEW
(Not to Scale)
V
11
DD
S1
S2
S3
DD
S2
S3
S4
D
S5
S6
S7
S8
10 S5
9
S6
NOTES
1. THE EXPOSED PAD IS
CONNECTED INTERNALLY. FOR
INCREASED RELIABILITY OF THE
SOLDER JOINTS AND MAXIMUM
THERMAL CAPABILITY, IT IS
RECOMMENDED THAT THE PAD BE
SOLDERED TO THE SUBSTRATE, V
.
SS
Figure 2. ADG5408 Pin Configuration (TSSOP)
Figure 3. ADG5408 Pin Configuration (LFCSP)
Table 8. ADG5408 Pin Function Descriptions
Pin No.
TSSOP
LFCSP
15
16
Mnemonic
Description
1
2
A0
EN
Logic Control Input.
Active High Digital Input. When low, the device is disabled and all switches are off. When high,
Ax logic inputs determine on switches.
3
1
VSS
Most Negative Power Supply Potential. In single-supply applications, this pin can be connected
to ground.
4
5
6
7
8
9
10
11
12
13
14
15
16
2
3
4
5
6
7
8
9
10
11
12
13
14
EP
S1
S2
S3
S4
D
S8
S7
S6
S5
VDD
GND
A2
A1
Source Terminal 1. This pin can be an input or an output.
Source Terminal 2. This pin can be an input or an output.
Source Terminal 3. This pin can be an input or an output.
Source Terminal 4. This pin can be an input or an output.
Drain Terminal. This pin can be an input or an output.
Source Terminal 8. This pin can be an input or an output.
Source Terminal 7. This pin can be an input or an output.
Source Terminal 6. This pin can be an input or an output.
Source Terminal 5. This pin can be an input or an output.
Most Positive Power Supply Potential.
Ground (0 V) Reference.
Logic Control Input.
Logic Control Input.
Exposed Pad The exposed pad is connected internally. For increased reliability of the solder joints and
maximum thermal capability, it is recommended that the pad be soldered to the substrate, VSS.
Table 9. ADG5408 Truth Table
A2
X
0
0
0
0
1
1
1
A1
X
0
0
1
1
0
0
1
A0
X
0
1
0
1
0
1
0
EN
0
1
1
1
1
1
1
1
On Switch
None
1
2
3
4
5
6
7
8
1
1
1
1
Rev. B | Page 10 of 24
Data Sheet
ADG5408/ADG5409
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
A0
EN
A1
GND
V
V
DD
SS
V
1
2
3
4
12 V
SS
DD
S1B
S2B
S3B
ADG5409
TOP VIEW
(Not to Scale)
S1A
S1B
S2B
S3B
S4B
DB
ADG5409
TOP VIEW
(Not to Scale)
11
10
9
S1A
S2A
S3A
S2A
S3A
S4A
DA
NOTES
1. THE EXPOSED PAD IS
CONNECTED INTERNALLY. FOR
INCREASED RELIABILITY OF THE
SOLDER JOINTS AND MAXIMUM
THERMAL CAPABILITY, IT IS
RECOMMENDED THAT THE PAD BE
SOLDERED TO THE SUBSTRATE, V
.
SS
Figure 4. ADG5409 Pin Configuration (TSSOP)
Figure 5. ADG5409 Pin Configuration (LFCSP)
Table 10. ADG5409 Pin Function Descriptions
Pin No.
TSSOP LFCSP
Mnemonic Description
1
2
15
16
A0
EN
Logic Control Input.
Active High Digital Input. When low, the device is disabled and all switches are off. When high,
Ax logic inputs determine on switches.
3
1
VSS
Most Negative Power Supply Potential. In single-supply applications, this pin can be connected
to ground.
4
5
6
7
8
9
10
11
12
13
14
15
16
2
3
4
5
6
7
8
9
10
11
12
13
14
EP
S1A
S2A
S3A
S4A
DA
Source Terminal 1A. This pin can be an input or an output.
Source Terminal 2A. This pin can be an input or an output.
Source Terminal 3A. This pin can be an input or an output.
Source Terminal 4A. This pin can be an input or an output.
Drain Terminal A. This pin can be an input or an output.
Drain Terminal B. This pin can be an input or an output.
Source Terminal 4B. This pin can be an input or an output.
Source Terminal 3B. This pin can be an input or an output.
Source Terminal 2B. This pin can be an input or an output.
Source Terminal 1B. This pin can be an input or an output.
Most Positive Power Supply Potential.
DB
S4B
S3B
S2B
S1B
VDD
GND
A1
Ground (0 V) Reference.
Logic Control Input.
Exposed
Pad
The exposed pad is connected internally. For increased reliability of the solder joints and maximum
thermal capability, it is recommended that the pad be soldered to the substrate, VSS.
Table 11. ADG5409 Truth Table
A1
A0
EN
0
On Switch Pair
X
X
None
0
0
1
1
0
1
0
1
1
1
1
1
1
2
3
4
Rev. B | Page 11 of 24
ADG5408/ADG5409
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
25
16
14
12
10
8
T
= 25°C
T
= 25°C
A
A
V
V
= +10V
= –10V
V
V
= +9V
= –9V
DD
SS
DD
SS
20
15
10
5
V
V
= +11V
= –11V
DD
SS
V
V
= 32.4V
= 0V
DD
SS
V
V
= 39.6V
= 0V
V
V
= 36V
= 0V
DD
SS
DD
SS
V
V
= +13.5V
= –13.5V
6
DD
SS
V
V
= +15V
= –15V
DD
SS
V
V
= +16.5V
= –16.5V
DD
SS
4
2
0
–18
0
–14
–10
–6
–2
2
6
10
14
18
0
5
10
15
20
25
30
35
40
45
V , V (V)
V , V (V)
S
D
S
D
Figure 9. RON as a Function of VS, VD (Single Supply)
Figure 6. RON as a Function of VS, VD (Dual Supply)
25
20
15
10
5
16
14
12
10
8
T
= 25°C
A
V
V
= +18V
= –18V
DD
SS
T
= +125°C
= +85°C
A
T
A
A
A
V
V
= +22V
= –22V
V
V
= +20V
= –20V
DD
SS
DD
T
T
= +25°C
= –40°C
SS
6
4
2
V
V
= +15V
= –15V
DD
SS
0
–15
0
–10
–5
0
5
10
15
–25 –20 –15 –10
–5
0
5
10
15
20
25
V , V (V)
V , V (V)
S
D
S
D
Figure 10. RON as a Function of VS (VD) for Different Temperatures,
15 V Dual Supply
Figure 7. RON as a Function of VS, VD (Dual Supply)
25
–35
–30
–25
–20
–15
–10
–5
V
V
= +20V
= –20V
T
= 25°C
DD
SS
A
V
V
= 10V
= 0V
DD
SS
V
V
= 10.8V
= 0V
DD
SS
V
V
= 9V
= 0V
20
15
10
5
DD
SS
T
= +125°C
= +85°C
A
T
A
A
A
V
V
= 11V
= 0V
DD
SS
V
V
= 12V
= 0V
DD
SS
T
T
= +25°C
= –40°C
V
V
= 13.2V
= 0V
DD
SS
0
–20
0
–15
–10
–5
0
5
10
15
20
0
–2
–4
–6
–8
V , V (V)
–10
–12
–14
S
D
V , V (V)
S
D
Figure 8. RON as a Function of VS, VD (Single Supply)
Figure 11. RON as a Function of VS (VD) for Different Temperatures,
20 V Dual Supply
Rev. B | Page 12 of 24
Data Sheet
ADG5408/ADG5409
40
35
30
25
20
15
10
5
1
0
V
V
V
= +20V
= –20V
BIAS
I
, I (ON) + +
S
DD
SS
D
I
(OFF) + –
S
= +15V/–15V
T
= +125°C
= +85°C
A
T
A
I
(OFF) – +
D
I
(OFF) – +
S
T
T
= +25°C
= –40°C
A
–1
–2
–3
I
, I (ON) – –
S
D
A
I
(OFF) + –
D
V
V
= 12V
= 0V
DD
SS
0
0
2
4
6
8
10
12
0
25
50
75
100
125
V , V (V)
TEMPERATURE (°C)
S
D
Figure 12. RON as a Function of VS (VD) for Different Temperatures,
12 V Single Supply
Figure 15. Leakage Currents vs. Temperature, 20 V Dual Supply
0.5
25
V
V
V
= 12V
= 0V
BIAS
V
V
= 36V
= 0V
I
, I (ON) + +
S
DD
SS
DD
SS
D
= 1V/10V
I
(OFF) + –
S
20
15
10
5
0
–0.5
–1.0
–1.5
–2.0
I
(OFF) – +
D
T
= +125°C
= +85°C
A
I
(OFF) – +
S
T
A
A
A
I
, I (ON) – –
S
D
T
T
= +25°C
= –40°C
I
(OFF) + –
D
0
0
5
10
15
20
25
30
35
40
0
25
50
75
100
125
V
, V (V)
D
TEMPERATURE (°C)
S
Figure 16. Leakage Currents vs. Temperature, 12 V Single Supply
Figure 13. RON as a Function of VD (VS) for Different Temperatures,
36 V Single Supply
1
0.5
V
V
V
= +15V
= –15V
BIAS
V
V
V
= +36V
= 0V
BIAS
I
, I (ON) + +
S
DD
SS
DD
SS
D
I
, I (ON) + +
S
D
I (OFF) + –
S
= +10V/–10V
I
(OFF) + –
= 1V/30V
S
0
–0.5
–1.0
–1.5
–2.0
0
–1
–2
–3
I
(OFF) – +
D
I
(OFF) – +
I
(OFF) – +
S
D
I
(OFF) – +
S
I
, I (ON) – –
S
D
I
, I (ON) – –
S
D
I
(OFF) + –
D
I
(OFF) + –
D
0
25
50
75
100
125
0
25
50
75
100
125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 17. Leakage Currents vs. Temperature, 36 V Single Supply
Figure 14. Leakage Currents vs. Temperature, 15 V Dual Supply
Rev. B | Page 13 of 24
ADG5408/ADG5409
Data Sheet
0
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
T
V
V
= 25°C
= +15V
T
= 25°C
= +15V
SS
A
A
DD
V
V
DD
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
= –15V
= –15V
SS
NO DECOUPLING
CAPACITORS
DECOUPLING
CAPACITORS
1k
10k
100k
1M
10M
100M
1G
1G
40
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 18. Off Isolation vs. Frequency, 15 V Dual Supply
Figure 21. ACPSRR vs. Frequency, 15 V Dual Supply
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
0.12
0.10
0.08
0.06
0.04
0.02
0
T
= 25°C
A
V
V
= +15V
= –15V
DD
SS
V
= 12V, V = 0V, V = 6V p-p
SS
DD
S
LOAD = 1kΩ
T
= 25°C
A
V
V
= 36V, V = 0V, V = 18V p-p
SS
DD
S
= 15V, V = 15V, V = 15V p-p
SS
DD
S
V
= 20V, V = 20V, V = 20V p-p
SS
DD
S
10k
100k
1M
10M
100M
0
5
10
FREQUENCY (kHz)
15
20
FREQUENCY (Hz)
Figure 19. Crosstalk vs. Frequency, 15 V Dual Supply
Figure 22. THD + N vs. Frequency
0
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
–3.5
–4.0
–4.5
–5.0
300
250
200
150
100
50
T
= 25°C
= +15V
A
T
= 25°C
A
V
V
= +20V
= –20V
V
V
DD
SS
DD
SS
= –15V
ADG5409
ADG5408
V
V
= +36V
= 0V
DD
SS
V
V
= +12V
= 0V
DD
SS
V
V
= +15V
= –15V
DD
SS
0
1k
10k
100k
1M
10M
100M
1G
20
10
0
10
20
30
FREQUENCY (Hz)
V
(V)
S
Figure 23. Bandwidth
Figure 20. Charge Injection vs. Source Voltage
Rev. B | Page 14 of 24
Data Sheet
ADG5408/ADG5409
400
350
300
250
200
150
V
= +12V, V = 0V
SS
DD
V
= +36V, V = 0V
SS
DD
V
= +15V, V = –15V
SS
DD
V
= +20V, V = –20V
SS
DD
100
50
0
–40
–20
0
20
40
60
80
100
120
TEMPERATURE (°C)
Figure 24. tTRANSITION Times vs. Temperature
Rev. B | Page 15 of 24
ADG5408/ADG5409
TEST CIRCUITS
Data Sheet
I
(ON)
A
I
(OFF)
A
I
D
(OFF)
A
D
S
Sx
D
Sx
Dx
NC
V
V
D
V
S
D
NC = NO CONNECT
Figure 29. Off Leakage
Figure 25. On Leakage
V
V
DD
SS
0.1µF
0.1µF
AUDIO PRECISION
V
V
DD
SS
R
S
I
DS
Sx
IN
V
S
V p-p
V1
D
V
OUT
V
IN
R
L
Sx
D
10kΩ
GND
V
S
R
= V /I
1 DS
ON
Figure 30. THD + Noise Figure
Figure 26. On Resistance
V
V
DD
SS
V
V
DD
SS
0.1µF
0.1µF
0.1µF
0.1µF
NETWORK
ANALYZER
NETWORK
ANALYZER
V
V
DD
SS
V
V
DD
SS
S1
V
OUT
R
L
50Ω
D
Sx
50Ω
S2
R
50Ω
L
V
S
D
V
OUT
V
S
R
L
50Ω
GND
GND
V
WITH SWITCH
OUT
V
OUT
INSERTION LOSS = 20 log
CHANNEL-TO-CHANNEL CROSSTALK = 20 log
V
WITHOUT SWITCH
V
OUT
S
Figure 31. Bandwidth
Figure 27. Channel-to-Channel Crosstalk
V
V
DD
SS
0.1µF
0.1µF
NETWORK
ANALYZER
V
V
DD
SS
50Ω
Sx
50Ω
V
S
D
V
OUT
R
L
50Ω
GND
V
V
OUT
OFF ISOLATION = 20 log
S
Figure 28. Off Isolation
Rev. B | Page 16 of 24
Data Sheet
ADG5408/ADG5409
V
V
V
V
DD
SS
3V
tr < 20ns
tf < 20ns
DD
SS
ADDRESS
DRIVE (V
50%
50%
A0
A1
A2
)
IN
S1
V
S1
0V
V
IN
50Ω
S2 TO S7
tTRANSITION
tTRANSITION
90%
S8
V
S8
ADG5408*
OUTPUT
D
2.4V
EN
OUTPUT
300Ω
GND
35pF
90%
*
SIMILAR CONNECTION FOR ADG5409.
Figure 32. Address to Output Switching Times, tTRANSITION
V
V
V
DD
SS
SS
3V
V
DD
ADDRESS
A0
A1
A2
DRIVE (V
)
IN
S1
V
S
V
IN
50Ω
0V
S2 TO S7
S8
80%
80%
ADG5408*
OUTPUT
OUTPUT
D
2.4V
EN
300Ω
GND
35pF
tD
*SIMILAR CONNECTION FOR ADG5409.
Figure 33. Break-Before-Make Delay, tD
V
V
V
V
DD
SS
3V
DD
SS
A0
A1
A2
ENABLE
DRIVE (V
50%
50%
)
S1
S2 TO S8
V
IN
S
0V
ADG5408*
tON (EN)
tOFF (EN)
OUTPUT
0.9V
0.9V
O
D
EN
O
OUTPUT
V
35pF
IN
50Ω
300Ω
GND
*SIMILAR CONNECTION FOR ADG5409.
Figure 34. Enable Delay, tON (EN), tOFF (EN)
V
V
DD
DD
SS
SS
V
V
3V
A0
A1
A2
V
V
IN
ADG5408*
R
S
Sx
D
OUT
V
ΔV
OUT
OUT
EN
C
1nF
L
V
Q
= C × ΔV
OUT
S
INJ
L
GND
V
IN
*SIMILAR CONNECTION FOR ADG5409.
Figure 35. Charge Injection
Rev. B | Page 17 of 24
ADG5408/ADG5409
Data Sheet
TERMINOLOGY
IDD
CIN
IN represents digital input capacitance.
ON (EN)
ON (EN) represents the delay time between the 50% and 90%
points of the digital input and switch on condition.
OFF (EN)
OFF (EN) represents the delay time between the 50% and 90%
I
DD represents the positive supply current.
C
ISS
t
t
I
SS represents the negative supply current.
VD, VS
VD and VS represent the analog voltage on Terminal D and
Terminal S, respectively.
t
t
points of the digital input and switch off condition.
RON
RON is the ohmic resistance between Terminal D and
tTRANSITION
Terminal S.
Delay time between the 50% and 90% points of the digital
inputs and the switch on condition when switching from one
address state to another.
∆RON
∆RON represents the difference between the RON of any two
channels.
tD
RFLAT (ON)
tD represents the off time measured between the 80% point of
both switches when switching from one address state to
another.
The difference between the maximum and minimum value of
on resistance as measured over the specified analog signal range
is represented by RFLAT (ON)
.
Off Isolation
IS (Off)
Off isolation is a measure of unwanted signal coupling through
an off channel.
IS (Off) is the source leakage current with the switch off.
ID (Off)
Charge Injection
Charge injection is a measure of the glitch impulse transferred
from the digital input to the analog output during switching.
ID (Off) is the drain leakage current with the switch off.
ID (On), IS (On)
ID (On) and IS (On) represent the channel leakage currents with
the switch on.
Crosstalk
Crosstalk is a measure of unwanted signal that is coupled
through from one channel to another as a result of parasitic
capacitance.
VINL
V
INL is the maximum input voltage for Logic 0.
VINH
INH is the minimum input voltage for Logic 1.
INL, IINH
INL and IINH represent the low and high input currents of the
Bandwidth
Bandwidth is the frequency at which the output is attenuated
by 3 dB.
V
I
I
On Response
On response is the frequency response of the on switch.
digital inputs.
Total Harmonic Distortion + Noise (THD + N)
The ratio of the harmonic amplitude plus noise of the signal to
the fundamental is represented by THD + N.
CD (Off)
CD (Off) represents the off switch drain capacitance, which is
measured with reference to ground.
AC Power Supply Rejection Ratio (ACPSRR)
CS (Off)
ACPSRR is a measure of the ability of a part to avoid coupling
noise and spurious signals that appear on the supply voltage pin
to the output of the switch. The dc voltage on the device is
modulated by a sine wave of 0.62 V p-p. The ratio of the
amplitude of signal on the output to the amplitude of the
modulation is the ACPSRR.
CS (Off) represents the off switch source capacitance, which is
measured with reference to ground.
CD (On), CS (On)
CD (On) and CS (On) represent on switch capacitances, which
are measured with reference to ground.
Rev. B | Page 18 of 24
Data Sheet
ADG5408/ADG5409
TRENCH ISOLATION
NMOS
PMOS
In the ADG5408/ADG5409, an insulating oxide layer (trench)
is placed between the NMOS and the PMOS transistors of each
CMOS switch. Parasitic junctions, which occur between the
transistors in junction isolated switches, are eliminated, and the
result is a completely latch-up proof switch.
In junction isolation, the N and P wells of the PMOS and
NMOS transistors form a diode that is reverse-biased under
normal operation. However, during overvoltage conditions, this
diode can become forward-biased. A silicon controlled rectifier
(SCR) type circuit is formed by the two transistors causing a
significant amplification of the current that, in turn, leads to
latch-up. With trench isolation, this diode is removed, and the
result is a latch-up proof switch.
P-WELL
N-WELL
TRENCH
BURIED OXIDE LAYER
HANDLE WAFER
Figure 36. Trench Isolation
Rev. B | Page 19 of 24
ADG5408/ADG5409
Data Sheet
APPLICATIONS INFORMATION
The ADG54xx family switches and multiplexers provide a
robust solution for instrumentation, industrial, aerospace, and
other harsh environments that are prone to latch-up, which is
an undesirable high current state that can lead to device failure
and persist until the power supply is turned off. The ADG5408/
ADG5409 high voltage switches allow single-supply operation
from 9 V to 40 V and dual-supply operation from 9 V to
22 V. The ADG5408/ADG5409 (as well as select devices
within the same family) achieve an 8 kV human body model
ESD rating that provides a robust solution eliminating the need
for separate protect circuitry designs in some applications.
Rev. B | Page 20 of 24
Data Sheet
ADG5408/ADG5409
OUTLINE DIMENSIONS
5.10
5.00
4.90
16
9
8
4.50
4.40
4.30
6.40
BSC
1
PIN 1
1.20
MAX
0.15
0.05
0.20
0.09
0.75
0.60
0.45
8°
0°
0.30
0.19
0.65
BSC
SEATING
PLANE
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-153-AB
Figure 37. 16-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-16)
Dimensions shown in millimeters
4.10
4.00 SQ
3.90
0.35
0.30
0.25
PIN 1
INDICATOR
PIN 1
INDICATOR
13
16
0.65
BSC
12
1
EXPOSED
PAD
2.70
2.60 SQ
2.50
4
9
8
5
0.45
0.40
0.35
0.20 MIN
TOP VIEW
BOTTOM VIEW
0.80
0.75
0.70
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.05 MAX
0.02 NOM
COPLANARITY
0.08
SECTION OF THIS DATA SHEET.
SEATING
PLANE
0.20 REF
COMPLIANT TO JEDEC STANDARDS MO-220-WGGC.
Figure 38. 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
4 mm × 4 mm Body, Very Very Thin Quad
(CP-16-17)
Dimensions shown in millimeters
Rev. B | Page 21 of 24
ADG5408/ADG5409
Data Sheet
ORDERING GUIDE
Model1
Temperature Range
Package Description
Package Option
RU-16
RU-16
CP-16-17
RU-16
RU-16
ADG5408BRUZ
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
ADG5408BRUZ-REEL7
ADG5408BCPZ-REEL7
ADG5409BRUZ
ADG5409BRUZ-REEL7
ADG5409BCPZ-REEL7
CP-16-17
1 Z = RoHS Compliant Part.
Rev. B | Page 22 of 24
Data Sheet
NOTES
ADG5408/ADG5409
Rev. B | Page 23 of 24
ADG5408/ADG5409
NOTES
Data Sheet
©2010–2012 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D09206-0-5/12(B)
Rev. B | Page 24 of 24
相关型号：
ADG5412BFBCPZ-RL7
Bidirectional Fault Protection and Detection, 10 Ω RON, Quad SPST Switches
ADI
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