ADGS1408BCPZ-RL7 [ADI]
SPI Interface, 4 Ω RON, ±15 V/12 V/±5 V, 1.8 V Logic Control, 8:1/Dual 4:1 Muxes;
| 型号： | ADGS1408BCPZ-RL7 |
| 厂家： | 
ADI |
| 描述： | SPI Interface, 4 Ω RON, ±15 V/12 V/±5 V, 1.8 V Logic Control, 8:1/Dual 4:1 Muxes |
| 文件： | 总34页 (文件大小：498K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SPI Interface, 4 Ω RON, ± ±1 ꢀV/±ꢁ ꢀV± 1 ꢀ,
±.8 ꢀ Logic Control, 8:±VDual 4:± Muxes
ADGS±408VADGS±409
Data Sheet
FEATURES
FUNCTIONAL BLOCK DIAGRAMS
SPI interface with error detection
ADGS1408
Includes CRC, invalid read/write address, and SCLK count
error detection
S1
Supports burst mode and daisy-chain mode
Industry-standard SPI Mode 0 and SPI Mode 3 interface
compatible
D
Round robin mode allows switching times comparable with a
parallel interface
General-purpose digital outputs to control other devices,
such as parallel switches from Analog Devices, Inc.
4 Ω typical on resistance at 25°C
S8
GPO1
GPO2
GPO3
GPO4
CNV
SDO
SPI
INTERFACE
0.5 Ω typical on-resistance flatness at 25°C
0.2 Ω typical on-resistance match between channels at 25°C
SCLK SDI CS RESET/V
L
Figure 1. ADGS1408 Functional Block Diagram
V
SS to VDD analog signal range
ADGS1409
Fully specified at 15 V, 5 V, and +12 V
Power-up sequence of VDD, VSS, and GND before applying
VL and digital/analog inputs
S1A
DA
S4A
1.8 V logic compatibility with 2.7 V ≤ VL ≤ 3.3 V
24-lead LFCSP package
S1B
APPLICATIONS
Automated test equipment
Data acquisition systems
Battery-powered systems
DB
S4B
GPO1
CNV
SDO
GPO2
GPO3
GPO4
GPO5
SPI
INTERFACE
Sample-and-hold systems
Audio signal routing
SCLK SDI CS RESET/V
Video signal routing
L
Communications systems
Figure 2. ADGS1409 Functional Block Diagram
Relay replacement
supplies. In the off condition, signal levels up to the supplies
are blocked.
The on-resistance profile is flat over the full analog input range,
which ensures linearity and low distortion when switching
audio signals.
GENERAL DESCRIPTION
The ADGS1408/ADGS1409 are analog multiplexers comprising
eight single channels and four differential channels, respectively.
A serial peripheral interface (SPI) controls the switches. The SPI
interface has robust error detection features such as cyclic
redundancy check (CRC) error detection, invalid read/write
address detection, and SCLK count error detection.
PRODUCT HIGHLIGHTS
1. SPI interface removes the need for parallel conversion,
logic traces, and reduces GPIO channel count.
2. Daisy-chain mode removes additional logic traces when
multiple devices are used.
It is possible to daisy-chain multiple ADGS1408/ADGS1409
devices together. Daisy-chain mode enables the configuration of
multiple devices with a minimal amount of digital lines. The
ADGS1408/ADGS1409 can also operate in burst mode to
decrease the time between SPI commands.
3. CRC error detection, invalid read/write address detection,
and SCLK count error detection ensure a robust digital
interface.
4. CRC and error detection capabilities allow the use of the
ADGS1408/ADGS1409 in safety critical systems.
5. Minimal distortion.
iCMOS construction ensures ultra low power dissipation, making
the devices ideally suited for portable and battery-powered
instruments.
Each switch conducts equally well in both directions when on,
and each switch has an input signal range that extends to the
Rev. 0
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Technical Support
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www.analog.com
ADGS±408VADGS±409
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Software Reset............................................................................. 24
Daisy-Chain Mode..................................................................... 24
Power-On Reset.......................................................................... 25
Round Robin Mode.................................................................... 26
General-Purpose Outputs (GPOs) .......................................... 27
Applications Information.............................................................. 28
Digital Input Buffers .................................................................. 28
Power Supply Rails..................................................................... 28
Power Supply Recommendations............................................. 28
Power Supply Sequencing ......................................................... 28
Register Summaries........................................................................ 29
Register Details ............................................................................... 30
Switch Data Register .................................................................. 30
Error Configuration Register.................................................... 31
Error Flags Register.................................................................... 31
Burst Enable Register................................................................. 32
Round Robin Enable Register................................................... 32
Round Robin Channel Configuration Register ..................... 32
CNꢀ Edge Select Register......................................................... 33
Software Reset Register ............................................................. 33
Outline Dimensions....................................................................... 34
Ordering Guide .......................................................................... 34
Applications....................................................................................... 1
Functional Block Diagrams............................................................. 1
General Description......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
15 ꢀ Dual Supply ....................................................................... 3
5 ꢀ Dual Supply ......................................................................... 5
12 ꢀ Single Supply........................................................................ 7
Continuous Current per Channel, Sx or Dx............................. 9
Timing Characteristics .............................................................. 10
Absolute Maximum Ratings.......................................................... 12
Thermal Resistance .................................................................... 12
ESD Caution................................................................................ 12
Pin Configurations and Function Descriptions ......................... 13
Typical Performance Characteristics ........................................... 15
Test Circuits..................................................................................... 19
Terminology .................................................................................... 22
Theory of Operation ...................................................................... 23
Address Mode ............................................................................. 23
Error Detection Features ........................................................... 23
Clearing the Error Flags Register ............................................. 24
Burst Mode.................................................................................. 24
REVISION HISTORY
6/2018—Revision 0: Initial Version
Rev. 0 | Page 2 of 34
Data Sheet
ADGS±408VADGS±409
SPECIFICATIONS
15 V DUAL SUPPLY
ꢀDD = +15 ꢀ 10%, ꢀSS = −15 ꢀ 10%, ꢀL = 2.7 ꢀ to 5.5 ꢀ, and GND = 0 ꢀ, unless otherwise noted.
Table 1.
Parameter
+25°C −40°C to +85°C −40°C to +125°C Unit
Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
VDD to VSS
6.7
V
4
4.7
0.2
Ω typ
Ω max
Ω typ
VS = 10 V, IS = −10 mA, see Figure 32
VDD = +13.5 V, VSS = −13.5 V
VS = 10 V, IS = −10 mA
5.7
On-Resistance Match Between
Channels, ∆RON
0.78
0.5
0.72
0.85
0.77
1.1
Ω max
Ω typ
Ω max
On-Resistance Flatness, RFLAT (ON)
VS = 10 V, IS = −10 mA
0.92
LEAKAGE CURRENTS
VDD = +16.5 V, VSS = −16.5 V
Source Off Leakage, IS (Off)
0.04
0.2
0.04
0.45
0.1
nA typ
nA max
nA typ
nA max
nA typ
nA max
VS = 10 V, VD = 10 V, see Figure 35
0.6
2.0
3.0
5.0
Drain Off Leakage, ID (Off)
VS = 10 V, VD = 10 V, see Figure 35
VS = VD = 10 V, see Figure 31
30.0
30.0
Channel On Leakage, ID (On), IS (On)
1.5
DIGITAL OUTPUTS
SDO
Output Voltage
Low, VOL
0.4
0.2
V max
V max
μA typ
ISINK = 5 mA
ISINK = 1 mA
VOUT = VGND or VL
High Impedance Leakage
Current
0.001
4
0.1
μA max
pF typ
High Impedance Output
Capacitance
GPOx
Output Voltage
High, VOH
Low, VOL
VL − 0.2 V
0.2
V min
V max
ISOURCE = 100 μA
ISINK = 100 μA
Timing
tON (GPO)
95
115
15
ns typ
ns max
ns typ
ns max
ns typ
CL = 15 pF, see Figure 43
CL = 15 pF, see Figure 43
CL = 15 pF, see Figure 44
115
25
115
25
tOFF (GPO)
20
Break-Before-Make Time Delay, 50
tD
35
ns min
DIGITAL INPUTS
Input Voltage
High, VINH
2
V min
V min
3.3 V < VL ≤ 5.5 V
2.7 V ≤ VL ≤ 3.3 V
3.3 V < VL ≤ 5.5 V
2.7 V ≤ VL ≤ 3.3 V
VIN = VGND or VL
1.35
0.8
0.8
Low, VINL
V max
V max
μA typ
μA max
pF typ
Input Current, IINL or IINH
Digital Input Capacitance, CIN
0.001
4
0.1
Rev. 0 | Page 3 of 34
ADGS±408VADGS±409
Data Sheet
Parameter
DYNAMIC CHARACTERISTICS1
+25°C −40°C to +85°C −40°C to +125°C Unit
Test Conditions/Comments
Transition Time, tTRANSITION
145
185
120
ns typ
ns max
ns typ
RL = 100 Ω, CL = 35 pF
VS = 10 V, see Figure 40
RL = 100 Ω, CL = 35 pF
220
185
245
200
tON (EN)
tOFF (EN)
165
125
155
ns max
ns typ
VS = 10 V, see Figure 41
RL = 100 Ω, CL = 35 pF
VS = 10 V, see Figure 41
175
195
20
ns max
Break-Before-Make Time Delay, tD 40
ns typ
ns min
pC typ
RL = 100 Ω, CL = 35 pF
VS1 = VS2 = 10 V, see Figure 39
VS = 0 V, RS = 0 Ω, CL = 1 nF,
see Figure 42
Charge Injection, QINJ
−50
Off Isolation
−64
dB typ
dB typ
% typ
RL = 50 Ω, CL = 5 pF, f = 1 MHz,
see Figure 34
RL = 50 Ω, CL = 5 pF, f = 1 MHz,
see Figure 33
RL = 110 Ω, 15 V p-p, f = 20 Hz to
20 kHz, see Figure 36
Channel to Channel Crosstalk
Total Harmonic Distortion + Noise
−70
0.025
−3 dB Bandwidth
ADGS1408
ADGS1409
RL = 50 Ω, CL = 5 pF, see Figure 37
60
115
0.24
MHz typ
MHz typ
dB typ
Insertion Loss
RL = 50 Ω, CL = 5 pF, f = 1 MHz,
see Figure 26 and Figure 27
CS (Off)
CD (Off)
14
pF typ
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
ADGS1408
ADGS1409
CD (On), CS (On)
ADGS1408
ADGS1409
POWER REQUIREMENTS
IDD
80
40
pF typ
pF typ
VS = 0 V, f = 1 MHz
135
90
pF typ
pF typ
VDD = +16.5 V, VSS = −16.5 V
All switches open
0.002
220
μA typ
μA max
μA typ
μA max
μA typ
μA max
1
S8/S4A closed, VL = 5.5 V
S8/S4A closed, VL = 2.7 V
380
440
270
IL
Inactive
6.3
μA typ
μA max
μA typ
μA typ
μA typ
μA typ
μA typ
μA typ
μA typ
μA typ
mA typ
Digital inputs = 0 V or VL
8.0
Inactive, SCLK = 1 MHz
SCLK = 50 MHz
14
CS = VL and SDI = 0 V or VL, VL = 5 V
CS = VL and SDI = 0 V or VL, VL = 3 V
CS = VL and SDI = 0 V or VL, VL = 5 V
CS = VL and SDI = 0 V or VL, VL = 3 V
CS and SCLK = 0 V or VL, VL = 5 V
CS and SCLK = 0 V or VL, VL = 3 V
CS and SCLK = 0 V or VL, VL = 5 V
CS and SCLK = 0 V or VL, VL = 3 V
7
390
210
15
Inactive, SDI = 1 MHz
SDI = 25 MHz
7.5
230
120
1.8
Active at 50 MHz
Digital inputs toggle between
0 V and VL, VL = 5.5 V
2.1
mA max
mA typ
0.7
Digital inputs toggle between
0 V and VL, VL = 2.7 V
1.0
mA max
Rev. 0 | Page 4 of 34
Data Sheet
ADGS±408VADGS±409
Parameter
+25°C −40°C to +85°C −40°C to +125°C Unit
0.002 μA typ
Test Conditions/Comments
ISS
Digital inputs = 0 V or VL
1
μA max
V min
VDD/VSS
4.5
GND = 0 V
GND = 0 V
16.5
V max
1 Guaranteed by design; not subject to production test.
5 V DUAL SUPPLY
ꢀDD = +5 ꢀ 10%, ꢀSS = −5 ꢀ 10%, ꢀL = 2.7 ꢀ to 5.5 ꢀ, and GND = 0 ꢀ, unless otherwise noted.
Table 2.
Parameter
+25°C −40°C to +85°C −40°C to +125°C Unit
Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
VDD to VSS
V
7.4
Ω typ
VS = 4.5 V, IS = −10 mA, see
Figure 32
9
0.3
10.5
12
Ω max
Ω typ
VDD = +4.5 V, VSS = −4.5 V
VS = 4.5 V, IS = −10 mA
On-Resistance Match Between
Channels, ∆RON
0.78
1.5
2.5
0.91
2.5
1.1
2.8
Ω max
Ω typ
Ω max
On-Resistance Flatness, RFLAT (ON)
VS = 4.5 V, IS = −10 mA
LEAKAGE CURRENTS
VDD = +5.5 V, VSS = −5.5 V
Source Off Leakage, IS (Off)
0.02
0.2
0.02
nA typ
nA max
nA typ
VS = 4.5 V, VD = 4.5 V, Figure 35
0.6
5.0
Drain Off Leakage, ID (Off)
VS = 4.5 V, VD = 4.5 V, see
Figure 35
0.45
0.04
0.3
0.8
1.1
20.0
22.0
nA max
nA typ
nA max
Channel On Leakage, ID (On), IS (On)
VS = VD = 4.5 V, see Figure 31
DIGITAL OUTPUTS
SDO
Output Voltage
Low, VOL
0.4
0.2
V max
V max
μA typ
μA max
pF typ
ISINK = 5 mA
ISINK = 1 mA
VOUT = VGND or VL
High Impedance Leakage Current 0.001
0.1
High Impedance Output
Capacitance
4
GPOx
Output Voltage
High, VOH
Low, VOL
VL − 0.2 V
0.2
V min
V max
ISOURCE = 100 μA
ISINK = 100 μA
Timing
tON (GPO)
95
115
15
20
ns typ
ns max
ns typ
ns max
ns typ
ns min
CL = 15 pF, see Figure 43
CL = 15 pF, see Figure 43
CL = 15 pF, see Figure 44
115
25
115
25
tOFF (GPO)
Break-Before-Make Time Delay, tD
50
35
Rev. 0 | Page 5 of 34
ADGS±408VADGS±409
Data Sheet
Parameter
+25°C −40°C to +85°C −40°C to +125°C Unit
Test Conditions/Comments
DIGITAL INPUTS
Input Voltage
High, VINH
2
V min
V min
3.3 V < VL ≤ 5.5 V
2.7 V ≤ VL ≤ 3.3 V
3.3 V < VL ≤ 5.5 V
2.7 V ≤ VL ≤ 3.3 V
VIN = VGND or VL
1.35
0.8
0.8
Low, VINL
V max
V max
μA typ
μA max
pF typ
Input Current, IINL or IINH
0.001
4
0.1
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS1
Transition Time, tTRANSITION
320
440
265
365
245
330
95
ns typ
ns max
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
RL = 100 Ω, CL = 35 pF
VS = 3 V, see Figure 40
RL = 100 Ω, CL = 35 pF
VS = 3 V, see Figure 41
RL = 100 Ω, CL = 35 pF
VS = 3 V, see Figure 41
RL = 100 Ω, CL = 35 pF
VS1 = VS2 = 3 V, see Figure 39
VS = 0 V, RS = 0 Ω, CL = 1 nF,
see Figure 42
RL = 50 Ω, CL = 5 pF, f = 1 MHz,
see Figure 34
515
425
370
570
470
400
55
tON (EN)
tOFF (EN)
Break-Before-Make Time Delay, tD
Charge Injection, QINJ
–10
–64
–70
0.06
Off Isolation
dB typ
dB typ
% typ
Channel to Channel Crosstalk
Total Harmonic Distortion + Noise
RL = 50 Ω, CL = 5 pF, f = 1 MHz,
see Figure 33
RL = 110 Ω, 5 V p-p, f = 20 Hz to
20 kHz, see Figure 36
−3 dB Bandwidth
ADGS1408
ADGS1409
RL = 50 Ω, CL = 5 pF, see Figure 37
40
80
0.5
MHz typ
MHz typ
dB typ
Insertion Loss
RL = 50 Ω, CL = 5 pF, f = 1 MHz,
see Figure 26 and Figure 27
CS (Off)
CD (Off)
20
pF typ
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
ADGS1408
ADGS1409
CD (On), CS (On)
ADGS1408
ADGS1409
POWER REQUIREMENTS
IDD
130
65
pF typ
pF typ
VS = 0 V, f = 1 MHz
180
120
pF typ
pF typ
VDD = +5.5 V, VSS = −5.5 V
Digital inputs = 0 V or VL, VL =
5.5 V
0.002
14
μA typ
1
μA max
μA typ
μA max
S8/S4A closed, VL = 2.7 V
20
Rev. 0 | Page 6 of 34
Data Sheet
ADGS±408VADGS±409
Parameter
IL
+25°C −40°C to +85°C −40°C to +125°C Unit
Test Conditions/Comments
Inactive
6.3
14
μA typ
μA max
μA typ
Digital inputs = 0 V or VL
8.0
Inactive, SCLK = 1 MHz
CS = VL and SDI = 0 V or VL, VL =
5 V
7
μA typ
μA typ
μA typ
CS = VL and SDI = 0 V or VL, VL =
3 V
CS = VL and SDI = 0 V or VL, VL =
5 V
CS = VL and SDI = 0 V or VL, VL =
3 V
SCLK = 50 MHz
390
210
Inactive, SDI = 1 MHz
SDI = 25 MHz
15
μA typ
μA typ
μA typ
μA typ
mA typ
CS and SCLK = 0 V or VL, VL = 5 V
7.5
230
120
1.8
CS and SCLK = 0 V or VL, VL = 3 V
CS and SCLK = 0 V or VL, VL = 5 V
CS and SCLK = 0 V or VL, VL = 3 V
Active at 50 MHz
Digital inputs toggle between
0 V and VL, VL = 5.5 V
2.1
mA max
mA typ
0.7
Digital inputs toggle between
0 V and VL, VL = 2.7 V
1.0
1.0
4.5
16.5
mA max
μA typ
μA max
V min
ISS
VDD/VSS
0.002
Digital inputs = 0 V or VL
GND = 0 V
GND = 0 V
V max
1 Guaranteed by design; not subject to production test.
12 V SINGLE SUPPLY
ꢀDD = 12 ꢀ 10%, ꢀSS = 0 ꢀ, ꢀL = 2.7 ꢀ to 5.5 ꢀ, and GND = 0 ꢀ, unless otherwise noted.
Table 3.
Parameter
+25°C −40°C to +85°C
−40°C to +125°C
Unit
Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
0 V to VDD
V
6.7
Ω typ
VS = 0 V to 10 V, IS = −10 mA,
see Figure 32
8.7
0.2
10.2
11.7
Ω max
Ω typ
VDD = 10.8 V, VSS = 0 V
VS = 0 V to 10 V, IS = −10 mA
On-Resistance Match Between
Channels, ∆RON
0.82
1.5
2.5
0.85
2.5
1.1
2.8
Ω max
Ω typ
Ω max
On-Resistance Flatness, RFLAT (ON)
VS = 0 V to 10 V, IS = −10 mA
VDD = 13.2 V, VSS = 0 V
LEAKAGE CURRENTS
Source Off Leakage, IS (Off)
0.04
nA typ
VS = 1 V/10 V, VD = 10 V/1 V,
see Figure 35
0.2
0.04
0.6
5.0
nA max
nA typ
Drain Off Leakage, ID (Off)
VS = 1 V/10 V, VD = 10 V/1 V,
see Figure 35
0.45
0.06
0.44
1.0
1.3
37.0
32.0
nA max
nA typ
nA max
Channel On Leakage, ID (On), IS (On)
VS = VD = 1 V/10 V, see Figure 31
Rev. 0 | Page 7 of 34
ADGS±408VADGS±409
Data Sheet
Parameter
DIGITAL OUTPUTS
SDO
+25°C −40°C to +85°C
−40°C to +125°C
Unit
Test Conditions/Comments
Output Voltage
Low, VOL
0.4
0.2
V max
V max
μA typ
μA max
pF typ
ISINK = 5 mA
ISINK = 1 mA
VOUT = VGND or VL
High Impedance Leakage Current
0.001
4
0.1
High Impedance Output
Capacitance
GPOx
Output Voltage
High, VOH
Low, VOL
VL − 0.2 V
0.2
V min
V max
ISOURCE = 100 μA
ISINK = 100 μA
Timing
tON (GPO)
95
115
15
20
50
ns typ
ns max
ns typ
ns max
ns typ
ns min
CL = 15 pF, see Figure 43
CL = 15 pF, see Figure 43
CL = 15 pF, see Figure 44
115
25
115
25
tOFF (GPO)
Break-Before-Make Time Delay, tD
35
DIGITAL INPUTS
Input Voltage
High, VINH
2
V min
V min
3.3 V < VL ≤ 5.5 V
2.7 V ≤ VL ≤ 3.3 V
3.3 V < VL ≤ 5.5 V
2.7 V ≤ VL ≤ 3.3 V
VIN = VGND or VL
1.35
0.8
0.8
Low, VINL
V max
V max
μA typ
μA max
pF typ
Input Current, IINL or IINH
0.001
4
0.1
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS1
Transition Time, tTRANSITION
210
280
195
250
145
185
90
ns typ
ns max
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
RL = 100 Ω, CL = 35 pF
VS = 8 V, see Figure 40
RL = 100 Ω, CL = 35 pF
VS = 8 V, see Figure 41
RL = 100 Ω, CL = 35 pF
VS = 8 V, see Figure 41
RL = 100 Ω, CL = 35 pF
VS1 = VS2 = 8 V, see Figure 39
VS = 6 V, RS = 0 Ω, CL = 1 nF,
see Figure 42
RL = 50 Ω, CL = 5 pF, f = 1 MHz,
see Figure 34
340
295
215
385
325
240
50
tON (EN)
tOFF (EN)
Break-Before-Make Time Delay, tD
Charge Injection, QINJ
Off Isolation
−12
−64
dB typ
dB typ
Channel to Channel Crosstalk
−3 dB Bandwidth
−70
RL = 50 Ω, CL = 5 pF, f = 1 MHz,
see Figure 33
RL = 50 Ω, CL = 5 pF, see
Figure 37
ADGS1408
ADGS1409
Insertion Loss
36
72
0.5
MHz typ
MHz typ
dB typ
RL = 50 Ω, CL = 5 pF, f = 1 MHz,
see Figure 26 and Figure 27
CS (Off)
CD (Off)
20
pF typ
VS = 6 V, f = 1 MHz
VS = 6 V, f = 1 MHz
ADGS1408
ADGS1409
120
60
pF typ
pF typ
Rev. 0 | Page 8 of 34
Data Sheet
ADGS±408VADGS±409
Parameter
+25°C −40°C to +85°C
−40°C to +125°C
Unit
Test Conditions/Comments
CD (On), CS (On)
ADGS1408
ADGS1409
VS = 6 V, f = 1 MHz
170
110
pF typ
pF typ
POWER REQUIREMENTS
IDD
VDD = 13.2 V
All switches open
0.002
220
μA typ
μA max
μA typ
μA max
μA typ
μA max
1
S8/S4A closed, VL = 5.5 V
S8/S4A closed, VL = 2.7 V
380
440
270
IL
Inactive
6.3
14
μA typ
μA max
μA typ
Digital inputs = 0 V or VL
8.0
Inactive, SCLK = 1 MHz
CS = VL and SDI = 0 V or VL,
VL = 5 V
7
μA typ
μA typ
μA typ
CS = VL and SDI = 0 V or VL,
VL = 3 V
CS = VL and SDI = 0 V or VL,
VL = 5 V
CS = VL and SDI = 0 V or VL,
VL = 3 V
SCLK = 50 MHz
390
210
Inactive, SDI = 1 MHz
SDI = 25 MHz
15
μA typ
μA typ
μA typ
μA typ
mA typ
CS and SCLK = 0 V or VL, VL = 5 V
7.5
230
120
1.8
CS and SCLK = 0 V or VL, VL = 3 V
CS and SCLK = 0 V or VL, VL = 5 V
CS and SCLK = 0 V or VL, VL = 3 V
Active at 50 MHz
Digital inputs toggle between
0 V and VL, VL = 5.5 V
2.1
mA max
mA typ
0.7
Digital inputs toggle between
0 V and VL, VL = 2.7 V
1.0
5
20
mA max
V min
V max
VDD
GND = 0 V, VSS = 0 V
GND = 0 V, VSS = 0 V
1 Guaranteed by design; not subject to production test.
CONTINUOUS CURRENT PER CHANNEL, Sx OR Dx
Table 4. ADGS1408, One Channel On
Parameter
25°C
85°C
125°C
Unit
CONTINUOUS CURRENT, Sx OR D1
VDD = 15 V, VSS = −15 V (θJA = 58.4°C/W)
VDD = 12 V, VSS = 0 V (θJA = 58.4°C/W)
VDD = 5 V, VSS = −5 V (θJA = 58.4°C/W)
304.9
259.7
247.2
133.6
122.7
119.3
48.9
48
47.6
mA max
mA max
mA max
1 Sx refers to the S1 to S8 pins.
Table 5. ADGS1409, Two Channels On
Parameter
25°C
85°C
125°C
Unit
CONTINUOUS CURRENT, Sx OR Dx1
VDD = 15 V, VSS = −15 V (θJA = 58.4°C/W)
VDD = 12 V, VSS = 0 V (θJA = 58.4°C/W)
VDD = 5 V, VSS = −5 V (θJA = 58.4°C/W
229.6
194.7
185.2
114.3
103
99.6
47.2
45.7
45.2
mA max
mA max
mA max
1 Sx refers to the S1A to S4A and S1B to S4B pins, and Dx refers to the DA and DB pins.
Rev. 0 | Page 9 of 34
ADGS±408VADGS±409
Data Sheet
TIMING CHARACTERISTICS
ꢀL = 2.7 ꢀ to 5.5 ꢀ, GND = 0 ꢀ, and all specifications TMIN to TMAX, unless otherwise noted. Guaranteed by design and characterization,
not production tested.
Table 6.
Parameter
Limit
Unit
Test Conditions/Comments
TIMING CHARACTERISTICS
t1
t2
t3
t4
t5
t6
t7
t8
20
8
8
10
6
8
10
20
20
20
20
8
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns max
ns max
ns min
ns min
ns min
SCLK or CNV period
SCLK or CNV high pulse width
SCLK or CNV low pulse width
CS falling edge to SCLK or CNV active edge
Data setup time
Data hold time
SCLK or CNV active edge to CS rising edge
CS falling edge to SDO data available
SCLK falling edge to SDO data available
CS rising edge to SDO returns to high impedance
CS high time between SPI commands
CS falling edge to SCLK/CNV becomes stable
CS rising edge to SCLK/CNV becomes stable
1
t9
t10
t11
t12
t13
8
1 Measured with the 1 kΩ pull-up resistor to VL and 20 pF load. t9 determines the maximum SCLK frequency when SDO is used.
Timing Diagrams
t1
SCLK
t2
t7
t4
t3
CS
t6
t5
SDI
R/W
A6
A5
1
D2
D2
D1
D1
D0
D0
t10
t9
SDO
0
0
t8
Figure 3. Address Mode Timing Diagram
Rev. 0 | Page 10 of 34
Data Sheet
ADGS±408VADGS±409
t1
SCLK
CS
t2
t3
t7
t4
t6
t5
SDI
D7
D6
D0
D7
D6
D1
D0
INPUT BYTE FOR DEVICE N
t9
INPUT BYTE FOR DEVICE N + 1
t10
SDO
0
0
0
D7
D6
D1
D0
ZERO BYTE
INPUT BYTE FOR DEVICE N
t8
Figure 4. Daisy-Chain Timing Diagram
t11
CS
SCLK OR CNV
t13
t12
CS
Figure 5. SCLK or CNV and Timing Relationship
t4
CS
t2
t3
t7
CNV
SDO
t9
t1
t10
RESYNC
MUX
CHANNEL
S1
S2
S(LAST)
Figure 6. Round Robin Timing Diagram
Rev. 0 | Page 11 of 34
ADGS±408VADGS±409
Data Sheet
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Table 7.
Parameter
Rating
VDD to VSS
35 V
−0.3 V to +25 V
+0.3 V to −25 V
VDD to GND
VSS to GND
VL to GND
For VDD ≤ 5.5V
For VDD > 5.5V
SDO
Only one absolute maximum rating can be applied at any one time.
−0.3 V to VDD + 0.3 V
−0.3 V to +6 V
−0.3 V to +6 V
−0.3 V to VL + 0.3 V
VSS − 0.3 V to VDD + 0.3 V or
30 mA, whichever occurs first
−0.3 V to +6 V
497 mA (pulsed at 1 ms,
10% duty cycle maximum)
Data + 15%
THERMAL RESISTANCE
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Close attention to
PCB thermal design is required.
GPOx
Analog Inputs1
Digital Inputs1
Peak Current, Sx or Dx Pins2
Table 8. Thermal Resistance
1
Package Type
CP-24-172
θJA
θJCB
ΨJT
Unit
58.4
17.2
2.2
°C/W
Continuous Current, Sx or Dx2, 3
Operating Temperature Range
Storage Temperature Range
Junction Temperature
Reflow Soldering Peak
Temperature, Pb-Free
1 θJCB is the junction to the bottom of the case value.
−40°C to +125°C
−65°C to +150°C
150°C
2 Thermal impedance simulated values are based on a JEDEC 2S2P thermal
test board with four thermal vias. See JEDEC JESD51.
ESD CAUTION
260(+0/−5)°C
1 Overvoltages at the digital Sx and Dx pins are clamped by internal diodes.
Limit current to the maximum ratings given.
2 Sx refers to the S1 to S4 pins, and Dx refers to the D1 to D4 pins.
3 See Table 4 and Table 5.
Rev. 0 | Page 12 of 34
Data Sheet
ADGS±408VADGS±409
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
1
18
17
16
V
V
DD
SS
S1 2
S5
3
4
CNV
S2
ADGS1408
TOP VIEW
(Not to Scale)
15 S6
14
GND
S3 5
RESET/V
L
GPO3 6
13 S7
NOTES
AD IS CONNECTED INTERNALLY.
1. THE EXPOSED P
FOR INCREASED RELIABILITY OF THE SOLDER JOINTS
AND MAXIMUM THERMAL CAPABILITY, IT IS RECOMMENDED
THAT THE EXPOSED PAD BE SOLDERED TO THE SUBSTRATE, V
2. NIC = NOT INTERNALLY CONNECTED.
.
SS
Figure 7. ADGS1408 Pin Configuration
Table 9. ADGS1408 Pin Function Descriptions
Pin No.
Mnemonic Description
1
2
3
4
5
6
7
8
9, 11
10
12
13
14
VSS
S1
S2
GND
S3
GPO3
S4
GPO4
NIC
D
Most Negative Power Supply Potential. In single-supply applications, tie this pin to ground.
Source Terminal 1. This pin can be an input or output.
Source Terminal 2. This pin can be an input or output.
Ground (0 V) Reference.
Source Terminal 3. This pin can be an input or output.
General-Purpose Output 3. This pin is a digital output.
Source Terminal 4. This pin can be an input or output.
General-Purpose Output 4. This pin is a digital output.
Not Internally Connected.
Drain Terminal. This pin can be an input or output.
S8
S7
RESET/VL
Source Terminal 8. This pin can be an input or output.
Source Terminal 7. This pin can be an input or output.
RESET/Logic Power Supply Input (VL). Under normal operation, drive the RESET/VL pin with a 2.7 V to 5.5 V supply.
Pull the RESET/VL pin low to complete a hardware reset. After a reset, all switches open, and the appropriate
registers are set to their default.
15
16
17
18
19
20
S6
CNV
S5
VDD
GPO1
SDO
Source Terminal 6. This pin can be an input or output.
Convert Digital Input. When in round robin mode, the CNV pin is used to cycle through the selected channels.
Source Terminal 5. This pin can be an input or output.
Most Positive Power Supply Potential.
General-Purpose Output 1. This pin is a digital output.
Serial Data Output. This pin can be used for daisy chaining a number of these devices together or for reading
back the data stored in a register for diagnostic purposes. The serial data is propagated on the falling edge of
SCLK. Pull this open-drain output to VL with an external resistor.
21
22
23
24
CS
Active Low Control Input. CS is the frame synchronization signal for the input data.
Serial Clock Input. Data is captured on the positive edge of SCLK. Data can be transferred at rates of up to 50 MHz.
Serial Data Input. Data is captured on the positive edge of the serial clock input.
General-Purpose Output 2. This pin is a digital output.
Exposed Pad. The exposed pad is connected internally. For increased reliability of the solder joints and
maximum thermal capability, it is recommended that the exposed pad be soldered to the substrate, VSS.
SCLK
SDI
GPO2
EPAD
Rev. 0 | Page 13 of 34
ADGS±408VADGS±409
Data Sheet
1
18
17
16
V
V
DD
SS
S1A 2
S1B
CNV
3
4
S2A
ADGS1409
TOP VIEW
(Not to Scale)
15 S2B
GND
S3A 5
14 RESET/V
13 S3B
L
GPO3 6
NOTES
1. THE EXPOSED PAD IS CONNECTED INTERNALLY.
FOR INCREASED RELIABILITY OF THE SOLDER JOINTS
Y, IT IS RECOMMENDED
AND MAXIMUM THERMAL CAPABILIT
AT THE EXPOSED PAD BE SOLDERED TO THE SUBSTRATE, V
TH
.
SS
Figure 8. ADGS1409 Pin Configuration
Table 10. ADGS1409 Pin Function Descriptions
Pin No.
Mnemonic Description
1
2
3
4
5
6
7
8
VSS
S1A
S2A
GND
S3A
GPO3
S4A
GPO4
DA
DB
GPO5
S4B
Most Negative Power Supply Potential. In single-supply applications, tie this pin to ground.
Source Terminal 1A. This pin can be an input or output.
Source Terminal 2A. This pin can be an input or output.
Ground (0 V) Reference.
Source Terminal 3A. This pin can be an input or output.
General-Purpose Output 3. This pin is a digital output.
Source Terminal 4A. This pin can be an input or output.
General-Purpose Output 4. This pin is a digital output.
Drain Terminal A. This pin can be an input or output.
Drain Terminal B. This pin can be an input or output.
General-Purpose Output 5. This pin is a digital output.
Source Terminal 4B. This pin can be an input or output.
Source Terminal 3B. This pin can be an input or output.
9
10
11
12
13
14
S3B
RESET/VL
RESET/Logic Power Supply Input (VL). Under normal operation, drive the RESET/VL pin with a 2.7 V to 5.5 V supply.
Pull the RESET/VL pin low to complete a hardware reset. After a reset, all switches open, and the appropriate
registers are set to their default.
15
16
17
18
19
20
S2B
CNV
S1B
VDD
GPO1
SDO
Source Terminal 2B. This pin can be an input or output.
Convert Digital Input. When in round robin mode, the CNV pin is used to cycle through the selected channels.
Source Terminal 1B. This pin can be an input or output.
Most Positive Power Supply Potential.
General-Purpose Output 1. This pin is a digital output.
Serial Data Output. This pin can be used for daisy chaining a number of these devices together or for reading
back the data stored in a register for diagnostic purposes. The serial data is propagated on the falling edge of
SCLK. Pull this open-drain output to VL with an external resistor.
21
22
23
24
CS
Active Low Control Input. CS is the frame synchronization signal for the input data.
Serial Clock Input. Data is captured on the positive edge of SCLK. Data can be transferred at rates of up to 50 MHz.
Serial Data Input. Data is captured on the positive edge of the serial clock input.
General-Purpose Output 2. This pin is a digital output.
Exposed Pad. The exposed pad is connected internally. For increased reliability of the solder joints and
maximum thermal capability, it is recommended that the exposed pad be soldered to the substrate, VSS.
SCLK
SDI
GPO2
EPAD
Rev. 0 | Page 14 of 34
Data Sheet
ADGS±408VADGS±409
TYPICAL PERFORMANCE CHARACTERISTICS
7
6
5
4
3
2
1
6
V
V
= +15V
= –15V
T
= 25°C
DD
SS
A
5
4
3
2
1
0
V
V
V
V
V
= +15V, V = –15V
SS
DD
DD
DD
DD
DD
T
T
T
T
= +25°C
= +85°C
= –40°C
= +125°C
A
A
A
A
= +13.5V, V = –13.5V
SS
= +12V, V = –12V
SS
= +10V, V = –10V
SS
= +16.5V, V = –16.5V
SS
0
–15
–10
–5
0
5
10
15
–16.5 –12.5 –8.5
–4.5
–0.5
3.5
7.5
11.5
15.5
SOURCE OR DRAIN VOLTAGE (V)
SOURCE OR DRAIN VOLTAGE (V)
Figure 9. On Resistance vs. VS or VD for Various Dual Supplies
Figure 12. On Resistance vs. VS or VD for Various Temperatures,
15 V Dual Supply
9
12
V
V
= +5V
= –5V
T
= 25°C
DD
SS
A
8
10
8
7
6
5
4
3
6
4
2
1
T
T
T
T
= +25°C
= +85°C
= –40°C
= +125°C
V
= +7V, V = –7V
SS
A
A
A
A
DD
DD
DD
DD
2
V
V
V
= +5.5V, V = –5.5V
SS
= +5V, V = –5V
SS
= +4.5V, V = –4.5V
SS
0
–5
0
–4
–3
–2
–1
0
1
2
3
4
5
–7 –6 –5 –4 –3 –2 –1
0
1
2
3
4
5
6
7
SOURCE OR DRAIN VOLTAGE (V)
SOURCE OR DRAIN VOLTAGE (V)
Figure 10. On Resistance vs. VS or VD for Various Dual Supplies
Figure 13. On Resistance vs. VS or VD for Various Temperatures,
5 V Dual Supply
13
10
T
V
= 25°C
= 0V
V
V
= 12V
= 0V
A
DD
SS
12
11
10
9
9
8
7
6
5
4
3
2
1
0
SS
8
7
6
5
4
3
2
1
0
V
V
V
V
V
= 12V
= 13.2V
= 10.8V
= 8V
DD
DD
DD
DD
DD
T
T
T
T
= +25°C
= +85°C
= –40°C
= +125°C
A
A
A
A
= 5V
0
1
2
3
4
5
6
7
8
9
10 11 12 13
0
2
4
6
8
10
12
SOURCE OR DRAIN VOLTAGE (V)
SOURCE OR DRAIN VOLTAGE (V)
Figure 11. On Resistance vs. VS or VD for Various Single Supplies
Figure 14. On Resistance vs. VS or VD for Various Temperatures,
12 V Single Supply
Rev. 0 | Page 15 of 34
ADGS±408VADGS±409
Data Sheet
1.0
18
16
14
12
10
8
I
(OFF) +–
(OFF) +–
(OFF) –+
(OFF) –+
I
(OFF) +–
(OFF) +–
(OFF) –+
(OFF) –+
V
V
V
= +15V
= –15V
V
V
V
= 12V
S
S
DD
SS
DD
SS
I
I
= 0V
= 1V/10V
D
D
0.8
0.6
0.4
I
I
S
= +10V/–10V
S
BIAS
BIAS
I
I
D
D
I
I
I
(ON) ++
(ON) ––
I
I
I
(ON) ++
(ON) ––
D,
S
S
D,
S
S
I
I
D,
D,
0.2
0
6
–0.2
–0.4
–0.6
–0.8
–1.0
4
2
0
–2
0
10
20
30
40
50
60
70
80
0
20
40
60
80
100
120
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 15. Leakage Current vs. Temperature, 15 V Dual Supply
Figure 18. Leakage Current vs. Temperature, 12 V Single Supply
14
200
I
I
I
I
I
I
(OFF) +–
(OFF) +–
(OFF) –+
(OFF) –+
V
V
V
= +15V
= –15V
S
DD
SS
T
= 25°C
A
D
S
12
10
150
100
50
= +10V/–10V
BIAS
D
D,
D,
I
I
(ON) ++
(ON) ––
S
S
8
6
V
V
= +5V
= –5V
DD
SS
0
4
V
V
= +12V
= 0V
DD
SS
–50
–100
–150
–200
2
V
V
= +15V
DD
SS
0
= –15V
–2
–4
0
20
40
60
80
100
120
–15
–10
–5
0
5
10
15
TEMPERATURE (°C)
V
(V)
S
Figure 16. Leakage Current vs. Temperature, 15 V Dual Supply
Figure 19. Charge Injection vs. Source Voltage (VS)
10
400
350
300
250
200
150
100
50
I
(OFF) +–
(OFF) +–
(OFF) –+
(OFF) –+
V
V
V
= +5V
= –5V
S
DD
SS
15V DS
12V SS
5.5V DS
I
9
8
7
6
5
D
I
= +4.5V/–4.5V
S
BIAS
I
D
I
I
I
(ON) ++
(ON) ––
D,
S
S
I
D,
4
3
2
1
0
–1
0
–40
0
20
40
60
80
100
120
–20
0
20
40
60
80
100
120
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 20. Transition Time vs. Temperature for Single Supply (SS) and
Dual Supply (DS)
Figure 17. Leakage Current vs. Temperature, 5 V Dual Supply
Rev. 0 | Page 16 of 34
Data Sheet
ADGS±408VADGS±409
0
0
NO DECOUPLING
100nF DECOUPLING CAP
10uF + 100nF DECOUPLING CAP
V
V
T
= +15V
= –15V
= 25°C
DD
SS
–10
–20
–40
A
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
V
V
T
= +15V
= –15V
DD
SS
= 25°C
A
–60
–80
–100
–120
–140
–120
1k
10k
100k
1M
10M
100M
1G
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 21. Off Isolation vs. Frequency, 15 V Dual Supply
Figure 24. AC Power Supply Rejection Ratio (ACPSRR) vs. Frequency,
15 V Dual Supply
0
0.10
V
V
T
= +15V
= –15V
= 25°C
LOAD = 110Ω
DD
SS
T
= 25°C
A
0.09
0.08
0.07
0.06
0.05
0.04
0.03
0.02
0.01
0
–20
–40
A
V
= +5V, V = –5V, V = +5V p-p
SS S
DD
–60
–80
–100
–120
–140
V
= +15V, V = –15V, V = +15V p-p
DD
SS
S
1k
10k
100k
1M
10M
100M
1G
10
100
1k
FREQUENCY (Hz)
10k
100k
FREQUENCY (Hz)
Figure 22. ADGS1408 Crosstalk vs. Frequency, 15 V Dual Supply
Figure 25. THD + N vs. Frequency
0
0
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
–3.5
–4.0
V
V
T
= +15V
= –15V
= 25°C
DD
SS
–20
–40
A
ADJACENT CHANNELS
NON-ADJACENT CHANNELS
–60
–80
–100
–120
–140
V
V
A
= +15V
= –15V
DD
SS
T
= 25°C
1k
10k
100k
1M
10M
100M
1G
100
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 23. ADGS1409 Crosstalk vs. Frequency, 15 V Dual Supply
Figure 26. ADGS1408 Insertion Loss vs. Frequency, 15 V Dual Supply
Rev. 0 | Page 17 of 34
ADGS±408VADGS±409
Data Sheet
0
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
250
200
150
100
50
±15V
+12V
T
= 25°C
A
ADGS1408 WITH S8 SELECTED
V
V
A
= +15V
= –15V
–3.5
DD
SS
±5V
T
= 25°C
0
–4.0
100
1k
10k
100k
1M
10M
100M
1G
2.7
3.0
3.5
4.0
(V)
4.5
5.0
5.5
V
FREQUENCY (Hz)
L
Figure 29. IDD vs. VL
Figure 27. ADGS1409 Insertion Loss vs. Frequency, 15 V Dual Supply
2.0
1.5
1.0
0.5
0
450
400
350
300
250
200
150
100
50
T
= 25°C
A
–0.5
–1.0
SCLK = 2.5MHz
V
V
= +15V
= –15V
= 25°C
DD
SS
–1.5
–2.0
SCLK IDLE
V
V
= 5V
= 3V
L
L
T
A
0
1
10
20
30
40
50
0
1
2
3
4
5
6
7
8
9
SCLK FREQUENCY (MHz)
TIME (µs)
Figure 28. Digital Feedthrough
Figure 30. IL vs. SCLK Frequency when CS is High
Rev. 0 | Page 18 of 34
Data Sheet
ADGS±408VADGS±409
TEST CIRCUITS
I
(OFF)
A
I
(OFF)
A
S
D
Sx
Dx
(ON)
D
Sx
Dx
V
V
D
V
S
S
V
D
Figure 31. On Leakage
Figure 35. Off Leakage
V
V
DD
SS
0.1µF
0.1µF
AUDIO PRECISION
V
V
DD
SS
R
S
I
DS
Sx
V
S
V1
V p-p
Dx
V
OUT
Sx
Dx
R
110ꢀ
L
GND
S
R
= V /I
1 DS
ON
Figure 32. On Resistance
Figure 36. THD + Noise
V
V
DD
SS
V
V
DD
SS
0.1µF
0.1µF
0.1µF
0.1µF
NETWORK
ANALYZER
NETWORK
ANALYZER
V
V
DD
SS
V
V
DD
SS
V
OUT
S1
R
L
50ꢀ
Sx
50ꢀ
D
R
L
50ꢀ
V
S2
S
Dx
V
V
OUT
S
R
50ꢀ
L
GND
GND
V
WITH SWITCH
V
OUT
OUT
INSERTION LOSS = 20 log
CHANNEL TO CHANNEL CROSSTALK = 20 log
V
WITHOUT SWITCH
V
S
S
Figure 37. −3 dB Bandwidth
Figure 33. Channel to Channel Crosstalk
V
V
SS
SS
V
V
DD
SS
NETWORK
ANALYZER
0.1µF
0.1µF
INTERNAL
BIAS
V
DD
NETWORK
ANALYZER
R
L
V
V
DD
SS
50ꢀ
V
S
Sx
50ꢀ
50ꢀ
V
S
V
NC
OUT
R
50ꢀ
S1
D1
L
Dx
GND
V
OUT
R
L
GND
50ꢀ
V
OUT
ACPSRR = 20 log
V
S
V
OUT
NOTES
OFF ISOLATION = 20 log
V
S
1. BOARD AND COMPONENT EFFECTS ARE NOT DE-EMBEDDED
FROM THE ACPSRR MEASUREMENT.
Figure 34. Off Isolation
Figure 38. ACPSRR
Rev. 0 | Page 19 of 34
ADGS±408VADGS±409
Data Sheet
V
V
V
V
DD
DD
SS
SS
SCLK
0V
S1
V
S
S2 TO S7
S8
V
= V
S8
S1
80%
80%
ADGS14081
OUTPUT
OUTPUT
D
100ꢀ
GND
35pF
tD
1
SIMILAR CONNECTION FOR THE ADGS1409.
Figure 39. Break-Before-Make Time Delay, tD
V
V
V
DD
DD
SS
V
SS
SCLK
50%
50%
ADGS14081
S1
V
V
S1
S8
S2 TO S7
S8
90%
V
D
OUT
R
100ꢀ
C
L
35pF
GND
L
10%
tTRANSITION
tTRANSITION
1
SIMILAR CONNECTION FOR THE THE ADGS1409.
Figure 40. Transition Time, tTRANSITION
V
V
V
V
DD
DD
SS
SS
SCLK
50%
50%
ADGS14081
S1
V
S1
S2 TO S8
90%
V
D
OUT
R
100ꢀ
C
L
35pF
GND
L
10%
tOFF (EN)
tON (EN)
1
SIMILAR CONNECTION FOR THE ADGS1409.
Figure 41. Switching Times, tON (EN) and tOFF (EN)
V
V
V
V
DD
SS
3V
DD
SS
SCLK
R
V
S
Sx
Dx
V
OUT
C
1nF
L
S
Q
= C × ∆V
L OUT
INJ
INPUT LOGIC
GND
V
OUT
∆V
OUT
SWITCH OFF
SWITCH ON
Figure 42. Charge Injection, QINJ
Rev. 0 | Page 20 of 34
Data Sheet
ADGS±408VADGS±409
V
V
V
V
DD
DD
SS
SS
SCLK
50%
50%
ADGS14081
GPOx
V
GPO
C
L
15pF
90%
GND
10%
tOFF (GPO)
tON (GPO)
1
SIMILAR CONNECTION FOR THE ADGS1409.
Figure 43. GPOx Timing, tON (GPO) and tOFF (GPO)
V
V
DD
SS
V
V
DD
SS
80%
80%
V
V
GPO1
0V
0V
GPO1
V
V
GPO1
80%
80%
C
15pF
L
GPO2
ADGS14081
GPO2
GPO2
C
L
15pF
tD (GPO)
tD (GPO)
GND
TIME DELAY BETWEEN
GPO1 TURNING OFF
AND GPO2 TURNING ON
1
SIMILAR CONNECTION FOR THE ADGS1409.
Figure 44. GPOx Break-Before-Make Time Delay, tD (GPO)
Rev. 0 | Page 21 of 34
ADGS±408VADGS±409
Data Sheet
TERMINOLOGY
IDD
CD (On), CS (On)
I
DD is the positive supply current.
CD (on) and CS (on) are the on switch capacitances, which are
measured with reference to ground.
ISS
I
SS is the negative supply current.
CIN
CIN is the digital input capacitance.
VD, VS
ꢀD and ꢀS are the analog voltages on Terminal Dx and Terminal Sx,
tON
respectively.
tON is the delay between applying the digital control input and
the output switching on.
RON
RON is the ohmic resistance between Terminal Dx and Terminal Sx.
tOFF
tOFF is the delay between applying the digital control input and
the output switching off.
ΔRON
ΔRON is the difference between the RON of any two channels.
Off Isolation
RFLAT (ON)
Off isolation is a measure of unwanted signal coupling through
an off switch.
RFLAT (ON) is flatness defined as the difference between the maximum
and minimum value of on resistance values measured over the
specified analog signal range.
Charge Injection
Charge injection is a measure of the glitch impulse transferred
from the digital input to the analog output during switching.
IS (Off)
IS (off) is the source leakage current with the switch off.
Crosstalk
ID (Off)
Crosstalk is a measure of unwanted signal that is coupled
through from one channel to another as a result of parasitic
capacitance.
ID (off) is the drain leakage current with the switch off.
IS (On), ID (On)
IS (on) and ID (on) are the channel leakage currents with the
switch on.
−3 dB Bandwidth
Bandwidth is the frequency at which the output is attenuated
by 3 dB.
VINL
ꢀINL is the maximum input voltage for Logic 0.
On Response
VINH
On response is the frequency response of the on switch.
ꢀINH is the minimum input voltage for Logic 1.
Insertion Loss
IINL, IINH
Insertion loss is the loss due to the on resistance of the switch.
I
INL and IINH are the low and high input currents of the digital
Total Harmonic Distortion + Noise (THD + N)
THD + N is the ratio of the harmonic amplitude plus noise of
the signal to the fundamental.
inputs.
CD (Off)
CD (off) is the off switch drain capacitance, which is measured
with reference to ground.
AC Power Supply Rejection Ratio (ACPSRR)
ACPSRR is the ratio of the amplitude of signal on the output to the
amplitude of the modulation. ACPSRR is a measure of the ability of
the devices to avoid coupling noise and spurious signals that appear
on the supply voltage pin to the output of the switch. The dc voltage
on the device is modulated by a sine wave of 0.62 ꢀ p-p.
CS (Off)
CS (off) is the off switch source capacitance, which is measured
with reference to ground.
Rev. 0 | Page 22 of 34
Data Sheet
ADGS±408VADGS±409
THEORY OF OPERATION
The target register address of an SPI command is determined on
the eighth SCLK rising edge. Data from this register propagates out
on SDO from the 9th to the 16th SCLK falling edge during SPI
reads. A register write occurs on the 16th SCLK rising edge
during SPI writes.
The ADGS1408/ADGS1409 are a set of serially controlled analog
multiplexers comprising eight single channels and four differential
channels, respectively, with error detection features. SPI Mode 0
and SPI Mode 3 can be used with the devices. The devices operate
with SCLK frequencies up to 50 MHz. The default mode for the
ADGS1408/ADGS1409 is address mode, in which the registers of
the device are accessed by a 16-bit SPI command bounded by
During any SPI command, SDO sends out eight alignment bits
on the first eight SCLK falling edges. The alignment bits observed
at SDO are 0x25.
CS
. The SPI command becomes 24-bit if the user enables CRC
error detection. Other error detection features include SCLK count
error and invalid read/write error. If any of these SPI interface
errors occur, they are detectable by reading the error flags
register. The ADGS1408/ADGS1409 can also operate in two
other modes, namely burst mode and daisy-chain mode.
ERROR DETECTION FEATURES
Protocol and communication errors on the SPI interface are
detectable. There are three detectable errors: incorrect SCLK error
detection, invalid read and write address error detection, and
CRC error detection. Each error has a corresponding enable bit
in the error configuration register. In addition, there is an error
flag bit for each error in the error flags register.
CS
The interface pins of the ADGS1408/ADGS1409 are , SCLK,
CS
SDI, and SDO. Hold low when using the SPI interface. Data is
captured on SDI on the rising edge of SCLK, and data is propagated
out on SDO on the falling edge of SCLK. SDO has an open-drain
output. Connect a pull-up to this output. When not pulled low by
the ADGS1408/ADGS1409, SDO is in a high impedance state.
CRC Error Detection
The CRC error detection feature extends a valid SPI frame by
eight SCLK cycles. These eight extra cycles are needed to send the
CRC byte for that SPI frame. The CRC byte is calculated by the SPI
ADDRESS MODE
W
block using the 16-bit payload: the R/ bit, Register Address
Address mode is the default mode for the ADGS1408/ADGS1409
on power-up. A single SPI frame in address mode is bounded by
Bits[6:0], and Register Data Bits[7:0]. The CRC polynomial
used in the SPI block is x8 + x2 + x1 + 1 with a seed value of 0.
For a timing diagram with CRC enabled, see Figure 46. Register
writes occur at the 24th SCLK rising edge with CRC error
checking enabled.
CS
CS
a
falling edge and the succeeding rising edge. An SPI frame
is comprised of 16 SCLK cycles. The timing diagram for address
mode is shown in Figure 45. The first SDI bit indicates if the SPI
command is a read or write command. When the first bit is set
to 0, a write command is issued, and if the first bit is set to 1, a
read command is issued. The next seven bits determine the target
register address. The remaining eight bits provide the data to the
addressed register. The last eight bits are ignored during a read
command, because during these clock cycles, SDO propagates out
the data contained in the addressed register.
During an SPI write, the microcontroller/CPU provides the
CRC byte through SDI. The SPI block checks the CRC byte just
before the 24th SCLK rising edge. On this same edge, the register
write is prevented if an incorrect CRC byte is received by the SPI
interface. In the case of the incorrect CRC byte being detected, the
CRC error flag is asserted in the error flags register.
During an SPI read, the CRC byte is provided to the micro-
controller through SDO.
The CRC error detection feature is disabled by default and can
be configured by the user through the error configuration register.
1
2
3
4
A4
8
5
6
7
8
9
10
11
12
13
14
15
16
CS
SCLK
SDI
R/W A6
0
A5
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
SDO
0
1
0
0
1
0
1
D7
D6
D5
D4
D3
D2
D1
D0
Figure 45. Address Mode Timing Diagram
1
2
9
10
16
17
18
19
20
21
22
23
24
CS
SCLK
SDI
R/W A6
0
A0
D7
D6
D0
C7
C6
C5
C4
C4
C3
C3
C2
C2
C1
C1
C0
C0
SDO
0
1
D7
D6
D0
C7
C6
C5
Figure 46. Timing Diagram with CRC Enabled
Rev. 0 | Page 23 of 34
ADGS±408VADGS±409
Data Sheet
SCLK Count Error Detection
BURST MODE
SCLK count error detection allows the user to detect if an
incorrect number of SCLK cycles are sent by the microcontroller/
CPU. When in address mode, with CRC disabled, 16 SCLK
cycles are expected. If 16 SCLK cycles are not detected, the
SCLK count error flag asserts in the error flags register. When
fewer than 16 SCLK cycles are received by the device, a write to
the register map never occurs. When the ADGS1408/ADGS1409
receive more than 16 SCLK cycles, a write to the memory map
still occurs at the 16th SCLK rising edge, and the flag asserts in
the error flags register. With CRC enabled, the expected number of
SCLK cycles is 24. SCLK count error detection is enabled by
default and can be configured by the user through the error
configuration register.
The SPI interface can accept consecutive SPI commands
CS
mode. Burst mode is enabled through the burst enable register.
This mode uses the same 16-bit command to communicate
with the device. In addition, the response of the device at SDO
is still aligned with the corresponding SPI command. Figure 47
shows an example of SDI and SDO during burst mode.
without the need to deassert the
line, which is called burst
The invalid read/write address and CRC error checking functions
operate similarly during burst mode as they do during address
mode. However, SCLK count error detection operates in a
slightly different manner. The total number of SCLK cycles
CS
within a given
frame are counted, and if the total is not a
multiple of 16, or a multiple of 24 when CRC is enabled, the
SCLK count error flag asserts.
Invalid Read/Write Address Error Detection
An invalid read/write address error detects when a nonexistent
register address is a target for a read or write. In addition, this
error asserts when a write to a read only register is attempted.
The invalid read/write address error flag asserts in the error
flags register when an invalid read/write address error occurs.
The invalid read/write address error is detected on the ninth
SCLK rising edge, which means a write to the register never
occurs when an invalid address is targeted. Invalid read/write
address error detection is enabled by default and can be disabled
by the user through the error configuration register.
CS
SDI
COMMAND0[15:0] COMMAND1[15:0] COMMAND2[15:0] COMMAND3[15:0]
SDO
RESPONSE0[15:0] RESPONSE1[15:0] RESPONSE2[15:0] RESPONSE3[15:0]
Figure 47. Burst Mode Frame
SOFTWARE RESET
When in address mode, the user can initiate a software reset. To
initiate a software reset, write two consecutive SPI commands,
namely 0xA3 followed by 0x05, targeting Register 0x0B. After a
software reset, all register values are set to default.
CLEARING THE ERROR FLAGS REGISTER
DAISY-CHAIN MODE
To clear the error flags register, write the special 16-bit SPI frame,
0x6CA9, to the device. This SPI command does not trigger the
invalid read/write address error. When CRC is enabled, the user
must also send the correct CRC byte for a successful error clear
command. At the 16th or 24th SCLK rising edge, the error flags
register resets to 0.
The connection of several ADGS1408/ADGS1409 devices in a
daisy-chain configuration is possible, and Figure 48 shows this
setup. All devices share the same and SCLK line, whereas the
SDO of a device forms a connection to the SDI of the next device,
creating a shift register. In daisy-chain mode, SDO is an eight-
cycle delayed version of SDI. When in daisy-chain mode, all
commands target the switch data register. Therefore, it is not
possible to make configuration changes while in daisy-chain mode.
CS
ADGS1408
DEVICE 1
ADGS1408
DEVICE 2
S1
S1
D
D
V
L
S8
S8
SPI
INTERFACE
SDO
SPI
INTERFACE
CNV
CNV
SDO
SDI
SCLK
CS
RESET/V
L
Figure 48. Two ADGS1408 Devices Connected in a Daisy-Chain Configuration
Rev. 0 | Page 24 of 34
Data Sheet
ADGS±408VADGS±409
The ADGS1408/ADGS1409 can only enter daisy-chain mode
when in address mode by sending the 16-bit SPI command,
0x2500 (see Figure 49). When the ADGS1408/ADGS1409
receive this command, the SDO of the device sends out the
same command because the alignment bits at SDO are 0x25,
which allows multiple daisy-connected devices to enter daisy-
chain mode in a single SPI frame. A hardware reset is required to
exit daisy-chain mode.
An SCLK rising edge reads in data on SDI while data is
propagated out of SDO on an SCLK falling edge. The expected
CS
goes high. When the expected number of SCLK cycles is not a
multiple of eight, the SPI interface sends the last eight bits
received to the switch data register.
number of SCLK cycles must be a multiple of eight before
POWER-ON RESET
The digital section of the ADGS1408/ADGS1409 goes through an
initialization phase during ꢀL power-up. This initialization also
occurs after a hardware or software reset. After ꢀL power-up or
a reset, ensure a minimum of 120 μs from the time of power-up or
reset before any SPI command is issued. Ensure that ꢀL does
not drop out during the 120 μs initialization phase because it
may result in incorrect operation of the ADGS1408/ADGS1409.
For the timing diagram of a typical daisy-chain SPI frame, see
CS
Figure 50. When
goes high, Device 1 writes Command 0,
Bits[7:0] to its switch data register, Device 2 writes Command 1,
Bits[7:0] to its switches, and so on. The SPI block uses the last
eight bits it received through SDI to update the switches. After
entering daisy-chain mode, the first eight bits sent out by SDO
CS
on each device in the chain are 0x00. When
goes high, the
internal shift register value does not reset back to zero.
1
0
2
0
3
1
4
0
5
0
6
1
7
0
8
1
9
0
10
0
11
0
12
0
13
0
14
0
15
0
16
0
CS
SCLK
SDI
SDO
0
0
1
0
0
1
0
1
0
0
0
0
0
0
0
0
Figure 49. SPI Command to Enter Daisy-Chain Mode
CS
SDI
COMMAND3[7:0] COMMAND2[7:0] COMMAND1[7:0] COMMAND0[7:0]
DEVICE 1
DEVICE 2
DEVICE 3
DEVICE 4
SDO
8’h00
8’h00
8’h00
COMMAND3[7:0] COMMAND2[7:0] COMMAND1[7:0]
SDO2
SDO3
8’h00
8’h00
COMMAND3[7:0] COMMAND2[7:0]
8’h00 COMMAND3[7:0]
NOTES
1. SDO2 AND SDO3 ARE THE OUTPUT COMMANDS FROM DEVICE 2 AND DEVICE 3, RESPECTIVELY.
Figure 50. Example of an SPI Frame Where Four ADGS1408/ADGS1409 Devices Connect in Daisy-Chain Mode
Rev. 0 | Page 25 of 34
ADGS±408VADGS±409
Data Sheet
After configuration completes, the round robin enable register
allows the ADGS1408/ADGS1409 to enter round robin mode.
When in round robin mode, the SPI is no longer used to switch
between channels. Instead, to switch from one channel to another,
ROUND ROBIN MODE
Round robin mode allows the ADGS1408/ADGS1409 to cycle
through the channels faster by reducing the overhead needed
from the digital interface to switch from one channel to the next.
The round robin configuration register selects which channels
are to be included in a cycle, and the CNꢀ edge select register
selects on which edge of CNꢀ the ADGS1408/ADGS1409 switch
to the next channel in the sequence. At the end of the channel
cycle, a resync pulse appears on SDO to inform the user that the
current cycle ended; then, SDO loops back to the start of the
sequence of channels. Figure 51 shows an example of the round
robin mode interface, and Figure 52 shows the CNꢀ signal of
the analog-to-digital converter (ADC) being used in conjunction
with the ADGS1408 in round robin mode.
CS
ensure that a digital signal is present on the CNꢀ pin while
is pulled low.
To exit round robin mode, either perform a hardware reset or send
the following two 16-bit addressable mode SPI frames: 0xA318,
followed by 0xE3B4. These frames are the only SPI commands
recognized by the SPI interface while in round robin mode.
Round robin mode is significantly faster than addressable mode
to cycle through channels because it removes the 16-bit overhead
required to change input channel. In addition, round robin mode
removes the need for SCLK to be running, which reduces the
digital current consumption, IL. The maximum CNꢀ frequency
is bound by the transition time of the device along with the
required settling time for the application.
ROUND ROBIN CYCLE
CS
CNV
MUX
X
S1
S2
S(LAST)
RESYNC
CHANNEL
SDO
Figure 51. Round Robin Mode Interface Example
tCYC
VIO
S1
IN1 S2
IN2
IN0
SDI
CNV
SDO
D
AD7980
IN±
S3
tACQ
tCONV
ADGS1408
CNV
SCK
IN7 S8
ACQUISITION
CONVERSION
ACQUISITION
CNV
CS SDI SCK
CONVERT
GPO
CLK
1
2
3
14
15
16
SCK
SDO
DATA IN
GPO
DIGITAL HOST
tDIS
tEN
D15
D14
D13
D1
D0
MUX
N
N + 1
N + 2
CHANNEL
Figure 52. Example of the CNV Signal of an ADC Cycling Through Channels in the ADGS1408
Rev. 0 | Page 26 of 34
Data Sheet
ADGS±408VADGS±409
or low. When the device is in round robin mode, the GPOs are
driven low. The logic low level is GND, and ꢀL sets the logic
high level. Figure 53 shows how the ADGS1408 can be used to
control another device, which in this example is the ADG758.
GENERAL-PURPOSE OUTPUTS (GPOs)
The ADGS1408 has four GPOs, and the ADGS1409 has five
GPOs. These digital outputs allow the control of other devices
using the ADGS1408/ADGS1409. The GPOs are controlled
from the SW_DATA register where they can be either set high
ADGS1408
ADG758
S1
S1
D
D
S8
S8
GPO1
GPO2
GPO3
GPO4
SDO
SPI
1 OF 8
DECODER
INTERFACE
CNV
A0
A1
A2
EN
SDI
SCLK
CS
RESET/V
L
Figure 53. ADGS1408 Device Controlling the ADG758
Rev. 0 | Page 27 of 34
ADGS±408VADGS±409
Data Sheet
APPLICATIONS INFORMATION
DIGITAL INPUT BUFFERS
There are input buffers present on the digital input pins (
SCLK, and SDI). These buffers are active at all times; as a result,
there is current drawn from the ꢀL supply if SCLK or SDI are
(LDOs), ADP7118 and ADP7182 (positive and negative LDOs,
respectively), that can be used to reduce the output ripple of
the ADP5070 in ultralow noise sensitive applications.
,
CS
The ADM7160 can be used to generate the ꢀL voltage required
to power digital circuitry within the ADGS1408/ADGS1409.
toggling, regardless of whether
is active. For typical values of
CS
ADM7160
+3.3V
this current draw, refer to the Specifications section and Figure 30.
LDO
POWER SUPPLY RAILS
+16.5V
–16.5V
ADP7118
LDO
+15V
–15V
+5V
INPUT
ADP5070
To guarantee correct operation of the ADGS1408/ADGS1409,
0.1 μF decoupling capacitors are required.
ADP7182
LDO
.
The ADGS1408/ADGS1409 can operate with bipolar supplies
between 4.5 ꢀ and 16.5 ꢀ. The supplies on ꢀDD and ꢀSS do
not need to be symmetrical; however, the ꢀDD to ꢀSS range must
not exceed 33 ꢀ. The ADGS1408/ADGS1409 can also operate
with single supplies between 5 ꢀ and 20 ꢀ with ꢀSS connected
to GND.
Figure 54. Bipolar Power Solution
Table 11. Recommended Power Management Devices
Product Description
ADP5070 1 A/0.6 A, dc-to-dc switching regulator with
independent positive and negative outputs
ADM7160 5.5 V, 200 mA, ultralow noise, linear regulator
The voltage range that can be supplied to ꢀL is from 2.7 ꢀ to 5.5 ꢀ.
ADP7118 20 V, 200 mA, low noise, CMOS LDO linear regulator
ADP7182 −28 V, −200 mA, low noise, LDO linear regulator
The device is fully specified at 15 ꢀ, 5 ꢀ, and +12 ꢀ analog
supply voltage ranges.
POWER SUPPLY SEQUENCING
POWER SUPPLY RECOMMENDATIONS
Take care to ensure correct power supply sequencing. Incorrect
power supply sequencing can result in the device being subjected to
stresses beyond the maximum ratings listed in Table 7. Ensure
that the analog power supplies (ꢀDD and ꢀSS) and ground (GND)
are present before applying ꢀL, the digital inputs, and the analog
inputs. Failure to adhere to this sequence may result in damage
to the device.
Analog Devices has a wide range of power management products
to meet the requirements of most high performance signal chains.
An example of a bipolar power solution is shown in Figure 54.
The ADP5070 dual switching regulator generates a positive and
negative supply rail for the ADGS1408/ADGS1409, an amplifier,
and/or a precision converter in a typical signal chain. Also
shown in Figure 54 are two optional low dropout regulators
Rev. 0 | Page 28 of 34
Data Sheet
ADGS±408VADGS±409
REGISTER SUMMARIES
Table 12. ADGS1408 Register Summary
Reg. Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Default RW
0x01 SW_DATA
0x02 ERR_CONFIG
0x03 ERR_FLAGS
0x05 BURST_EN
0x06 ROUND_ROBIN_EN
GPO4 GPO3 GPO2 GPO1 A2
A1
A0
EN
0x00
0x06
0x00
R/W
R/W
R
Reserved
Reserved
RW_ERR_EN
SCLK_ERR_EN
CRC_ERR_EN
RW_ERR_FLAG SCLK_ERR_FLAG CRC_ERR_FLAG
Reserved
Reserved
BURST_MODE_EN 0x00
ROUND_ROBIN_EN 0x00
R/W
R/W
R/W
R/W
R/W
0x07 RROBIN_CHANNEL_CONFIG S8_EN S7_EN S6_EN S5_EN S4_EN S3_EN
S2_EN
S1_EN
0xFF
0x00
0x00
0x09 CNV_EDGE_SEL
0x0B SOFT_RESETB
Reserved
SOFT_RESETB
CNV_EDGE_SEL
Table 13. ADGS1409 Register Summary
Reg. Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Default RW
0x01 SW_DATA
GPO5 GPO4 GPO3 GPO2 GPO1 A1
A0
EN
0x00
0x06
0x00
0x00
R/W
R/W
R
0x02 ERR_CONFIG
0x03 ERR_FLAGS
Reserved
Reserved
RW_ERR_EN
SCLK_ERR_EN
CRC_ERR_EN
RW_ERR_FLAG SCLK_ERR_FLAG CRC_ERR_FLAG
Reserved BURST_MODE_EN
0x05 BURST_EN
R/W
R/W
R/W
R/W
R/W
0x06 ROUND_ROBIN_EN
0x07 RROBIN_CHANNEL_CONFIG
0x09 CNV_EDGE_SEL
0x0B SOFT_RESETB
Reserved
ROUND_ROBIN_EN 0x00
Reserved
S4_EN S3_EN
Reserved
S2_EN
S1_EN
0x0F
0x00
0x00
CNV_EDGE_SEL
SOFT_RESETB
Rev. 0 | Page 29 of 34
ADGS±408VADGS±409
REGISTER DETAILS
Data Sheet
SWITCH DATA REGISTER
Address: 0x01, Reset: 0x00, Name: SW_DATA
The switch data register controls the status of the eight switches of the ADGS1408/ADGS1409, as well as the general-purpose digital
outputs. Use the ADGS1408/ADGS1409 truth tables in conjunction with the bit descriptions.
Table 14. Bit Descriptions for SW_DATA, ADGS1408
Bit(s)
Bit Name
GPO4
GPO3
GPO2
GPO1
A2
Settings
Description
Default Access
7
6
5
4
3
2
1
0
Enable bit for GPO4.
Enable bit for GPO3.
Enable bit for GPO2.
Enable bit for GPO1.
Enable bit for A2.
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
A1
Enable bit for A1.
A0
Enable bit for A0.
EN
Enable bit for ADGS1408.
ADGS1408 disabled.
ADGS1408 enabled.
0
1
Table 15. Bit Descriptions for SW_DATA, ADGS1409
Bit(s)
Bit Name
GPO5
GPO4
GPO3
GPO2
GPO1
A1
Settings
Description
Default Access
7
6
5
4
3
2
1
0
Enable bit for GPO5.
Enable bit for GPO4.
Enable bit for GPO3.
Enable bit for GPO2.
Enable bit for GPO1.
Enable bit for A1.
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
A0
Enable bit for A0.
EN
Enable bit for ADGS1409.
ADGS1409 disabled.
ADGS1409 enabled.
0
1
Table 16. ADGS1408 Truth Table1
A2
X
0
0
0
0
1
1
1
A1
X
0
0
1
1
0
0
1
A0
EN
0
1
1
1
1
1
1
1
On Switch
X
0
1
0
1
0
1
0
1
None
S1
S2
S3
S4
S5
S6
S7
S8
1
1
1
1 X means don’t care.
Table 17. ADGS1409 Truth Table1
A1
A0
EN
0
1
On Switch Pair
X
0
X
0
None
S1
0
1
1
S2
1
0
1
S3
1
1
1
S4
1 X means don’t care.
Rev. 0 | Page 30 of 34
Data Sheet
ADGS±408VADGS±409
ERROR CONFIGURATION REGISTER
Address: 0x02, Reset: 0x06, Name: ERR_CONFIG
The error configuration register allows the user to enable and disable the relevant error features as required.
Table 18. Bit Descriptions for ERR_CONFIG
Bit(s)
[7:3]
2
Bit Name
Settings
Description
Default Access
Reserved
These bits are reserved. Set these bits to 0.
0x0
0x1
R
RW_ERR_EN
Enable bit for detecting an invalid read/write address.
R/W
0
1
Disabled.
Enabled.
1
0
SCLK_ERR_EN
CRC_ERR_EN
Enable bit for detecting the correct number of SCLK cycles in an SPI frame. 0x1
16 SCLK cycles are expected when CRC is disabled and burst mode is disabled.
24 SCLK cycles are expected when CRC is enabled and burst mode is disabled.
A multiple of 16 SCLK cycles is expected when CRC is disabled and burst
mode is enabled. A multiple of 24 SCLK cycles is expected when CRC is
enabled and burst mode is enabled.
R/W
R/W
0
1
Disabled.
Enabled.
Enable bit for CRC error detection. SPI frames are 24 bits wide when
enabled.
0x0
0
1
Disabled.
Enabled.
ERROR FLAGS REGISTER
Address: 0x03, Reset: 0x00, Name: ERR_FLAGS
The error flags register allows the user to determine if an error occurred. To clear the error flags register, write the special 16-bit SPI
command, 0x6CA9, to the device. This SPI command does not trigger the invalid R/W address error. When CRC is enabled, the user
must include the correct CRC byte during the SPI write for the clear error flags register command to succeed.
Table 19. Bit Descriptions for ERR_FLAGS
Bit(s)
[7:3]
2
Bit Name
Settings
Description
Default Access
Reserved
These bits are reserved. Set these bits to 0.
0x0
0x0
R
R
RW_ERR_FLAG
Error flag for invalid read/write address. The error flag asserts during an
SPI read if the target address does not exist. The error flag also asserts
when the target address of an SPI write does not exist or is read only.
0
1
No error.
Error.
1
0
SCLK_ERR_FLAG
CRC_ERR_FLAG
Error flag for the detection of the correct number of SCLK cycles in an SPI
frame.
No error.
0x0
0x0
R
R
0
1
Error.
Error flag that determines if a CRC error occurred during a register write.
0
1
No error.
Error.
Rev. 0 | Page 31 of 34
ADGS±408VADGS±409
Data Sheet
BURST ENABLE REGISTER
Address: 0x05, Reset: 0x00, Name: BURST_EN
The burst enable register allows the user to enable or disable burst mode. When enabled, the user can send multiple consecutive SPI
CS
commands without deasserting
.
Table 20. Bit Descriptions for BURST_EN
Bit(s)
[7:1]
0
Bit Name
Settings
Description
Default Access
Reserved
These bits are reserved. Set these bits to 0.
0x0
0x0
R
BURST_MODE_EN
Burst mode enable bit.
Disabled.
Enabled.
R/W
0
1
ROUND ROBIN ENABLE REGISTER
Address: 0x06, Reset: 0x00, Name: ROUND_ROBIN_EN
The round robin register allows the user to enable or disable round robin mode. When enabled, the user can cycle through the channels
enabled in the round robin configuration register by presenting the relevant edge on the CNꢀ pin.
Table 21. Bit Descriptions for ROUND_ROBIN_EN
Bit(s)
[7:1]
0
Bit Name
Settings
Description
Default Access
Reserved
These bits are reserved. Set these bits to 0.
Round robin mode enable bit.
Disabled.
0x0
0x0
R
ROUND_ROBIN_EN
R/W
0
1
Enabled.
ROUND ROBIN CHANNEL CONFIGURATION REGISTER
Address: 0x07, Reset: 0xFF (ADGS1408), 0x0F (ADGS1409), Name: RROBIN_CHANNEL_CONFIG
The round robin channel configuration register controls which channels are included in a cycle during round robin mode. During round
robin mode, the channels are cycled through in ascending order.
Table 22. Bit Descriptions for RROBIN_CHANNEL_CONFIG, ADGS1408
Bit(s)
Bit Name
Settings
Description
Default Access
7
S8_EN
Enable bit for S8.
0x1
0x1
0x1
0x1
0x1
0x1
R/W
R/W
R/W
R/W
R/W
R/W
0
1
S8 disabled during round robin mode.
S8 enabled during round robin mode.
Enable bit for S7.
S7 disabled during round robin mode.
S7 enabled during round robin mode.
Enable bit for S6.
S6 disabled during round robin mode.
S6 enabled during round robin mode.
Enable bit for S5.
S5 disabled during round robin mode.
S5 enabled during round robin mode.
Enable bit for S4.
6
5
4
3
2
S7_EN
S6_EN
S5_EN
S4_EN
S3_EN
0
1
0
1
0
1
0
1
S4 disabled during round robin mode.
S4 enabled during round robin mode.
Enable bit for S3.
0
1
S3 disabled during round robin mode.
S3 enabled during round robin mode.
Rev. 0 | Page 32 of 34
Data Sheet
ADGS±408VADGS±409
Bit(s)
Bit Name
Settings
Description
Default Access
1
S2_EN
Enable bit for S2.
0x1
R/W
0
1
S2 disabled during round robin mode.
S2 enabled during round robin mode.
Enable bit for S1.
0
S1_EN
0x1
R/W
0
1
S1 disabled during round robin mode.
S1 enabled during round robin mode.
Table 23. Bit Descriptions for RROBIN_CHANNEL_CONFIG, ADGS1409
Bit(s)
[7:4]
3
Bit Name
Reserved
S4_EN
Settings
Description
Default Access
These bits are reserved. Set these bits to 0.
Enable bit for S4.
0x0
0x1
R
R/W
0
1
S4 disabled during round robin mode.
S4 enabled during round robin mode.
Enable bit for S3.
2
1
0
S3_EN
S2_EN
S1_EN
0x1
0x1
0x1
R/W
R/W
R/W
0
1
S3 disabled during round robin mode.
S3 enabled during round robin mode.
Enable bit for S2.
S2 disabled during round robin mode.
S2 enabled during round robin mode.
Enable bit for S1.
0
1
0
1
S1 disabled during round robin mode.
S1 enabled during round robin mode.
CNV EDGE SELECT REGISTER
Address: 0x06, Reset: 0x00, Name: CNV_EDGE_SEL
The CNꢀ edge select register allows the user to select the active edge of the CNꢀ pin when the device is in round robin mode.
Table 24. Bit Descriptions for CNV_EDGE_SEL
Bit(s)
[7:1]
0
Bit Name
Settings
Description
Default Access
Reserved
These bits are reserved. Set these bits to 0.
CNV active edge select bit.
0x0
0x0
R
CNV_EDGE_SEL
R/W
0
1
Falling edge of CNV is the active edge.
Rising edge of CNV is the active edge.
SOFTWARE RESET REGISTER
Address: 0x0B, Reset: 0x00, Name: SOFT_RESETB
Use the software reset register to perform a software reset. Write 0xA3 followed by 0x05 consecutively to this register, and the registers of
the device reset to their default state.
Table 25. Bit Descriptions for SOFT_RESETB
Bit(s)
Bit Name
Settings
Description
Default Access
[7:0]
SOFT_RESETB
To perform a software reset, consecutively write 0xA3 followed by 0x05 to 0x0
this register.
R
Rev. 0 | Page 33 of 34
ADGS±408VADGS±409
OUTLINE DIMENSIONS
Data Sheet
DETAIL A
(JEDEC 95)
4.10
4.00 SQ
3.90
0.30
0.25
0.18
PIN 1
INDICATOR
PIN 1
NS
INDIC ATOR AREA OPTIO
(SEE DETAIL A)
24
19
18
1
0.50
BSC
2.70
2.60 SQ
2.50
EXPOSED
PAD
13
12
6
7
0.50
0.40
0.30
0.20 MIN
TOP VIEW
BOTTOM VIEW
1.00
0.95
0.90
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.05 MAX
0.02 NOM
COPLANARITY
0.08
SECTION OF THIS DATA SHEET.
SEATING
PLANE
0.20 REF
COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-8.
Figure 55. 24-Lead Lead Frame Chip Scale Package [LFCSP]
4 mm × 4 mm Body and 0.95 mm Package Height
(CP-24-17)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
ADGS1408BCPZ
ADGS1408BCPZ-RL7
ADGS1409BCPZ
ADGS1409BCPZ-RL7
EVAL-ADGS1408SDZ
EVAL-ADGS1409SDZ
Temperature Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Package Description
Package Option
CP-24-17
CP-24-17
24-Lead Lead Frame Chip Scale Package [LFCSP]
24-Lead Lead Frame Chip Scale Package [LFCSP]
24-Lead Lead Frame Chip Scale Package [LFCSP]
24-Lead Lead Frame Chip Scale Package [LFCSP]
ADGS1408 Evaluation Board
CP-24-17
CP-24-17
ADGS1409 Evaluation Board
1 Z = RoHS Compliant Part.
©2018 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D16791-0-6/18(0)
Rev. 0 | Page 34 of 34
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