ADM3483 [ADI]
3.3 V Slew Rate Limited, Half- and Full-Duplex, RS-485/RS-422 Transceivers; 3.3 V摆率限制，半双工和全双工， RS - 485 / RS -422收发器
| 型号： | ADM3483 |
| 厂家： | 
ADI |
| 描述： | 3.3 V Slew Rate Limited, Half- and Full-Duplex, RS-485/RS-422 Transceivers |
| 文件： | 总20页 (文件大小：460K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
3.3 V Slew Rate Limited, Half- and
Full-Duplex, RS-485/RS-422 Transceivers
ADM3483/ADM3485/ADM3488/ADM3490/ADM3491
FUNCTIONAL BLOCK DIAGRAMS
FEATURES
V
Operate with 3.3 V supply
CC
Interoperable with 5 V logic
EIA RS-422 and RS-485 compliant over full
common-mode range
Data rate options
ADM3483/ADM3488: 250 kbps
ADM3483/
ADM3485
R
RO
RE
DE
DI
A
B
ADM3485/ADM3490/ADM3491: 10 Mbps
Half- and full-duplex options
D
Reduced slew rates for low EMI (ADM3483 and ADM3488)
2 nA supply current in shutdown mode
(ADM3483/ADM3485/ADM3491)
GND
Figure 1.
Up to 32 transceivers on the bus
V
CC
−7 V to +12 V bus common-mode range
Specified over the –40°C to +85°C temperature range
8 ns skew (ADM3485/ADM3490/ADM3491)
8-lead SOIC and 14-lead SOIC (ADM3491 only) packages
A
B
R
RO
ADM3488/
ADM3490
APPLICATIONS
Z
Y
Low power RS-485/RS-422 applications
Telecom
DI
D
Industrial process control
HVAC
GND
Figure 2.
GENERAL DESCRIPTION
ADM3491
The ADM3483/ADM3485/ADM3488/ADM3490/ADM3491 are
low power, differential line transceivers designed to operate using a
single 3.3 V power supply. Low power consumption, coupled with a
shutdown mode, makes the ADM3483/ADM3485/ADM3488/
ADM3490/ADM3491 ideal for power-sensitive applications.
A
B
Z
R
RO
RE
DE
DI
D
Y
The ADM3488/ADM3490/ADM3491 feature full-duplex com-
munication, while the ADM3483/ADM3485 are designed for
half-duplex communication.
Figure 3.
The ADM3483/ADM3488 feature slew rate limited drivers that
minimize EMI and reduce reflections caused by improperly ter-
minated cables, allowing error-free data transmission at data rates
up to 250 kbps.
in the internal driver circuitry during fault conditions, then the
thermal shutdown circuit forces the driver output into a high
impedance state. If the inputs are unconnected (floating), the
receiver contains a fail-safe feature that results in a logic high
output state. The parts are fully specified over the commercial
and industrial temperature ranges. The ADM3483/ADM3485/
ADM3488/ADM3490 are available in 8-lead SOIC_N; the
ADM3491 is available in a 14-lead SOIC_N.
The ADM3485/ADM3490/ADM3491 transmit at up to 10 Mbps.
The receiver input impedance is 12 kΩ, allowing up to 32 trans-
ceivers to be connected on the bus. A thermal shutdown circuit
prevents excessive power dissipation caused by bus contention or
by output shorting. If a significant temperature increase is detected
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2006 Analog Devices, Inc. All rights reserved.
ADM3483/ADM3485/ADM3488/ADM3490/ADM3491
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagrams............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 4
Timing Specifications—ADM3485/ADM3490/ADM3491.... 5
Timing Specifications—ADM3483/ADM3488........................ 5
Typical Performance Characteristics ........................................... 12
Circuit Description......................................................................... 14
Devices with Receiver/Driver Enables—
ADM3483/ADM3485/ADM3491............................................ 14
Devices Without Receiver/Driver Enables—
ADM3488/ADM3490................................................................ 14
Reduced EMI and Reflections—ADM3483/ADM3488 ....... 14
Low Power Shutdown Mode..................................................... 14
Driver Output Protection.......................................................... 14
Propagation Delay...................................................................... 14
Typical Applications................................................................... 14
Line Length vs. Data Rate ......................................................... 15
Outline Dimensions....................................................................... 17
Ordering Guide .......................................................................... 18
Timing Specifications—ADM3483/ADM3485/ADM3488/
ADM3490/ADM3491.................................................................. 6
Absolute Maximum Ratings............................................................ 7
ESD Caution.................................................................................. 7
Pin Configurations and Function Descriptions ........................... 8
Test Circuits....................................................................................... 9
Switching Characteristics .............................................................. 11
REVISION HISTORY
10/06—Rev. A to Rev. B
Updated Format..................................................................Universal
Added ADM3491................................................................Universal
Changes to Specifications Section.................................................. 4
Changes to Typical Applications Section .................................... 14
7/06—Rev. 0 to Rev. A
Changes to Applications .................................................................. 1
Changes to General Description .................................................... 1
Changes to Figure 19...................................................................... 10
Changes to Typical Applications Section .................................... 13
Changes to Figure 31 and Figure 32............................................. 14
Updated Outline Dimensions....................................................... 15
10/05—Revision 0: Initial Version
Rev. B | Page 2 of 20
ADM3483/ADM3485/ADM3488/ADM3490/ADM3491
Table 1. ADM34xx Part Comparison
Guaranteed Data
Rate (Mbps)
Supply
Half-/Full-
Duplex
Slew Rate
Limited
Driver/Receiver
Enable
Shutdown
Current (nA)
Pin
Count
Part No.
Voltage (V)
3.0 to 3.6
3.0 to 3.6
3.0 to 3.6
3.0 to 3.6
3.0 to 3.6
ADM3483 0.25
ADM3485 10
ADM3488 0.25
ADM3490 10
ADM3491 10
Half
Half
Full
Full
Full
Yes
No
Yes
No
No
Yes
Yes
No
No
Yes
2
2
N/A
N/A
2
8
8
8
8
14
Rev. B | Page 3 of 20
ADM3483/ADM3485/ADM3488/ADM3490/ADM3491
SPECIFICATIONS
VCC = 3.3 V 0.3 V, TA = TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter
Min
Typ
Max
Unit Test Conditions/Comments
DRIVER
Differential Output Voltage (VOD
)
2.0
1.5
1.5
V
V
V
V
V
V
RL = 100 Ω (RS-422), VCC = 3.3 V 5% (see Figure 7)
RL = 54 Ω (RS-485) (see Figure 7)
RL = 60 Ω (RS-485), VCC = 3.3 V (see Figure 8)
RL = 54 Ω or 100 Ω (see Figure 7)
RL = 54 Ω or 100 Ω (see Figure 7)
RL = 54 Ω or 100 Ω (see Figure 7)
Δ |VOD| for Complementary Output States1
Common-Mode Output Voltage (VOC
Δ |VOC| for Common-Mode Output Voltage1
0.2
3
0.2
)
DRIVER INPUT LOGIC
CMOS Input Logic Threshold Low (VIH)
CMOS Input Logic Threshold High (VIL)
0.8
V
DE, DI, RE
2.0
V
DE, DI, RE
CMOS Logic Input Current (IIN1
)
2
μA
mA
mA
μA
DE, DI, RE
Input Current—A, B (IIN2
)
1.0
−0.8
VIN = 12 V, DE = 0 V, VCC = 0 V or 3.6 V
VIN = −7 V, DE = 0 V, VCC = 0 V or 3.6 V
VIN = 12 V, DE = 0 V, RE = 0 V, VCC = 0 V or 3.6 V,
ADM3491 only
Output Leakage—Y, Z (IO)
0.1
−0.1
0.01
−0.01
μA
μA
μA
VIN = −7 V, DE = 0 V, RE = 0 V, VCC = 0 V or 3.6 V,
ADM3491 only
VIN = 12 V, DE = 0 V, RE = VCC, VCC = 0 V or 3.6 V,
ADM3491 only
Output Leakage (Y, Z) in Shutdown Mode (IO)
VIN = −7 V, DE = 0 V, RE = VCC, VCC = 0 V or 3.6 V,
ADM3491 only
RECEIVER
Differential Input Threshold Voltage (VTH
Input Hysteresis (Δ VTH
CMOS Output Voltage High (VOH
CMOS Output Voltage Low (VOL
)
−0.2
+0.2
V
mV
V
V
μA
kΩ
−7 V < VCM < +12 V
VCM = 0 V
IOUT = −1.5 mA, VID = 200 mV (see Figure 9)
IOUT = 2.5 mA, VID = 200 mV (see Figure 9)
VCC = 3.6 V, 0 V ≤ VOUT ≤ VCC
−7 V < VCM < +12 V
)
50
)
VCC – 0.4
)
0.4
1
Three-State Output Leakage Current (IOZR
Input Resistance (RIN)
)
12
POWER SUPPLY CURRENT
Supply Current (ICC
)
1.1
2.2
mA
DE = VCC, RE = 0 V or VCC, no load, DI = 0 V or VCC
DE = 0 V, RE = 0 V, no load, DI = 0 V or VCC
DE = 0 V, RE = VCC, DI = VCC or 0 V
VOUT = −7 V
0.95
0.002
1.9
1
mA
μA
Supply Current in Shutdown Mode (ISHDN
Driver Short-Circuit Output Current (IOSD
)
)
−250
250
60
mA
mA
mA
V
OUT = 12 V
Receiver Short-Circuit Output Current (IOSR
)
8
0 V < VRO < VCC
1ΔVOD and ΔVOC are the changes in VOD and VOC, respectively, when DI input changes state.
Rev. B | Page 4 of 20
ADM3483/ADM3485/ADM3488/ADM3490/ADM3491
TIMING SPECIFICATIONS—ADM3485/ADM3490/ADM3491
VCC = 3.3 V, TA = 25°C, unless otherwise noted.
Table 3.
Parameter
DRIVER
Min
Typ
Max
Unit
Test Conditions/Comments
Differential Output Delay (tDD
)
1
3
7
7
22
8
35
25
35
35
8
ns
ns
ns
ns
ns
RL = 60 Ω (see Figure 10 and Figure 16)
RL = 60 Ω (see Figure 10 and Figure 16)
RL = 27 Ω (see Figure 11 and Figure 17)
RL = 27 Ω (see Figure 11 and Figure 17)
RL = 27 Ω (see Figure 11 and Figure 17)
Differential Output Transition Time (tTD
)
Propagation Delay, Low-to-High Level (tPLH
)
)
22
22
Propagation Delay, High-to-Low Level (tPHL
|tPLH – tPHL| Propagation Delay Skew1 (tPDS
)
DRIVER OUTPUT ENABLE/DISABLE TIMES (ADM3485/
ADM3491 ONLY)
Output Enable Time to Low Level (tPZL
Output Enable Time to High Level (tPZH
Output Disable Time from High Level (tPHZ
Output Disable Time from Low Level (tPLZ
Output Enable Time from Shutdown to Low Level (tPSL
)
45
90
ns
ns
ns
ns
ns
ns
RL = 110 Ω (see Figure 13 and Figure 19)
RL = 110 Ω (see Figure 12 and Figure 18)
RL = 110 Ω (see Figure 12 and Figure 18)
RL = 110 Ω (see Figure 13 and Figure 19)
RL = 110 Ω (see Figure 13 and Figure 19)
RL = 110 Ω (see Figure 12 and Figure 18)
)
45
90
)
40
80
)
40
80
)
650
650
900
900
Output Enable Time from Shutdown to High Level (tPSH
)
1 Measured on |tPLH (Y) − tPHL (Y)| and |tPLH (Z) − tPHL (Z)|.
TIMING SPECIFICATIONS—ADM3483/ADM3488
VCC = 3.3 V, TA = 25°C, unless otherwise noted.
Table 4.
Parameter
DRIVER
Min
Typ
Max
Unit
Test Conditions/Comments
Differential Output Delay (tDD
)
600
400
700
700
900
1400
1200
1500
1500
ns
ns
ns
ns
ns
RL = 60 Ω (see Figure 10 and Figure 16)
RL = 60 Ω (see Figure 10 and Figure 16)
RL = 27 Ω (see Figure 11 and Figure 17)
RL = 27 Ω (see Figure 11 and Figure 17)
RL = 27 Ω (see Figure 11 and Figure 17)
Differential Output Transition Time (tTD
)
700
Propagation Delay, Low-to-High Level (tPLH
)
)
1000
1000
100
Propagation Delay, High-to-Low Level (tPHL
|tPLH – tPHL| Propagation Delay Skew1 (tPDS
DRIVER OUTPUT ENABLE/DISABLE TIMES (ADM3483 ONLY)
Output Enable Time to Low Level (tPZL
Output Enable Time to High Level (tPZH
Output Disable Time from High Level (tPHZ
Output Disable Time from Low Level (tPLZ
Output Enable Time from Shutdown to Low Level (tPSL
)
)
900
600
50
1300
800
80
ns
ns
ns
ns
ꢀs
ꢀs
RL = 110 Ω (see Figure 13 and Figure 19)
RL = 110 Ω (see Figure 12 and Figure 18)
RL = 110 Ω (see Figure 12 and Figure 18)
RL = 110 Ω (see Figure 13 and Figure 19)
RL = 110 Ω (see Figure 13 and Figure 19)
RL = 110 Ω (see Figure 12 and Figure 18)
)
)
)
50
80
)
1.9
2.2
2.7
3.0
Output Enable Time from Shutdown to High Level (tPSH
)
1 Measured on |tPLH (Y) − tPHL (Y)| and |tPLH (Z) − tPHL (Z)|.
Rev. B | Page 5 of 20
ADM3483/ADM3485/ADM3488/ADM3490/ADM3491
TIMING SPECIFICATIONS—ADM3483/ADM3485/ADM3488/ADM3490/ADM3491
VCC = 3.3 V, TA = 25°C, unless otherwise noted.
Table 5.
Parameter
Min Typ
Max
Unit
Test Conditions/Comments
RECEIVER
Time to Shutdown (tSHDN
)
ADM3483/ADM3485/ADM34911
80
190
300
ns
Propagation Delay, Low-to-High Level (tRPLH
ADM3485/ADM3490/ADM3491
ADM3483/ADM3488
)
25
25
65
75
90
120
ns
ns
VID = 0 V to 3.0 V, CL = 15 pF (see Figure 14 and Figure 20)
VID = 0 V to 3.0 V, CL = 15 pF (see Figure 14 and Figure 20)
VID = 0 V to 3.0 V, CL = 15 pF (see Figure 14 and Figure 20)
Propagation Delay, High-to-Low Level (tRPHL
ADM3485/ADM3490/ADM3491
ADM3483/ADM3488
)
25
25
65
75
90
120
ns
ns
|tPLH – tPHL| Propagation Delay Skew (tRPDS
ADM3485/ADM3490/ADM3491
ADM3483/ADM3488
)
10
20
ns
ns
RECEIVER OUTPUT ENABLE/DISABLE TIMES
(ADM3483/ADM3485/ADM3491 ONLY)
Output Enable Time to Low Level (tPRZL
Output Enable Time to High Level (tPRZH
Output Disable Time from High Level (tPRHZ
)
25
25
25
25
720
50
50
45
45
ns
ns
ns
ns
ns
CL = 15 pF (see Figure 15 and Figure 21)
CL = 15 pF (see Figure 15 and Figure 21)
CL = 15 pF (see Figure 15 and Figure 21)
CL = 15 pF (see Figure 15 and Figure 21)
CL = 15 pF (see Figure 15 and Figure 21)
)
)
Output Disable Time from Low Level (tPRLZ
)
Output Enable Time from Shutdown to
1400
Low Level (tPRSL
Output Enable Time from Shutdown to
High Level (tPRSH
)
720
1400
ns
CL = 15 pF (see Figure 15 and Figure 21)
)
1
RE
The transceivers are put into shutdown by bringing the high and DE low. If the inputs are in this state for less than 80 ns, the parts are guaranteed not to enter
shutdown. If the parts are in this state for 300 ns or more, the parts are guaranteed to enter shutdown.
Rev. B | Page 6 of 20
ADM3483/ADM3485/ADM3488/ADM3490/ADM3491
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 6.
Parameter
VCC to GND
Digital I/O Voltage (DE, RE, DI)
Digital I/O Voltage (RO)
Driver Output/Receiver Input Voltage
Operating Temperature Range
Storage Temperature Range
θJA Thermal Impedance
8-Lead SOIC
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rating
7 V
−0.3 V to VCC + 0.3 V
VCC − 0.5 V to VCC + 0.5 V
−7.5 V to +12.5 V
−40°C to +85°C
−65°C to +125°C
ESD CAUTION
121°C/W
86°C/W
14-Lead SOIC
Lead Temperature
Soldering (10 sec)
Vapor Phase (60 sec)
Infrared (15 sec)
300°C
215°C
220°C
Rev. B | Page 7 of 20
ADM3483/ADM3485/ADM3488/ADM3490/ADM3491
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
NC
RO
1
2
3
4
5
6
7
14
13
12
11
10
9
V
V
CC
CC
RO
RE
DE
DI
1
2
3
4
8
7
6
5
V
V
1
2
3
4
8
7
6
5
A
B
Z
RE
A
CC
CC
ADM3491
ADM3483/
ADM3485
TOP VIEW
(Not to Scale)
ADM3488/
ADM3490
TOP VIEW
(Not to Scale)
DE
TOP VIEW
B
B
RO
DI
(Not to Scale)
DI
Z
A
GND
GND
Y
GND
GND
Y
8
NC
NC = NO CONNECT
Figure 4. ADM3483/ADM3485 Pin Configuration
Figure 5. ADM3488/ADM3490 Pin Configuration
Figure 6. ADM3491 Pin Configuration
Table 7. Pin Function Descriptions
ADM3483/ADM3485 ADM3488/ADM3490 ADM3491
Pin No.
Pin No.
Pin No.
Mnemonic Description
1
2
2
RO
Receiver Output. When enabled, if A > B by 200 mV, then
RO = high. If A < B by 200 mV, then RO = low.
2
3
4
N/A
N/A
3
3
4
5
RE
Receiver Output Enable. A low level enables the receiver
output, RO. A high level places it in a high impedance
state. If RE is high and DE is low, the device enters a low
power shutdown mode.
Driver Output Enable. A high level enables the driver differential
Output A and Output B. A low level places it in a high impedance
state. If RE is high and DE is low, the device enters a low power
shutdown mode.
Driver Input. With a half-duplex part when the driver is enabled, a
logic low on DI forces A low and B high while a logic high on
DI forces A high and B low. With a full-duplex part when the
driver is enabled, a logic low on DI forces Y low and Z high
while a logic high on DI forces Y high and Z low.
DE
DI
5
4
5
6
N/A
6, 7
9
10
GND
Ground.
Noninverting Driver Output.
Inverting Driver Output.
Noninverting Receiver Input A and Noninverting Driver
Output A.
N/A
N/A
6
Y
Z
A
N/A
N/A
7
N/A
8
8
N/A
7
1
N/A
12
N/A
11
13, 14
1, 8
A
B
B
VCC
NC
Noninverting Receiver Input A.
Inverting Receiver Input B and Inverted Driver Output B.
Inverting Receiver Input B.
Power Supply (3.3 V 0.3 V).
No Connect.
N/A
Rev. B | Page 8 of 20
ADM3483/ADM3485/ADM3488/ADM3490/ADM3491
TEST CIRCUITS
C
L
A/Y
R
60Ω
=
L
OUT
D
R /2
L
1
GENERATOR
50Ω
V
OD
V
CC
2
C
= 15pF
L
V
R /2
OC
L
B/Z
1
2
PPR = 250kHz, 50% DUTY CYCLE, tR ≤ 6.0ns, Z = 50ꢀ.
L
O
C
INCLUDES PROBE AND STRAY CAPACITANCE.
Figure 7. Differential Output Voltage
and Common-Mode Voltage Drivers
Figure 10. Driver Differential Output Delay and Transition Times
V
OM
R
= 27ꢀ
L
375Ω
S1
OUT
2
D
C
= 15pF
L
1
GENERATOR
V
=
CM
–7V TO +12V
50ꢀ
V
R
OD
L
V
D
CC
V
+ V
OL
OH
V
CC
V
=
≈ 1.5V
375Ω
OM
2
1
2
PPR = 250kHz, 50% DUTY CYCLE, tR ≤ 6.0ns, Z = 50ꢀ.
L
O
C
INCLUDES PROBE AND STRAY CAPACITANCE.
Figure 8. Differential Output Voltage Drivers
with Varying Common-Mode Voltage
Figure 11. Driver Propagation Delays
S1
OUT
0V OR 3V
D
2
= 50pF
R
= 110ꢀ
C
L
L
R
V
ID
1
GENERATOR
50ꢀ
0
V
+ V
OL
OH
V =
OM
≈ 1.5V
V
V
I
I
OH
(–)
OL
OH
OL
2
(+)
1
2
PPR = 250kHz, 50% DUTY CYCLE, tR ≤ 6.0ns, Z = 50ꢀ.
L
O
C
INCLUDES PROBE AND STRAY CAPACITANCE.
Figure 9. CMOS Output Voltage High and
CMOS Output Voltage Low Receivers
Figure 12. Driver Enable and Disable Times (tPZH, tPSH, tPHZ)
Rev. B | Page 9 of 20
ADM3483/ADM3485/ADM3488/ADM3490/ADM3491
V
CC
S1
S2
S3
+1.5V
–1.5V
V
CC
1kꢀ
R
= 110ꢀ
L
V
ID
R
S1
OUT
0V OR 3V
D
2
C
L
2
= 50pF
C
L
1
GENERATOR
50ꢀ
1
GENERATOR
50ꢀ
1
PPR = 250kHz, 50% DUTY CYCLE, tR ≤ 6.0ns, Z = 50ꢀ.
O
1
2
2
C
L
PPR = 250kHz, 50% DUTY CYCLE, tR ≤ 6.0ns, Z = 50ꢀ.
L
INCLUDES PROBE AND STRAY CAPACITANCE.
O
C
INCLUDES PROBE AND STRAY CAPACITANCE.
Figure 13. Driver Enable and Disable Times (tPZL, tPSL, tPLZ
)
Figure 15. Receiver Enable and Disable Times
OUT
V
ID
R
1
GENERATOR
50ꢀ
2
C
= 15pF
L
1.5V
0
V
CC
V
=
OM
2
1
2
PPR = 250kHz, 50% DUTY CYCLE, tR ≤ 6.0ns, Z = 50ꢀ.
L
O
C
INCLUDES PROBE AND STRAY CAPACITANCE.
Figure 14. Receiver Propagation Delays
Rev. B | Page 10 of 20
ADM3483/ADM3485/ADM3488/ADM3490/ADM3491
SWITCHING CHARACTERISTICS
+3V
3V
IN
1.5V
1.5V
1.5V
1.5V
IN
0
0
V
0
tDD
tDD
tPZH
tPHZ
≈ +2V
≈ –2V
90%
90%
OH
0.25V
50%
10%
50%
10%
OUT
OUT
V
OM
tTD
tTD
Figure 16. Driver Differential Output Delay and Transition Times
Figure 18. Driver Enable and Disable Times (tPZH, tPSH, tPHZ
)
3V
IN
1.5V
1.5V
3V
0V
IN
1.5V
1.5V
tPLH
tPHL
0
V
V
OH
OL
A/Y
tPSL
tPLZ
V
V
V
V
OM
OM
OUT
V
CC
OL
OUT
V
OM
tPHL
tPLH
0.25V
V
V
V
OH
OL
B/Z
OUT
OM
OM
Figure 17. Driver Propagation Delays
Figure 19. Driver Enable and Disable Times (tPZL, tPSL, tPLZ
)
3V
0
1.5V
1.5V
IN
tRPLH
tRPHL
V
0
CC
V
V
OM
OUT
OM
Figure 20. Receiver Propagation Delays
+3V
+3V
0
S1 OPEN
S2 CLOSED
S3 = +1.5V
S1 CLOSED
S2 OPEN
S3 = –1.5V
1.5V
IN
1.5V
IN
0
tPRZL
tPRSL
tPRZH
tPRSH
V
V
OH
CC
OUT
OUT
1.5V
1.5V
0
V
OL
+3V
0
+3V
0
S1 OPEN
S2 CLOSED
S3 = +1.5V
S1 CLOSED
S2 OPEN
S3 = –1.5V
1.5V
IN
1.5V
IN
tPRHZ
tPRLZ
V
V
OH
CC
OL
OUT
+0.25V
OUT
+0.25V
0
V
Figure 21. Receiver Enable and Disable Times
Rev. B | Page 11 of 20
ADM3483/ADM3485/ADM3488/ADM3490/ADM3491
TYPICAL PERFORMANCE CHARACTERISTICS
30
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
25
20
15
10
5
0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
–40 –30 –20 –10
0
10 20 30 40 50 60 70 80
TEMPERATURE (°C)
OUTPUT VOLTAGE (V)
Figure 25. Receiver Output Low Voltage vs. Temperature, IRO = 2.5 mA
Figure 22. Output Current vs. Receiver Output Low Voltage
–16
100
90
80
70
60
50
40
30
20
10
0
–14
–12
–10
–8
–6
–4
–2
0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
Figure 23. Output Current vs. Receiver Output High Voltage
Figure 26. Driver Output Current vs. Differential Output Voltage
3.30
2.6
2.5
2.4
2.3
2.2
2.1
2.0
1.9
1.8
1.7
1.6
3.25
3.20
3.15
3.10
3.05
3.00
–40 –30 –20 –10
0
10 20 30 40 50 60 70 80
TEMPERATURE (°C)
–40 –30 –20 –10
0
10 20 30 40 50 60 70 80
TEMPERATURE (°C)
Figure 24. Receiver Output High Voltage vs. Temperature, IRO = 1.5 mA
Figure 27. Driver Differential Output Voltage vs. Temperature, RL = 54 Ω
Rev. B | Page 12 of 20
ADM3483/ADM3485/ADM3488/ADM3490/ADM3491
140
120
100
80
1.2
1.1
1.0
0.9
0.8
DE = RE = X*
0.7
60
0.6
40
DE = RE = GND
0.5
20
0.4
*X = DON’T CARE
0
0.3
–40 –30 –20 –10
0
2
4
6
8
10
12
0
10 20 30 40 50 60 70 80
TEMPERATURE (°C)
OUTPUT VOLTAGE (V)
Figure 28. Output Current vs. Driver Output Low Voltage
Figure 30. Supply Current vs. Temperature
–125
90
80
70
60
50
40
30
20
10
0
–115
–105
–95
–85
–75
–65
–55
–45
–35
–25
–15
–5
–7
–6
–5
–4
–3
–2
–1
0
1
2
3
–40 –30 –20 –10
0
10 20 30 40 50 60 70 80
TEMPERATURE (°C)
OUTPUT VOLTAGE (V)
Figure 29. Output Current vs. Driver Output High Voltage
Figure 31. Shutdown Current vs. Temperature
Rev. B | Page 13 of 20
ADM3483/ADM3485/ADM3488/ADM3490/ADM3491
CIRCUIT DESCRIPTION
The ADM3483/ADM3485/ADM3488/ADM3490/ADM3491
REDUCED EMI AND REFLECTIONS—
ADM3483/ADM3488
are low power transceivers for RS-485 and RS-422 communi-
cations. The ADM3483/ADM3488 transmit and receive at data
rates up to 250 kbps; the ADM3485/ADM3490/ADM3491 trans-
mit at up to 10 Mbps. The ADM3488/ADM3490/ADM3491 are
full-duplex transceivers, while the ADM3483/ADM3485 are half-
The ADM3483/ADM3488 are slew rate limited transceivers,
minimizing EMI and reducing reflections caused by improp-
erly terminated cables.
duplex transceivers. Driver enable (DE) and receiver enable (
)
RE
LOW POWER SHUTDOWN MODE
pins are included on the ADM3483/ADM3485/ADM3491. When
disabled, the driver and receiver outputs are high impedance.
(ADM3483/ADM3485/ADM3491)
A low power shutdown mode is initiated by bringing
high
RE
DEVICES WITH RECEIVER/DRIVER ENABLES—
ADM3483/ADM3485/ADM3491
and DE low. The devices do not shut down unless both the driver
and receiver are disabled (high impedance). In shutdown mode,
the devices typically draw only 2 nA of supply current. For these
devices, the tPSH and tPSL enable times assume the part is in the
low power shutdown mode; the tPZH and tPZL enable times assume
the receiver or driver was disabled, but the part is not shut down.
Table 8. Transmitting Truth Table
Transmitting Input
Transmitting Output
RE
DE
DI
B1
A1
Mode
X2
X2
0
1
1
0
0
1
0
X2
X2
0
1
1
0
Normal
Normal
Normal
Shutdown
DRIVER OUTPUT PROTECTION
Two methods are implemented to prevent excessive output
current and power dissipation caused by faults or by bus
contention. Current limit protection on the output stage
provides immediate protection against short circuits over
the whole common-mode voltage range (see the Typical
Performance Characteristics section). In addition, a ther-
mal shutdown circuit forces the driver outputs into a high
impedance state if the die temperature rises excessively.
High-Z3
High-Z3
High-Z3
High-Z3
1
1 A and B outputs are Z and Y respectively, for full-duplex part (ADM3491).
2 X = don’t care.
3 High-Z = high impedance.
Table 9. Receiving Truth Table
Receiving Input
DE1
Receiving Output
RO
RE
A – B
Mode
PROPAGATION DELAY
0
0
0
1
0
0
0
0
≥ +0.2 V
≤ −0.2 V
Inputs Open
X2
1
0
1
Normal
Normal
Normal
Shutdown
Skew time is the difference between the low-to-high and high-
to-low propagation delays. Small driver/receiver skew times help
maintain a symmetrical mark-space ratio (50% duty cycle).
The receiver skew time (|tPRLH − tPRHL|) is under 10 ns (20 ns
for ADM3483/ADM3488). The driver skew times are 8 ns for
ADM3485/ADM3490/ADM3491 and typically under 100 ns for
ADM3483/ADM3488.
High-Z3
1 DE is a don’t care; X for the full-duplex part (ADM3491).
2 X = don’t care.
3 High-Z = high impedance.
DEVICES WITHOUT RECEIVER/DRIVER ENABLES—
ADM3488/ADM3490
TYPICAL APPLICATIONS
The ADM3483/ADM3485/ADM3491 transceivers are designed
for half-duplex bidirectional data communications on multipoint
bus transmission lines, Figure 32 and Figure 33 show typical
network applications circuits. The ADM3488 and the ADM3490
full-duplex transceivers are designed to be used in a daisy-chain
network topology or in a point-to-point application, see Figure 34
and Figure 35. The ADM3491 can be used as line repeat Figure 36.
To minimize reflections, the line must be terminated at both
ends in its characteristic impedance, and stub lengths off the main
line must be kept as short as possible. The slew rate limited
ADM3483/ADM3488 are more tolerant of imperfect termination.
Table 10. Transmitting Truth Table
Transmitting Input
Transmitting Output
DI
1
0
Z
0
1
Y
1
0
Table 11. Receiving Truth Table
Receiving Input
A – B
Receiving Output
RO
1
≥ +0.2 V
≤ −0.2 V
0
Inputs open
1
Rev. B | Page 14 of 20
ADM3483/ADM3485/ADM3488/ADM3490/ADM3491
LINE LENGTH VS. DATA RATE
The RS-485 and RS-422 standards cover line lengths up to 4000 feet. For line lengths greater than 4000 feet, see Figure 36.
MAXIMUM NUMBER OF TRANSCEIVERS ON BUS = 32
ADM3483/
ADM3485
ADM3483/
ADM3485
V
CC
R1
R
R
RO
RE
DE
DI
RO
RE
DE
DI
A
A
R
R
T
T
B
B
D
D
R2
A
B
A
B
ADM3483/
ADM3485
ADM3483/
ADM3485
R
R
D
D
RO RE DE DI
RO RE DE DI
NOTES
1. R IS EQUAL TO THE CHARACTERISTIC IMPEDANCE OF THE CABLE.
T
Figure 32. ADM3483/ADM3485 Typical Half-Duplex RS-485 Network
MAXIMUM NUMBER OF NODES = 32
V
T
CC
R1
MASTER
R
SLAVE
D
A
B
Z
Y
Z
RO
RE
DE
DI
DI
R
R
T
DE
RE
RO
V
CC
R1
R
R2
B
A
R
T
T
D
R
Y
R2
ADM3491
ADM3491
A
B
Z
Y
A
B
Z
Y
SLAVE
SLAVE
R
R
D
D
ADM3491
ADM3491
RO RE DE DI
RO RE DE DI
NOTES
1. R IS EQUAL TO THE CHARACTERISTIC IMPEDANCE OF THE CABLE.
T
Figure 33. ADM3491 Typical Full-Duplex RS-485 Network
Rev. B | Page 15 of 20
ADM3483/ADM3485/ADM3488/ADM3490/ADM3491
MASTER
SLAVE
ADM3488/
ADM3490
ADM3488/
ADM3490
A
Y
RO
DI
R
D
DI
B
Z
Z
B
D
R
RO
Y
A
A
B
Z
Y
A
B
Z
Y
ADM3488/
ADM3490
ADM3488/
ADM3490
SLAVE
SLAVE
R
R
D
D
RO
DI
RO
DI
Figure 34. ADM3488/ADM3490 Full-Duplex Daisy-Chain Network
MASTER
SLAVE
ADM3488/
ADM3490
ADM3488/
ADM3490
A
Y
RO
DI
R
D
DI
B
Z
Z
B
R
RO
D
Y
A
Figure 35. ADM3488/ADM3490 Full-Duplex Point-to-Point Applications
ADM3491
A
RO
R
R
R
DATA IN
T
B
Z
Y
RE
DE
DI
DATA OUT
T
D
NOTES
1. R IS EQUAL TO THE CHARACTERISTIC IMPEDANCE OF THE CABLE.
T
Figure 36. Line Repeater for ADM3491
Rev. B | Page 16 of 20
ADM3483/ADM3485/ADM3488/ADM3490/ADM3491
OUTLINE DIMENSIONS
5.00 (0.1968)
4.80 (0.1890)
8
1
5
4
6.20 (0.2440)
5.80 (0.2284)
4.00 (0.1574)
3.80 (0.1497)
1.27 (0.0500)
BSC
0.50 (0.0196)
0.25 (0.0099)
× 45°
1.75 (0.0688)
1.35 (0.0532)
0.25 (0.0098)
0.10 (0.0040)
8°
0.51 (0.0201)
0.31 (0.0122)
0° 1.27 (0.0500)
COPLANARITY
0.10
0.25 (0.0098)
0.17 (0.0067)
SEATING
PLANE
0.40 (0.0157)
COMPLIANT TO JEDEC STANDARDS MS-012-AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 37. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-8)
Dimensions shown in millimeters and (inches)
8.75 (0.3445)
8.55 (0.3366)
8
7
14
1
4.00 (0.1575)
3.80 (0.1496)
6.20 (0.2441)
5.80 (0.2283)
1.27 (0.0500)
BSC
0.50 (0.0197)
0.25 (0.0098)
1.75 (0.0689)
1.35 (0.0531)
× 45°
0.25 (0.0098)
0.10 (0.0039)
8°
0°
0.51 (0.0201)
0.31 (0.0122)
SEATING
PLANE
1.27 (0.0500)
0.40 (0.0157)
COPLANARITY
0.10
0.25 (0.0098)
0.17 (0.0067)
COMPLIANT TO JEDEC STANDARDS MS-012-AB
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 38. 14-Lead Narrow Body Small Outline [SOIC_N]
Narrow Body
(R-14)
Dimensions shown in millimeters and (inches)
Rev. B | Page 17 of 20
ADM3483/ADM3485/ADM3488/ADM3490/ADM3491
ORDERING GUIDE
Model
Temperature Range Package Description
Package Option Ordering Quantity
ADM3483ARZ1
ADM3483ARZ–REEL71
ADM3485ARZ1
ADM3485ARZ–REEL71
ADM3488ARZ1
ADM3488ARZ–REEL71
ADM3490ARZ1
ADM3490ARZ–REEL71
ADM3491AR
ADM3491AR-REEL
ADM3491AR-REEL7
ADM3491ARZ1
8-Lead Narrow Body Small Outline (SOIC_N)
8-Lead Narrow Body Small Outline (SOIC_N)
8-Lead Narrow Body Small Outline (SOIC_N)
8-Lead Narrow Body Small Outline (SOIC_N)
8-Lead Narrow Body Small Outline (SOIC_N)
8-Lead Narrow Body Small Outline (SOIC_N)
8-Lead Narrow Body Small Outline (SOIC_N)
R-8
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
R-8
R-8
R-8
R-8
R-8
R-8
1,000
1,000
1,000
1,000
8-Lead Narrow Body Small Outline (SOIC_N)
14-Lead Narrow Body Small Outline (SOIC_N)
14-Lead Narrow Body Small Outline (SOIC_N)
14-Lead Narrow Body Small Outline (SOIC_N)
14-Lead Narrow Body Small Outline (SOIC_N)
14-Lead Narrow Body Small Outline (SOIC_N)
14-Lead Narrow Body Small Outline (SOIC_N)
R-8
R-14
R-14
R-14
R-14
R-14
R-14
2,500
1,000
ADM3491ARZ-REEL1
ADM3491ARZ-REEL71
2,500
1,000
1 Z = Pb-free part.
Rev. B | Page 18 of 20
ADM3483/ADM3485/ADM3488/ADM3490/ADM3491
NOTES
Rev. B | Page 19 of 20
ADM3483/ADM3485/ADM3488/ADM3490/ADM3491
NOTES
©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05524-0-10/06(B)
Rev. B | Page 20 of 20
相关型号：
ADM3483EARZ-REEL7
3.3 V, 【15 kV ESD-Protected, Half- and Full-Duplex, RS-485/RS-422 Transceivers
ADI
©2020 ICPDF网 联系我们和版权申明