ADM7151 [ADI]
High PSRR, RF Linear Regulator;
| 型号： | ADM7151 |
| 厂家： | 
ADI |
| 描述： | High PSRR, RF Linear Regulator |
| 文件： | 总23页 (文件大小：840K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
1.2 A, Ultralow Noise,
High PSRR, RF Linear Regulator
ADP7156
Data Sheet
FEATURES
TYPICAL APPLICATION CIRCUIT
Input voltage range: 2.3 V to 5.5 V
16 standard voltages between 1.2 V and 3.3 V available
Maximum load current: 1.2 A
ADP7156
V
= 3.8V
V
= 3.3V
IN
OUT
C
VIN
VOUT
C
10µF
IN
OUT
10µF
VOUT_SENSE
Low noise
ON
0.9 μV rms total integrated noise from 100 Hz to 100 kHz
1.6 μV rms total integrated noise from 10 Hz to 100 kHz
Noise spectral density: 1.7 nV/√Hz from 10 kHz to 1 MHz
Power supply rejection ratio (PSRR)
EN
REF
OFF
C
REF
1µF
BYP
C
BYP
REF_SENSE
1µF
80 dB from 1 kHz to 100 kHz; 60 dB at 1 MHz, VOUT = 3.3 V,
VREG
C
REG
1µF
VIN = 4.0 V
GND (EPAD)
Dropout voltage: 120 mV typical at IOUT = 1.2 A, VOUT = 3.3 V
Initial accuracy: 0.6ꢀ at ILOAD = 10 mA
Initial accuracy over line, load, and temperature: 1.5ꢀ
Quiescent current: IGND = 4.0 mA at no load, 7 mA at 1.2 A
Low shutdown current: 0.2 ꢁA
Figure 1.
Table 1. Related Devices
Stable with a 10 μF ceramic output capacitor
10-lead, 3 mm × 3 mm LFCSP and 8-lead SOIC packages
Precision enable
Input
Voltage
Output
Fixed/
Model
Current Adj1
Package
ADP7158,
ADP7159
2.3 V to 5.5 V
2 A
Fixed/
Adj
10-lead LFCSP/
8-lead SOIC
Supported by ADIsimPower tool
APPLICATIONS
ADP7157
2.3 V to 5.5 V
4.5 V to 16 V
2.3 V to 5.5 V
2.2 V to 5.5 V
1.2 A
Fixed/
Adj
Fixed/
Adj
Fixed/
Adj
Fixed
10-lead LFCSP/
8-lead SOIC
8-lead LFCSP/
8-lead SOIC
8-lead LFCSP/
8-lead SOIC
6-lead LFCSP/
5-lead TSOT
Regulation to noise sensitive applications: phase-locked
loops (PLLs), voltage controlled oscillators (VCOs), and
PLLs with integrated VCOs
Communications and infrastructure
Backhaul and microwave links
ADM7150,
ADM7151
ADM7154,
ADM7155
800 mA
600 mA
200 mA
ADM7160
GENERAL DESCRIPTION
1 Adj means adjustable.
The ADP7156 is a linear regulator that operates from 2.3 V to 5.5 V
and provides up to 1.2 A of output current. Using an advanced
proprietary architecture, it provides high power supply rejection
and ultralow noise, achieving excellent line and load transient
response with only a 10 μF ceramic output capacitor.
1k
C
C
C
C
= 1µF
BYP
BYP
BYP
BYP
= 10µF
= 100µF
= 1000µF
100
10
1
There are 16 standard output voltages for the ADP7156. The
following voltages are available from stock: 1.2 V, 1.8 V, 2.0 V,
2.5 V, 2.8 V, 3.0 V and 3.3 V. Additional voltages available by
special order are 1.3 V, 1.5 V, 1.6 V, 2.2 V, 2.6 V, 2.7 V, 2.9 V,
3.1 V, and 3.2 V.
The ADP7156 regulator typical output noise is 0.9 ꢀV rms
from 100 Hz to 100 kHz and 1.7 nV/√Hz for noise spectral
density from 10 kHz to 1 MHz. The ADP7156 is available in a
10-lead, 3 mm × 3 mm LFCSP and 8-lead SOIC packages,
making it not only a very compact solution, but also providing
excellent thermal performance for applications requiring up to
1.2 A of output current in a small, low profile footprint.
0.1
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
Figure 2. Noise Spectral Density at Different Values of CBYP, VOUT = 3.3 V
Rev. A
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Tel: 781.329.4700
Technical Support
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www.analog.com
ADP7156* Product Page Quick Links
Last Content Update: 11/01/2016
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ADP7156
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications Information .............................................................. 14
ADIsimPower Design Tool ....................................................... 14
Capacitor Selection .................................................................... 14
Undervoltage Lockout (UVLO) ............................................... 15
Programmable Precision Enable .............................................. 16
Start-Up Time ............................................................................. 17
REF, BYP, and VREG Pins......................................................... 17
Current-Limit and Thermal Shutdown................................... 17
Thermal Considerations............................................................ 17
Printed Circuit Board (PCB) Layout Considerations................ 20
Outline Dimensions....................................................................... 21
Ordering Guide .......................................................................... 22
Applications....................................................................................... 1
General Description......................................................................... 1
Typical Application Circuit ............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Input and Output Capacitors, Recommended Specifications 4
Absolute Maximum Ratings............................................................ 5
Thermal Data ................................................................................ 5
Thermal Resistance ...................................................................... 5
ESD Caution.................................................................................. 5
Pin Configurations and Function Descriptions ........................... 6
Typical Performance Characteristics ............................................. 7
Theory of Operation ...................................................................... 13
REVISION HISTORY
5/2016—Rev. 0 to Rev. A
Changes to Table 2............................................................................ 3
Changes to Programmable Precision Enable Section................ 16
Changes to Current-Limit and Thermal Shutdown Section .... 17
3/2016—Revision 0: Initial Version
Rev. A | Page 2 of 22
Data Sheet
ADP7156
SPECIFICATIONS
VIN = VOUT + 0.5 V or 2.3 V, whichever is greater; VEN = VIN; ILOAD = 10 mA; CIN = COUT = 10 µF; CREG = CREF = CBYP = 1 µF;
TA = 25°C for typical specifications; TA = −40°C to +125°C for minimum/maximum specifications, unless otherwise noted.
Table 2.
Parameter
Symbol
VIN
Test Conditions/Comments
Min
Typ
Max
Unit
V
INPUT VOLTAGE RANGE
LOAD CURRENT
2.3
5.5
1.2
8.0
12.0
4
ILOAD
A
OPERATING SUPPLY CURRENT
IGND
ILOAD = 0 µA
ILOAD = 1.2 A
4.0
7.0
0.2
mA
mA
µA
SHUTDOWN CURRENT
NOISE1
Output Noise
IIN_SD
EN = GND
VOUT = 1.2 V to 3.3 V
10 Hz to 100 kHz
100 Hz to 100 kHz
10 kHz to 1 MHz
OUTNOISE
1.6
0.9
1.7
80
µV rms
µV rms
nV/√Hz
dB
Noise Spectral Density
POWER SUPPLY REJECTION RATIO1
OUTNSD
PSRR
1 kHz to 100 kHz, VIN = 4.0 V, VOUT = 3.3 V,
I
LOAD = 1.2 A
1 MHz, VIN = 4.0 V, VOUT = 3.3 V, ILOAD = 1.2 A
1 kHz to 100 kHz, VIN = 2.6 V, VOUT = 1.8 V,
60
80
dB
dB
I
LOAD = 1.2 A
1 MHz, VIN = 2.6 V, VOUT = 1.8 V, ILOAD = 1.2 A
60
dB
OUTPUT VOLTAGE ACCURACY
Output Voltage2
VOUT
1.2
3.3
V
Initial Accuracy
ILOAD = 10 mA, TA = 25°C
10 mA < ILOAD < 1.2 A, TA= 25°C
10 mA < ILOAD < 1.2 A, TA = −40°C to +125°C
−0.6
−1.0
−1.5
+0.6
+1.0
+1.5
%
%
%
REGULATION
Line
∆VOUT/∆VIN
VIN = VOUT + 0.5 V or 2.3 V, whichever is greater
to 5.5 V
IOUT = 10 mA to 1.2 A
−0.1
+0.1
0.3
%/V
%/A
Load3
∆VOUT/∆IOUT
ILIMIT
CURRENT-LIMIT THRESHOLD4
REF
VOUT
DROPOUT VOLTAGE5
22
1.8
60
mA
A
1.4
2.4
80
170
VDROPOUT
IOUT = 600 mA, VOUT = 3.3 V
IOUT = 1.2 A, VOUT = 3.3 V
EN = 0 V, VIN = 5.5 V
VOUT = 1 V
VREG = 1 V
VREF = 1 V
mV
mV
120
PULL-DOWN RESISTANCE
VOUT
VREG
REF
VOUT_PULL
VREG_PULL
VREF_PULL
VBYP_PULL
650
31
850
650
Ω
kΩ
Ω
BYP
VBYP = 1 V
Ω
START-UP TIME1, 6
VOUT = 3.3 V
VOUT
VREG
REF
tSTART-UP
tREG_START-UP
tREF_START-UP
1.2
0.6
0.5
ms
ms
ms
THERMAL SHUTDOWN1
Threshold
Hysteresis
TSSD
TSSD_HYS
TJ rising
150
15
°C
°C
UNDERVOLTAGE THRESHOLDS
Input Voltage
Rising
Falling
Hysteresis
UVLORISE
UVLOFALL
UVLOHYS
2.22 2.29
2.02
200
V
V
mV
1.95
Rev. A | Page 3 of 22
ADP7156
Data Sheet
Parameter
Symbol
Test Conditions/Comments
Min
Typ
Max
Unit
VREG UVLO THRESHOLDS7
Rising
Falling
Hysteresis
VREGUVLORISE
VREGUVLOFALL
VREGUVLOHYS
1.94
V
V
mV
1.60
185
EN INPUT PRECISION
EN Input
2.3 V ≤ VIN ≤ 5.5 V
Logic High
Logic Low
Logic Hysteresis
LEAKAGE CURRENT
REF_SENSE
EN
VEN_HIGH
VEN_LOW
VEN_HYS
1.13
1.05
1.22 1.31
1.13 1.22
90
V
V
mV
IREF_SENSE_LKG
IEN_LKG
10
nA
µA
EN = VIN or GND
0.01
1
1 Guaranteed by characterization; not production tested.
2 The ADP7156 is available in 16 standard voltages between 1.2 V and 3.3 V, including 1.2 V, 1.3 V, 1.5 V, 1.6 V, 1.8 V, 2.0 V, 2.2 V, 2.5 V, 2.6 V, 2.7 V, 2.8 V, 2.9 V, 3.0 V, 3.1 V,
3.2 V, and 3.3 V.
3 Based on an endpoint calculation using 10 mA and 1.2 A loads.
4 Current-limit threshold is defined as the current at which the output voltage drops to 90% of the specified typical value. For example, the current limit for a 3.0 V
output voltage is defined as the current that causes the output voltage to drop to 90% of 3.0 V, or 2.7 V.
5 Dropout voltage is defined as the input to output voltage differential when the input voltage is set to the nominal output voltage. Dropout voltage applies only for
output voltages greater than 2.3 V.
6 Start-up time is defined as the time between the rising edge of VEN to VOUT, VREG, or VREF being at 90% of its nominal value.
7 The output voltage is disabled until the VREG UVLO rise threshold is crossed. The VREG output is disabled until the input voltage UVLO rising threshold is crossed.
INPUT AND OUTPUT CAPACITORS, RECOMMENDED SPECIFICATIONS
Table 3.
Parameter
Symbol
Test Conditions/Comments
Min
Typ
Max
Unit
MINIMUM CAPACITANCE
Input1
TA = −40°C to +125°C
CIN
10.0
1.0
10.0
1.0
µF
µF
µF
µF
µF
Regulator
CREG
COUT
CBYP
CREF
Output1
Bypass
Reference
1.0
CAPACITOR EFFECTIVE SERIES RESISTANCE (ESR)
TA = −40°C to +125°C
COUT, CIN
CREG, CREF
CBYP
RESR
RESR
RESR
0.001
0.001
0.001
0.1
0.2
2.0
Ω
Ω
Ω
1 The minimum input and output capacitance must be greater than 7.0 μF over the full range of operating conditions. The full range of operating conditions in the
application must be considered during device selection to ensure that the minimum capacitance specification is met. X7R and X5R type capacitors are recommended;
Y5V and Z5U capacitors are not recommended for use with any low dropout regulator.
Rev. A | Page 4 of 22
Data Sheet
ADP7156
ABSOLUTE MAXIMUM RATINGS
Junction to ambient thermal resistance (θJA) of the package is
based on modeling and calculation using a 4-layer board. The
junction to ambient thermal resistance is highly dependent on
the application and board layout. In applications where high
maximum power dissipation exists, close attention to thermal
board design is required. The value of θJA may vary, depending
on PCB material, layout, and environmental conditions. The
specified values of θJA are based on a 4-layer, 4 in. × 3 in. circuit
board. See JESD51-7 and JESD51-9 for detailed information on
the board construction.
Table 4.
Parameter
Rating
VIN to Ground
VREG to Ground
−0.3 V to +7 V
−0.3 V to VIN, or +4 V
(whichever is less)
VOUT to Ground
−0.3 V to VREG, or +4 V
(whichever is less)
VOUT_SENSE to Ground
−0.3 V to VREG, or +4 V
(whichever is less)
VOUT to VOUT_SENSE
BYP to VOUT
0.3 V
0.3 V
ΨJB is the junction to board thermal characterization parameter
with units of °C/W. ΨJB of the package is based on modeling and
calculation using a 4-layer board. JESD51-12, Guidelines for
Reporting and Using Electronic Package Thermal Information,
states that thermal characterization parameters are not the same
as thermal resistances. ΨJB measures the component power
flowing through multiple thermal paths rather than a single
path as in thermal resistance, θJB. Therefore, ΨJB thermal paths
include convection from the top of the package as well as
radiation from the package, factors that make ΨJB more useful
in real-world applications. Maximum junction temperature (TJ)
is calculated from the board temperature (TB) and power
dissipation (PD) using the following formula:
EN to Ground
BYP to Ground
−0.3 V to +7 V
−0.3 V to VREG, or +4 V
(whichever is less)
−0.3 V to VREG, or +4 V
(whichever is less)
−0.3 V to +4 V
REF to Ground
REF_SENSE to Ground
Storage Temperature Range
Operational Junction Temperature
Range
Soldering Conditions
−65°C to +150°C
−40°C to +125°C
JEDEC J-STD-020
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
TJ = TB + (PD × ΨJB)
See JESD51-8 and JESD51-12 for more detailed information
about ΨJB.
THERMAL RESISTANCE
THERMAL DATA
θJA, θJC, and ΨJB are specified for the worst case conditions, that
is, a device soldered in a circuit board for surface-mount
packages.
Absolute maximum ratings apply individually only, not in
combination. The ADP7156 can be damaged when the junction
temperature limits are exceeded. Monitoring ambient tempera-
ture does not guarantee that TJ is within the specified temperature
limits. In applications with high power dissipation and poor
thermal resistance, the maximum ambient temperature may
need to be derated.
Table 5. Thermal Resistance
Package Type
10-Lead LFCSP
8-Lead SOIC
θJA
θJC
ΨJB
Unit
°C/W
°C/W
53.8
50.4
15.6
42.3
29.1
30.1
In applications with moderate power dissipation and low
printed circuit board (PCB) thermal resistance, the maximum
ambient temperature can exceed the maximum limit as long as
the junction temperature is within specification limits. The
junction temperature (TJ) of the device is dependent on the
ambient temperature (TA), the power dissipation of the device
(PD), and the junction to ambient thermal resistance of the
package (θJA).
ESD CAUTION
Calculate the maximum junction temperature (TJ) from the
ambient temperature (TA) and power dissipation (PD) using
the following formula:
TJ = TA + (PD × θJA)
Rev. A | Page 5 of 22
ADP7156
Data Sheet
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
10
VOUT
1
2
3
4
5
VIN
VOUT
9
8
7
6
VIN
VOUT
VOUT_SENSE
BYP
1
2
3
4
8
7
6
5
VIN
ADP7156
TOP VIEW
(Not to Scale)
VOUT_SENSE
BYP
VREG
REF
ADP7156
TOP VIEW
(Not to Scale)
VREG
REF
EN
REF_SENSE
EN
REF_SENSE
NOTES
NOTES
1. THE EXPOSED PAD IS LOCATED ON THE BOTTOM OF
THE PACKAGE. THE EXPOSED PAD ENHANCES THERMAL
PERFORMACE, AND IT IS ELECTRICALLY CONNECTED TO
GROUND INSIDE THE PACKAGE. CONNECT THE EXPOSED
PAD TO THE GROUND PLANE ON THE BOARD TO ENSURE
PROPER OPERATION.
1. THE EXPOSED PAD IS LOCATED ON THE BOTTOM OF
THE PACKAGE. THE EXPOSED PAD ENHANCES THERMAL
PERFORMACE, AND IT IS ELECTRICALLY CONNECTED TO
GROUND INSIDE THE PACKAGE. CONNECT THE EXPOSED
PAD TO THE GROUND PLANE ON THE BOARD TO ENSURE
PROPER OPERATION.
Figure 3. 10-Lead LFCSP Pin Configuration
Figure 4. 8-Lead SOIC Pin Configuration
Table 6. Pin Function Descriptions
Pin No.
LFCSP SOIC
Mnemonic
Description
Regulated Output Voltage. Bypass VOUT to ground with a 10 µF or greater capacitor.
1, 2
3
1
2
VOUT
VOUT_SENSE Output Sense. VOUT_SENSE is internally connected to VOUT with a 10 Ω resistor. Connect
VOUT_SENSE as close to the load as possible.
4
5
3
4
BYP
Low Noise Bypass Capacitor. Connect a 1 µF capacitor from the BYP pin to ground to reduce noise.
Do not connect a load to this pin.
Enable. Drive EN high to turn on the regulator; drive EN low to turn off the regulator. For automatic
startup, connect EN to VIN.
EN
6
7
5
6
REF_SENSE
REF
Reference Sense. Connect REF_SENSE to the REF pin. Do not connect REF_SENSE to VOUT or GND.
Low Noise Reference Voltage Output. Bypass REF to ground with a 1 µF or greater capacitor. Short
REF_SENSE to REF for fixed output voltages. Do not connect a load to this pin.
8
7
8
VREG
Regulated Input Supply Voltage to Low Dropout (LDO) Amplifier. Bypass VREG to ground with a
1 µF or greater capacitor.
Regulator Input Supply Voltage. Bypass VIN to ground with a 10 µF or greater capacitor.
Exposed Pad. The exposed pad is located on the bottom of the package. The exposed pad
enhances thermal performance, and it is electrically connected to ground inside the package.
Connect the exposed pad to the ground plane on the board to ensure proper operation.
9, 10
VIN
EP
Rev. A | Page 6 of 22
Data Sheet
ADP7156
TYPICAL PERFORMANCE CHARACTERISTICS
VIN = VOUT + 0.5 V or 2.3 V, whichever is greater; VEN = VIN; ILOAD = 10 mA; CIN = COUT = 10 µF; CREG = CREF = CBYP = 1 µF;
TA = 25°C unless otherwise noted.
3.35
3.34
3.33
3.32
3.31
3.30
3.29
3.28
3.27
3.26
3.25
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
2.3V
2.5V
3.0V
4.0V
5.0V
5.5V
I
I
I
I
I
= 0mA
= 10mA
LOAD
LOAD
= 100mA
= 600mA
= 1200mA
LOAD
LOAD
LOAD
3.8
4.0
4.2
4.4
4.6
V
4.8
(V)
5.0
5.2
5.4
5.6
–40
–20
0
20
40
60
80
100
120
140
TEMPERATURE (°C)
IN
Figure 5. Shutdown Current (IIN_SD) vs. Temperature
at Various Input Voltages (VIN), VOUT = 1.8 V
Figure 8. Output Voltage (VOUT) vs. Input Voltage (VIN)
at Various Loads, VOUT = 3.3 V
3.35
3.34
3.33
3.32
3.31
3.30
3.29
3.28
3.27
3.26
3.25
14
13
12
11
10
9
I
I
I
I
I
= 0mA
LOAD
LOAD
LOAD
LOAD
LOAD
= 10mA
= 100mA
= 600mA
= 1200mA
8
7
6
5
4
I
I
I
I
I
= 0mA
LOAD
LOAD
LOAD
LOAD
LOAD
= 10mA
= 100mA
= 600mA
= 1200mA
3
2
1
0
–40
–20
0
20
40
60
80
100
120
140
–40
–20
0
20
40
60
80
100
120
140
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 9. Ground Current (IGND) vs. Temperature
at Various Loads, VOUT = 3.3 V
Figure 6. Output Voltage (VOUT) vs. Temperature
at Various Loads, VOUT = 3.3 V
14
13
12
11
10
9
3.35
3.34
3.33
3.32
3.31
3.30
3.29
3.28
3.27
3.26
3.25
8
7
6
5
4
3
2
1
0
0.1m
1m
10m
100m
(A)
1
10
0.1m
1m
10m
100m
(A)
1
10
I
I
LOAD
LOAD
Figure 10. Ground Current (IGND) vs. Load Current (ILOAD), VOUT = 3.3 V
Figure 7. Output Voltage (VOUT) vs. Load Current (ILOAD), VOUT = 3.3 V
Rev. A | Page 7 of 22
ADP7156
Data Sheet
14
13
12
11
10
9
14
13
12
11
10
9
I
I
I
I
I
= 0mA
LOAD
LOAD
LOAD
LOAD
LOAD
= 10mA
= 100mA
= 600mA
= 1200mA
8
8
7
7
6
6
5
5
4
4
I
I
I
I
I
= 0mA
LOAD
LOAD
LOAD
LOAD
LOAD
= 10mA
= 100mA
= 600mA
= 1200mA
3
3
2
2
1
1
0
0
3.8
4.0
4.2
4.4
4.6
V
4.8
(V)
5.0
5.2
5.4
5.6
3.1
3.2
3.3
3.4
3.5
(V)
3.6
3.7
3.8
V
IN
IN
Figure 11. Ground Current (IGND) vs. Input Voltage (VIN)
at Various Loads, VOUT = 3.3 V
Figure 14. Ground Current (IGND) vs. Input Voltage (VIN) at Various Loads in
Dropout, VOUT = 3.3 V
0.16
0.14
0.12
0.10
0.08
0.06
0.04
0.02
0
1.85
I
I
I
I
I
= 0mA
LOAD
LOAD
LOAD
LOAD
LOAD
1.84
1.83
1.82
1.81
1.80
1.79
1.78
1.77
1.76
1.75
= 10mA
= 100mA
= 600mA
= 1200mA
10m
100
1
10
–40
–20
0
20
40
60
80
100
120
140
I
(A)
TEMPERATURE (ºC)
LOAD
Figure 12. Dropout Voltage (VDROPOUT) vs. Load Current (ILOAD), VOUT = 3.3 V
Figure 15. Output Voltage (VOUT) vs. Temperature at Various Loads, VOUT = 1.8 V
1.85
1.84
1.83
1.82
1.81
1.80
1.79
1.78
1.77
1.76
1.75
3.40
3.35
3.30
3.25
I
I
I
I
I
= 0mA
LOAD
LOAD
LOAD
LOAD
LOAD
= 10mA
= 100mA
= 600mA
= 1200mA
3.20
3.15
3.10
3.05
3.00
0.1m
1m
10m
100m
(A)
1
10
3.0
3.1
3.2
3.3
3.4
V
3.5
(V)
3.6
3.7
3.8
I
LOAD
IN
Figure 16. Output Voltage (VOUT) vs. Load Current (ILOAD), VOUT = 1.8 V
Figure 13. Output Voltage (VOUT) vs. Input Voltage (VIN) at Various Loads in
Dropout, VOUT = 3.3 V
Rev. A | Page 8 of 22
Data Sheet
ADP7156
1.85
1.84
1.83
1.82
1.81
1.80
1.79
1.78
1.77
1.76
1.75
14
13
12
11
10
9
I
I
I
I
I
= 0mA
= 10mA
= 100mA
= 600mA
= 1200mA
LOAD
LOAD
LOAD
LOAD
LOAD
I
I
I
I
I
= 0mA
LOAD
LOAD
LOAD
LOAD
LOAD
= 10mA
= 100mA
= 600mA
= 1200mA
8
7
6
5
4
3
2
1
0
2.3 2.6 2.9 3.2 3.5 3.8 4.1 4.4 4.7
5
5.3 5.6
2.3
2.7
3.1
3.5
V
3.9
(V)
4.3
4.7
5.1
5.5
V
(V)
IN
IN
Figure 17. Output Voltage (VOUT) vs. Input Voltage (VIN)
at Various Loads, VOUT = 1.8 V
Figure 20. Ground Current (IGND) vs. Input Voltage (VIN)
at Various Loads, VOUT = 1.8 V
14
13
12
11
10
9
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
I
I
I
I
= 10mA
LOAD
LOAD
LOAD
LOAD
= 100mA
= 600mA
= 1200mA
8
7
6
5
4
I
I
I
I
I
= 0mA
LOAD
LOAD
LOAD
LOAD
LOAD
3
= 10mA
= 100mA
= 600mA
= 1200mA
2
1
0
–40
–20
0
20
40
60
80
100
120
140
1
10
100
1k
10k
100k
1M
10M
TEMPERATURE (ºC)
FREQUENCY (Hz)
Figure 18. Ground Current (IGND) vs. Temperature
at Various Loads, VOUT = 1.8 V
Figure 21. Power Supply Rejection Ratio (PSRR) vs. Frequency
at Various Loads, VOUT = 3.3 V, VIN = 4.0 V
14
13
12
11
10
9
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
900mV
800mV
700mV
600mV
500mV
8
7
6
5
4
3
2
1
0
0.1m
1m
10m
100m
(A)
1
10
1
10
100
1k
10k
100k
1M
10M
I
FREQUENCY (Hz)
LOAD
Figure 19. Ground Current (IGND) vs. Load Current (ILOAD), VOUT = 1.8 V
Figure 22. Power Supply Rejection Ratio (PSRR) vs. Frequency at Various
Headroom Voltages, VOUT = 3.3 V, 1.2 A Load
Rev. A | Page 9 of 22
ADP7156
Data Sheet
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
10Hz
100Hz
1kHz
10kHz
100kHz
1MHz
10MHz
10Hz
100Hz
1kHz
10kHz
100kHz
1MHz
10MHz
–100
0.5
0.6
0.7
0.8
0.9
0.5
0.6
0.7
0.8
0.9
HEADROOM VOLTAGE (V)
HEADROOM VOLTAGE (V)
Figure 23. Power Supply Rejection Ratio (PSRR) vs. Headroom Voltage
at Various Frequencies, VOUT = 3.3 V, 1.2 A Load
Figure 26. Power Supply Rejection Ratio (PSRR) vs. Headroom Voltage
at Various Frequencies, VOUT = 1.8 V, 1.2 A Load
0
0
I
I
I
I
= 10mA
LOAD
LOAD
LOAD
LOAD
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–10
= 100mA
= 600mA
= 1200mA
C
C
C
C
= 1µF
BYP
BYP
BYP
BYP
–20
–30
–40
–50
–60
–70
–80
–90
–100
= 10µF
= 100µF
= 1000µF
1
10
100
1k
10k
100k
1M
10M
1
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 24. Power Supply Rejection Ratio (PSRR) vs. Frequency
at Various Loads, VOUT = 1.8 V, VIN = 2.6 V
Figure 27. Power Supply Rejection Ratio (PSRR) vs. Frequency
at Various CBYP Values, VOUT = 3.3 V, VIN = 4.0 V, 1.2 A Load
0
2.0
–10
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
10Hz TO 100kHz
100Hz TO 100kHz
–20
–30
–40
–50
–60
–70
–80
–90
–100
900mV
800mV
700mV
600mV
500mV
1
10
100
1k
10k
100k
1M
10M
10m
100m
1
10
FREQUENCY (Hz)
LOAD CURRENT (A)
Figure 25. Power Supply Rejection Ratio (PSRR) vs. Frequency
at Various Headroom Voltages, VOUT = 1.8 V, 1.2 A Load
Figure 28. RMS Output Noise vs. Load Current
Rev. A | Page 10 of 22
Data Sheet
ADP7156
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
1k
100
10
I
I
I
I
= 10mA
LOAD
LOAD
LOAD
LOAD
= 100mA
= 600mA
= 1200mA
10Hz TO 100kHz
100Hz TO 100kHz
1
0.1
1.0
1.5
2.0
2.5
3.0
3.5
10
100
1k
10k
100k
1M
10M
OUTPUT VOLTAGE (V)
FREQUENCY (Hz)
Figure 29. RMS Output Noise vs. Output Voltage
Figure 32. Output Noise Spectral Density vs. Frequency at Various Loads,
10 Hz to 10 MHz
1k
T
C
C
C
C
= 1µF
BYP
BYP
BYP
BYP
SLEW RATE = 2.5A/µs
= 10µF
= 100µF
= 1000µF
100
10
1
I
OUT
1
2
V
OUT
0.1
10
B
B
CH1 500mA
CH2 5.0mV
M4.00µs
21.10%
A CH1 700mA
W
W
100
1k
10k
100k
1M
10M
T
FREQUENCY (Hz)
Figure 33. Load Transient Response, ILOAD = 100 mA to 1.2 A,
Figure 30. Noise Spectral Density vs. Frequency at Various Values of CBYP
VOUT = 3.3 V, VIN = 4.0 V, Channel 1 = IOUT, Channel 2 = VOUT
100k
T
I
I
I
I
= 10mA
LOAD
LOAD
LOAD
LOAD
SLEW RATE = 1.5A/µs
= 100mA
= 600mA
= 1200mA
10k
1k
I
OUT
1
2
100
10
V
OUT
1
0.1
0.1
B
B
CH1 500mA
CH2 5mV
M4.00µs
A CH1 690mA
W
W
1
10
100
1k
10k
100k
1M
T
22.60%
FREQUENCY (Hz)
Figure 34. Load Transient Response, ILOAD = 100 mA to 1.2 A,
OUT = 3.3 V, VIN = 4.0 V, COUT = 22 µF, Channel 1 = IOUT, Channel 2 = VOUT
Figure 31. Output Noise Spectral Density vs. Frequency at Various Loads,
0.1 Hz to 1 MHz
V
Rev. A | Page 11 of 22
ADP7156
Data Sheet
T
T
SLEW RATE = 2.5A/µs
SLEW RATE = 1V/µs
V
V
IN
I
OUT
1
2
OUT
2
1
V
OUT
B
B
B
B
CH1 500mA
CH2 5mV
M4.00µs
A
CH1 740mA
CH1 1.0V
CH2 2.0mV
M10.0µs
21.80%
A
CH1 3.00V
W
W
W
W
T
21.30%
T
Figure 35. Load Transient Response, ILOAD = 100 mA to 1.2 A,
Figure 38. Line Transient Response, 1 V Input Step, ILOAD = 1.2 A,
OUT = 1.8 V, VIN = 2.5 V, Channel 1= VIN, Channel 2 = VOUT
VOUT = 1.8 V, VIN = 2.5 V, Channel 1 = IOUT, Channel 2 = VOUT
V
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
T
SLEW RATE = 2.4A/µs
I
OUT
1
2
V
OUT
V
EN
3.3V
2.5V
1.8V
B
B
CH1 500mA
CH2 5mV
M4.00µs
A CH1 740mA
20.70%
W
W
–2
–1
0
1
2
3
4
5
6
7
8
T
TIME (ms)
Figure 36. Load Transient Response, ILOAD = 100 mA to 1.2 A,
OUT = 1.8 V, VIN = 2.5 V, COUT = 22 µF, Channel 1 = IOUT, Channel 2 = VOUT
Figure 39. VOUT Start-Up Time After VEN Rising,
at Various Output Voltages, VIN = 5 V, CBYP = 1 μF
V
3.5
T
SLEW RATE = 1V/µs
3.0
2.5
2.0
1.5
1.0
0.5
0
V
V
1µF
4.7µF
10µF
IN
EN
V
OUT
2
1
B
B
CH1 1.0V
CH2 5mV
M10.0µs A CH1 4.34mA
21.10%
W
W
–2
0
2
4
6
8
10
12
14
16
18
20
T
TIME (ms)
Figure 37. Line Transient Response, 1 V Input Step, ILOAD = 1.2 A,
OUT = 3.3 V, VIN = 3.8 V, Channel 1 = VIN, Channel 2 = VOUT
Figure 40. VOUT Start-Up Time Behavior at Various Values of CBYP
,
V
VOUT = 3.3 V
Rev. A | Page 12 of 22
Data Sheet
ADP7156
THEORY OF OPERATION
The ADP7156 is an ultralow noise, high PSRR linear regulator
targeting radio frequency (RF) applications. The input voltage
range is 2.3 V to 5.5 V, and it can deliver up to 1.2 A of load
current. Typical shutdown current consumption is 0.2 µA at
room temperature.
feedback voltage is higher than the reference voltage, the gate of
the PMOS device is pulled higher, allowing less current to pass
and decreasing the output voltage.
By heavily filtering the reference voltage, the ADP7156 can
achieve 1.7 nV/√Hz typical output noise spectral density from
10 kHz to 1 MHz. Because the error amplifier is always in unity
gain, the output noise is independent of the output voltage.
Optimized for use with 10 µF ceramic capacitors, the ADP7156
provides excellent transient performance.
The ADP7156 uses the EN pin to enable and disable the VOUT pin
under normal operating conditions. When EN is high, VOUT
turns on, and when EN is low, VOUT turns off. For automatic
startup, tie EN to VIN.
VIN
VOUT
VOUT_SENSE
CURRENT-LIMIT,
THERMAL
INTERNAL
VREG
BYP
PROTECT
REGULATOR
GND (EPAD)
VIN
7V
OTA
REFERENCE
VREG
4V
REF
REF_SENSE
REF
REF_SENSE
4V
SHUTDOWN
EN
BYP
4V
VOUT
Figure 41. Simplified Internal Block Diagram
4V
4V 4V 4V 4V 4V 4V 7V
VOUT_SENSE
Internally, the ADP7156 consists of a reference, an error ampli-
fier, and a P-channel MOSFET pass transistor. The output current
is delivered via the PMOS pass device, which is controlled by
the error amplifier. The error amplifier compares the reference
voltage with the feedback voltage from the output and amplifies
the difference. If the feedback voltage is lower than the reference
voltage, the gate of the PMOS device is pulled lower, allowing
more current to pass and increasing the output voltage. If the
7V
EN
GND (EPAD)
Figure 42. Simplified ESD Protection Block Diagram
The ESD protection devices are shown in the block diagram as
Zener diodes (see Figure 42).
Rev. A | Page 13 of 22
ADP7156
Data Sheet
APPLICATIONS INFORMATION
Input and VREG Capacitor
ADIsimPOWER DESIGN TOOL
Connecting a 10 µF capacitor from VIN to ground reduces the
circuit sensitivity to PCB layout, especially when long input
traces or high source impedance are encountered.
The ADP7156 is supported by the ADIsimPower™ design tool
set. ADIsimPower is a collection of tools that produce complete
power designs optimized for a specific design goal. These tools
enable the user to generate a full schematic, bill of materials,
and calculate performance within minutes. ADIsimPower can
optimize designs for cost, area, efficiency, and device count,
taking into consideration the operating conditions and limita-
tions of the IC and all real external components. For more
information about, and to obtain the ADIsimPower design
tools, visit www.analog.com/ADIsimPower.
To maintain the best possible stability and PSRR performance,
connect a 1 µF or greater capacitor from VREG to ground.
REF Capacitor
The REF capacitor, CREF, is necessary to stabilize the reference
amplifier. Connect at 1 µF or greater capacitor between REF and
ground.
BYP Capacitor
CAPACITOR SELECTION
The BYP capacitor, CBYP, is necessary to filter the reference
buffer. A 1 µF capacitor is typically connected between BYP and
ground. Capacitors as small as 0.1 µF can be used; however, the
output noise voltage of the LDO increases as a result.
Multilayer ceramic capacitors (MLCCs) combine small size, low
ESR, low ESL, and a wide operating temperature range, making
them an ideal choice for bypass capacitors. They are not without
faults, however. Depending on the dielectric material, the
capacitance can vary dramatically with temperature, dc bias,
and ac signal level. Therefore, selecting the proper capacitor
results in the best circuit performance.
In addition, the BYP capacitor value can be increased to reduce
the noise below 1 kHz at the expense of increasing the start-up
time of the LDO regulator. Very large values of CBYP signifi-
cantly reduce the noise below 10 Hz. Tantalum capacitors are
recommended for capacitors larger than approximately 33 µF
because solid tantalum capacitors are less prone to microphonic
noise issues. A 1 μF ceramic capacitor in parallel with the larger
tantalum capacitor is recommended to ensure good noise
performance at higher frequencies.
Output Capacitor
The ADP7156 is designed for operation with ceramic capacitors
but functions with most commonly used capacitors when care is
taken with regard to the ESR value. The ESR of the output capaci-
tor affects the stability of the LDO control loop. A minimum of
10 µF capacitance with an ESR of 0.1 Ω or less is recommended
to ensure the stability of the ADP7156. Output capacitance also
affects transient response to changes in load current. Using a larger
value of output capacitance improves the transient response of the
ADP7156 to large changes in load current. Figure 43 shows the
transient responses for an output capacitance value of 10 µF.
2.0
1.8
1.6
10Hz TO 100kHz
1.4
1.2
1.0
T
SLEW RATE = 2.5A/µs
100Hz TO 100kHz
0.8
0.6
0.4
0.2
I
OUT
1
0
1
10
100
1000
V
OUT
C
(µF)
BYP
2
Figure 44. RMS Output Noise vs. Bypass Capacitance (CBYP
)
B
B
CH1 1.0V
CH2 2.0mV
M4.0µs
A CH1 700mV
W
W
T
21.10%
Figure 43. Output Transient Response, VOUT = 3.3 V, COUT = 10 µF,
Channel 1 = Load Current, Channel 2 = VOUT
Rev. A | Page 14 of 22
Data Sheet
ADP7156
1k
Use Equation 1 to determine the worst case capacitance
accounting for capacitor variation over temperature,
component tolerance, and voltage.
C
C
C
C
= 1µF
BYP
BYP
BYP
BYP
= 10µF
= 100µF
= 1000µF
100
10
1
C
EFF = CBIAS × (1 − tempco) × (1 − TOL)
(1)
where:
C
C
EFF is the worst case capacitance.
BIAS is the effective capacitance at the operating voltage.
tempco is the worst case capacitor temperature coefficient.
TOL is the worst case component tolerance.
In this example, the worst case temperature coefficient
(tempco) over −40°C to +85°C is assumed to be 15% for an X5R
dielectric. The tolerance of the capacitor (TOL) is assumed to
be 10%, and CBIAS is 9.72 µF at 5 V, as shown in Figure 46.
0.1
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
Figure 45. Noise Spectral Density vs. Frequency at Various CBYP Values
Substituting these values in Equation 1 yields
Capacitor Properties
CEFF = 9.72 µF × (1 − 0.15) × (1 − 0.1) = 7.44 µF
Any good quality ceramic capacitors can be used with the
ADP7156 if they meet the minimum capacitance and maximum
ESR requirements. Ceramic capacitors are manufactured with a
variety of dielectrics, each with different behavior over tempera-
ture and applied voltage. Capacitors must have a dielectric adequate
to ensure the minimum capacitance over the necessary tempera-
ture range and dc bias conditions. X5R or X7R dielectrics with
a voltage rating of 6.3 V to 50 V are recommended. However,
Y5V and Z5U dielectrics are not recommended because of their
poor temperature and dc bias characteristics.
Therefore, the capacitor chosen in this example meets the
minimum capacitance requirement of the LDO over
temperature and tolerance at the chosen output voltage.
To guarantee the performance of the ADP7156, it is imperative
that the effects of dc bias, temperature, and tolerances on the
behavior of the capacitors be evaluated for each application.
UNDERVOLTAGE LOCKOUT (UVLO)
The ADP7156 also incorporates an internal UVLO circuit to
disable the output voltage when the input voltage is less than the
minimum input voltage rating of the regulator. The upper and
lower thresholds are internally fixed with 200 mV (typical) of
hysteresis.
Figure 46 depicts the capacitance vs. dc bias voltage of a 1206,
10 µF, 10 V, X5R capacitor. The voltage stability of a capacitor is
strongly influenced by the capacitor size and voltage rating. In
general, a capacitor in a larger package or higher voltage rating
exhibits better stability. The temperature variation of the X5R
dielectric is ~ 15% over the −40°C to +85°C temperature range
and is not a function of package or voltage rating.
12
2.5
+125°C
+25°C
–40°C
2.0
1.5
1.0
0.5
0
10
8
6
4
1.9
2.0
2.1
(V)
2.2
2.3
V
IN
2
Figure 47. Typical UVLO Behavior at Various Temperatures, VOUT = 3.3 V
Figure 47 shows the typical behavior of the UVLO function.
This hysteresis prevents on/off oscillations that can occur when
caused by noise on the input voltage as it passes through the
threshold points.
0
0
2
4
6
8
10
DC BIAS VOLTAGE (V)
Figure 46. Capacitance vs. DC Bias Voltage
Rev. A | Page 15 of 22
ADP7156
Data Sheet
1.250
1.225
1.200
1.175
1.150
1.125
1.100
PROGRAMMABLE PRECISION ENABLE
The ADP7156 uses the EN pin to enable and disable the VOUT pin
under normal operating conditions. As shown in Figure 48, when
a rising voltage on EN crosses the upper threshold, nominally
1.22 V, VOUT turns on. When a falling voltage on EN crosses the
lower threshold, nominally 1.13 V, VOUT turns off. The hysteresis
of the EN threshold is typically 90 mV.
EN RISING
ADP7156 includes a discharge resistor on each VOUT, VREG,
REF, and BYP pin. These resistors turn on when the device is
disabled, and helps to discharge the associated capacitor very
quickly.
EN FALLING
3.5
2.5
3.0
3.5
4.0
4.5
5.0
5.5
–40°C
INPUT VOLTAGE (V)
–5°C
25°C
85°C
3.0
Figure 50. Typical EN Precision Threshold vs. Input Voltage (VIN)
125°C
2.5
2.0
1.5
1.0
0.5
0
The upper and lower thresholds are user-programmable and
can be set higher than the nominal 1.22 V threshold by using
two resistors. Determine the resistance values, REN1 and REN2
from
,
R
EN1 = REN2 × (VEN − 1.22 V)/1.22 V
where:
EN2 typically ranges from 10 kΩ to 100 kΩ.
EN is the desired turn-on voltage.
R
V
1.00
1.05
1.10
1.15
1.20
1.25
1.30
The hysteresis voltage increases by the factor
EN PIN VOLTAGE (V)
(REN1 + REN2)/REN2
Figure 48. Typical VOUT Response to EN Pin Operation
3.5
For the example shown in Figure 51, the EN threshold is 2.44 V
with a hysteresis of 200 mV.
3.0
2.5
2.0
1.5
1.0
0.5
0
V
V
EN
OUT
ADP7156
V
= 3.8V
V
= 3.3V
OUT
IN
VIN
VOUT
C
C
OUT
IN
10µF
10µF
VOUT_SENSE
R
EN1
ON
100kΩ
EN
REF
C
1µF
REF
OFF
R
EN2
BYP REF_SENSE
100kΩ
C
BYP
1µF
VREG
C
REG
1µF
GND (EPAD)
–2
–1
0
1
2
3
4
5
6
7
8
Figure 51. Typical EN Pin Voltage Divider
TIME (ms)
Figure 49. Typical VOUT Response to EN Pin Operation (VEN),
OUT = 3.3 V, VIN = 5 V, CBYP = 1 µF
Figure 51 shows the typical voltage divider configuration of the
EN pin. This configuration prevents on/off oscillations that can
occur due to noise on the EN pin as it passes through the
threshold points.
V
Rev. A | Page 16 of 22
Data Sheet
ADP7156
START-UP TIME
CURRENT-LIMIT AND THERMAL SHUTDOWN
The ADP7156 uses an internal soft start to limit the inrush current
when the output is enabled. The start-up time for a 3.3 V output is
approximately 1.2 ms from the time the EN active threshold is
crossed to when the output reaches 90% of its final value.
The ADP7156 is protected against damage due to excessive
power dissipation by current and thermal overload protection
circuits. The ADP7156 is designed to current limit when the
output load reaches 1.8 A (typical). When the output load
exceeds 1.8 A, the output voltage is reduced to maintain a
constant current limit.
The rise time in seconds of the output voltage (10% to 90%) is
approximately
When the ADP7156 junction temperature exceeds 150°C, the
thermal shutdown circuit turns off the output voltage, reducing
the output current to zero. Extreme junction temperature can be
the result of high current operation, poor circuit board design or
high ambient temperature. A 15°C hysteresis is included so that
the ADP7156 does not return to operation after thermal shutdown
until the on-chip temperature falls below 135°C. When the device
exits thermal shutdown, a soft start is initiated to reduce the
inrush current.
0.0012 × CBYP
where CBYP is measured in microfarads.
3.5
3.0
V
1µF
4.7µF
10µF
EN
2.5
2.0
1.5
1.0
0.5
0
Current-limit and thermal shutdown protections are intended
to protect the device against accidental overload conditions. For
example, a hard short from VOUT to ground or an extremely
long soft start timer usually causes thermal oscillations between
the current limit and thermal shutdown.
THERMAL CONSIDERATIONS
–2
0
2
4
6
8
10
12
14
16
18
20
TIME (ms)
In applications with a low input to output voltage differential,
the ADP7156 does not dissipate much heat. However, in applica-
tions with high ambient temperature and/or high input voltage,
the heat dissipated in the package may become large enough
that it causes the junction temperature of the die to exceed the
maximum junction temperature of 125°C.
Figure 52. Typical Start-Up Behavior with CBYP = 1 μF to 10 μF
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
The junction temperature of the die is the sum of the ambient
temperature of the environment and the temperature rise of the
package due to the power dissipation, as shown in Equation 2.
To guarantee reliable operation, the junction temperature of the
ADP7156 must not exceed 125°C. To ensure that the junction
temperature stays below this maximum value, the user must be
aware of the parameters that contribute to junction temperature
changes. These parameters include ambient temperature, power
dissipation in the power device, and thermal resistances between
the junction and ambient air (θJA). The θJA number is dependent
on the package assembly compounds that are used and the
amount of copper used to solder the exposed pad (ground) to
the PCB.
V
EN
10µF
47µF
100µF
–20
0
20
40
60
80
100
120
140
160
TIME (ms)
Figure 53. Typical Start-Up Behavior with CBYP = 10 μF to 100 μF
REF, BYP, AND VREG PINS
REF, BYP, and VREG generate voltages internally (VREF, VBYP
and VREG) that require external bypass capacitors for proper
,
operation. Do not, under any circumstances, connect any loads
to these pins, because doing so compromises the noise and
PSRR performance of the ADP7156. Using larger values of CBYP
CREF, and CREG is acceptable but can increase the start-up time,
as described in the Start-Up Time section.
,
Rev. A | Page 17 of 22
ADP7156
Data Sheet
140
120
100
80
Table 7 shows the typical θJA values of the 8-lead SOIC and
10-lead LFCSP packages for various PCB copper sizes. Table 8
shows the typical ΨJB values of the 8-lead SOIC and 10-lead
LFCSP.
Table 7. Typical θJA Values
θJA (°C/W)
60
Copper Size (mm2)
251
100
500
1000
6400
10-Lead LFCSP
8-Lead SOIC
123.8
90.4
130.2
93.0
65.8
55.6
44.1
2
6400mm
500mm
40
2
2
25mm
66.0
56.6
45.5
20
T
MAX
J
0
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0
TOTAL POWER DISSIPATION (W)
1 Device soldered to minimum size pin traces.
Figure 54. Junction Temperature vs. Total Power Dissipation for
the 10-Lead LFCSP, TA = 25°C
Table 8. Typical ΨJB Values
Package
140
120
100
80
ΨJB (°C/W)
29.1
30.1
10-Lead LFCSP
8-Lead SOIC
Calculate the junction temperature (TJ) of the ADP7156 from
the following equation:
TJ = TA + (PD × θJA)
(2)
where:
60
TA is the ambient temperature.
2
6400mm
500mm
2
PD is the power dissipation in the die, given by
2
25mm
40
T
MAX
PD = ((VIN − VOUT) × ILOAD) + (VIN × IGND
where:
VIN and VOUT are the input and output voltages, respectively.
)
(3)
J
20
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6
TOTAL POWER DISSIPATION (W)
I
I
LOAD is the load current.
GND is the ground current.
Figure 55. Junction Temperature vs. Total Power Dissipation for
the 10-Lead LFCSP, TA = 50°C
Power dissipation caused by ground current is quite small and
can be ignored. Therefore, the junction temperature equation
simplifies to the following:
130
125
120
115
110
105
100
TJ = TA + (((VIN − VOUT) × ILOAD) × θJA)
(4)
As shown in Equation 4, for a given ambient temperature, input
to output voltage differential, and continuous load current, a
minimum copper size requirement exists for the PCB to ensure
that the junction temperature does not rise above 125°C.
2
6400mm
500mm
95
90
85
80
2
The heat dissipation from the package can be improved by increas-
ing the amount of copper attached to the pins and exposed pad
of the ADP7156. Adding thermal planes underneath the package
also improves thermal performance. However, as shown in Table 7,
a point of diminishing returns is eventually reached, beyond which
an increase in the copper area does not yield significant reduc-
tion in the junction to ambient thermal resistance.
2
25mm
T
MAX
J
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
TOTAL POWER DISSIPATION (W)
Figure 56. Junction Temperature vs. Total Power Dissipation for
the 10-Lead LFCSP, TA = 85°C
Figure 54 to Figure 59 show junction temperature calculations
for various ambient temperatures, power dissipation, and areas
of PCB copper.
Rev. A | Page 18 of 22
Data Sheet
ADP7156
140
120
100
80
Thermal Characterization Parameter (ΨJB)
When the evaluation board temperature is known, use the
thermal characterization parameter, ΨJB, to estimate the junction
temperature rise (see Figure 60 and Figure 61). Calculate the
maximum junction temperature (TJ) from the evaluation board
temperature (TB) and power dissipation (PD) using the following
formula:
60
TJ = TB + (PD × ΨJB)
(5)
2
6400mm
500mm
40
2
The typical value of ΨJB is 29.1°C/W for the 10-lead LFCSP
package and 30.1°C/W for the 8-lead SOIC package.
2
25mm
20
T
MAX
J
140
0
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4
TOTAL POWER DISSIPATION (W)
120
100
80
Figure 57. Junction Temperature vs. Total Power Dissipation for
the 8-Lead SOIC, TA = 25°C
130
120
110
100
90
T
T
T
T
T
= 85°C
= 65°C
= 50°C
= 25°C
MAX
B
B
B
B
J
60
40
20
0
80
2
6400mm
500mm
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
TOTAL POWER DISSIPATION (W)
70
60
50
40
2
2
25mm
Figure 60. Junction Temperature vs. Total Power Dissipation for
the 10-Lead LFCSP
T
MAX
J
140
120
100
80
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
TOTAL POWER DISSIPATION (W)
Figure 58. Junction Temperature vs. Total Power Dissipation for
the 8-Lead SOIC, TA = 50°C
130
125
120
115
110
105
100
T
T
T
T
T
= 85°C
= 65°C
= 50°C
= 25°C
MAX
B
B
B
B
J
60
40
20
0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
2
6400mm
500mm
95
90
85
80
2
TOTAL POWER DISSIPATION (W)
2
25mm
Figure 61. Junction Temperature vs. Total Power Dissipation for
the 8-Lead SOIC
T
MAX
J
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
TOTAL POWER DISSIPATION (W)
Figure 59. Junction Temperature vs. Total Power Dissipation for
the 8-Lead SOIC, TA = 85°C
Rev. A | Page 19 of 22
ADP7156
Data Sheet
PRINTED CIRCUIT BOARD (PCB) LAYOUT CONSIDERATIONS
Place the input capacitor as close as possible between the
VIN pin and ground. Place the output capacitor as close as possible
between the VOUT pin and ground. Place the bypass capacitors
(CREG, CREF, and CBYP) for VREG, VREF, and VBYP close to the respec-
tive pins (VREG, REF, and BYP) and ground. The use of a 0805,
0603, or 0402 size capacitor achieves the smallest possible
footprint solution on boards where area is limited. Maximize
the amount of ground metal for the exposed pad, and use as
many vias as possible on the component side to improve thermal
dissipation.
Figure 63. Sample 8-Lead SOIC PCB Layout
Figure 62. Sample 10-Lead LFCSP PCB Layout
Rev. A | Page 20 of 22
Data Sheet
ADP7156
OUTLINE DIMENSIONS
2.48
2.38
2.23
3.10
3.00 SQ
2.90
0.50 BSC
10
6
PIN 1 INDEX
EXPOSED
PAD
1.74
1.64
1.49
AREA
0.50
0.40
0.30
0.20 MIN
1
5
BOTTOM VIEW
TOP VIEW
PIN 1
INDICATOR
(R 0.15)
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.80
0.75
0.70
0.05 MAX
0.02 NOM
COPLANARITY
0.08
SECTION OF THIS DATA SHEET.
SEATING
PLANE
0.30
0.25
0.20
0.20 REF
Figure 64. 10-Lead Lead Frame Chip Scale Package [LFCSP]
3 mm × 3 mm Body and 0.75 mm Package Height
(CP-10-9)
Dimensions shown in millimeters
5.00
4.90
4.80
2.29
0.356
5
4
6.20
6.00
5.80
8
1
4.00
3.90
3.80
2.29
0.457
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
BOTTOM VIEW
45°
1.27 BSC
3.81 REF
TOP VIEW
SECTION OF THIS DATA SHEET.
1.65
1.25
1.75
1.35
0.50
0.25
0.25
0.17
0.10 MAX
0.05 NOM
SEATING
PLANE
8°
0°
0.51
0.31
1.04 REF
COPLANARITY
0.10
1.27
0.40
COMPLIANT TO JEDEC STANDARDS MS-012-AA
Figure 65. 8-Lead Standard Small Outline Package, with Exposed Pad [SOIC_N_EP]
Narrow Body
(RD-8-1)
Dimensions shown in millimeters
Rev. A | Page 21 of 22
ADP7156
Data Sheet
ORDERING GUIDE
Model1, 2
Temperature Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Output Voltage (V)
Package Description
10-Lead LFCSP
10-Lead LFCSP
10-Lead LFCSP
10-Lead LFCSP
10-Lead LFCSP
10-Lead LFCSP
10-Lead LFCSP
8-Lead SOIC_N_EP
8-Lead SOIC_N_EP
8-Lead SOIC_N_EP
8-Lead SOIC_N_EP
8-Lead SOIC_N_EP
8-Lead SOIC_N_EP
8-Lead SOIC_N_EP
Evaluation Board
Package Option
Branding
LST
LSU
LTQ
LSV
LSW
LSY
LSZ
ADP7156ACPZ-1.2-R7
ADP7156ACPZ-1.8-R7
ADP7156ACPZ-2.0-R7
ADP7156ACPZ-2.5-R7
ADP7156ACPZ-2.8-R7
ADP7156ACPZ-3.0-R7
ADP7156ACPZ-3.3-R7
ADP7156ARDZ-1.2-R7
ADP7156ARDZ-1.8-R7
ADP7156ARDZ-2.0-R7
ADP7156ARDZ-2.5-R7
ADP7156ARDZ-2.8-R7
ADP7156ARDZ-3.0-R7
ADP7156ARDZ-3.3-R7
ADP7156CP-3.3EVALZ
1.2
1.8
2.0
2.5
2.8
3.0
3.3
1.2
1.8
2.0
2.5
2.8
3.0
3.3
CP-10-9
CP-10-9
CP-10-9
CP-10-9
CP-10-9
CP-10-9
CP-10-9
RD-8-1
RD-8-1
RD-8-1
RD-8-1
RD-8-1
RD-8-1
RD-8-1
1 Z = RoHS Compliant Part.
2 To order a device with voltage options of 1.3 V, 1.5 V, 1.6 V, 2.2 V, 2.6 V, 2.7 V, 2.9 V, 3.1 V, and 3.2 V, contact your local Analog Devices, Inc., sales or distribution
representative.
©2016 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D12937-0-5/16(A)
Rev. A | Page 22 of 22
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