ADN4661BRZ-REEL71 [ADI]
Single, 3 V, CMOS, LVDS, High Speed Differential Driver; 单， 3 V ， CMOS ， LVDS ，高速差分驱动器
| 型号： | ADN4661BRZ-REEL71 |
| 厂家： | 
ADI |
| 描述： | Single, 3 V, CMOS, LVDS, High Speed Differential Driver |
| 文件： | 总12页 (文件大小：251K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Single, 3 V, CMOS, LVDS,
High Speed Differential Driver
ADN4661
FUNCTIONAL BLOCK DIAGRAM
FEATURES
V
CC
15 kV ESD protection on output pins
600 Mbps (300 MHz) switching rates
Flow-through pinout simplifies PCB layout
300 ps typical differential skew
700 ps maximum differential skew
1.5 ns maximum propagation delay
3.3 V power supply
ADN4661
D
D
OUT+
D
IN
OUT–
NC GND NC NC
NC = NO CONNECT
355 mV differential signaling
Low power dissipation: 23 mW typical
Interoperable with existing 5 V LVDS receivers
Conforms to TIA/EIA-644 LVDS standards
Industrial operating temperature range (−40°C to +85°C)
Available in surface-mount (SOIC) package
Figure 1.
APPLICATIONS
Backplane data transmission
Cable data transmission
Clock distribution
GENERAL DESCRIPTION
The ADN4661 is a single, CMOS, low voltage differential
signaling (LVDS) line driver offering data rates of over
600 Mbps (300 MHz) and ultra-low power consumption.
It features a flow-through pinout for easy PCB layout and
separation of input and output signals.
The ADN4661 and a companion LVDS receiver offer a new
solution to high speed point-to-point data transmission, and a
low power alternative to emitter-coupled logic (ECL) or positive
emitter-coupled logic (PECL).
The device accepts low voltage TTL/CMOS logic signals and
converts them to a differential current output of typically
3.1 mA for driving a transmission medium such as a twisted-
pair cable. The transmitted signal develops a differential voltage
of typically 3ꢀꢀ mV across a termination resistor at the receiv-
ing end, and this is converted back to a TTL/CMOS logic level
by a line receiver.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2008 Analog Devices, Inc. All rights reserved.
ADN4661
TABLE OF CONTENTS
Features .............................................................................................. 1
ESD Caution...................................................................................ꢀ
Pin Configuration and Function Descriptions..............................6
Typical Performance Characteristics ..............................................7
Theory of Operation ...................................................................... 10
Applications Information.......................................................... 10
Outline Dimensions....................................................................... 11
Ordering Guide .......................................................................... 11
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
AC Characteristics........................................................................ 4
Absolute Maximum Ratings............................................................ ꢀ
REVISION HISTORY
12/08—Revision 0: Initial Version
Rev. 0 | Page 2 of 12
ADN4661
SPECIFICATIONS
VCC = 3 V to 3.6 V; RL = 100 Ω; CL = 1ꢀ pF to GND; all specifications TMIN to TMAX, unless otherwise noted.
Table 1.
Parameter1, 2
Symbol Min
Typ Max
Unit
Test Conditions
LVDS OUTPUTS (DOUT+, DOUT−
)
Differential Output Voltage
Change in Magnitude of VOD for Complementary
Output States
VOD
ΔVOD
250
355 450
mV
|mV|
See Figure 2 and Figure 4
See Figure 2 and Figure 4
1
35
Offset Voltage
Change in Magnitude of VOS for Complementary ΔVOS
Output States
VOS
1.125 1.2
3
1.375
25
V
|mV|
See Figure 2 and Figure 4
See Figure 2 and Figure 4
Output High Voltage
Output Low Voltage
VOH
VOL
1.4
1.1
1.6
V
V
See Figure 2 and Figure 4
See Figure 2 and Figure 4
0.90
INPUTS (DIN, VCC
)
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
VIH
VIL
IIH
IIL
VCL
2.0
VCC
0.8
+10
+10
V
V
μA
μA
V
GND
−10
−10
−1.5
2
1
−0.6
VIN = 3.3 V or 2.4 V
VIN = GND or 0.5 V
ICL = −18 mA
Input Clamp Voltage
LVDS OUTPUT PROTECTION (DOUT+, DOUT−
)
Output Short-Circuit Current3
IOS
−5.7 −8.0
mA
μA
DIN = VCC, DOUT+ = 0 V or DIN = GND, DOUT− = 0 V
VOUT = VCC or GND, VCC = 0 V
LVDS OUTPUT LEAKAGE (DOUT+, DOUT−
)
Power-Off Leakage
IOFF
−10
1
+10
POWER SUPPLY
Supply Current, Unloaded
Supply Current, Loaded
ESD PROTECTION
ICC
ICCL
4.0
7
8.0
10
mA
mA
No load, DIN = VCC or GND
DIN = VCC or GND
DOUT+, DOUT− Pins
All Pins Except DOUT+, DOUT−
15
4
kV
kV
Human body model
Human body model
1 Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground except VOD, ΔVOD, and ΔVOS
2 The ADN4661 is a current mode device and functions within data sheet specifications only when a resistive load is applied to the driver outputs. Typical range is
90 Ω to 110 Ω.
.
3 Output short-circuit current (IOS) is specified as magnitude only; minus sign indicates direction only.
Rev. 0 | Page 3 of 12
ADN4661
AC CHARACTERISTICS
1
VCC = 3 V to 3.6 V; RL = 100 Ω; CL = 1ꢀ pF to GND; all specifications TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter2
Symbol
tPHLD
tPLHD
tSKD1
tSKD3
tSKD4
tTLH
Min
0.3
0.3
0
0
0
Typ
0.8
1.1
0.3
Max
1.5
1.5
0.7
1.0
1.2
1.0
1.0
Unit
ns
ns
ns
ns
Ns
ns
ns
MHz
Conditions/Comments3, 4
See Figure 3 and Figure 4
See Figure 3 and Figure 4
See Figure 3 and Figure 4
See Figure 3 and Figure 4
See Figure 3 and Figure 4
See Figure 3 and Figure 4
See Figure 3 and Figure 4
See Figure 3
Differential Propagation Delay High to Low
Differential Propagation Delay Low to High
Differential Pulse Skew |tPHLD − tPLHD
Differential Part-to-Part Skew6
Differential Part-to-Part Skew7
Rise Time
5
|
0.2
0.2
0.5
0.5
350
Fall Time
Maximum Operating Frequency8
tTHL
fMAX
1 CL includes probe and jig capacitance.
2 AC parameters are guaranteed by design and characterization.
3 Generator waveform for all tests, unless otherwise specified: f = 50 MHz, ZO = 50 Ω, tTLH ≤ 1 ns, and tTHL ≤ 1 ns.
4 All input voltages are for one channel unless otherwise specified. Other inputs are set to GND.
5 tSKD1 = |tPHLD − tPLHD| is the magnitude difference in differential propagation delay time between the positive going edge and the negative going edge of the
same channel.
6 tSKD3, differential part-to-part skew, is defined as the difference between the minimum and maximum specified differential propagation delays. This specification
applies to devices at the same VCC and within 5°C of each other within the operating temperature range.
7 tSKD4, differential part-to-part skew, is the differential channel-to-channel skew of any event between devices. This specification applies to devices over recommended
operating temperatures and voltage ranges, and across process distribution. tSKD4 is defined as |maximum − minimum| differential propagation delay.
8 fMAX generator input conditions: tTLH = tTHL < 1 ns (0% to 100%), 50% duty cycle, 0 V to 3 V. Output criteria: duty cycle = 45% to 55%, VOD > 250 mV, all channels
switching.
Test Circuits and Timing Diagrams
D
OUT+
V
CC
V
CC
R /2
L
D
IN
V
V
OD
V
V
OS
R /2
L
D
OUT–
Figure 2. Test Circuit for Driver VOD and VOS
V
CC
D
D
OUT+
C
L
L
D
IN
SIGNAL
GENERATOR
OUT–
50Ω
C
NOTES
1. C INCLUDES PROBE AND JIG CAPACITANCE.
L
Figure 3. Test Circuit for Driver Propagation Delay, Transition Time, and Maximum Operating Frequency
3V
D
1.5V
IN
0V
tPLHD
tPHLD
V
OD
D
V
OUT–
OH
0V (DIFFERENTIAL)
D
OUT+
V
OL
80%
0V
V
DIFF
20%
V
= D – D
OUT+ OUT–
DIFF
tTLH
tTHL
Figure 4. Driver Propagation Delay and Transition Time Waveforms
Rev. 0 | Page 4 of 12
ADN4661
ABSOLUTE MAXIMUM RATINGS
TA = 2ꢀ°C, unless otherwise noted. All voltages are relative to
their respective ground.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Table 3.
Parameter
Rating
VCC to GND
−0.3 V to +4 V
−0.3V to VCC + 0.3 V
−0.3V to VCC + 0.3 V
Continuous
Input Voltage (DIN) to GND
Output Voltage (DOUT+, DOUT−) to GND
Short-Circuit Duration (DOUT+, DOUT−) to GND
Operating Temperature Range
Industrial
Storage Temperature Range
Junction Temperature (TJ max)
Power Dissipation
ESD CAUTION
−40°C to +85°C
−65°C to +150°C
150°C
(TJ max − TA)/θJA
SOIC Package
θJA Thermal Impedance
Reflow Soldering Peak Temperature
Pb-Free
149.5°C/W
260°C 5°C
Rev. 0 | Page 5 of 12
ADN4661
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
V
1
2
3
4
8
7
6
5
D
D
CC
OUT–
ADN4661
D
IN
OUT+
NC
NC
NC
TOP VIEW
(Not to Scale)
GND
NC = NO CONNECT
Figure 5. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. Mnemonic Description
1
VCC
Power Supply Input. The part can be operated from 3.0 V to 3.6 V, and the supply should be decoupled with a
10 μF solid tantalum capacitor in parallel with a 0.1 μF capacitor to GND.
2
3
4
5
6
7
8
DIN
NC
GND
NC
NC
Driver Logic Input.
No Connect. This pin should be left unconnected.
Ground. Reference point for all circuitry on the part.
No Connect. This pin should be left unconnected.
No Connect. This pin should be left unconnected.
Noninverting Output Current Driver. When DIN is high, current flows out of DOUT+. When DIN is low, current flows into DOUT+
Inverting Output Current Driver. When DIN is high, current flows into DOUT−. When DIN is low, current flows out of DOUT−
DOUT+
DOUT−
.
.
Rev. 0 | Page 6 of 12
ADN4661
TYPICAL PERFORMANCE CHARACTERISTICS
1.415
325.0
324.8
324.6
324.4
324.2
324.0
T
R
= 25°C
= 100Ω
T
R
= 25°C
= 100Ω
A
A
L
L
1.414
1.413
1.412
3.0
3.1
3.2
3.3
3.4
3.5
3.6
3.0
3.1
3.2
3.3
3.4
3.5
3.6
POWER SUPPLY VOLTAGE, V (V)
POWER SUPPLY VOLTAGE, V (V)
CC
CC
Figure 6. Output High Voltage vs. Power Supply Voltage
Figure 9. Differential Output Voltage vs. Power Supply Voltage
1.090
1.089
1.088
1.087
500
T
R
= 25°C
= 100Ω
T
V
= 25°C
= 3.3V
A
A
L
CC
450
400
350
300
250
3.0
3.1
3.2
3.3
3.4
3.5
3.6
90
100
110
120
130
140
150
POWER SUPPLY VOLTAGE, V (V)
LOAD RESISTOR, R (Ω)
CC
L
Figure 7. Output Low Voltage vs. Power Supply Voltage
Figure 10. Differential Output Voltage vs. Load Resistor
–3.9
–4.0
–4.1
–4.2
1.252
1.251
T
R
= 25°C
= 100Ω
A
T
= 25°C
A
L
V
= GND OR V
IN
CC
= 0V
V
OUT
1.250
1.249
3.0
3.1
3.2
3.3
3.4
3.5
3.6
3.0
3.1
3.2
3.3
3.4
3.5
3.6
POWER SUPPLY VOLTAGE, V (V)
POWER SUPPLY VOLTAGE, V (V)
CC
CC
Figure 8. Output Short-Circuit Current vs. Power Supply Voltage
Figure 11. Offset Voltage vs. Power Supply Voltage
Rev. 0 | Page 7 of 12
ADN4661
1200
1100
1000
900
T
= 25°C
A
T
V
V
C
R
= 25°C
A
19
17
15
13
11
9
f = 1MHz
C
R
= 3.3V
CC
= 15pF
= 100Ω
L
L
= 0V TO 3V
= 15pF
IN
L
L
= 100Ω
t
PHLD
t
PLHD
7
5
3.0
3.1
3.2
3.3
3.4
3.5
3.6
0.01
0.1
1
10
100
1k
POWER SUPPLY VOLTAGE, V (V)
SWITCHING FREQUENCY (MHz)
CC
Figure 12. Power Supply Current vs. Switching Frequency
Figure 15. Differential Propagation Delay vs. Power Supply Voltage
10.0
9.5
9.0
8.5
1200
V
= 3.3V
CC
T
= 25°C
A
f = 1MHz
C
R
f = 1MHz
V
C
R
= 15pF
= 100Ω
L
L
= 0V TO 3V
= 15pF
IN
L
L
t
PLHD
= 100Ω
1100
1000
900
t
PHLD
8.0
7.5
7.0
6.5
3.0
–40
–20
0
20
40
60
80
100
3.3
POWER SUPPLY VOLTAGE, V (V)
3.6
AMBIENT TEMPERATURE, T (°C)
CC
A
Figure 13. Power Supply Current vs. Power Supply Voltage
Figure 16. Differential Propagation Delay vs. Ambient Temperature
9
8
100
T
= 25°C
V
= 3.3V
A
CC
f = 1MHz
f = 1MHz
C
R
= 15pF
= 100Ω
L
L
V
= 0V
= 15pF
= 100Ω
IN
80
60
40
20
C
R
L
L
7
6
0
3.0
5
–40
3.1
3.2
3.3
3.4
3.5
3.6
–15
10
35
60
85
POWER SUPPLY VOLTAGE, V (V)
AMBIENT TEMPERATURE, T (°C)
CC
A
Figure 14. Power Supply Current vs. Ambient Temperature
Figure 17. Differential Skew vs. Power Supply Voltage
Rev. 0 | Page 8 of 12
ADN4661
50
40
30
20
10
400
380
360
340
320
V
= 3.3V
V
= 3.3V
CC
f = 1MHz
CC
f = 1MHz
C
R
= 15pF
= 100Ω
C
R
= 15pF
= 100Ω
L
L
L
L
t
TLH
t
THL
0
–40
–20
0
20
40
60
80
100
–40
–20
0
20
40
60
80
100
AMBIENT TEMPERATURE, T (°C)
AMBIENT TEMPERATURE, T (°C)
A
A
Figure 18. Differential Skew vs. Ambient Temperature
Figure 20. Transition Time vs. Ambient Temperature
400
380
T
= 25°C
A
f = 1MHz
C
R
= 15pF
= 100Ω
L
L
t
TLH
360
340
320
t
THL
3.0
3.1
3.2
3.3
3.4
3.5
3.6
POWER SUPPLY VOLTAGE, V (V)
CC
Figure 19. Transition Time vs. Power Supply Voltage
Rev. 0 | Page 9 of 12
ADN4661
THEORY OF OPERATION
The ADN4661 is a single line driver for low voltage differential
signaling. It takes a single-ended 3 V logic signal and converts
it to a differential current output. The data can then be trans-
mitted for considerable distances, over media such as a twisted-
pair cable or PCB backplane, to an LVDS receiver, where it
develops a voltage across a terminating resistor, RT. This resistor
is chosen to match the characteristic impedance of the medium,
typically around 100 ꢁ. The differential voltage is detected by
the receiver and converted back into a single-ended logic signal.
A current-mode device simply reverses a constant current
between its two outputs, with no significant overlap currents.
This is similar to emitter-coupled logic (ECL) and positive
emitter-coupled logic (PECL), but without the high quiescent
current of ECL and PECL.
APPLICATIONS INFORMATION
Figure 21 shows a typical application for point-to-point data
transmission using the ADN4661 as the driver and the LVDS
receiver.
When DIN is high (Logic 1), current flows out of the DOUT+ pin
(current source) through RT and back to the DOUT− pin (current
sink). At the receiver, this current develops a positive differential
voltage across RT (with respect to the inverting input) and results
in a Logic 1 at the receiver output. When DIN is low (Logic 0),
+3.3V
10µF
TANTALUM
+3.3V
10µF
TANTALUM
+
+
0.1µF
0.1µF
V
V
CC
CC
ADN4661
LVDS RECEIVER
D
D
D
OUT+
IN+
D
OUT+ sinks current and DOUT− sources current. A negative differen-
R
100Ω
T
tial voltage across RT results in a Logic 0 at the receiver output.
D
D
OUT
IN
D
OUT–
IN–
The output drive current is between 2.ꢀ mA and 4.ꢀ mA
(typically 3.ꢀꢀ mA), developing between 2ꢀ0 mV and 4ꢀ0 mV
across a 100 ꢁ termination resistor. The received voltage is centered
around the receiver offset of 1.2 V. Therefore, the noninverting
receiver input for Logic 1 is typically (1.2 V + [3ꢀꢀ mV/2]) =
1.377 V, and the inverting receiver input is (1.2 V − [3ꢀꢀ mV/2])
= 1.023 V. For Logic 0, the inverting and noninverting output
voltages are reversed. Note that because the differential voltage
reverses polarity, the peak-to-peak voltage swing across RT is
twice the differential voltage.
GND
GND
Figure 21. Typical Application Circuit
Current-mode drivers offer considerable advantages over
voltage mode drivers such as RS-422 drivers. The operating
current remains fairly constant with increased switching
frequency, whereas the current of voltage mode drivers
increases exponentially in most cases. This is caused by the
overlap as internal gates switch between high and low, which
causes currents to flow from the device power supply to ground.
Rev. 0 | Page 10 of 12
ADN4661
OUTLINE DIMENSIONS
5.00 (0.1968)
4.80 (0.1890)
8
1
5
4
6.20 (0.2441)
5.80 (0.2284)
4.00 (0.1574)
3.80 (0.1497)
0.50 (0.0196)
0.25 (0.0099)
1.27 (0.0500)
BSC
45°
1.75 (0.0688)
1.35 (0.0532)
0.25 (0.0098)
0.10 (0.0040)
8°
0°
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
1.27 (0.0500)
0.40 (0.0157)
0.25 (0.0098)
0.17 (0.0067)
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MS-012-AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 22. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-8)
Dimensions shown in millimeters and (inches)
ORDERING GUIDE
Model
Temperature Range Package Description
Package Option
ADN4661BRZ1
−40°C to +85°C
−40°C to +85°C
8-Lead Standard Small Outline Package [SOIC-N]
8-Lead Standard Small Outline Package [SOIC-N]
R-8
R-8
ADN4661BRZ-REEL71
1 Z = RoHS Compliant Part.
Rev. 0 | Page 11 of 12
ADN4661
NOTES
©2008 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07876-0-12/08(0)
Rev. 0 | Page 12 of 12
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