ADP2386ACPZN-R7 [ADI]
20 V, 6 A, Synchronous Step-Down DC-to-DC Regulator; 20 V ， 6 A，同步降压型的DC- DC稳压器
| 型号： | ADP2386ACPZN-R7 |
| 厂家： | 
ADI |
| 描述： | 20 V, 6 A, Synchronous Step-Down DC-to-DC Regulator |
| 文件： | 总24页 (文件大小：711K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
20 V, 6 A, Synchronous Step-Down
DC-to-DC Regulator
Data Sheet
ADP2386
FEATURES
TYPICAL APPLICATIONS CIRCUIT
Input voltage: 4.5 V to 20 V
Integrated MOSFET: 44 mΩ/11 mΩ
Reference voltage: 0.6 V 1%
ADP2386
BST
V
PVIN
EN
IN
C
BST
L
C
IN
SW
V
OUT
Continuous output current: 6 A
C
OUT
PGOOD
SYNC
RT
R
TOP
Programmable switching frequency: 200 kHz to 1.4 MHz
Synchronizes to external clock: 200 kHz to 1.4 MHz
180° out of phase clock synchronization
Precision enable and power good
FB
COMP
SS
R
T
R
C
R
VREG
BOT
C
C
VREG
GND PGND
C
C
External compensation
SS
Internal soft start with external adjustable option
Startup into a precharged output
Supported by ADIsimPower design tool
Figure 1.
APPLICATIONS
100
95
90
85
80
75
70
65
60
55
50
Communications infrastructure
Networking and servers
Industrial and instrumentation
Healthcare and medical
Intermediate power rail conversion
DC-to-dc point-of-load applications
V
V
V
= 5.0V
= 3.3V
= 1.2V
OUT
OUT
OUT
0
1
2
3
4
5
6
OUTPUT CURRENT (A)
Figure 2. Efficiency vs. Output Current, VIN = 12 V, fSW = 300 kHz
GENERAL DESCRIPTION
The ADP2386 is a synchronous step-down, dc-to-dc regulator with
an integrated 44 mΩ, high-side power MOSFET and an 11 mΩ,
synchronous rectifier MOSFET to provide a high efficiency
solution in a compact 4 mm × 4 mm LFCSP package. This device
uses a peak current mode, constant frequency pulse-width
modulation (PWM) control scheme for excellent stability and
transient response. The switching frequency of the ADP2386
can be programmed from 200 kHz to 1.4 MHz. To minimize
system noise, the synchronization function allows the switching
frequency to be synchronized to an external clock.
and delivers up to 6 A of continuous current. Each IC draws less
than 110 μA current from the input source when it is disabled.
This regulator targets high performance applications that require
high efficiency and design flexibility. External compensation and an
adjustable soft start function provide design flexibility. The power-
good output and precision enable input provide simple and reliable
power sequencing.
Other key features include undervoltage lockout (UVLO),
overvoltage protection (OVP), overcurrent protection (OCP),
short-circuit protection (SCP), and thermal shutdown (TSD).
The ADP2386 requires minimal external components and
operates from an input voltage of 4.5 V to 20 V. The output
voltage can be adjusted from 0.6 V to 90% of the input voltage
The ADP2386 operates over the −40°C to +125°C junction
temperature range and is available in a 24-lead, 4 mm × 4 mm
LFCSP package.
Rev. A
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ADP2386
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Thermal Shutdown .................................................................... 14
Applications Information .............................................................. 15
Input Capacitor Selection.......................................................... 15
Output Voltage Setting .............................................................. 15
Voltage Conversion Limitations............................................... 15
Inductor Selection ...................................................................... 15
Output Capacitor Selection....................................................... 16
Programming the Input Voltage UVLO.................................. 17
Compensation Design ............................................................... 17
ADIsimPower Design Tool ....................................................... 17
Design Example.............................................................................. 18
Output Voltage Setting .............................................................. 18
Frequency Setting....................................................................... 18
Inductor Selection ...................................................................... 18
Output Capacitor Selection....................................................... 19
Compensation Components..................................................... 19
Soft Start Time Program ........................................................... 19
Input Capacitor Selection.......................................................... 19
Recommended External Components .................................... 20
Circuit Board Layout Recommendations ................................... 21
Typical Applications Circuits........................................................ 22
Outline Dimensions....................................................................... 23
Ordering Guide .......................................................................... 23
Applications....................................................................................... 1
Typical Applications Circuit............................................................ 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 5
Thermal Resistance ...................................................................... 5
ESD Caution.................................................................................. 5
Pin Configuration and Function Descriptions............................. 6
Typical Performance Characteristics ............................................. 7
Functional Block Diagram ............................................................ 11
Theory of Operation ...................................................................... 12
Control Scheme .......................................................................... 12
Precision Enable/Shutdown ...................................................... 12
Internal Regulator (VREG)....................................................... 12
Bootstrap Circuitry .................................................................... 12
Oscillator ..................................................................................... 12
Synchronization.......................................................................... 12
Soft Start ...................................................................................... 13
Power Good................................................................................. 13
Peak Current-Limit and Short-Circuit Protection................. 13
Overvoltage Protection (OVP)................................................. 14
Undervoltage Lockout (UVLO) ............................................... 14
REVISION HISTORY
4/13—Rev. 0 to Rev. A
Changes to Figure 4 and Figure 7....................................................7
Updated Outline Dimensions........................................................23
Changes to Ordering Guide ...........................................................23
11/12—Revision 0: Initial Version
Rev. A | Page 2 of 24
Data Sheet
ADP2386
SPECIFICATIONS
VPVIN = 12 V, T J = −40°C to +125°C for minimum/maximum specifications, and TA = 25°C for typical specifications, unless otherwise noted.
Table 1.
Parameter
Symbol
Test Conditions/Comments
Min
Typ
Max
Unit
PVIN
PVIN Voltage Range
Quiescent Current
Shutdown Current
PVIN Undervoltage Lockout Threshold
VPVIN
IQ
ISHDN
UVLO
4.5
2.4
50
20
V
No switching
EN = GND
PVIN rising
PVIN falling
2.9
80
4.3
3.8
3.6
110
4.4
mA
µA
V
3.6
V
FB
FB Regulation Voltage
VFB
IFB
−40°C < TJ < 85°C
−40°C < TJ < 125°C
0.594
0.591
0.6
0.6
0.01
0.606
0.609
0.1
V
V
µA
FB Bias Current
ERROR AMPLIFIER (EA)
Transconductance
EA Source Current
gm
ISOURCE
ISINK
380
45
45
480
60
60
580
75
75
µS
µA
µA
EA Sink Current
INTERNAL REGULATOR (VREG)
VREG Voltage
Dropout Voltage
VVREG
VPVIN = 12 V, IVREG = 50 mA
VPVIN = 12 V, IVREG = 50 mA
7.6
62
8
340
100
8.4
V
mV
mA
Regulator Current Limit
137
SW
High-Side On Resistance1
Low-Side On Resistance1
High-Side Peak Current Limit
Low-Side Negative Current-Limit2
SW Minimum On Time
SW Minimum Off Time
BST
VBST − VSW = 5 V
VVREG = 8 V
44
11
9.6
2.5
125
200
70
18
11.5
mΩ
mΩ
A
A
ns
ns
7.2
tMIN_ON
tMIN_OFF
165
260
Bootstrap Voltage
VBOOT
4.6
5
5.4
V
OSCILLATOR (RT PIN)
Switching Frequency
Switching Frequency Range
SYNC
fSW
fSW
RT = 100 kΩ
540
200
600
660
1400
kHz
kHz
Synchronization Range
SYNC Minimum Pulse Width
SYNC Positive Pulse Maximum Duty Cycle
SYNC Input High Voltage
SYNC Input Low Voltage
SS
200
100
1400
50
kHz
ns
%
V
V
DMAX_SYNC
1.3
0.4
Internal Soft Start
SS Pin Pull-Up Current
1600
3.2
Clock cycles
µA
ISS_UP
2.3
3.9
Rev. A | Page 3 of 24
ADP2386
Data Sheet
Parameter
Symbol
Test Conditions/Comments
Min
Typ
Max
Unit
PGOOD
Power-Good Range
FB Rising Threshold
FB Rising Hysteresis
FB Falling Threshold
FB Falling Hysteresis
Power-Good Deglitch Time
PGOOD from low to high
PGOOD from high to low
PGOOD from low to high
PGOOD from high to low
PGOOD from low to high
PGOOD from high to low
VPGOOD = 5 V
95
5
%
%
%
%
105
11.7
1024
16
0.01
125
Clock cycles
Clock cycles
µA
Power-Good Leakage Current
Power-Good Output Low Voltage
EN
0.1
190
IPGOOD = 1 mA
mV
EN Rising Threshold
EN Falling Threshold
EN Source Current
1.17
1.07
5
1.25
V
V
µA
µA
0.97
EN voltage below falling threshold
EN voltage above rising threshold
1
THERMAL SHUTDOWN
Thermal Shutdown Threshold
Thermal Shutdown Hysteresis
150
25
°C
°C
1 Pin-to-pin measurement.
2 Guaranteed by design.
Rev. A | Page 4 of 24
Data Sheet
ADP2386
ABSOLUTE MAXIMUM RATINGS
Table 2.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a 4-layer, JEDEC standard circuit board for surface-
mount packages.
Parameter
Rating
PVIN, EN, PGOOD
SW
−0.3 V to +22 V
−1 V to +22 V
BST
VSW + 6 V
Table 3. Thermal Resistance
Package Type
FB, SS, CO M P, SYNC, RT
VREG
PGND to GND
Operating Junction Temperature Range
Storage Temperature Range
Soldering Conditions
−0.3 V to +6 V
−0.3 V to +12 V
−0.3 V to +0.3 V
−40°C to +125°C
−65°C to +150°C
JEDEC J-STD-020
θJA
Unit
24-Lead LFCSP_WQ
42.6
°C/W
ESD CAUTION
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rev. A | Page 5 of 24
ADP2386
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
18
17
16
15
14
13
COMP
FB
PVIN
PVIN
PVIN
BST
SW
25
GND
VREG
GND 4
26
SW
5
6
SW
SW
PG
ND
ADP2386
TOP VIEW
NOTES
1. THE EXPOSED GND PAD MUST BE SOLDERED
TO A LARGE, EXTERNAL, COPPER GND PLANE
TO REDUCE THERMAL RESISTANCE.
2. THE EXPOSED SW PAD MUST BE CONNECTED
TO THE SW PINS OF THE ADP2386 BY USING
SHORT, WIDE TRACES, OR ELSE SOLDERED
TO A LARGE, EXTERNAL, COPPER SW PLANE
TO REDUCE THERMAL RESISTANCE.
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
Mnemonic Description
1
2
3
COMP
FB
VREG
Error Amplifier Output. Connect an RC network from COMP to GND.
Feedback Voltage Sense Input. Connect to a resistor divider from the output voltage, VOUT
Output of the Internal 8 V Regulator. The control circuits are powered from this voltage. Place a 1 µF,
X7R or X5R ceramic capacitor between this pin and GND.
.
4
GND
SW
PGND
BST
PVIN
EN
Analog Ground. Return of internal control circuit.
Switch Node Output. Connect to the output inductor.
Power Ground. Return of low-side power MOSFET.
Supply Rail for the High-Side Gate Drive. Place a 0.1 µF, X7R or X5R capacitor between SW and BST.
Power Input. Connect to the input power source and connect a bypass capacitor between this pin and PGND.
5, 6, 7, 14
8, 9, 10, 11, 12, 13
15
16, 17, 18, 19
20
Precision Enable Pin. An external resistor divider can be used to set the turn-on threshold. To enable the
part automatically, connect the EN pin to the PVIN pin.
21
22
PGOOD
RT
Power-Good Output (Open Drain). A pull-up resistor of 10 kΩ to 100 kΩ is recommended.
Frequency Setting. Connect a resistor between RT and GND to program the switching frequency from
200 kHz to 1.4 MHz.
23
SYNC
Synchronization Input. Connect this pin to an external clock to synchronize the switching frequency
within a range from 200 kHz to 1.4 MHz. See the Oscillator section and Synchronization section for
more information.
24
25
26
SS
Soft Start Control. Connect a capacitor from SS to GND to program the soft start time. If this pin is open,
the regulator uses the internal soft start time.
The exposed GND pad must be soldered to a large, external, copper GND plane to reduce thermal
resistance.
The exposed SW pad must be connected to the SW pins of the ADP2386 by using short, wide traces, or
else soldered to a large, external, copper SW plane to reduce thermal resistance.
EP, G N D
E P, S W
Rev. A | Page 6 of 24
Data Sheet
ADP2386
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VIN = 12 V, VOUT = 3.3 V, L = 2.2 µH, COUT = 100 µF + 47 µF, fSW = 600 kHz, unless otherwise noted.
100
95
90
85
80
75
70
65
60
55
50
100
95
90
85
80
75
70
65
60
55
50
V
V
V
V
V
= 1.2V
= 1.8V
= 2.5V
= 3.3V
= 5V
OUT
OUT
OUT
OUT
OUT
V
V
V
V
V
= 1.2V
= 1.8V
= 2.5V
= 3.3V
= 5V
OUT
OUT
OUT
OUT
OUT
0
0
4
1
2
3
4
5
6
0
1
2
3
4
5
6
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
Figure 4. Efficiency at VIN = 12 V, fSW = 600 kHz
Figure 7. Efficiency at VIN = 12 V, fSW = 300 kHz
100
95
90
85
80
75
70
65
60
55
50
100
95
90
85
80
75
70
65
60
55
50
V
V
V
V
V
V
= 1.0V
= 1.2V
= 1.5V
= 1.8V
= 2.5V
= 3.3V
OUT
OUT
OUT
OUT
OUT
OUT
V
V
V
V
= 1.8V
= 2.5V
= 3.3V
= 5V
OUT
OUT
OUT
OUT
1
2
3
4
5
6
0
1
2
3
4
5
6
OUTPUT CURRENT (A)
OUTPUT CURRENT (A)
Figure 5. Efficiency at VIN = 18 V, fSW = 600 kHz
Figure 8. Efficiency at VIN = 5 V, fSW = 600 kHz
100
90
80
70
60
50
3.2
3.0
2.8
2.6
2.4
2.2
2.0
1.8
T
T
T
= –40°C
= +25°C
= +125°C
T
T
T
= –40°C
= +25°C
= +125°C
J
J
J
J
J
J
6
8
10
12
14
16
18
20
4
6
8
10
12
14
16
18
20
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
Figure 6. Shutdown Current vs. Input Voltage (VIN
)
Figure 9. Quiescent Current vs. VIN
Rev. A | Page 7 of 24
ADP2386
Data Sheet
1.25
1.20
1.15
1.10
1.05
1.00
0.95
4.5
RISING
FALLING
RISING
FALLING
4.4
4.3
4.2
4.1
4.0
3.9
3.8
3.7
3.6
–40
–20
0
20
40
60
80
100
120
–40
–20
0
20
40
60
80
100
120
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 13. EN Threshold vs. Temperature
Figure 10. PVIN UVLO Threshold vs. Temperature
606
604
602
600
598
596
594
3.30
3.25
3.20
3.15
3.10
3.05
3.00
2.95
2.90
–40
–20
0
20
40
60
80
100
120
–40
–20
0
20
40
60
80
100
120
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 14. Feedback Voltage vs. Temperature
Figure 11. SS Pin Pull-Up Current vs. Temperature
8.4
8.3
8.2
8.1
8.0
7.9
7.8
7.7
630
620
610
600
590
580
570
R
= 100kΩ
T
–40
–20
0
20
40
60
80
100
120
–40
–20
0
20
40
60
80
100
120
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 12. Frequency vs. Temperature
Figure 15. VREG Voltage vs. Temperature
Rev. A | Page 8 of 24
Data Sheet
ADP2386
10.5
10.0
9.5
65
HIGH-SIDE R
DSON
DSON
LOW-SIDE R
55
45
35
25
15
5
9.0
8.5
8.0
7.5
–40
–40
–20
0
20
40
60
80
100
120
–20
0
20
40
60
80
100
120
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 16. MOSFET RDSON vs. Temperature
Figure 19. Current-Limit Threshold vs. Temperature
V
(AC)
OUT
1
EN
3
I
L
V
OUT
1
2
PGOOD
SW
3
2
I
OUT
4
B
B
CH1 10mV
CH3 2A
CH2 10V
M2.00µs
50.2%
A CH2
6V
CH1 2V
CH3 10V
CH2 5V
CH4 5A Ω
M2.00ms
50%
A CH2
5.8V
W
W
Ω
T
T
Figure 17. Working Mode Waveform
Figure 20. Soft Start with Full Load
EN
SYNC
4
V
2
OUT
1
2
SW
PGOOD
4
I
L
3
B
CH1 2V
CH3 5A
CH2 5V
CH4 10V
M2.00ms
50%
A CH2
2V
M1.00µs
50%
A CH4
7.8V
W
CH2 5V
CH4 10V
Ω
T
T
Figure 18. Voltage Precharged Output
Figure 21. External Synchronization
Rev. A | Page 9 of 24
ADP2386
Data Sheet
V
(AC)
V
(AC)
OUT
OUT
1
1
V
IN
SW
3
2
I
OUT
4
B
B
B
B
CH1 20mV
CH3 5V
CH2 10V
M1.00ms
A CH3
12.4V
CH1 100mV
M200µs
70.4%
A CH4
2.8A
W
W
W
W
T
20%
CH4 2A
Ω
T
Figure 22. Load Transient Response, 1 A to 5 A
Figure 25. Line Transient Response, VIN from 8 V to 14 V, IOUT = 6 A
V
OUT
V
OUT
1
2
4
1
2
4
SW
SW
I
L
I
L
B
CH1 2V
CH2 10V
M4.00ms
30.2%
A CH1
2.12V
B
M4.00ms
70.4%
A CH1
2.12V
W
CH1 2V
CH2 10V
W
Ω
CH4 5A
T
T
Ω
CH4 5A
Figure 23. Output Short Entry
Figure 26. Output Short Recovery
7
6
5
4
3
2
1
7
6
5
4
3
2
1
0
V
V
V
V
V
V
= 1V
OUT
OUT
OUT
OUT
OUT
OUT
V
V
V
V
V
= 1.2V
= 1.8V
= 2.5V
= 3.3V
= 5V
= 1.2V
= 1.8V
= 2.5V
= 3.3V
= 5V
OUT
OUT
OUT
OUT
OUT
0
25
40
55
70
85
100
25
40
55
70
85
100
AMBIENT TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
Figure 27. Load Current vs. Ambient Temperature at VIN = 12 V,
SW = 300 kHz
Figure 24. Load Current vs. Ambient Temperature at VIN = 12 V,
SW = 600 kHz
f
f
Rev. A | Page 10 of 24
Data Sheet
ADP2386
FUNCTIONAL BLOCK DIAGRAM
VREG
CLK
BIAS AND DRIVER
REGULATOR
RT
PVIN
OSC
SLOPE RAMP
SYNC
UVLO
EN
EN_BUF
BOOST
REGULATOR
1.17V
1µA
4µA
A
CS
+
HICCUP
MODE
OCP
–
V
SLOPE RAMP
I_MAX
Σ
BST
SW
COMP
0.6V
+
NFET
NFET
+
CMP
–
I
DRIVER
SS
SS
FB
+
AMP
–
CONTROL
LOGIC
AND MOSFET
DRIVER WITH
ANTICROSS
VREG
OVP
PROTECTION
DRIVER
CLK
PGND
0.7V
–
NEG CURRENT
CMP
–
+
+
–
V
I_NEG
0.54V
+
PGOOD
GND
DEGLITCH
Figure 28.
Rev. A | Page 11 of 24
ADP2386
Data Sheet
THEORY OF OPERATION
The ADP2386 is a synchronous step-down, dc-to-dc regulator
that uses a current-mode architecture with an integrated high-
side power switch and a low-side synchronous rectifier. The
regulator targets high performance applications that require
high efficiency and design flexibility.
BOOTSTRAP CIRCUITRY
The ADP2386 includes a regulator to provide the gate drive
voltage for the high-side N-MOSFET. It uses differential sensing to
generate a 5 V bootstrap voltage between the BST and SW pins.
It is recommended that a 0.1 µF, X7R or X5R ceramic capacitor
be placed between the BST pin and the SW pin.
The ADP2386 operates from an input voltage that ranges from
4.5 V to 20 V and regulates the output voltage from 0.6 V to 90%
of the input voltage. Additional features that maximize design
flexibility include the following: programmable switching
frequency, programmable soft start, external compensation,
precision enable, and a power-good output.
OSCILLATOR
The ADP2386 switching frequency is controlled by the RT pin.
A resistor from RT to GND can program the switching frequency
according to the following equation:
CONTROL SCHEME
69120
f
SW (kHz) =
RT (kΩ) + 15
The ADP2386 uses a fixed frequency, peak current-mode PWM
control architecture. At the start of each oscillator cycle, the high-
side N-MOSFET is turned on, putting a positive voltage across
the inductor. When the inductor current crosses the peak inductor
current threshold, the high-side N-MOSFET is turned off and
the low-side N-MOSFET is turned on. This puts a negative voltage
across the inductor, causing the inductor current to decrease.
The low-side N-MOSFET stays on for the rest of the cycle (see
Figure 17).
A 100 kΩ resistor sets the frequency to 600 kHz, and a 42.2 kΩ
resistor sets the frequency to 1.2 MHz. Figure 29 shows the
typical relationship between fSW and RT.
1400
1200
1000
800
600
400
200
0
PRECISION ENABLE/SHUTDOWN
The EN input pin has a precision analog threshold of 1.17 V
(typical) with 100 mV of hysteresis. When the enable voltage
exceeds 1.17 V, the regulator turns on; when it falls to less than
1.07 V (typical), the regulator turns off. To force the regulator
to automatically start when input power is applied, connect EN
to PVIN.
20
60
100
140
180
(kΩ)
220
260
300
R
T
The precision EN pin has an internal pull-down current source
(5 µA) that provides a default turn-off when the EN pin is open.
Figure 29. Switching Frequency vs. RT
When the EN pin voltage exceeds 1.17 V (typical), the ADP2386
is enabled and the internal pull-down current source at the EN
pin decreases to 1 µA, which allows users to program the PVIN
UVLO and hysteresis.
SYNCHRONIZATION
To synchronize the ADP2386, connect an external clock to the
SYNC pin. The external clock frequency can be in the range
of 200 kHz to 1.4 MHz. During synchronization, the regulator
operates in continuous conduction mode (CCM), and the rising
edge of the switching waveform runs 180° out of phase to the rising
edge of the external clock.
INTERNAL REGULATOR (VREG)
The on-board regulator provides a stable supply for the internal
circuits. It is recommended that a 1 µF ceramic capacitor be
placed between the VREG and GND pins. The internal regulator
includes a current-limit circuit to protect the output if the
maximum external load current is exceeded.
When the ADP2386 operates in synchronization mode, a resistor
must be connected from the RT pin to GND to program the
internal oscillator to run at 90% to 110% of the external
synchronization clock.
Rev. A | Page 12 of 24
Data Sheet
ADP2386
V
RISING
V
FALLING
OUT
OUT
SOFT START
116.7%
The ADP2386 has integrated soft start circuitry to limit the output
voltage rising time and reduce inrush current at startup. The
internal soft start time is calculated using the following equation:
105%
100%
95%
90%
1600
tSS_INT
=
(ms)
fSW (kHz)
PGOOD
A slower soft start time can be programmed by using the SS pin.
When a capacitor is connected between the SS pin and GND, an
internal current charges the capacitor to establish the soft start
ramp. The soft start time is calculated using the following equation:
1024 CYCLE
DEGLITCH
16 CYCLE
DEGLITCH
1024 CYCLE
DEGLITCH
16 CYCLE
DEGLITCH
Figure 30. PGOOD Rising and Falling Thresholds
PEAK CURRENT-LIMIT AND SHORT-CIRCUIT
PROTECTION
0.6V CSS
=
tSS_EXT
ISS _UP
The ADP2386 has a peak current-limit protection circuit to
prevent current runaway. During the initial soft start, the
ADP2386 uses frequency foldback to prevent output current
runaway. The switching frequency is reduced according to the
voltage on the FB pin, which allows more time for the inductor
to discharge. The correlation between the switching frequency
and the FB pin voltage is shown in Table 5.
where:
CSS is the soft start capacitance.
SS_UP is the soft start pull-up current (3.2 μA).
I
The internal error amplifier includes three positive inputs: the
internal reference voltage, the internal digital soft start voltage,
and the SS pin voltage. The error amplifier regulates the FB
voltage to the lowest of the three voltages.
Table 5. FB Pin Voltage and Switching Frequency
If the output voltage is charged prior to turn-on, the ADP2386
prevents reverse inductor current that would discharge the output
capacitor. This function remains active until the soft start
voltage exceeds the voltage on the FB pin.
FB Pin Voltage
Switching Frequency
VFB ≥ 0.4 V
fSW
0.4 V > VFB ≥ 0.2 V
VFB < 0.2 V
fSW/2
fSW/4
POWER GOOD
For protection against heavy loads, the ADP2386 uses a hiccup
mode for overcurrent protection. When the inductor peak
current reaches the current-limit value, the high-side MOSFET
turns off and the low-side MOSFET turns on until the next cycle.
The overcurrent counter increments during this process. If the
overcurrent counter reaches 10, or the FB pin voltage falls to
0.4 V after the soft start, the regulator enters hiccup mode. The
high-side and low-side MOSFETs are both turned off. The
regulator remains in hiccup mode for 4096 clock cycles and then
attempts to restart. If the current-limit fault has cleared, the
regulator resumes normal operation. Otherwise, it reenters
hiccup mode.
The power-good pin (PGOOD) is an active high, open-drain
output that requires an external resistor to pull it up to a voltage.
A logic high on the PGOOD pin indicates that the voltage on
the FB pin (and, therefore, the output voltage) is within regulation.
The power-good circuitry monitors the output voltage on the
FB pin and compares it to the rising and falling thresholds that
are specified in Table 1. If the rising output voltage exceeds the
target value, the PGOOD pin is held low. The PGOOD pin
continues to be held low until the falling output voltage returns
to the target value.
If the output voltage falls below the target output voltage, the
PGOOD pin is held low. The PGOOD pin continues to be held
low until the rising output voltage returns to the target value.
The ADP2386 also provides a sink current limit to prevent the
low-side MOSFET from sinking a lot of current from the load.
When the voltage across the low-side MOSFET exceeds the sink
current-limit threshold, which is typically 2.5 A, the low-side
MOSFET turns off immediately for the rest of the cycle. Both high-
side and low-side MOSFETs turn off until the next clock cycle.
The power-good rising and falling thresholds are shown in
Figure 30. There is a 1024-cycle waiting period (deglitch) before
the PGOOD pin is pulled from low to high, and there is a
16-cycle waiting period (deglitch) before the PGOOD pin is
pulled from high to low.
In some cases, the input voltage (VPVIN) ramp rate is too slow or
the output capacitor is too large for the output to reach regulation
during the soft start process, which causes the regulator to enter
the hiccup mode. To avoid such occurrences, use a resistor
divider at the EN pin to program the input voltage UVLO,
or use a longer soft start time.
Rev. A | Page 13 of 24
ADP2386
Data Sheet
power switch and synchronous rectifier turn off. When the
PVIN voltage rises to greater than 4.3 V typical, the soft start
period is initiated, and the part is enabled.
OVERVOLTAGE PROTECTION (OVP)
V
The ADP2386 includes an overvoltage protection feature
to protect the regulator against an output short to a higher
voltage supply or when a strong load disconnect transient
occurs. If the feedback voltage increases to 0.7 V, the internal
high-side and low-side MOSFETs are turned off until the
voltage at the FB pin decreases to 0.63 V. At that time, the
ADP2386 resumes normal operation.
THERMAL SHUTDOWN
If the ADP2386 junction temperatures rises to greater than 150°C,
the internal thermal shutdown circuit turns off the regulator for
self-protection. Extreme junction temperatures can be the result of
high current operation, poor circuit board thermal design,
and/or high ambient temperature. A 25°C hysteresis is included
in the thermal shut-down circuit so that, if an overtemperature
event occurs, the ADP2386 does not return to normal operation
until the on-chip temperature falls to less than 125°C. Upon
recovery, a soft start is initiated before normal operation begins.
UNDERVOLTAGE LOCKOUT (UVLO)
Undervoltage lockout circuitry is integrated in the ADP2386 to
prevent the occurrence of power-on glitches. If the VPVIN voltage
falls to less than 3.8 V typical, the part shuts down, and both the
Rev. A | Page 14 of 24
Data Sheet
ADP2386
APPLICATIONS INFORMATION
The maximum output voltage for a given input voltage and
INPUT CAPACITOR SELECTION
switching frequency is constrained by the minimum off time
and the maximum duty cycle. The minimum off time is typically
200 ns, and the maximum duty cycle of the ADP2386 is
typically 90%.
The input capacitor reduces the input voltage ripple caused by
the switch current on PVIN. Place the input capacitor as close
as possible to the PVIN pin. A ceramic capacitor in the 10 μF to
47 μF range is recommended. The loop that is composed of this
input capacitor, the high-side N-MOSFET, and the low-side N-
MOSFET must be kept as small as possible.
The maximum output voltage, limited by the minimum off time
at a given input voltage and switching frequency, can be calculated
using the following equation:
The voltage rating of the input capacitor must be greater than
the maximum input voltage. Ensure that the rms current rating
of the input capacitor is larger than the value calculated from
the following equation:
V
OUT_MAX = VIN × (1 − tMIN_OFF × fSW) − (RDSON_HS − RDSON_LS) ×
OUT_MAX × (1 − tMIN_OFF × fSW) − (RDSON_LS + RL) × IOUT_MAX (2)
where:
I
V
OUT_MAX is the maximum output voltage.
ICIN RMS = IOUT
×
D × (1 − D)
_
V
IN is the input voltage.
MIN_OFF is the minimum off time.
OUTPUT VOLTAGE SETTING
t
f
R
R
I
SW is the switching frequency.
DSON_HS is the high-side MOSFET on resistance.
DSON_LS is the low-side MOSFET on resistance.
The output voltage of the ADP2386 is set by an external resistive
divider. The resistor values are calculated using
RTOP
RBOT
OUT_MAX is the maximum output current.
V
OUT = 0.6 × 1 +
RL is the series resistance of the output inductor.
The maximum output voltage, limited by the maximum duty
cycle at a given input voltage, can be calculated using the
following equation:
To limit the output voltage accuracy degradation due to the FB
bias current (0.1 µA maximum) to less than 0.5% (maximum),
ensure that RBOT < 30 kΩ.
V
OUT_MAX = DMAX × VIN
(3)
Table 6 lists the recommended resistor divider values for the
various output voltages.
where DMAX is the maximum duty cycle; VIN is the input voltage.
Table 6. Resistor Divider Values for Various Output Voltages
As shown in Equation 1 to Equation 3, reducing the switching
frequency alleviates the minimum on time and minimum off
time limitation.
VOUT (V)
RTOP 1% (kΩ)
RBOT 1% (kΩ)
1.0
1.2
1.5
1.8
2.5
3.3
5.0
10
10
15
20
47.5
10
22
15
10
10
10
15
2.21
3
INDUCTOR SELECTION
The inductor value is determined by the operating frequency,
input voltage, output voltage, and inductor ripple current. Using
a small inductor value leads to a faster transient response; however,
it degrades efficiency, due to a larger inductor ripple current.
Using a large inductor value leads to smaller ripple current and
better efficiency, but it results in a slower transient response.
VOLTAGE CONVERSION LIMITATIONS
The minimum output voltage for a given input voltage and
switching frequency is constrained by the minimum on time.
The minimum on time of the ADP2386 is typically 125 ns.
The minimum output voltage for a given input voltage and
switching frequency can be calculated using the following:
As a guideline, the inductor ripple current, ΔIL, is typically set
to one-third of the maximum load current. The inductor value
is calculated using the following equation:
(VIN −VOUT ) × D
L =
V
OUT_MIN = VIN × tMIN_ON × fSW − (RDSON_HS − RDSON_LS) ×
OUT_MIN × tMIN_ON × fSW − (RDSON_LS + RL) × IOUT_MIN
where:
∆IL × fSW
I
(1)
where:
V
V
IN is the input voltage.
OUT is the output voltage.
V
V
OUT_MIN is the minimum output voltage.
IN is the input voltage.
D is the duty cycle (D = VOUT/VIN).
t
MIN_ON is the minimum on time.
ΔIL is the inductor current ripple.
fSW is the switching frequency.
fSW is the switching frequency.
R
R
DSON_HS is the high-side MOSFET on resistance.
DSON_LS is the low-side MOSFET on resistance.
The ADP2386 uses adaptive slope compensation in the current
loop to prevent subharmonic oscillations when the duty cycle
is larger than 50%. The internal slope compensation limits the
minimum inductor value.
IOUT_MIN is the minimum output current.
RL is the series resistance of the output inductor.
Rev. A | Page 15 of 24
ADP2386
Data Sheet
For a duty cycle that is larger than 50%, the minimum inductor
value is determined using the following equation:
where:
UV is a factor, with a typical setting of KUV = 2.
ΔISTEP is the load step.
K
VOUT × (1− D)
L (Minimum) =
ΔVOUT_UV is the allowable undershoot on the output voltage.
2 × fSW
The peak inductor current is calculated by
∆IL
Another example occurs when a load is suddenly removed from
the output, and the energy stored in the inductor rushes into
the output capacitor, causing the output to overshoot.
IPEAK = IOUT +
2
The output capacitance that is required to meet the overshoot
requirement can be calculated using the following equation:
The saturation current of the inductor must be larger than the peak
inductor current. For ferrite core inductors with a quick saturation
characteristic, the saturation current rating of the inductor must
be higher than the current-limit threshold of the switch. This
prevents the inductor from reaching saturation.
2
KOV × ∆ISTEP × L
(VOUT + ∆VOUT _OV )2 −VOUT
COUT_OV
=
2
where:
ΔVOUT_OV is the allowable overshoot on the output voltage.
OV is a factor, with a typical setting of KOV = 2.
The rms current of the inductor is calculated as follows:
K
2
∆IL
12
2
IRMS
=
IOUT
+
The output ripple is determined by the ESR and the value of the
capacitance. Use the following equations to select a capacitor
that can meet the output ripple requirements:
Shielded ferrite core materials are recommended for low core
loss and low EMI. Table 7 lists some recommended inductors.
∆IL
COUT_RIPPLE
=
OUTPUT CAPACITOR SELECTION
8 × fSW × ∆VOUT _ RIPPLE
The output capacitor selection affects the output ripple voltage
load step transient and the loop stability of the regulator.
∆VOUT _ RIPPLE
RESR
where:
=
∆IL
For example, during a load step transient where the load is
suddenly increased, the output capacitor supplies the load until
the control loop can ramp up the inductor current. The delay
caused by the control loop causes output undershoot. The
output capacitance that is required to satisfy the voltage droop
requirement can be calculated using the following equation:
ΔIL is the inductor current ripple.
ΔVOUT_RIPPLE is the allowable output ripple voltage.
ESR is the equivalent series resistance of the output capacitor
in ohms (Ω).
R
Select the largest output capacitance given by COUT_UV, COUT_OV
and COUT_RIPPLE to meet both load transient and output ripple
performance.
,
2
KUV × ∆ISTEP × L
COUT_UV
=
2 × (VIN −VOUT ) × ∆VOUT _UV
Table 7. Recommended Inductors
Vendor
Part No.
Value (µH)
0.47
0.75
1.0
1.5
2.2
ISAT (A)
15.6
10.9
9.5
13.7
11.4
9.8
IRMS (A)
14.1
10.7
9.5
14.6
11.6
9.0
DCR (mΩ)
3.7
6.2
8.5
4.6
Toko
FDVE0630-R47M
FDVE0630-R75M
FDVE0630-1R0M
FDVE1040-1R5M
FDVE1040-2R2M
FDVE1040-3R3M
FDVE1040-4R7M
IHLP3232DZ-R47M-11
IHLP3232DZ-R68M-11
IHLP3232DZ-1R0M-11
IHLP4040DZ-1R5M-01
IHLP4040DZ-2R2M-01
IHLP4040DZ-3R3M-01
IHLP4040DZ-4R7M-01
744 325 120
6.8
3.3
4.7
10.1
13.8
2.38
3.22
4.63
5.8
8.2
8.0
Vishay
0.47
0.68
1.0
1.5
2.2
14
14.5
12
27.5
25.6
18.6
17
25
22.2
18.2
15
12
10
9
3.3
4.7
14.4
16.5
1.8
9.5
Wurth Elektronik
1.2
25
20
744 325 180
1.8
18
16
3.5
744 325 240
744 325 330
2.4
3.3
17
15
14
12
4.75
5.9
744 325 420
4.2
14
11
7.1
Rev. A | Page 16 of 24
Data Sheet
ADP2386
The selected output capacitor voltage rating must be greater
than the output voltage. The rms current rating of the output
capacitor must be larger than the value that is calculated by
using the following equation:
The ADP2386 uses a transconductance amplifier for the error
amplifier and to compensate the system. Figure 32 shows the
simplified, peak current-mode control, small signal circuit.
V
V
OUT
OUT
∆IL
ICOUT
=
_RMS
R
R
TOP
12
V
C
R
COMP
C
OUT
–
gm
+
–
A
VI
PROGRAMMING THE INPUT VOLTAGE UVLO
+
R
BOT
R
C
The ADP2386 has a precision enable input that can be used to
program the UVLO threshold of the input voltage (see Figure 31).
CP
ESR
C
C
PVIN
ADP2386
Figure 32. Simplified Peak Current Mode Control, Small Signal Circuit
R
TOP_EN
The compensation components, RC and CC, contribute a zero,
and RC and the optional CCP contribute an optional pole.
EN CMP
EN
1.17V
4µA
The closed-loop transfer equation is as follows:
R
BOT_EN
1µA
RBOT
− gm
TV (s) =
×
×
RBOT + RTOP CC + CCP
1 + RC × CC × s
RC × CC × CCP
Figure 31. Programming the Input Voltage UVLO
Use the following equations to calculate RTOP_EN and RBOT_EN
1.07V ×VIN _ RISING − 1.17V ×VIN _ FALLING
× GVD (s)
s × (1 +
× s)
:
CC + CCP
The following design guideline shows how to select the RC, CC,
and CCP compensation components for ceramic output
capacitor applications:
RTOP_EN
=
1.07 V × 5μA − 1.17V ×1 μA
1.17V× RTOP_ EN
RBOT_EN
where:
=
1. Determine the cross frequency, fC. Generally, fC is between
VIN _ RISING − RTOP_ EN × 5μA − 1.17 V
f
SW/12 and fSW/6.
2. Calculate RC, using the following equation:
VIN_RISING is the VIN rising threshold.
VIN_FALLING is the VIN falling threshold.
2 × π ×VOUT × COUT × fC
RC =
0.6V × gm × A
VI
COMPENSATION DESIGN
3. Place the compensation zero at the domain pole, fP; then
determine CC by using the following equation:
For peak current-mode control, the power stage can be simplified
as a voltage controlled current source supplying current to the
output capacitor and load resistor. It is composed of one domain
pole and a zero that is contributed by the output capacitor ESR.
The control-to-output transfer function is based on the following:
(R + RESR ) × COUT
CC =
RC
4. CCP is optional. It can be used to cancel the zero caused by
the ESR of the output capacitor.
s
1 +
1 +
RESR × COUT
CCP
=
2 × π × fZ
VOUT (s)
G
VD (s) =
= AVI × R ×
RC
V COMP (s)
s
ADIsimPOWER DESIGN TOOL
2 × π × fP
The ADP2386 is supported by the ADIsimPower™ design tool
set. ADIsimPower is a collection of tools that produce complete
power designs that are optimized for a specific design goal. The
tools enable the user to generate a full schematic and bill of
materials and calculate performance in minutes. ADIsimPower
can optimize designs for cost, area, efficiency, and part count,
while taking into consideration the operating conditions and
limitations of the IC and all real external components. For more
information about theADIsimPower design tools, refer to
www.analog.com/ADIsimPower. The tool set is available from
this website, and users can request an unpopulated board.
1
fZ =
fP =
2 × π × RESR × COUT
1
2 ×π × (R + RESR ) × COUT
where:
VI = 8.7 A/V.
R is the load resistance.
OUT is the output capacitance.
ESR is the equivalent series resistance of the output capacitor.
A
C
R
Rev. A | Page 17 of 24
ADP2386
Data Sheet
DESIGN EXAMPLE
V
= 12V
C
IN
PVIN
BST
SW
IN
10µF
25V
C
BST
0.1µF
EN
L1
2.2µF
PGOOD
SYNC
V
= 3.3V
OUT
R
10kΩ
TOP
C
C
OUT1
100
6.3V
OUT2
47
6.3V
ADP2386
R
T
µ
F
µ
F
1%
100kΩ
RT
FB
C
VREG
1µF
R
TOP
COMP
2.21kΩ
1%
VREG
SS
R
C
44.2kΩ
C
SS
22nF
C
C
1.2nF
GND PGND
CP
4.7pF
C
Figure 33. Schematic for Design Example
This section describes the procedures for selecting the external
components, based on the example specifications that are listed
in Table 8. See Figure 33 for the schematic of this design example.
This calculation results in L = 2.215 μH. Choose the standard
inductor value of 2.2 μH.
The peak-to-peak inductor ripple current can be calculated by
using the following equation:
Table 8. Step-Down DC-to-DC Regulator Requirements
Parameter
Specification
VIN = 12.0 V 10%
VOUT = 3.3 V
(VIN −VOUT ) × D
ΔIL =
Input Voltage
L× fSW
Output Voltage
Output Current
Output Voltage Ripple
Load Transient
This calculation results in ∆IL = 1.81 A.
Use the following equation to calculate the peak inductor current:
IOUT = 6 A
∆VOUT_RIPPLE = 33 mV
5%, 1 A to 5 A, 2 A/μs
fSW = 600 kHz
∆IL
2
IPEAK = IOUT +
Switching Frequency
OUTPUT VOLTAGE SETTING
This calculation results in IPEAK = 6.905 A.
Choose a 10 kΩ resistor as the top feedback resistor (RTOP),
and calculate the bottom feedback resistor (RBOT) by using the
following equation:
Use the following equation to calculate the rms current flowing
through the inductor:
2
∆IL
12
2
IRMS
=
IOUT
+
0.6
RBOT = RTOP ×
VOUT − 0.6
This calculation results in IRMS = 6.023 A.
To set the output voltage to 3.3 V, the resistors values are as
follows: RTOP = 10 kΩ, and RBOT = 2.21 kΩ.
Based on the calculated current value, select an inductor with
a minimum rms current rating of 6.03 A and a minimum
saturation current rating of 6.91 A.
FREQUENCY SETTING
To set the switching frequency to 600 kHz, connect a 100 kΩ
resistor from the RT pin to GND.
However, to protect the inductor from reaching its saturation
point under the current-limit condition, the inductor should be
rated for at least a 9.6 A saturation current for reliable operation.
INDUCTOR SELECTION
Based on the requirements described previously, select a 2.2 μH
inductor, such as the FDVE1040-2R2M from Toko, which has
a 6.8 mΩ DCR and a 11.4 A saturation current.
The peak-to-peak inductor ripple current, ∆IL, is set to 30% of
the maximum output current. Use the following equation to
estimate the inductor value:
(VIN − VOUT ) × D
L =
∆IL × fSW
where:
V
IN = 12 V.
VOUT = 3.3 V.
D = 0.275.
∆IL = 1.8 A.
fSW = 600 kHz.
Rev. A | Page 18 of 24
Data Sheet
ADP2386
The 100 µF and 47 µF ceramic output capacitors have a derated
value of 62 µF and 32 µF.
OUTPUT CAPACITOR SELECTION
The output capacitor is required to meet both the output voltage
ripple and load transient response requirements.
2 ×π × 3.3V × 94 μF × 60kHz
0.6V × 480 μs × 8.7A/ V
RC =
= 46.7 kΩ
To meet the output voltage ripple requirement, use the following
equation to calculate the ESR and capacitance value of the output
capacitor:
(0.55 Ω + 0.002 Ω) × 94 μF
46.7 kΩ
CC =
= 1111 pF
∆IL
0.002 Ω × 94 μF
COUT_RIPPLE
=
CCP
=
= 4.0 pF
8 × fSW × ∆VOUT _ RIPPLE
46.7 kΩ
Choose standard components, as follows: RC = 44.2 kΩ,
CC = 1200 pF, and CCP = 4.7 pF.
∆VOUT _ RIPPLE
RESR
=
∆IL
Figure 34 shows the bode plot at 6 A. The cross frequency is
58 kHz, and the phase margin is 61°.
This calculation results in COUT_RIPPLE = 11.4 μF, and RESR = 18 mΩ.
To meet the 5% overshoot and undershoot transient
requirements, use the following equations to calculate the
capacitance:
60
180
144
108
72
48
36
2
KOV × ∆ISTEP × L
(VOUT + ∆VOUT _OV )2 −VOUT
COUT_OV
=
24
2
12
36
2
0
0
KUV × ∆ISTEP × L
COUT_UV
=
–12
–24
–36
–48
–60
–36
–72
–108
–144
–180
2 × (VIN − VOUT ) × ∆VOUT _UV
where:
OV = KUV = 2 are the coefficients for estimation purposes.
∆ISTEP = 4 A is the load transient step.
K
∆VOUT_OV = 5% VOUT is the overshoot voltage.
1k
10k
100k
1M
∆VOUT_UV = 5% VOUT is the undershoot voltage.
FREQUENCY (Hz)
This calculation results in COUT_OV = 63.1 μF, and COUT_UV = 24.5 μF.
Figure 34. Bode Plot at 6 A
According to the calculation, the output capacitance must be
greater than 63 μF, and the ESR of the output capacitor must be
smaller than 18 mΩ. It is recommended that one 100 μF/X5R/
6.3 V ceramic capacitor and one 47 μF/X5R/6.3 V ceramic
capacitor be used, such as the GRM32ER60J107ME20 and
GRM32ER60J476ME20 from Murata, with an ESR of 2 mΩ.
SOFT START TIME PROGRAM
The soft start feature allows the output voltage to ramp up in a
controlled manner, eliminating output voltage overshoot during
soft start and limiting the inrush current. Set the soft start time
to 4 ms.
tSS _ EXT × ISS _
4 ms × 3.2μA
UP
COMPENSATION COMPONENTS
CSS
=
=
= 21.3 nF
0.6
0.6V
For better load transient and stability performance, set the cross
frequency, fC, to fSW/10. In this case, fSW is running at 600 kHz;
therefore, the fC is set to 60 kHz.
Choose a standard component value, as follows: CSS = 22 nF.
INPUT CAPACITOR SELECTION
Place a minimum 10 μF ceramic capacitor near the PVIN pin.
In this application, it is recommended that one 10 μF, X5R, 25 V
ceramic capacitor be used.
Rev. A | Page 19 of 24
ADP2386
Data Sheet
RECOMMENDED EXTERNAL COMPONENTS
Table 9. Recommended External Components for Typical Applications with 6 A Output Current
fSW (kHz)
VIN (V)
12
12
12
12
12
12
12
5
VOUT (V)
L (µH)
1.5
2.2
2.2
3.3
3.3
4.7
4.7
1.5
1.5
2.2
2.2
2.2
2.2
1
COUT (µF)1
680 + 2 × 100
680 + 2 × 100
680
RTOP (kΩ)
RBOT (kΩ)
RC (kΩ)
57.6
68.1
73.2
88.7
84.5
44.2
33
CC (pF)
2200
2200
2200
2200
2200
2200
2200
2200
2200
2200
2200
2200
2200
1200
1200
1200
1200
1200
1200
1200
1200
1200
1200
1200
680
CCP (pF)
150
120
100
82
300
1
10
15
1.2
1.5
1.8
2.5
3.3
5
10
10
15
10
680
20
10
470
47.5
10
15
47
3 × 100
100 + 47
680 + 2 × 100
680
2.21
3
8.2
4.7
150
120
100
82
22
1
10
15
57.6
57.6
73.2
61.9
33
5
1.2
1.5
1.8
2.5
3.3
1.5
1.8
2.5
3.3
5
10
10
5
680
15
10
5
470
20
10
5
3 × 100
3 × 100
3 × 100
3 × 100
2 × 100
100 + 47
100
47.5
10
15
10
5
2.21
10
44.2
39
8.2
10
600
12
12
12
12
12
5
15
1.5
2.2
2.2
3.3
1
20
10
47
8.2
4.7
4.7
2.2
68
47.5
10
15
44.2
44.2
44.2
97.6
82
2.21
3
22
1
680
10
15
5
1.2
1.5
1.8
2.5
3.3
2.5
3.3
5
1
470
10
10
47
5
1
3 × 100
2 × 100
100
15
10
39
10
5
1
20
10
33
8.2
4.7
4.7
3.3
2.2
2.2
8.2
6.8
4.7
4.7
3.3
2.2
5
1
47.5
10
15
22
5
1
100 + 47
100
2.21
15
44.2
37.4
47
1000
12
12
12
5
1
47.5
10
1.5
1.5
0.47
0.47
0.68
0.68
0.68
0.68
100
2.21
3
680
100
22
73.2
44.2
34.8
33
680
1
3 × 100
2 × 100
100 + 47
100 + 47
100
10
15
680
5
1.2
1.5
1.8
2.5
3.3
10
10
680
5
15
10
680
5
20
10
39
680
5
47.5
10
15
37.4
47
680
5
100
2.21
680
1 680 μF: 4 V, Sanyo 4TPF680M; 470 μF: 6.3 V, Sanyo 6TPF470M; 100 μF: 6.3 V, X5R, Murata GRM32ER60J107ME20; 47 μF: 6.3 V, X5R, Murata GRM32ER60J476ME20.
Rev. A | Page 20 of 24
Data Sheet
ADP2386
CIRCUIT BOARD LAYOUT RECOMMENDATIONS
Good printed circuit board (PCB) layout is essential for obtaining
the best performance from the ADP2386. Poor PCB layout can
degrade the output regulation, as well as the electromagnetic
interference (EMI) and electromagnetic compatibility (EMC)
performance. Figure 36 shows an example of a good PCB layout
for the ADP2386. For optimum layout, refer to the following
guidelines:
Connect the exposed GND pad of the ADP2386 to a large,
external copper ground plane to maximize its power
dissipation capability and minimize junction temperature.
In addition, connect the exposed SW pad to the SW pins
of the ADP2386, using short, wide traces; or connect the
exposed SW pad to a large copper plane of the switching
node for high current flow.
Place the feedback resistor divider network as close as
possible to the FB pin to prevent noise pickup. Minimize
the length of the trace that connects the top of the feedback
resistor divider to the output while keeping the trace away
from the high current traces and the switching node to
avoid noise pickup. To further reduce noise pickup, place
an analog ground plane on either side of the FB trace and
ensure that the trace is as short as possible to reduce the
parasitic capacitance pickup.
Use separate analog ground planes and power ground
planes. Connect the ground reference of sensitive analog
circuitry, such as output voltage divider components, to
analog ground. In addition, connect the ground reference
of power components, such as input and output capacitors,
to power ground. Connect both ground planes to the
exposed GND pad of the ADP2386.
Place the input capacitor, inductor, and output capacitor as
close as possible to the IC, and use short traces.
Ensure that the high current loop traces are as short and as
wide as possible. Make the high current path from the input
capacitor through the inductor, the output capacitor, and the
power ground plane back to the input capacitor as short as
possible. To accomplish this, ensure that the input and output
capacitors share a common power ground plane.
ADP2386
V
PVIN
EN
BST
SW
IN
C
C
IN
BST
V
L
OUT
PGOOD
SYNC
C
OUT
R
TOP
FB
In addition, ensure that the high current path from the power
ground plane through the inductor and output capacitor
back to the power ground plane is as short as possible by
tying the PGND pins of the ADP2386 to the PGND plane
as close as possible to the input and output capacitors.
R
RT
COMP
SS
BOT
R
C
VREG
R
T
C
GND PGND
VREG
C
C
C
SS
Figure 35. High Current Path in the PCB Circuit
ANALOG GROUND PLANE
R
BOT
PVIN
COMP
PVIN
R
TOP
FB
INPUT
INPUT
GND
SW
PVIN
BYPASS BULK
CAP
CAP
VREG
PVIN
BST
C
VREG
GND
SW
+
C
BST
SW
SW
PGND
SW
INDUCTOR
POWER GROUND PLANE
OUTPUT
CAPACITOR
VOUT
VIA
BOTTOM LAYER TRACE
COPPER PLANE
Figure 36. Recommended PCB Layout
Rev. A | Page 21 of 24
ADP2386
Data Sheet
TYPICAL APPLICATIONS CIRCUITS
V
= 12V
IN
BST
SW
PVIN
C
IN
C
BST
0.1µF
L1
1µH
10µF
25V
EN
V
= 1.2V
OUT
PGOOD
C
470µF
C
OUT2
10µF
6.3V
OUT1
R
10kΩ
TOP
SYNC
R
ADP2386
T
6.3V
1%
124kΩ
FB
RT
R
BOT
10kΩ
1%
VREG
SS
COMP
C
VREG
1µF
R
C
66.5kΩ
C
C
1.5nF
CP
68pF
GND PGND
C
C
SS
22nF
Figure 37. Typical Applications Circuit, VIN = 12 V, VOUT = 1.2 V, IOUT = 6 A, fSW = 500 kHz
V
= 12V
IN
PVIN
C
IN
BST
SW
10µF
25V
EN
C
0.1µF
BST
L1
1.5µH
V
= 1.8V
PGOOD
OUT
C
OUT3
SYNC
C
100µF
C
100µF
OUT1
OUT2
R
20kΩ
TOP
100µF
6.3V
R
PGOOD
100kΩ
ADP2386
6.3V
6.3V
1%
FB
VREG
RT
R
BOT
10kΩ
1%
C
VREG
1µF
COMP
R
T
R
C
47kΩ
100kΩ
SS
C
8.2pF
C
CP
GND PGND
C
1.2nF
Figure 38. Typical Applications Circuit Using Internal Soft Start, VIN = 12 V, VOUT = 1.8 V, IOUT = 6 A, fSW = 600 kHz
V
= 12V
IN
PVIN
R
C
TOP_EN
IN
BST
SW
10µF
25V
16.9kΩ
EN
C
0.1µF
R
BST
L1
BOT_EN
PGOOD
SYNC
3.3µH
V
= 5V
2kΩ
OUT
C
100µF
6.3V
OUT
R
22kΩ
TOP
ADP2386
R
T
1%
100kΩ
FB
RT
C
R
VREG
BOT
3kΩ
1%
1µF
COMP
R
C
VREG
SS
44.2kΩ
C
C
CP
GND PGND
C
C
SS
22nF
2.2pF
1.2nF
Figure 39. Programming Input Voltage UVLO Rising Threshold at 11 V, Falling Threshold at 10 V, VIN = 12 V, VOUT = 5 V, IOUT = 6 A, fSW = 600 kHz
Rev. A | Page 22 of 24
Data Sheet
ADP2386
OUTLINE DIMENSIONS
4.10
4.00 SQ
3.90
2.80
2.70
2.60
0.20
MIN
0.20 MIN
PIN 1
INDICATOR
1.50
PIN 1
INDICATOR
0.20
MIN
19
24
18
1.40
1
1.30
0.45
EXPOSED
PAD
0.35
0.25
0.50
BSC
EXPOSED
PAD
1.05
0.95
0.85
6
13
7
12
0.50
0.40
0.30
TOP VIEW
BOTTOM VIEW
0.20
MIN
0.80
0.75
0.70
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.05 MAX
0.02 NOM
COPLANARITY
0.08
SECTION OF THIS DATA SHEET.
SEATING
PLANE
0.25
0.20
0.15
0.203 REF
COMPLIANT TO JEDEC STANDARDS MO-220-WGGD .
Figure 40. 24-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
4 mm × 4 mm Body, Very Very Thin Quad
(CP-24-12)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
Temperature Range
Package Description
Package Option
CP-24-12
ADP2386ACPZN-R7
ADP2386-EVALZ
ADP2386BB-EVALZ
−40°C to +125°C
24-Lead LFCSP_WQ, 7”Tape and Reel
Evaluation Board
Inverting Buck-Boost Evaluation Board
1 Z = RoHS Compliant Part.
Rev. A | Page 23 of 24
ADP2386
NOTES
Data Sheet
©2012–2013 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D10211-0-4/13(A)
Rev. A | Page 24 of 24
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