ADP3182JRQZ-RL [ADI]
Adjustable Output 1-/2-/3-Phase Synchronous Buck Controller; 可调输出1 /2 / 3相同步降压控制器
| 型号： | ADP3182JRQZ-RL |
| 厂家： | 
ADI |
| 描述： | Adjustable Output 1-/2-/3-Phase Synchronous Buck Controller |
| 文件： | 总20页 (文件大小：406K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Adjustable Output 1-/2-/3-Phase
Synchronous Buck Controller
ADP3182
GENERAL DESCRIPTION
FEATURES
Selectable 1-, 2-, or 3-phase operation at up to 1 MHz per
phase
2ꢀ worst-case differential sensing error over temperature
Externally adjustable 0.8 V to >5 V output from a 12 V supply
Logic-level PWM outputs for interface to external high
power drivers
Active current balancing between all output phases
Built-in power good/crowbar functions
The ADP3182 is a highly efficient multiphase, synchronous,
buck-switching regulator controller optimized for converting a
12 V main supply into a high current, low voltage supply for use
in point-of-load (POL) applications. It uses a multimode PWM
architecture to drive the logic-level outputs at a programmable
switching frequency that can be optimized for VR size and
efficiency. The phase relationship of the output signals can be
programmed to provide 1-, 2-, or 3-phase operation, allowing
for the construction of up to three complementary buck-
switching stages. The ADP3182 also provides accurate and
reliable short-circuit protection and adjustable current limiting.
Programmable short-circuit protection with programmable
latch-off delay
APPLICATIONS
Auxiliary supplies
DDR memory supplies
Point-of-load modules
ADP3182 is specified over the commercial temperature range of
0°C to +85°C and is available in a 20-lead QSOP package.
FUNCTIONAL BLOCK DIAGRAM
RAMPADJ RT
VCC
1
9
8
UVLO
SHUTDOWN
& BIAS
OSCILLATOR
6
EN
SET
EN
14
GND
20
19
CMP
RESET
PWM1
PWM2
950mV
FB
CURRENT
BALANCING
CIRCUIT
CMP
RESET
2 / 3-PHASE
DRIVER LOGIC
650mV
18
CMP
RESET
CROWBAR
PWM3
CURRENT
LIMIT
1.05V
FB
5
DELAY
PWRGD
ILIMIT
10
17
16
15
SW1
SW2
EN
SW3
12
11
13
CSSUM
CURRENT
LIMIT
CIRCUIT
7
4
DELAY
COMP
CSREF
SOFT
START
CSCOMP
3
FB
800mV
REFERENCE
ADP3182
2
FBRTN
Figure 1.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.326.8703
www.analog.com
© 2004 Analog Devices, Inc. All rights reserved.
ADP3182
TABLE OF CONTENTS
Specifications..................................................................................... 3
Output Enable and UVLO ........................................................ 12
Applications..................................................................................... 14
Setting the Clock Frequency..................................................... 14
Soft Start and Current Limit Latch-Off Delay Time ............. 14
Inductor Selection...................................................................... 14
Output Current Sense................................................................ 15
Output Voltage............................................................................ 16
Power MOSFETs......................................................................... 16
Ramp Resistor Selection............................................................ 17
Current Limit Setpoint .............................................................. 17
Feedback Loop Compensation Design.................................... 17
Input Capacitor Selection and Input Current di/dt............... 18
Inductor DCR Temperature Correction ................................. 18
Layout and Component Placement ......................................... 19
Outline Dimensions....................................................................... 20
Ordering Guide .......................................................................... 20
Test Circuits ....................................................................................... 5
Absolute Maximum Ratings............................................................ 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Description .............................. 7
Typical Performance Characteristics ............................................. 8
Theory of Operation ........................................................................ 9
Start-Up Sequence........................................................................ 9
Master Clock Frequency.............................................................. 9
Output Voltage Differential Sensing.......................................... 9
Output Current Sensing .............................................................. 9
Current Control Mode and Thermal Balance ........................ 10
Voltage Control Mode................................................................ 10
Soft Start ...................................................................................... 10
Current Limit, Short-Circuit, and Latch-off Protection ....... 10
Power Good Monitoring ........................................................... 11
Output Crowbar ......................................................................... 11
REVISION HISTORY
10/04—Revision 0: Initial Version
Rev. 0 | Page 2 of 20
ADP3182
SPECIFICATIONS
VCC = 12 V, FBRTN = GND, TA = 0°C to 85°C, unless otherwise noted.1
Table 1.
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
OSCILLATOR
Frequency Range2
Frequency Variation
fOSC
fPHASE
0.25
155
3
245
MHz
kHz
kHz
kHz
V
200
400
600
2.0
TA = 25°C, RT = 348 kΩ, 3-phase
TA = 25°C, RT = 174 kΩ, 3-phase
TA = 25°C, RT = 100 kΩ, 3-phase
RT = 100 kΩ to GND
Output Voltage
VRT
1.9
−50
0
2.1
RAMPADJ Output Voltage
RAMPADJ Input Current Range
VRAMPADJ
IRAMPADJ
RAMPADJ − FB
+50
100
mV
µA
VOLTAGE ERROR AMPLIFIER
Output Voltage Range2
Accuracy
VCOMP
VFB
0.7
784
3.1
816
V
mV
%
Referenced to FBRTN
VCC = 10 V to 14 V
FB = 800 mV
800
0.05
Line Regulation
∆VFB
IFB
Input Bias Current
FBRTN Current
−4
+4
µA
IFBRTN
IO(ERR)
GBW(ERR)
100
500
20
140
µA
µA
MHz
Output Current
FB forced to VOUT − 3%
COMP = FB
CCOMP = 10 pF
Gain Bandwidth Product
Slew Rate
25
V/µs
CURRENT SENSE AMPLIFIER
Offset Voltage
Input Bias Current
Gain Bandwidth Product
Slew Rate
VOS(CSA)
IBIAS(CSSUM)
GBW(CSA)
CSSUM − CSREF, Figure 2
−5.5
−50
+5.5
+50
mV
nA
MHz
10
10
CCSCOMP = 10 pF
V/µs
Input Common-Mode Range
Output Voltage Range
Output Current
CSSUM and CSREF
0
0.05
VCC − 2.5
VCC − 2.5
V
V
ICSCOMP
500
µA
CURRENT BALANCE CIRCUIT
Common-Mode Range
Input Resistance
VSW(X)CM
RSW(X)
ISW(X)
−600
20
+200
40
mV
kΩ
µA
%
SW(X) = 0 V
SW(X) = 0 V
SW(X) = 0 V
30
7
Input Current
4
10
Input Current Matching
−7
+7
∆ISW(X)
CURRENT LIMIT COMPARATOR
Output Voltage
Normal Mode
VILIMIT(NM)
VILIMIT(SD)
IILIMIT(NM)
2.9
3
3.1
V
EN > 2 V, RILIMIT = 250 kΩ
EN < 0.8 V, IILIMIT = −100 µA
EN > 2 V, RILIMIT = 250 kΩ
In Shutdown Mode
400
mV
Output Current, Normal Mode
Maximum Output Current2
Current Limit Threshold Voltage
Current Limit Setting Ratio
DELAY Normal Mode Voltage
DELAY Overcurrent Threshold
Latch-Off Delay Time
12
µA
µA
mV
60
VCL
105
125
10.4
3
145
VCSREF − VCSCOMP, RILIMIT = 250 kΩ
VCL/IILIMIT
mV/µA
V
VDELAY(NM)
VDELAY(OC)
tDELAY
2.9
1.7
3.1
1.9
RDELAY = 250 kΩ
RDELAY = 250 kΩ
1.8
1.5
V
ms
RDELAY = 250 kΩ, CDELAY = 12 nF
SOFT START
Output Current, Soft Start Mode
Soft Start Delay Time
IDELAY(SS)
tDELAY(SS)
During start-up, DELAY < 2.4 V
15
20
25
µA
µs
500
RDELAY = 250 kΩ, CDELAY = 12 nF
Rev. 0 | Page 3 of 20
ADP3182
Parameter
Symbol
Conditions
Min
Typ
Max
0.8
Unit
ENABLE INPUT
Input Low Voltage
Input High Voltage
Input Current
VIL(EN)
VIH(EN)
IIN(EN)
V
V
2.0
−1
+1
µA
POWER GOOD COMPARATOR
Undervoltage Threshold
Overvoltage Threshold
Output Low Voltage
Power Good Delay Time
Crowbar Trip Point
Crowbar Reset Point
Crowbar Delay Time
PWM OUTPUTS
VPWRGD(UV)
VPWRGD(OV)
VOL(PWRGD)
Relative to FBRTN
Relative to FBRTN
IPWRGD(SINK) = 4 mA
600
880
660
940
225
200
1.05
650
400
720
1000
400
mV
mV
mV
ns
V
mV
ns
VCROWBAR
tCROWBAR
Relative to FBRTN
Relative to FBRTN
Overvoltage to PWM going low
0.975
550
1.1
750
Output Low Voltage
Output High Voltage
VOL(PWM)
VOH(PWM)
160
5
500
mV
V
IPWM(SINK) = −400 µA
IPWM(SOURCE) = 400 µA
4.0
SUPPLY
DC Supply Current
UVLO Threshold Voltage
UVLO Hysteresis
5
6.9
0.9
10
7.3
1.1
mA
V
V
VUVLO
VCC rising
6.5
0.7
1 All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC).
2 Guaranteed by design or bench characterization, not tested in production.
Rev. 0 | Page 4 of 20
ADP3182
TEST CIRCUITS
ADP3182
1
V
12V
CC
CSCOMP
CSSUM
13
12
39kΩ
100nF
1kΩ
CSREF
GND
11
14
CSCOMP –0.8V
40
0.8V
VOS =
Figure 2. Current Sense Amplifier VOS
Rev. 0 | Page 5 of 20
ADP3182
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or
any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability. Absolute maximum ratings apply individually
only, not in combination. Unless otherwise specified, all other
voltages are referenced to GND.
Rating
VCC
FBRTN
EN, DELAY, ILIMIT, RT,
PWM1 to PWM3, COMP
SW1 to SW3
All Other Inputs and Outputs
Storage Temperature
Operating Ambient Temperature Range
Operating Junction Temperature
Thermal Impedance (θJA)
Lead Temperature
−0.3 V to +15 V
−0.3 V to +0.3 V
−0.3 V to 5.5 V
−5 V to +25 V
−0.3 V to VCC + 0.3 V
−65°C to +150°C
0°C to 85°C
125°C
100°C/W
Soldering (10 s)
Infrared (15 s)
300°C
260°C
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. 0 | Page 6 of 20
ADP3182
PIN CONFIGURATION AND FUNCTION DESCRIPTION
1
20
19
18
17
16
15
14
13
12
11
VCC
FBRTN
FB
PWM1
PWM2
PWM3
SW1
2
3
4
COMP
PWRGD
EN
ADP3182
5
SW2
TOP VIEW
(Not to Scale)
6
SW3
7
DELAY
RT
GND
8
CSCOMP
CSSUM
CSREF
9
RAMPADJ
ILIMIT
10
Figure 3. Pin Configuration
Table 3. Pin Function Descriptions
Pin No.
Mnemonic
Description
Supply Voltage for the Device.
Feedback Return. Voltage error amplifier reference for remote sensing of the output voltage.
Feedback Input. Error amplifier input for remote sensing of the output voltage. An external resistor divider
between the output and FBRTN connected to this pin sets the output voltage point. This pin is also the reference
point for the power good and crowbar comparators.
1
2
3
VCC
FBRTN
FB
4
5
COMP
PWRGD
Error Amplifier Output and Compensation Point.
Power Good Output. Open-drain output that signals when the output voltage is outside the proper operating
range.
6
7
EN
DELAY
Power Supply Enable Input. Pulling this pin to GND disables the PWM outputs and pulls the PWRGD output low.
Soft Start Delay and Current Limit Latch-Off Delay Setting Input. An external resistor and capacitor connected
between this pin and GND sets the soft start, ramp-up time and the overcurrent latch-off delay time.
8
RT
Frequency Setting Resistor Input. An external resistor connected between this pin and GND sets the oscillator
frequency of the device.
9
RAMPADJ
ILIMIT
PWM Ramp Current Input. An external resistor from the converter input voltage to this pin sets the internal
PWM ramp.
Current Limit Setpoint/Enable Output. An external resistor from this pin to GND sets the current limit threshold
of the converter. This pin is actively pulled low when the ADP3182’s EN input is low, or when VCC is below its
UVLO threshold, to signal to the driver IC that the driver high-side and low-side outputs should go low.
10
11
12
13
CSREF
Current Sense Reference Voltage Input. The voltage on this pin is used as the reference for the current sense
amplifier. This pin should be connected to the common point of the output inductors.
Current Sense Summing Node. External resistors from each switch node to this pin sum the average inductor
currents together to measure the total output current.
Current Sense Compensation Point. A resistor and a capacitor from this pin to CSSUM determines the gain of the
current sense amplifier.
CSSUM
CSCOMP
14
GND
Ground. All internal biasing and the logic output signals of the device are referenced to this ground.
15 to 17
SW3 to SW1
Current Balance Inputs. Inputs for measuring the current level in each phase. The SW pins of unused phases
should be left open.
18 to 20
PWM3 to
PMW1
Logic-Level PWM Outputs. Each output is connected to the input of an external MOSFET driver such as the
ADP3418. Connecting the PWM3 output to GND causes that phase to turn off, allowing the ADP3182 to operate
as a 1- or 2-phase controller.
Rev. 0 | Page 7 of 20
ADP3182
TYPICAL PERFORMANCE CHARACTERISTICS
5.4
5.3
5.2
5.1
5.0
4.9
4.8
4.7
3
T
= 25ºC
A
3-PHASE OPERATION
2
1
0
0
0.5
1.0
1.5
2.0
2.5
3.0
0
50
100
150
200
250
300
OSCILLATOR FREQUENCY (MHz)
R
VALUE (kΩ)
T
Figure 4. Master Clock Frequency vs. RT
Figure 5. Supply Current vs. Oscillator Frequency
Rev. 0 | Page 8 of 20
ADP3182
THEORY OF OPERATION
cycle is possible. Also, more than one output can be on at the
same time for overlapping phases.
The ADP3182 combines a multimode, fixed frequency PWM
control with multiphase logic outputs for use in 1-, 2-, and
3-phase, synchronous, buck, point-of-load supply power
converters. Multiphase operation is important for producing the
high currents and low voltages demanded by auxiliary supplies
in desktop computers, workstations, and servers. Handling the
high currents in a single-phase converter would place high
thermal demands on the components in the system, such as the
inductors and MOSFETs.
MASTER CLOCK FREQUENCY
The clock frequency of the ADP3182 is set with an external
resistor connected from the RT pin to ground. The frequency
follows the graph in Figure 4. To determine the frequency per
phase, the clock is divided by the number of phases in use. If
PWM3 is grounded, then divide the master clock by 2 for the
frequency of the remaining two phases.
The multimode control of the ADP3182 ensures a stable, high
performance topology for
It is important to note that if only one phase is used, the clock
will switch as if two phases were operating. This means that the
oscillator frequency must be set at twice the expected value to
program the desired PWM frequency.
•
•
Balancing currents and thermals between phases
High speed response at the lowest possible switching
frequency and output decoupling
OUTPUT VOLTAGE DIFFERENTIAL SENSING
•
Minimizing thermal switching losses due to lower
frequency operation
The ADP3182 uses a differential-sensing, low offset voltage error
amplifier. This maintains a worst-case specification of 2%
differential-sensing error over its full operating output voltage
and temperature range. The output voltage is sensed between
the FB and FBRTN pins. FB should be connected through a
resistor to the regulation point, usually the local bypass
capacitor for the load. FBRTN should be connected directly to
the remote sense ground point. The internal precision reference
is referenced to FBRTN, which has a minimal current of 100 µA
to allow accurate remote sensing. The internal error amplifier
compares the output of the reference to the FB pin to regulate
the output voltage.
•
•
•
•
Tight regulation and accuracy
Reduced output ripple due to multiphase cancellation
PC board layout noise immunity
Ease of use and design due to independent component
selection
•
Flexibility in operation for tailoring design to low cost or
high performance
START-UP SEQUENCE
During start-up, the number of operational phases and their
phase relationship is determined by the internal circuitry that
monitors the PWM outputs. Normally, the ADP3182 operates
as a 3-phase PWM controller. Grounding the PWM3 pin
programs 1/2-phase operation.
OUTPUT CURRENT SENSING
The ADP3182 provides a dedicated current sense amplifier
(CSA) to monitor the total output current for current limit
detection. Sensing the load current at the output gives the total
average current being delivered to the load, which is an
inherently more accurate method than peak current detection
or sampling the current across a sense element such as the low-
side MOSFET. This amplifier can be configured several ways
depending on the objectives of the system:
When the ADP3182 is enabled, the controller outputs a voltage
on PWM3 that is approximately 675 mV. An internal comparator
checks the pin’s voltage vs. a threshold of 300 mV. If the pin is
grounded, it is below the threshold and the phase is disabled.
The output resistance of the PWM pin is approximately 5 kΩ
during this detection time. Any external pull-down resistance
connected to the PWM pin should be more than 25 kΩ to
ensure proper operation. PWM1 and PWM2 are disabled
during the phase detection interval, which occurs during the
first two clock cycles of the internal oscillator. After this time, if
the PWM output is not grounded, the 5 kΩ resistance is
removed, and the PWM output switches between 0 V and 5 V. If
the PWM output is grounded, it remains off.
•
•
•
Output inductor DCR sensing without a thermistor for
lowest cost
Output inductor DCR sensing with a thermistor for
improved accuracy for tracking inductor temperature
Sense resistors for highest accuracy measurements
The positive input of the CSA is connected to the CSREF pin,
which is connected to the output voltage. The inputs to the
amplifier are summed together through resistors from the
sensing element (such as the switch node side of the output
inductors) to the inverting input, CSSUM. The feedback resistor
between CSCOMP and CSSUM sets the gain of the amplifier,
and a filter capacitor is placed in parallel with this resistor. The
The PWM outputs are logic-level devices intended for driving
external gate drivers such as the ADP3418. Because each phase
is monitored independently, operation approaching 100% duty
Rev. 0 | Page 9 of 20
ADP3182
gain of the amplifier is programmable by adjusting the feedback
resistor. The current information is then given as the difference
of CSREF − CSCOMP. This difference in signal is used as a
differential input for the current limit comparator.
SOFT START
The power-on, ramp-up time of the output voltage is set with a
capacitor and resistor in parallel from the DELAY pin to ground.
The RC time constant also determines the current limit latch-
off time as explained in the following section. In UVLO or
when EN is logic low, the DELAY pin is held at ground. After
the UVLO threshold is reached and EN is logic high, the
DELAY capacitor is charged with an internal 20 µA current
source. The output voltage follows the ramping voltage on the
DELAY pin, limiting the inrush. The soft start time depends on
To provide the best accuracy for sensing current, the CSA is
designed to have a low offset input voltage. In addition, the
sensing gain is determined by external resistors so that the gain
can be made extremely accurate.
CURRENT CONTROL MODE AND
THERMAL BALANCE
the value of CDLY, with a secondary effect from RDLY
.
The ADP3182 has individual inputs for each phase that are used
for monitoring the current in each phase. This information is
combined with an internal ramp to create a current balancing
feedback system, which has been optimized for initial current
balance accuracy and dynamic thermal balancing during
operation. This current balance information is independent of
the average output current information used for the current
limit described previously.
If either EN is taken low or VCC drops below UVLO, the
DELAY capacitor is reset to ground to prepare for another soft
start cycle. Figure 6 shows a typical soft start sequence for the
ADP3182.
The magnitude of the internal ramp can be set to optimize the
transient response of the system. It also monitors the supply
voltage for feed-forward control to compensate for changes in
the supply voltage. A resistor connected from the power input
voltage to the RAMPADJ pin determines the slope of the
internal PWM ramp. External resistors can be placed in series
with individual phases to create, if desired, an intentional
current imbalance such as when one phase may have better
cooling and can support higher currents. Resistors RSW1 through
RSW3 (see the typical application circuit in Figure 9) can be used
for adjusting thermal balance. Add placeholders for these
resistors during the initial layout so that adjustments can be made
after completing thermal characterization of the design.
Figure 6. Typical Start-Up Waveforms
Channel 1: CSREF, Channel 2: DELAY,
Channel 3: PWRGD, Channel 4: COMP
To increase the current in any given phase, increase RSW for that
phase (set RSW = 0 for the hottest phase and do not change it
during balancing). Increasing RSW to only 500 Ω substantially
increases the phase current. Increase each RSW value by small
amounts to achieve balance, starting with the coolest phase.
CURRENT LIMIT, SHORT-CIRCUIT, AND
LATCH-OFF PROTECTION
The ADP3182 compares a programmable current limit setpoint
to the voltage from the output of the current sense amplifier.
The level of current limit is set with the resistor from the ILIMIT
pin to ground. During normal operation, the voltage on ILIMIT
is 3 V. The current through the external resistor is internally
scaled to produce a current limit threshold of 10.4 mV/µA. If
the difference in voltage between CSREF and CSCOMP rises
above the current limit threshold, the internal current limit
amplifier controls the internal COMP voltage to maintain the
average output current at the limit.
VOLTAGE CONTROL MODE
A high gain-bandwidth voltage mode error amplifier is used for
the voltage-mode control loop. The control input voltage to the
positive input is derived from the internal 800 mV reference.
The output of the amplifier is the COMP pin, which sets the
termination voltage for the internal PWM ramps.
The negative input (FB) is tied to the center point of a resistor
divider from the output sense location. The main loop
compensation is incorporated into the feedback network
between FB and COMP.
Rev. 0 | Page 10 of 20
ADP3182
After the limit is reached, the 3 V pull-up on the DELAY pin is
disconnected, and the external delay capacitor is discharged
through the external resistor. A comparator monitors the DELAY
voltage and shuts off the controller when the voltage drops
below 1.8 V. The current limit latch-off delay time is therefore
set by the RC time constant discharging from 3 V to 1.8 V.
Typical overcurrent latch-off waveforms are shown in Figure 7.
Because the controller continues to cycle the phases during the
latch-off delay time, the controller returns to normal operation
if the short is removed before the 1.8 V threshold is reached.
The recovery characteristic depends on the state of PWRGD. If
the output voltage is within the PWRGD window, the controller
resumes normal operation. However, if a short circuit has
caused the output voltage to drop below the PWRGD threshold,
a soft start cycle is initiated.
Figure 7. Overcurrent Latch-Off Waveforms
Channel 1: CSREF, Channel 2: COMP,
Channel 3: Phase 1 Switch Node, Channel 4: DELAY
The latch-off function can be reset by either removing and
reapplying VCC to the ADP3182, or by pulling the EN pin low
for a short time. To disable the short-circuit latch-off function,
the external resistor to ground should be left open, and a high-
value (>1 MΩ) resistor should be connected from DELAY to
VCC. This prevents the DELAY capacitor from discharging, so
the 1.8 V threshold is never reached. The resistor has an impact
on the soft start time because the current through it adds to the
internal 20 µA current source.
During start-up when the output voltage is below 200 mV, a
secondary current limit is active. This is necessary because the
voltage swing of CSCOMP cannot go below ground. This
secondary current limit controls the internal COMP voltage to
the PWM comparators to 2 V. This limits the voltage drop
across the low-side MOSFETs through the current balance
circuitry.
Figure 8. Shutdown Waveforms
Channel 1: CSREF, Channel 2: DELAY,
Channel 3: PWRGD, Channel 4: COMP
An inherent per phase current limit protects individual phases
if one or more phases stop functioning because of a faulty
component. This limit is based on the maximum normal mode
COMP voltage.
OUTPUT CROWBAR
As part of the protection for the load and output components of
the supply, the PWM outputs are driven low (turning on the
low-side MOSFETs) when the output voltage exceeds the upper
crowbar threshold. This crowbar action stops once the output
voltage falls below the release threshold of approximately 650 mV.
POWER GOOD MONITORING
The power good comparator monitors the output voltage via the
FB pin. The PWRGD pin is an open-drain output whose high
level (when connected to a pull-up resistor) indicates that the
output voltage is within the nominal limits specified in the
electrical table. PWRGD goes low if the output voltage is
outside this specified range or the EN pin is pulled low. Figure 8
shows the PWRGD output response when the input power is
removed from the regulator.
Turning on the low-side MOSFETs pulls down the output as the
reverse current builds up in the inductors. If the output over-
voltage is due to a short in the high-side MOSFET, this action
limits the current of the input supply or blows the fuse to
protect the microprocessor from being destroyed.
Rev. 0 | Page 11 of 20
ADP3182
In the application circuit, the ILIMIT pin should be connected
to the pins of the ADP3418 drivers. The ILIMIT being
OUTPUT ENABLE AND UVLO
OD
For the ADP3182 to begin switching, the input supply (VCC) to
the controller must be higher than the UVLO threshold, and
the EN pin must be higher than its logic threshold. If UVLO is
less than the threshold or the EN pin is logic low, the ADP3182 is
disabled. This holds the PWM outputs at ground, shorts the
DELAY capacitor to ground, and holds the ILIMIT pin at ground.
grounded disables the drivers such that both DRVH and DRVL
are grounded. This feature is important in preventing the
discharge of the output capacitors when the controller is shut
off. If the driver outputs were not disabled, a negative voltage
could be generated during output due to the high current
discharge of the output capacitors through the inductors.
Rev. 0 | Page 12 of 20
ADP3182
L1
1µH
V
IN
12V
+
+
C5
4.7µF
C1
C2
2700µF
16V
V
IN
2700µF
16V
D2
RTN
C4
100nF
1N4148WS
U2
ADP3418
D1
Q1
NTD40N02
1
2
3
4
8
BST
DRVH
SW
1N4148WS
L2
1200µF/6.3V × 5
15mΩ ESR (EACH)
600nH/1.4mΩ
IN
OD
V
7
6
5
V
OUT
1.8V
55A
PGND
DRVL
+
+
C6
4.7nF
R1
2.2Ω
V
CC
OUT
C3
RTN
1µF
C17
C21
Q2
NTD110N02
C9
4.7µF
D3
4.7µF × 10
6.3V
MLCC
C8
100nF
1N4148WS
U3
ADP3418
Q3
1
2
3
4
8
BST
IN
DRVH
SW
NTD40N02
L3
7
6
5
600nH/1.4mΩ
OD
PGND
DRVL
C10
4.7nF
V
CC
C7
1µF
R2
2.2Ω
Q4
NTD110N02
C13
4.7µF
D4
C12
100nF
1N4148WS
U4
ADP3418
Q5
NTD40N02
1
2
3
4
8
BST
DRVH
SW
L4
600nH/1.4mΩ
IN
OD
V
7
6
5
PGND
DRVL
C14
4.7nF
CC
R3
C11
Q6
1µF
NTD110N02
2.2Ω
R4
10Ω
+
U1
ADP3182
C15
1µF
C16
33µF
R
R
332kΩ
1
2
3
4
20
PWM1
V
CC
FBRTN
FB
PWM2 19
PWM3 18
R
R
1.00kΩ
B1
R
A
6.04kΩ
C
R
FB
SW1
*
1.24kΩ
100pF
B2
17
16
15
14
13
12
11
COMP
PWRGD
EN
SW1
SW2
C
R
A
SW2
1.2nF
POWER
GOOD
*
5
6
7
R
SW3
*
SW3
ENABLE
R
R
PH1
R
PH2
PH3
DELAY
RT
GND
140kΩ
140kΩ
140kΩ
R
CS
C
R
100kΩ
DLY
DLY
8
9
CSCOMP
39nF
470kΩ
C
5.6nF
CS
R
T
258kΩ
RAMPADJ CSSUM
10 ILIMIT
CSREF
R
LIM
287kΩ
Figure 9. 1.8 V, 55 A Application Circuit
Rev. 0 | Page 13 of 20
ADP3182
APPLICATIONS
The design parameters for the typical high current point-of-
load dc/dc buck converter shown in Figure 9 are as follows:
The value for CDLY can be approximated using
⎛
⎜
⎝
⎞
⎟
⎟
⎠
VOUT
2 × RDLY
tSS
VOUT
⎜
(2)
CDLY = 20 μA −
×
•
•
•
•
•
•
•
Input voltage (VIN) = 12 V
VID setting voltage (VOUT) = 1.8 V
Duty cycle (D) = 0.15
where:
tSS is the desired soft start time.
Assuming an RDLY of 390 kΩ and a desired soft start time of 3
ms, CDLY is 36 nF.
The closest standard value for CDLY is 39 nF.
Output current IO = 55 A
Maximum output current (ILIM) = 110 A
Number of phases (n) = 3
Once CDLY is chosen, RDLY can be calculated for the current limit
latch-off time using
Switching frequency per phase (fSW) = 250 kHz
1.96 ×tDELAY
RDLY
=
(3)
CDLY
SETTING THE CLOCK FREQUENCY
The ADP3182 uses a fixed-frequency control architecture. The
frequency is set by an external timing resistor (RT). The clock
frequency and the number of phases determine the switching
frequency per phase, which relates directly to switching losses
and the sizes of the inductors and the input and output
capacitors. With n = 3 for three phases, a clock frequency of
750 kHz sets the switching frequency (fSW) of each phase to
250 kHz, which represents a practical trade-off between the
switching losses and the sizes of the output filter components.
Equation 1 shows that to achieve a 750 kHz oscillator frequency,
the correct value for RT is 256 kΩ. Alternatively, the value for RT
can be calculated using
If the result for RDLY is less than 200 kΩ, a smaller soft start time
should be considered by recalculating the equation for CDLY, or a
longer latch-off time should be used. RDLY should never be less
than 200 kΩ. In this example, a delay time of 9 ms results in
RDLY = 452 kΩ. The closest standard 5% value is 470 kΩ.
INDUCTOR SELECTION
The amount of inductance determines the ripple current in the
inductor. Less inductance leads to more ripple current, which
increases the output ripple voltage and conduction losses in the
MOSFETs, but allows using smaller inductors and, for a
specified peak- peak transient deviation, less total output
capacitance. Conversely, a higher inductance means lower
ripple current and reduced conduction losses, but requires
larger inductors and more output capacitance for the same
peak-peak transient deviation. In any multiphase converter, a
practical value for the peak-peak inductor ripple current is less
than 50% of the maximum dc current in the same inductor.
Equation 4 shows the relationship between the inductance,
oscillator frequency, and peak-peak ripple current in the
inductor.
1
RT =
RT =
−27 kΩ
(1)
n × fSW × 4.7 pF
1
− 27 kΩ = 256 kΩ
3 × 250 kHz × 4.7 pF
where 4.7 pF and 27 kΩ are internal IC component values. For
good initial accuracy and frequency stability, a 1% resistor is
recommended. The closest standard 1% value for this design is
258 kΩ.
Equation 5 can be used to determine the minimum inductance
based on a given output ripple voltage.
SOFT START AND CURRENT LIMIT LATCH-OFF
DELAY TIME
VOUT
×
(
1− D
)
IR
=
(4)
(5)
Because the soft start and current limit latch-off delay functions
share the DELAY pin, these two parameters must be considered
together. The first step is to set CDLY for the soft start ramp. This
ramp is generated with a 20 µA internal current source. The
value of RDLY has a second-order impact on the soft start time
because it sinks part of the current source to ground. However,
as long as RDLY is kept greater than 200 kΩ, this effect is minor.
fSW × L
VOUT × Rx × 1− n × D
L ≥
fSW ×VRIPPLE
where:
RX is ESR of output bulk capacitors.
Rev. 0 | Page 14 of 20
ADP3182
Solving Equation 5 for a 20 mV p-p output ripple and an RX of
Selecting a Standard Inductor
3 mΩ voltage yields
The following power inductor manufacturers can provide design
consultation and deliver power inductors optimized for high
power applications upon request.
1.8 V × 3 mΩ × 1−3×0.15
( )
L ≥
= 594 nH
250 kHz × 20 mV
•
•
•
•
Coilcraft
(847) 639-6400
www.coilcraft.com
If the resulting ripple voltage is too low, the level of inductance
can be decreased until the desired ripple value is met. This
allows optimal transient response and minimum output
decoupling.
Coiltronics
(561) 752-5000
www.coiltronics.com
The smallest possible inductor should be used to minimize the
number of output capacitors. For this example, choosing a
600 nH inductor is a good starting point that produces a
calculated ripple current of 6.6 A. The inductor should not
saturate at the peak current of 21.6 A and should be able to
handle the sum of the power dissipation caused by the average
current of 18.3 A in the winding and core loss.
Sumida Electric Company
(510) 668-0660
www.sumida.com
Vishay Intertechnology
(402) 563-6866
Another important factor in the inductor design is the DCR,
which is used for measuring the phase currents. A large DCR
can cause excessive power losses, whereas too small a value can
lead to increased measurement error. For this design, a DCR of
1.4 mΩ was chosen.
www.vishay.com
OUTPUT CURRENT SENSE
The output current can be measured by summing the voltage
across each inductor and passing the signal through a low-pass
filter. The CS amplifier is configured with resistors RPH(X) (for
summing the voltage), and RCS and CCS (for the low-pass filter).
The output current IO is set by the following equations:
Designing an Inductor
Once the inductance and DCR are known, the next step is to
either design an inductor or find a standard inductor that
comes as close as possible to meeting the overall design goals.
The first decision in designing the inductor is to choose the
core material. Several possibilities for providing low core loss at
high frequencies include the powder cores (e.g., Kool-Mµ® from
Magnetics, Inc., or from Micrometals) and the gapped soft
ferrite cores (e.g., 3F3 or 3F4 from Philips). Low frequency
powdered iron cores should be avoided, especially when the
inductor value is relatively low and the ripple current is high, due
to their high core loss.
RPH(x)
RCS
VDRP
RL
(6)
(7)
IO
=
×
L
CCS
≥
RL × RCS
where:
RL is the DCR of the output inductors.
DRP is the voltage drop from CSCOMP to CSREF.
V
When load current reaches its limit, VDRP is at its maximum
(VDRPMAX). VDRPMAX can be in the range of 100 to 200 mV. In this
example, it is 110 mV.
The best choice for a core geometry is a closed-loop type such
as a potentiometer core, a PQ, U, or E core, or a toroid core. A
good compromise between price and performance is a core with
a toroidal shape.
One has the flexibility of choosing either RCS or RPH(X). It is
recommended to select RCS equal to 100 kΩ, and then solve for
RPH(X) by rearranging Equation 6.
Many useful references for magnetics design are available for
quickly designing a power inductor, such as
•
Magnetic Designer Software
Intusoft (www.intusoft.com)
ILIM
VDRPMAX
RPH = RL × RCS
×
x
( )
•
Designing Magnetic Components for High-Frequency DC-
DC Converters, by William T. McLyman, Kg Magnetics,
Inc., ISBN 1883107008
110A
110 mV
RPH x =1.4 mΩ ×100 kΩ ×
=140 kΩ
(
)
Rev. 0 | Page 15 of 20
ADP3182
RDS(SF) (per MOSFET) < 7.5 mΩ. This RDS(SF) is also at a junction
temperature of about 120°C, so one must account for this when
making this selection. This example uses a lower-side MOSFET
with 4.8 mΩ at 120°C.
The closest standard 1% value for RPH(X) is 140 kΩ. Next, use
Equation 7 to solve for CCS.
600 nH
CCS
≥
≥ 4.29 nF
1.4 mΩ ×100 kΩ
Another important factor for the synchronous MOSFET is the
input capacitance and feedback capacitance. The ratio of
feedback to input must be small (less than 10% is recom-
mended) to prevent accidentally turning on the synchronous
MOSFETs when the switch node goes high.
Choose the closest standard value that is greater than the result
given by Equation 7. This example uses a CCS value of 5.6 nF.
OUTPUT VOLTAGE
ADP3182 has an internal FBRTN voltage reference VREF of
800 mV. The output voltage can be set up using a voltage
divider made up of resistors RB1 and RB2:
Also, the time to switch the synchronous MOSFETs off should
not exceed the nonoverlap dead time of the MOSFET driver
(40 ns typical for the ADP3418). The output impedance of the
driver is approximately 2 Ω, and the typical MOSFET input gate
resistances are about 1 Ω to 2 Ω; therefore, one should adhere to
a total gate capacitance of less than 6000 pF. Because there are
two MOSFETs in parallel, the input capacitance for each
synchronous MOSFET should be limited to 3000 pF.
R
B1 + RB2
RB1
(8)
VOUT
=
×VREF
Rearranging Equation 8 to solve for RB2 using the ADP3182
with an internal FB voltage of 800 mV and assuming a 1%, 1 kΩ
resistor for RB1 yields
The high-side (main) MOSFET must handle two main power
dissipation components: conduction and switching losses. The
switching loss is related to the amount of time for the main
MOSFET to turn on and off, and to the current and voltage that
are being switched. Basing the switching speed on the rise and
fall time of the gate driver impedance and MOSFET input
capacitance, the following expression provides an approximate
value for the switching loss per main MOSFET:
⎛
⎜
⎜
⎝
⎞
⎟
⎠
1.8 V
0.8 V
⎛
⎜
⎜
⎝
⎞
⎟
⎠
VOUT
VREF
⎟
⎟
RB2
=
−1 × RB1
=
−1 ×1 kΩ =1.25 kΩ
The closest standard 1% resistor value for RB2 is 1.24 kΩ.
POWER MOSFETS
For this example, one high-side, N-channel power MOSFET
and two low-side, N-channel power MOSFETs per phase have
been selected. The main selection parameters for the power
MOSFETs are VGS(TH), QG, CISS, CRSS, and RDS(ON). The minimum
gate drive voltage (the supply voltage to the ADP3418) dictates
whether standard threshold or logic-level threshold MOSFETs
must be used. With VGATE ~10 V, logic-level threshold MOSFETs
(VGS(TH) < 2.5 V) are recommended.
VCC × IO
nMF
nMF
n
P (
= 2 × fSW
MF
)
×
× RG ×
× CISS
(10)
S
where:
MF is the total number of main MOSFETs.
RG is the total gate resistance (2 Ω for the ADP3418 and about
1 Ω for typical high speed switching MOSFETs, making RG = 3 Ω).
ISS is the input capacitance of the main MOSFET.
n
C
The maximum output current (IO) determines the RDS(ON)
requirement for the low-side (synchronous) MOSFETs. With
the ADP3182, currents are balanced between phases, thus the
current in each low-side MOSFET is the output current divided
by the total number of MOSFETs (nSF). With conduction losses
being dominant, the following expression shows the total power
being dissipated in each synchronous MOSFET in terms of the
ripple current per phase (IR) and the average total output current
(IO):
Note that adding more main MOSFETs (nMF) does not help the
switching loss per MOSFET because the additional gate
capacitance slows switching. The most efficient way to reduce
switching loss is to use lower gate capacitance devices.
The conduction loss of the main MOSFET is given by the
following equation:
2
2
⎡
⎢
⎤
⎥
n × I
⎛
⎜
⎜
⎝
⎞
⎟
⎟
⎠
⎛
⎜
⎜
⎝
⎞
⎟
⎟
⎠
IO
nMF
1
12
R
2
2
PC
= D ×
+
×
×RDS
MF
( )
(11)
(
MF
)
⎡
⎢
⎤
⎥
⎛
⎜
⎜
⎝
⎞
⎟
⎟
⎠
⎛
⎜
⎜
⎝
⎞
⎟
⎟
⎠
n IR
nSF
IO
1
12
nMF
⎢
⎣
⎥
⎦
P
=
(1− D
)
×
+
×
× RDS
(9)
SF
(
SF )
nSF
⎢
⎣
⎥
⎦
where:
DS(MF) is the on resistance of the MOSFET.
R
Knowing the maximum output current and the maximum
allowed power dissipation, one can determine the required
Typically, for main MOSFETs, the highest speed (low CISS)
device is preferred, but faster devices usually have higher on
resistance. Select a device that meets the total power dissipation
RDS(ON) for the MOSFET. For D-PAK MOSFETs up to an
ambient temperature of 50°C, a safe limit for PSF is 1 W to 1.5 W
at 120°C junction temperature. Therefore, for this example,
Rev. 0 | Page 16 of 20
ADP3182
(about 1.5 W for a single D-PAK) when combining the
switching and conduction losses.
The internal ramp voltage magnitude can be calculated by using
AR ×
(
1− D
)×VOUT
VR =
For this example, an NTD40N03L was selected as the main
MOSFET (three total; nMF = 3), with a CISS = 584 pF (max) and
RDS(MF) = 19 mΩ (max at TJ = 120°C), and an NTD110N02L was
selected as the synchronous MOSFET (three total; nSF = 3), with
RR × CR × fSW
(14)
0.2 ×
1−0.15 ×1.8 V
( )
VR =
= 737 m V
332 kΩ × 5 pF × 250 kHz
CISS = 2710 pF (max) and RDS(SF) = 4.8 mΩ (max at TJ = 120°C).
The synchronous MOSFET CISS is less than 3000 pF, satisfying
that requirement. Solving for the power dissipation per MOSFET
at IO = 55 A and IR = 6.6 A yields 894 mW for each synchronous
MOSFET and 1.16 W for each main MOSFET. These numbers
comply with the guideline to limit the power dissipation to
around 1 W per MOSFET.
The size of the internal ramp can be made larger or smaller. If it
is made larger, stability and transient response improve, but
thermal balance degrades. Likewise, if the ramp is made
smaller, thermal balance improves but transient response and
stability degrade. The factor of three in the denominator of
Equation 13 sets a ramp size with optimal balance for good
stability, transient response, and thermal balance.
One last thing to consider is the power dissipation in the driver
for each phase. This is best described in terms of the QG for the
MOSFETs and is given by the following equation:
CURRENT LIMIT SETPOINT
To select the current limit setpoint, first find the resistor value
for RLIM. The current limit threshold for the ADP3182 is set
with a 3 V source (VLIM) across RLIM with a gain of 10.4 mV/µA
(ALIM). RLIM can be found using
⎡
⎢
⎤
fSW
2 × n
PDRV
=
×
(
nMF × QGMF + nSF × QGSF
)
+ ICC × V
⎥
CC
⎢
⎥
⎦
⎣
(12)
ALIM ×VLIM
where:
RLIM
=
(15)
VDRPMAX
Q
Q
GMF is the total gate charge for each main MOSFET.
GSF is the total gate charge for each synchronous MOSFET.
For values of RLIM greater than 500 kΩ, the current limit may be
lower than expected and therefore necessitate some adjustment of
LIM. Here, ILIM is the average current limit for the output of the
supply. In this example, using the VDRPMAX value of 110 mV from
Equations 6 and 7 and choosing a peak current limit of 110 A
for ILIM results in RLIM = 284 kΩ, for which 287 kΩ is chosen as
the nearest 1% value.
Also shown is the standby dissipation factor (ICC × VCC) for the
driver. For the ADP3418, the maximum dissipation should be
less than 400 mW. In this example, with ICC = 7 mA, QGMF
9 nC, and QGSF = 46 nC, there is 165 mW in each driver, which
is below the 400 mW dissipation limit. See the ADP3418 data
sheet for more details.
R
=
The limit of the per phase current limit described earlier is
determined by
RAMP RESISTOR SELECTION
The ramp resistor (RR) is used for setting the size of the internal
PWM ramp. The value of this resistor is chosen to provide the
best combination of thermal balance, stability, and transient
response. The following expression is used to determine the
optimum value:
VCOMP
) −VR −VBIAS
MAX
IR
2
(
IPHLIM
≅
+
(16)
AD × RDS
(
MAX
)
FEEDBACK LOOP COMPENSATION DESIGN
Optimized compensation of the ADP3182 allows the best
AR × L
RR
=
possible response of the regulator’s output to a load change. The
basis for determining the optimum compensation is to make
the regulator and output decoupling appear as an output
impedance that is entirely resistive over the widest possible
frequency range, including dc.
3 × AD × RDS(ON)(SF) × CR
(13)
0.2 × 600 nH
RR
=
= 333 kΩ
3 × 5 × 4.8 mΩ × 5 pF
With the multimode feedback structure of the ADP3182, the
feedback compensation must be set so that the converter’s
output impedance, working in parallel with the output
decoupling, will meet this goal. One will need to compensate for
the several poles and zeros created by the output inductor and
decoupling capacitors (output filter).
where:
AR is the internal ramp amplifier gain.
AD is the current balancing amplifier gain.
R
DS(ON)(SF) is the total low-side MOSFET on resistance.
CR is the internal ramp capacitor value.
The closest standard 1% resistor value is 332 kΩ.
Rev. 0 | Page 17 of 20
ADP3182
A type three compensator on the voltage feedback is adequate
for proper compensation of the output filter. Equations 20 to 22
are intended to yield an optimal starting point for the design;
some adjustments may be necessary to account for PCB and
component parasitic effects.
INDUCTOR DCR TEMPERATURE CORRECTION
With the inductor’s DCR being used as the sense element and
copper wire being the source of the DCR, one needs to
compensate for temperature changes in the inductor’s winding
if a highly accurate safety current limit setpoint is desired.
Fortunately, copper has a well-known temperature coefficient
(TC) of 0.39%/°C.
CX ×RX
4×RB2
n×RX
(17)
CA
=
×
VR
VOUT
×RL + AD ×RDS
If RCS is designed to have an opposite and equal percentage of
change in resistance to that of the wire, it cancels the tempera-
ture variation of the inductor’s DCR. Due to the nonlinear
nature of NTC thermistors, resistors RCS1 and RCS2 are needed.
See Figure 10 for instructions on how to linearize the NTC and
produce the desired temperature tracking.
⎛
⎞
⎟
L V
×
AD ×R
DS
RX ×VOUT 2× fSW ×RX
4 R
n×CX ×RX
×
B2
R
⎜
(18)
(19)
RA
=
×
−
⎜
⎟
⎠
⎝
1
CFB
=
2×n× fSW ×RA
PLACE AS CLOSE AS POSSIBLE
TO NEAREST INDUCTOR
If CX is 6000 µF (five 1200 µF capacitors in parallel) with an
equivalent ESR of 3 mΩ, the equations above give the following
compensation values:
TO
OR LOW-SIDE MOSFET
TO
V
SWITCH
NODES
OUT
R
TH
SENSE
CA = 1.33 nF
RA = 6.05 kΩ
CFB = 110 pF
R
R
PH2
R
PH1
PH3
ADP3182
R
R
CSCOMP
CS2
CS1
18
17
16
C
C
CS2
CS1
KEEP THIS PATH
Using the nearest standard value for each of these components
yields CA = 1.2 nF, RA = 6.04 kΩ, and CFB = 100 pF.
CSSUM
CSREF
AS SHORT AS POSSIBLE
AND WELL AWAY FROM
SWITCH NODE LINES
INPUT CAPACITOR SELECTION AND
INPUT CURRENT di/dt
Figure 10. Temperature Compensation Circuit Values
In continuous inductor current mode, the source current of the
high-side MOSFET is approximately a square wave with a duty
ratio equal to n × VOUT/VIN and an amplitude of one-nth the
maximum output current. To prevent large voltage transients, a
low ESR input capacitor, sized for the maximum rms current,
must be used. The maximum rms capacitor current is given by
The following procedures and expressions yield values to use
for RCS1, RCS2, and RTH (the thermistor value at 25°C) for a given
RCS value.
1. Select an NTC based on type and value. Because we do not
have a value yet, start with a thermistor with a value close
to RCS. The NTC should also have an initial tolerance of
better than 5%.
1
ICRMS = D × IO
×
−1
N × D
(20)
2. Based on the type of NTC, find its relative resistance value
at two temperatures. The temperatures that work well are
50°C and 90°C. These resistance values are called A
(RTH(50°C)/RTH(25°C)) and B (RTH(90°C)/RTH(25°C)). Note that the
NTC’s relative value is always 1 at 25°C.
1
ICRMS = 0.15 × 55 A ×
−1 = 9.1A
3 × 0.15
Note that manufacturers often base capacitor ripple current
rating on only 2,000 hours of life. Therefore, it advisable to
3. Find the relative value of RCS required for each of these
temperatures. This is based on the percentage of change
needed, which in this example is initially 0.39%/°C. These
are called r1 (1/(1 + TC × (T1 − 25))) and r2 (1/(1 + TC ×
(T2 − 25))), where TC = 0.0039 for copper. T1 = 50°C and
T2 = 90°C are chosen. From this, one can calculate that r1 =
0.9112 and r2 = 0.7978.
further derate the capacitor or to choose a capacitor rated at a
higher temperature than required. Several capacitors may be
placed in parallel to meet size or height requirements in the
design. In this example, the input capacitor bank is formed by
two 2,700 µF, 16 V aluminum electrolytic capacitors and three
4.7 µF ceramic capacitors.
To reduce the input current di/dt to a level below the recom-
mended maximum of 0.1 A/µs, an additional small inductor
(L > 370 nH @ 10 A) can be inserted between the converter and
the supply bus. That inductor also acts as a filter between the
converter and the primary power source.
4. Compute the relative values for RCS1, RCS2, and RTH using
(
A − B
)
× r1 × r2 − A ×
(1− B
)
× r2 + B ×
(
1− A
)
× r1
(21)
rCS2
=
A × 1− B × r1 − B ×
(
)
(
1− A
)
× r2 −
(
A − B
)
Rev. 0 | Page 18 of 20
ADP3182
keep short and away from other traces are the FB and CSSUM
pins. The output capacitors should be connected as close as
possible to the load or connector. If the load is distributed, the
capacitors should also be distributed and generally be in pro-
portion to where the load tends to be more dynamic. Avoid
crossing any signal lines over the switching power path loop,
described in the following section.
(
1− A
)
rCS1
=
=
(22)
(23)
1
A
−
1−rCS2 r1 −rCS2
1
rTH
1
1
−
1−rCS2 rCS1
5. Calculate RTH = rTH × RCS, then select the closest value of
thermistor available. Also, compute a scaling factor k based
on the ratio of the actual thermistor value used relative to
the computed one:
Power Circuitry Recommendations
To minimize radiated switching noise energy (i.e., EMI) and
conduction losses in the board, the switching power path should
be routed on the PCB to encompass the shortest possible length.
Failure to take proper precautions often results in EMI problems
for the entire PC system as well as noise-related operational
problems in the power-converter control circuitry. The switching
power path is the loop formed by the current path through the
input capacitors and the power MOSFETs, including all inter-
connecting PCB traces and planes. Using short and wide
interconnection traces is especially critical in this path for two
reasons: it minimizes the inductance in the switching loop,
which can cause high energy ringing, and it accommodates the
high current demand with minimal voltage loss.
RTH
(
ACTUAL)
k =
(24)
RTH
(
CALCULATED)
6. Calculate values for RCS1 and RCS2 using
RCS1 = RCS × k ×rCS1 (25)
RCS2 = RCS
×
(
1−k
)
+ k ×rCS2
(26)
LAYOUT AND COMPONENT PLACEMENT
The following guidelines are recommended for optimal
performance of a switching regulator in a PC system.
When a power-dissipating component, for example, a power
MOSFET, is soldered to a PCB, the liberal use of vias, both
directly on the mounting pad and immediately surrounding it,
is recommended. Two important reasons for this are improved
current rating through the vias and improved thermal
performance from vias that extend to the opposite side of the
PCB, where a plane can more readily transfer the heat to the air.
To optimize thermal dissipation, make a mirror image of the
pads in use to heat sink the MOSFETs on the opposite side of
the PCB. To further improve thermal performance, use the
largest possible pad area.
General Recommendations
For good results, a PCB with at least four layers is recommended.
This should allow the needed versatility for control circuitry
interconnections with optimal placement, power planes for
ground, input and output power, and wide interconnection
traces in the remainder of the power delivery current paths.
Keep in mind that each square unit of 1 ounce copper trace
has a resistance of ~0.53 mΩ at room temperature.
When high currents must be routed between PCB layers, vias
should be used liberally to create several parallel current paths
so that the resistance and inductance introduced by these current
paths is minimized and the via current rating is not exceeded.
The output power path should also be routed to encompass a
short distance. The output power path is formed by the current
path through the inductor, the output capacitors, and the load.
If critical signal lines (including the output voltage sense lines of
the ADP3182) must cross through power circuitry, a signal
ground plane should be interposed between those signal lines
and the traces of the power circuitry. This serves as a shield to
minimize noise injection into the signals at the expense of
making the signal ground a bit noisier.
For best EMI containment, a solid power ground plane should
be used as one of the inner layers, extending fully under all the
power components.
Signal Circuitry Recommendations
The output voltage is sensed and regulated between the FB pin
and the FBRTN pin, which connect to the signal ground at the
load. To avoid differential mode noise pickup in the sensed signal,
the loop area should be small. Therefore, the FB and FBRTN
traces should be routed adjacent to each other on top of the
power ground plane back to the controller. The feedback traces
from the switch nodes should be connected as close as possible
to the inductor. The CSREF signal should be connected to the
output voltage at the nearest inductor to the controller.
An analog ground plane should be used around and under the
ADP3182 as a reference for the components associated with the
controller. This plane should be tied to the nearest output de-
coupling capacitor ground, but it should not be tied to any other
power circuitry to prevent power currents from flowing in it.
The components around the ADP3182 should be located close
to the controller with short traces. The most important traces to
Rev. 0 | Page 19 of 20
ADP3182
OUTLINE DIMENSIONS
0.341
BSC
20
1
11
10
0.154
BSC
0.236
BSC
PIN 1
0.065
0.049
0.069
0.053
8°
0°
0.010
0.004
0.025
BSC
0.012
0.008
SEATING
PLANE
0.050
0.016
0.010
0.006
COPLANARITY
0.004
COMPLIANT TO JEDEC STANDARDS MO-137AD
Figure 11. 20-Lead Shrink Small Outline Package [QSOP]
(RQ-20)
Dimensions shown in inches
ORDERING GUIDE
Model
ADP3182JRQZ-RL1
Temperature Range
0°C to 85°C
Package Description
Package Option
Quantity per Reel
Shrink SOIC 13” Reel
RQ-20
2500
1 Z = Pb-free part.
©
2004 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D04938–0–10/04(0)
Rev. 0 | Page 20 of 20
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