ADP5014_技术文档

Integrated Power Solution

with Quad Low Noise Buck Regulators

Data Sheet

ADP5014

FEATURES

TYPICAL APPLICATION CIRCUIT

Input voltage range: 2.75 V to 6.0 V

ADP5014

VREF

R

RT

Programmable output voltage range: 0.5 V to 0.9 × PVINx

Low output noise: ~25 μV rms when V_OUT≤ V_REF

1.0ꢀ output accuracy over full temperature range

500 kHz to 2.5 MHz adjustable switching frequency

Power regulation

Channel 1 and Channel 2: programmable 2 A/4 A sync

buck regulators, or single 8 A output in parallel

Channel 3 and Channel 4: programmable 1 A/2 A sync

buck regulators, or single 4 A output in parallel

Flexible parallel operation

C1

OSC

REF

EN1/ENALL

EN2/DL12

EN3/UV

CFG1

CFG2

GPIO

LOGIC DECODER

EN4/DL34

AVIN

FB1

2.75V TO 6.0V

PVIN1

SW1

C2

L1

CH 1

LOW-NOISE BUCK

(2A/4A)

VOUT1

C3

PVIN1

VSET1

VREF

PGND1

COMP1

PVIN2

FB2

Precision enable with 0.6 V threshold

Manual or sequence mode for power-up and power-down

sequence

SW2

C4

CH 2

LOW-NOISE BUCK

(2A/4A)

L2

VOUT2

C5

VREF

VSET2

PGND2

Selective FPWM or PSM operation mode

Precision undervoltage comparator

Frequency synchronization input or output

Active output discharge switch

Power-good flag on selective channels via factory fuse

UVLO, OVP, OCP, and TSD protection

COMP2

PVIN3

L3

VOUT3

C7

SW3

FB3

C6

VREF

CH 3

VSET3

LOW-NOISE BUCK

(1A/2A)

PGND3

COMP3

40-lead, 6 mm × 6 mm LFCSP package

−40°C to +125°C junction temperature

PVIN4

L4

VOUT4

C9

SW4

FB4

C8

VREF

CH 4

LOW-NOISE BUCK

(1A/2A)

VSET4

APPLICATIONS

PGND4

COMP4

RF transceiver, high speed analog-to-digital converter

(ADC)/digital-to-analog converter (DAC), mixed signal ASIC

FPGA and processor applications

AGND

EXPOSED PAD

Security and surveillance

Figure 1.

Medical applications

GENERAL DESCRIPTION

The ADP5014 combines four high performance, low noise

buck regulators in a 40-lead LFCSP package. Relying on its low

output noise (~25 μV rms when V_OUT≤ V_REF), the low noise

buck regulator enables the powering up of the noise sensitive

signal chain products.

The ADP5014 features two enable modes. The manual mode

has four individual precision enable pins to enable each

regulator manually. Alternatively, the sequence mode has one

grouped precision enable signal with programmable power-up

and power-down delay timers on each rail for specific rail

sequence requirements.

All channels in the ADP5014 integrate high-side and low-side

power metal-oxide semiconductor field effect transistors

(MOSFET). Channel 1 and Channel 2 deliver a programmable

output current of 2 A or 4 A. Combining Channel 1 and

Channel 2 in a parallel configuration provides a single output

with up to 8 A of current.

The switching frequency of the ADP5014 can be programmed

or synchronized to an external clock from 500 kHz to 2.5 MHz.

The ADP5014 offers other key features like selective forced

pulse width modulation (FPWM)/power saving mode (PSM),

an undervoltage output (UVO), active output discharge, and a

power-good flag. Other safety features include input under-

voltage lockout (UVLO), overvoltage protection (OVP),

overcurrent protection (OCP) and thermal shutdown (TSD).

Channel 3 and Channel 4 deliver a programmable output current

of 1 A or 2 A. Combining Channel 3 and Channel 4 in a parallel

configuration can provide a single output with up to 4 A of

current.

Rev. A

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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Technical Support

www.analog.com

ADP5014

Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

Overvoltage Protection.............................................................. 20

Undervoltage Lockout ............................................................... 20

Active Output Discharge Switch .............................................. 21

Thermal Shutdown .................................................................... 21

Applications Information .............................................................. 22

ADIsimPower Design Tool ....................................................... 22

Programming the Output Voltage ........................................... 22

Voltage Conversion Limitations............................................... 22

Current-Limit Setting................................................................ 23

Soft Start Setting......................................................................... 23

Inductor Selection ...................................................................... 23

Output Capacitor Selection....................................................... 24

Input Capacitor Selection.......................................................... 24

Programming the UVLO Input................................................ 24

Compensation Components Design ....................................... 24

Power Dissipation....................................................................... 25

Junction Temperature................................................................ 26

Design Examples ............................................................................ 27

Setting the Switching Frequency.............................................. 27

Setting the Output Voltage........................................................ 27

Setting the Configuations (CFG1 and CFG2)........................ 27

Selecting the Inductor................................................................ 27

Selecting the Output Capacitor ................................................ 28

Designing the Compensation Network................................... 28

Low Noise Output Design......................................................... 28

PCB Layout Recommendations.................................................... 30

Typical Application Circuits ......................................................... 31

Factory Programmable Options................................................... 33

Factory Default Options............................................................ 33

Outline Dimensions....................................................................... 34

Ordering Guide .......................................................................... 34

Applications....................................................................................... 1

Typical Application Circuit ............................................................. 1

General Description......................................................................... 1

Revision History ............................................................................... 2

Detailed Functional Block Diagram .............................................. 3

Specifications..................................................................................... 4

Buck Regulator Specifications .................................................... 5

Absolute Maximum Ratings............................................................ 7

Thermal Resistance ...................................................................... 7

ESD Caution.................................................................................. 7

Pin Configuration and Function Descriptions............................. 8

Typical Performance Characteristics ........................................... 10

Theory of Operation ...................................................................... 14

Buck Regulator Operational Modes......................................... 14

Low Noise Architecture............................................................. 14

Internal Reference (VREF)........................................................ 14

Adjustable Output Voltage ........................................................ 14

Function Configurations (CFG1 and CFG2) ......................... 15

Parallel Operation....................................................................... 16

Manual/Sequence Mode............................................................ 16

General Purpose Input/Output (GPIO).................................. 18

Oscillator ..................................................................................... 18

Synchronization Input/Output................................................. 19

Power-Good Function ............................................................... 19

UV Comparator (Sequence Mode Only) ................................ 19

Soft Start ...................................................................................... 20

Startup with Precharged Output .............................................. 20

Current-Limit Protection .......................................................... 20

Frequency Fold Back.................................................................. 20

Short-Circuit Protection (SCP) ................................................ 20

REVISION HISTORY

8/2019—Rev. 0 to Rev. A

6/2017—Revision 0: Initial Version

Changes to Parallel Operation Section........................................ 16

Updated Outline Dimensions ....................................................... 34

Rev. A | Page 2 of 34

Data Sheet

ADP5014

DETAILED FUNCTIONAL BLOCK DIAGRAM

CHANNEL 1 – BUCK

UVLO1

PVIN1

EN1/ENALL

EN_BUF

+

–

+

0.6V

3µA

A_CS1

–

1µA

+

–

HICCUP

MODE

PVIN1

CLK1

Q1

Q2

OCP

DRIVER

SLOPE

COMP

+

CMP1

–

SW1

COMP1

VSET1

PVIN1

CONTROL LOGIC

AND MOSFET

DRIVER WITH

ANTICROSS

+

DRIVER

EA1

–

CLK1

PROTECTION

PGND1

FREQ

FOLDBACK

ZERO

CROSS

FB1

OVP

LATCH-UP

–

+

NEG CURRENT

CMP

0.9

1.15

PWRGD1

VID1

+

–

CURRENT BALANCE

EN2/DL12

COMP2

PVIN2

SW2

CHANNEL 2 – BUCK

DUPLICATE

CHANNEL 1

VSET2

FB2

PGND2

OSCILLATOR

RT

CLK

CFG1

CFG2

HOUSE-KEEPING

LOGIC

FUNCTION

DECODER

REF

VREF

AVIN

UVLO

GPIO

CHANNEL 3 – BUCK

UVLO3

PVIN3

EN_BUF

EN3/UV

+

–

+

0.6V

3µA

A_CS3

–

1µA

+

HICCUP

MODE

PVIN3

CLK3

Q5

–

OCP

DRIVER

SLOPE

COMP

+

CMP3

SW3

–

PVIN3

COMP3

VSET3

Q6

CONTROL LOGIC

AND MOSFET

DRIVER WITH

ANTICROSS

+

DRIVER

EA3

–

CLK3

PGND3

PROTECTION

FREQ

FOLDBACK

ZERO

CROSS

FB3

OVP

LATCH-UP

–

+

NEG CURRENT

CMP

0.9

1.15

PWRGD3

VID3

+

–

CURRENT BALANCE

PVIN4

SW4

EN4/DL34

COMP4

VSET4

FB4

CHANNEL 4 – BUCK

DUPLICATE

CHANNEL 3

PGND4

Figure 2.

Rev. A | Page 3 of 34

ADP5014

Data Sheet

SPECIFICATIONS

V_IN= 5 V, T _J= −40°C to +125°C for minimum and maximum specifications, and T_A= 25°C for typical specifications, unless otherwise noted.

Table 1.

Parameter

Symbol

Min

Typ

Max

Unit

Test Conditions/Comments

INPUT SUPPLY VOLTAGE RANGE

V_IN

2.75

6.0

V

AVIN, PVIN1, PVIN2, PVIN3,

PVIN4 pins

QUIESCENT CURRENT

AVIN, PVIN1, PVIN2, PVIN3,

PVIN4 pins

Operating Quiescent Current

Shutdown Current

I_Q

I_SHDN

UVLO

5.4

47

7.0

85

mA

µA

No switching, all ENx pins high

All ENx pins low

UNDERVOLTAGE LOCKOUT

AVIN, PVIN1, PVIN2, PVIN3,

PVIN4 pins

Threshold, Rising

Threshold, Falling

Hysteresis

V_UVLO-RISING

V_UVLO-FALLING

V_HYS

2.65

2.40

0.25

2.75

V

2.30

REFERENCE

Output Voltage

V_REF

2.0

V

Accuracy

Maximum Load

−1.0

1

+1.0

%

mA

OSCILLATOR CIRCUIT

Switching Frequency Range

Switching Frequency

Sync Input

500

1000

2500

1400

kHz

f_SW

1200

R_RT= 82.5 kΩ

Input Clock Range

Input Clock Pulse Width

Minimum On Time

Minimum Off Time

Input Clock High Voltage

Input Clock Low Voltage

Sync Output

f_SYNC

500

2500

kHz

t_{SYNC_MIN_ON}

t_{SYNC_MIN_OFF}

V_H(SYNC)

100

1.3

ns

V

V_L(SYNC)

0.4

V

Clock Frequency

Positive Pulse Duty Cycle

Rise or Fall Time

f_CLK

f_SW

50

10

V_AVIN

kHz

%

ns

V

t_{CLK_PULSE_DUTY}

t_{CLK_RISE_FALL}

V_{H(SYNC_OUT)}

High Level Voltage

PRECISION ENABLING

High Level Threshold

Low Level Threshold

Source Current

EN1, EN2, EN3, EN4 pins

V_{TH_H(EN)}

V_{TH_L(EN)}

I_{TH_L(EN)}

0.6

0.57

4

0.65

48

V

µA

0.52

6

Below the falling threshold

DELAY TIMER

Programmable Delay Timer Range

Delay Timer

t_DELAY

ms

6

48

Timer ×1 option

Timer ×8 option

POWER GOOD

Internal Power-Good Rising Threshold V_PWRGD(RISE)

87

90

3

50

2

16

0.1

70

93

%

µs

ms

µA

mV

Internal Power-Good Hysteresis

Internal Power-Good Falling Delay

Rising Delay for PWRGD Pin

V_PWRGD(HYS)

t_{PWRGD_FALL}

t_{PWRGD_PIN_RISE}

Timer ×1 option

Timer ×8 option

Leakage Current for PWRGD Pin

Output Low Voltage for PWRGD Pin

I_{PWRGD_LEAKAGE}

V_{PWRGD_LOW}

1

150

I_PWRGD= 1 mA

Rev. A | Page 4 of 34

Data Sheet

ADP5014

Parameter

Symbol

Min

Typ

Max

Unit

Test Conditions/Comments

THERMAL SHUTDOWN

Thermal Shutdown Threshold

Thermal Shutdown Hysteresis

T_SHDN

T_HYS

150

15

°C

BUCK REGULATOR SPECIFICATIONS

V_IN= 5 V, f _SW= 1.2 MHz for all channels, T_J= −40°C to +125°C for minimum and maximum specifications, and T_A= 25°C for typical

specifications, unless otherwise noted.

Table 2.

Parameter

Symbol

Min

Typ

Max

Unit

Test Conditions/Comments

CHANNEL 1 SYNC BUCK REGULATOR

Load Current

I_LOAD1

4

A

Output Characteristics

V_FB1Voltage Accuracy

−40°C ≤ T_J≤ +125°C

V_SET1= V_REF

V_SET1= ½ × V_REF

V_FB1

−0.6

−1.0

+0.6

+1.0

0.1

%

µA

μA

Feedback Bias Current

VSET1 Bias Current

SW1 Pin

I_FB1

I_VSET1

0.1

High-Side Power Field Effect

Transistor (FET) On Resistance

Low-Side Power FET

On Resistance

R_DS(ON)1H

R_DS(ON)1L

I_TH(ILIM1)

49

37

80

60

mΩ

Pin to pin measurement

Current-Limit Threshold

5.2

2.5

6.9

3.5

60

8.6

4.5

90

A

ns

R_CFG1= 0 kΩ

R_CFG1= 17.8 kΩ

f_SW= 500 kHz to 2.5 MHz

Minimum On Time

Minimum Off Time

Error Amplifier, COMP1 Pin

EA Transconductance

Soft Start Time

t_{MIN_ON1}

t_{MIN_OFF1}

50

80

g_m1

t_SS1

700

2

800

2

16

900

16

µS

ms

Ω

Timer ×1 option

Timer ×8 option

Programmable Soft Start Range

Hiccup Time

C_OUTDischarge Switch On

Resistance

t_HICCUP1

R_DIS1

7 × t_SS1

85

CHANNEL 2 SYNC BUCK REGULATOR

Load Current

I_LOAD2

4

A

Output Characteristics

V_FB2Voltage Accuracy

−40°C ≤ T_J≤ +125°C

V_SET2= V_REF

V_SET2= ½ × V_REF

V_FB2

−0.6

−1.0

+0.6

+1.0

0.1

%

µA

Feedback Bias Current

VSET2 Bias Current

SW2 Pin

I_FB2

I_VSET2

0.1

High-Side Power FET On

Resistance

Low-Side Power FET On

Resistance

R_DS(ON)2H

R_DS(ON)2L

I_TH(ILIM2)

49

37

80

60

mΩ

Pin to pin measurement

Current-Limit Threshold

5.2

2.5

6.9

3.5

60

8.6

4.5

90

A

ns

R_CFG1= 0 kΩ

R_CFG1= 17.8 kΩ

f_SW= 500 kHz to 2.5 MHz

Minimum On Time

Minimum Off Time

t_{MIN_ON2}

t_{MIN_OFF2}

50

80

Error Amplifier, COMP2 Pin

Transconductance

g_m2

700

800

900

µS

Rev. A | Page 5 of 34

ADP5014

Data Sheet

Parameter

Symbol

Min

Typ

2

16

Max

Unit

ms

Ω

Test Conditions/Comments

Timer ×1 option

Timer ×8 option

Soft Start Time

t_SS2

Programmable Soft Start Range

Hiccup Time

C_OUTDischarge Switch On

Resistance

2

16

t_HICCUP2

R_DIS2

7 × t_SS2

85

CHANNEL 3 SYNC BUCK REGULATOR

Load Current

I_LOAD3

2

A

Output Characteristics

V_FB3Voltage Accuracy

−40°C ≤ T_J≤ +125°C

V_SET3= V_REF

V_SET3= ½ × V_REF

V_FB3

−0.6

−1.0

+0.6

+1.0

0.1

%

µA

Feedback Bias Current

VSET3 Bias Current

SW3 Pin

I_FB3

I_VSET3

0.1

High-Side Power FET On

Resistance

Low-Side Power FET On

Resistance

R_DS(ON)3H

R_DS(ON)3L

I_TH(ILIM3)

95

73

135

110

mΩ

Pin to pin measurement

Current-Limit Threshold

2.5

1.2

3.5

1.8

60

4.5

2.4

90

A

ns

R_CFG1= 0 kΩ

R_CFG1= 17.8 kΩ

f_SW= 500 kHz to 2.5 MHz

Minimum On Time

Minimum Off Time

Error Amplifier, COMP3 Pin

EA Transconductance

Soft Start Time

t_{MIN_ON3}

t_{MIN_OFF3}

50

80

g_m3

t_SS3

700

2

800

2

16

900

16

µS

ms

Ω

Timer ×1 option

Timer ×8 option

Programmable Soft Start Range

Hiccup Time

C_OUTDischarge Switch On Resistance R_DIS3

CHANNEL 4 SYNC BUCK REGULATOR

t_HICCUP3

7 × t_SS3

85

Load Current

I_LOAD4

2

A

Output Characteristics

V_FB4Voltage Accuracy

−40°C ≤ T_J≤ +125°C

V_SET4= V_REF

V_SET4= ½ × V_REF

V_FB4

−0.6

−1.0

+0.6

+1.0

0.1

%

µA

μA

Feedback Bias Current

VSET4 Bias Current

SW4 Pin

I_FB4

I_VSET4

0.1

High-Side Power FET On

Resistance

Low-Side Power FET On

Resistance

R_DS(ON)4H

R_DS(ON)4L

I_TH(ILIM4)

95

73

135

110

mΩ

Pin to pin measurement

Current-Limit Threshold

2.5

1.2

3.5

1.8

60

4.5

2.4

90

A

ns

R_CFG1= 0 kΩ

R_CFG1= 17.8 kΩ

f_SW= 500 kHz to 2.5 MHz

Minimum On Time

Minimum Off Time

Error Amplifier, COMP4 Pin

EA Transconductance

Soft Start Time

t_{MIN_ON4}

t_{MIN_OFF4}

50

80

g_m4

t_SS4

700

2

800

2

16

900

16

µS

ms

Ω

Timer ×1 option

Timer ×8 option

Programmable Soft Start Range

Hiccup Time

C_OUTDischarge Switch On Resistance R_DIS4

t_HICCUP4

7 × t_SS4

85

Rev. A | Page 6 of 34

Data Sheet

ADP5014

ABSOLUTE MAXIMUM RATINGS

Table 3.

Stresses at or above those listed under Absolute Maximum

Ratings may cause permanent damage to the product. This is a

stress rating only; functional operation of the product at these

or any other conditions above those indicated in the operational

section of this specification is not implied. Operation beyond

the maximum operating conditions for extended periods may

affect product reliability.

Parameter

Rating

AVIN to Ground

PVIN1 to PGND1

PVIN2 to PGND2

PVIN3 to PGND3

PVIN4 to PGND4

SW1 to PGND1

SW2 to PGND2

SW3 to PGND3

SW4 to PGND4

PGND to Ground

CFG1, CFG2 to Ground

EN1/ENALL, EN2/DL12, EN3/UV,

EN4/DL34 to Ground

GPIO to Ground

RT to Ground

VREF to Ground

−0.3 V to +6.5 V

−0.3 V to + 0.3 V

−0.3 V to +6.5 V

THERMAL RESISTANCE

Thermal performance is directly linked to printed circuit board

(PCB) design and operating environment. Close attention to

PCB thermal design is required.

Table 4. Thermal Resistance

Package Type

θ_JA

θ_JC

Unit

CP-40-10

40

11.1

°C/W

−0.3 V to +6.5 V

ESD CAUTION

FB1, FB2, FB3, FB4 to Ground ¹

COMP1, COMP2, COMP3, COMP4

to Ground

VSET1, VSET2, VSET3, VSET4 to

Ground

−0.3 V to +6.5 V

Storage Temperate Range

Operational Junction Temperature

Range

−65°C to +150°C

−40°C to +125°C

¹The rating for the FB1, FB2, FB3, and FB4 pins applies to the adjustable

output voltage models of the ADP5014.

Rev. A | Page 7 of 34

ADP5014

Data Sheet

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

FB3

COMP3

PVIN3

SW3

1

2

3

4

5

6

7

8

9

30 PVIN1

29

28

SW1

27 PGND1

ADP5014

PGND3

PGND4

SW4

26

25

PGND1

PGND2

TOP VIEW

(Not to Scale)

24 PGND2

23 SW2

22 SW2

21 PVIN2

PVIN4

COMP4

FB4 10

NOTES

1. EXPOSED PAD. THE EXPOSED PAD MUST BE

CONNECTED AND SOLDERED TO AN EXTERNAL

GROUND PLANE.

Figure 3. Pin Configuration

Table 5. Pin Function Descriptions

Pin No.

Mnemonic

Description

1

FB3

Feedback Sensing Input for Channel 3.

2

3

4

COMP3

PVIN3

SW3

Error Amplifier Output for Channel 3. Connect a resistor capacitor (RC) network from this pin to ground.

Power Input for Channel 3.

Switching Node Output for Channel 3.

5

6

7

PGND3

PGND4

SW4

Power Ground for Channel 3

Power Ground for Channel 4.

Switching Node Output for Channel 4.

8

9

10

11

PVIN4

COMP4

FB4

Power Input for Channel 4.

Error Amplifier Output for Channel 4. Connect an RC network from this pin to ground.

Feedback Sensing Input for Channel 4.

General-Purpose Input or Output Signal. This pin can be configured as power good, synchronization clock

output (CLK-OUT) or undervoltage comparator output (UVO).

GPIO

12

13

EN4/DL34

EN3/UV

Enable Input for Channel 4 in Manual Mode (EN4).

Delay Timer Setting for Channel 3 and Channel 4 in Sequence Mode (DL34). Connect one resistor from this pin

to ground to program the start-up and shutdown sequence delay timer for Channel 3 and Channel 4.

Enable Input for Channel 3 in Manual Mode (EN3).

Under Voltage Comparator Input in Sequence Mode (UV).

14

15

16

CFG2

System Configuration Pin 1. Connect one resistor from this pin to ground to program sequence or manual

mode, the delay timer, PSM or FPWM operation mode, and GPIO mapping for all channels.

System Configuration Pin 2. Connect one resistor from this pin to ground to program current limit, and the

parallel output for all channels.

CFG1

EN2/DL12

Enable Input for Channel 2 in Manual Mode (EN2).

Delay Timer Setting for Channel 1 and Channel 2 in Sequence Mode (DL12). Connect one resistor from this pin

to ground to program the start-up and shutdown sequence delay timer for Channel 1 and Channel 2.

17

EN1/ENALL

Enable Input for Channel 1 in Manual Mode (EN1).

Grouped Enable Input for All Channels in Sequence Mode (ENALL).

Feedback Sensing Input for Channel 2.

18

FB2

19

COMP2

PVIN2

SW2

PGND2

PGND1

SW1

Error Amplifier Output for Channel 2. Connect an RC network from this pin to ground.

Power Input for Channel 2.

Switching Node Output for Channel 2.

Power Ground for Channel 2.

Power Ground for Channel 1.

20, 21

22, 23

24, 25

26, 27

28, 29

Switching Node Output for Channel 1.

Rev. A | Page 8 of 34

Data Sheet

ADP5014

Pin No.

30, 31

32

Mnemonic

Description

PVIN1

COMP1

FB1

Power Input for Channel 1.

Error Amplifier Output for Channel 1. Connect an RC network from this pin to ground.

Feedback Sensing Input for Channel 1.

33

34

AVIN

Analog Power Input for the Internal Control Circuitry. Connect a bypass capacitor between this pin and ground.

Connect a small (10 Ω) resistor between this pin and PVINx.

35

36

37

38

39

40

RT

Frequency Setting. Connect a resistor from RT to ground to program the switching frequency.

Channel 1 Reference Voltage Setting Input.

Channel 2 Reference Voltage Setting Input.

Internal Low Noise Voltage Reference Output.

Channel 3 Reference Voltage Setting Input.

VSET1

VSET2

VREF

VSET3

VSET4

Channel 4 Reference Voltage Setting Input.

Exposed Pad Analog Ground. The exposed pad must be connected and soldered to an external ground plane.

Rev. A | Page 9 of 34

ADP5014

Data Sheet

TYPICAL PERFORMANCE CHARACTERISTICS

100

90

80

70

60

50

40

30

20

10

0

90

80

70

60

50

40

30

V

= 1.2V FPWM

= 1.8V FPWM

= 3.3V FPWM

= 1.2V PSM

= 1.8V PSM

= 3.3V PSM

OUT

V

= 1.2V

= 1.5V

= 1.8V

= 2.5V

= 3.3V

OUT

20

10

0

0.01

0.1

1

10

0

1.0

2.0

(A)

3.0

4.0

I

(A)

I

OUT

Figure 4. Channel 1/Channel 2 Efficiency Curve, V_IN= 5 V, f_SW= 1.2 MHz,

FPWM Mode

Figure 7. Channel 1/Channel 2 Efficiency Curve, V_IN= 5 V, f_SW= 1.2 MHz,

FPWM and Automatic PWM/PSM Modes

100

90

80

70

60

50

40

30

20

100

90

80

70

60

50

40

30

V

= 1.2V

= 1.5V

= 1.8V

= 2.5V

= 3.3V

20

10

0

OUT

V

= 1.2V

= 1.5V

= 1.8V

= 2.5V

OUT

10

0

1.0

2.0

(A)

3.0

4.0

0

0.5

1.0

(A)

1.5

2.0

I

OUT

Figure 5. Channel 1/Channel 2 Efficiency Curve, V_IN= 3.3 V, f_SW= 1.2 MHz,

FPWM Mode

Figure 8. Channel 3/Channel 4 Efficiency Curve, V_IN= 5 V, f_SW= 1.2 MHz,

FPWM Mode

100

90

80

70

60

50

40

30

100

90

80

70

60

50

40

30

20

V

= 1.2V

= 1.5V

= 1.8V

= 2.5V

f_SW= 500kHz

OUT

10

f_SW= 1.2MHz

10

0

f_SW= 2.4MHz

0

1.0

2.0

(A)

3.0

4.0

0

0.5

1.0

(A)

1.5

2.0

I

OUT

I

OUT

Figure 6. Channel 1/Channel 2 Efficiency Curve, V_IN= 5 V, V_OUT= 3.3 V, FPWM

Mode

Figure 9. Channel 3/Channel 4 Efficiency Curve, V_IN= 3.3 V, f_SW= 1.2 MHz,

FPWM Mode

Rev. A | Page 10 of 34

Data Sheet

ADP5014

100

90

80

70

60

50

40

30

20

10

1500

1400

1300

1200

1100

1000

f_SW= 500kHz

f_SW= 1.2MHz

f_SW= 2.5MHz

0

–50

–20

10

40

70

100

130

0.5

1.0

(A)

1.5

2.0

TEMPERATURE (°C)

I

OUT

Figure 13. Frequency vs. Temperature, V_IN= 5 V, f_SW= 1.2 MHz

Figure 10. Channel 3/Channel 4 Efficiency Curve, V_IN= 5 V, V_OUT= 3.3 V,

FPWM Mode

6.0

5.5

5.0

4.5

4.0

3.5

3.0

100

80

60

40

V

= 1.2V FPWM

= 1.8V FPWM

= 3.3V FPWM

= 1.2V PSM

= 1.8V PSM

= 3.3V PSM

OUT

20

0

100

–50

0

50

0.01

0.1

1

10

TEMPERATURE (°C)

I

(A)

OUT

Figure 14. Quiescent Current vs. Temperature (Includes PVIN1, PVIN2, PVIN3,

and PVIN4)

Figure 11. Channel 3/Channel 4 Efficiency Curve, V_IN= 5 V, f_SW= 1.2 MHz,

FPWM and Automatic PWM/PSM Modes

90

2.010

2.005

2.000

1.995

1.990

V

= 3.3V

= 5V

IN

85

80

75

70

65

60

55

50

45

40

= 6V

–50

–20

10

40

70

100

130

–50

–20

10

40

70

100

130

TEMPERATURE (°C)

Figure 15. Shutdown Current vs. Temperature (EN1/ENALL, EN2/DL12,

EN3/UV, and EN4/DL34 Low)

Figure 12. 2.0 V Reference Voltage Accuracy vs. Temperature

Rev. A | Page 11 of 34

ADP5014

Data Sheet

3.0

2.9

2.8

2.7

2.6

2.5

2.4

2.3

2.2

2.1

1

2

RISING

FALLING

2.0

–50

B

CH1 10mV

CH2 2.00V

M400ns

25.60%

A CH2

2.96V

W

–20

10

40

70

100

130

T

TEMPERATURE (°C)

Figure 19. Steady State Waveform at Heavy Load, V_IN= 5 V, V_OUT= 1.2 V,

Figure 16. UVLO Threshold vs. Temperature

I_OUT= 3 A, f_SW= 1.2 MHz, L = 0.8 µH, C_OUT= 47 µF × 2, FPWM Mode,

Channel 1 = V_OUTX, Channel 2 = SW_X

10

4A RATED

2A RATED

9

8

7

6

5

4

3

2

1

2

B

CH1 50mV

M100µs

25.60%

A CH2

2.96A

W

–50

–20

10

40

70

100

130

CH4 2.00A Ω

T

TEMPERATURE (°C)

Figure 20. Channel 1/Channel 2 Load Transient, 0.5 A to 3.5 A, V_IN= 5 V,

V_OUT= 1.2 V, f_SW= 1.2 MHz, L = 0.8 µH, C_OUT= 47 µF × 2, Channel 1 = V_OUTX

Channel 2 = I_OUTX

Figure 17. Channel 1/Channel 2 Current Limit vs. Temperature

,

4

2A RATED

1A RATED

1

3

2

1

3

4

B

–50

–20

10

40

70

100

130

CH1 50mV

M 100µs

29.60%

A CH3

4.12A

W

T

CH3 2A Ω

CH4 2.00A Ω

TEMPERATURE (°C)

Figure 21. Load Transient, Channel 1/Channel 2 Parallel Output, 1 A to 6 A,

V_IN= 5 V, V_OUT= 1.2 V, f_SW= 1.2 MHz, L = 0.8 µH, C_OUT= 47 µF × 4, Channel 1 = V_OUT,

Channel 3 = I_L1, Channel 4 = I_L2

Figure 18. Channel 3/Channel 4 Current Limit vs. Temperature

Rev. A | Page 12 of 34

Data Sheet

ADP5014

1

2

3

2

3

4

B

CH1 1.00V

CH3 2.00V

CH2 2.00V

CH4 2.00V

M 4.00ms

A CH1

820mV

CH1 5.00V

CH3 5.00V

CH2 500mV

CH4 5.00A Ω

M 20.0ms

T 42.8%

A

CH2

780mV

W

B

T

24.20%

Figure 22. Startup for All Channels Under Sequence Enable Mode,

Channel 1 = V_OUT1,Channel 2 = V_OUT2,Channel 3 = V_OUT3, Channel 4 = V_OUT4

Figure 25. Channel 1 Shutdown with Active Output Discharge, V_IN= 5 V, V_OUT=

1.2 V, f_SW= 1.2 MHz, L = 0.8 µH, C_OUT= 47 µF × 2, Channel 1 = EN1/ENALL,

Channel 2 = V_OUT1, Channel 3 = PWRGD, Channel 4 = I_OUT1

1

2

3

4

B

W

CH1 1.00V

CH3 2.00V

CH2 2.00V

CH4 2.00V

M 10.0ms

A

CH1

780mV

CH1 500mV

CH2 5.00V

CH4 5.00A Ω

M 10.0ms

25.60%

A

CH1

520mV

W

B

T

72.00%

W

Figure 23. Shutdown for All Channels Under Sequence Enable Mode,

Channel 1 = V_OUT1,Channel 2 = V_OUT2,Channel 3 = V_OUT3, Channel 4 = V_OUT4

Figure 26. Short-Circuit Protection Entry, V_IN= 5 V, V_OUT= 1.2 V, f_SW= 1.2 MHz,

L = 0.8 µH, C_OUT= 47 µF × 2, Channel 1 = V_OUTX, Channel 2 = SW_X,

Channel 4 = I_LX

1

2

3

4

B

CH1 5.00V

CH3 5.00V

CH2 500mV

M 1.00ms

A

CH2

780mV

CH1 500mV

CH2 5.00V

CH4 5.00A Ω ^B

M10.0ms

80.60%

A CH1

1.01V

W

CH4 5.00A Ω ^B

T

42.80%

W

T

Figure 24. Channel 1 Startup with Full Load, V_IN= 5 V, V_OUT= 1.2 V,

Channel 1 = EN1/ENALL, Channel 2 = V_OUT1, Channel 3 = PWRGD,

Channel 4 = I_OUT1

Figure 27. Short-Circuit Protection Recovery, V_IN= 5 V, V_OUT= 1.2 V, f_SW= 1.2 MHz,

L = 0.8 µH, C_OUT= 47 µF × 2, Channel 1 = V_OUTX, Channel 2 = SW_X,

Channel 4 = I_LX

Rev. A | Page 13 of 34

ADP5014

Data Sheet

THEORY OF OPERATION

The ADP5014 is a power management unit that combines four

high performance, low noise buck regulators in a 40-lead LFCSP

package.

operation; in PSM mode, the regulator operates with a reduced

switching frequency to maintain high efficiency. The low-side

MOSFET turns off when the output current reaches 0 A, causing

the regulator to operate in discontinuous mode (DCM).

BUCK REGULATOR OPERATIONAL MODES

Use the CFG2 pin to configure the operational mode of all four

buck regulators to operate in PWM mode or automatic

PWM/PSM mode.

PWM Mode

In PWM mode, the buck regulators in the ADP5014 operate at

a fixed frequency; this frequency is set by an internal oscillator

that is programmed by the RT pin. At the start of each

oscillator cycle, the high-side MOSFET switch turns on and sends

a positive voltage across the inductor. The inductor current

increases until the current sense signal exceeds the peak

inductor current threshold that turns off the high-side

MOSFET switch. This threshold is set by the error amplifier

output. During the high-side MOSFET off time, the inductor

current decreases through the low-side MOSFET switch until

the next oscillator clock pulse starts a new cycle. The buck

regulators in the ADP5014 regulate the output voltage by

adjusting the peak inductor current threshold.

LOW NOISE ARCHITECTURE

Traditional dc-to-dc or linear regulator output noise is typically

proportional to the output voltage setting. The ADP5014 optimizes

many analog blocks to achieve lower output noise at low frequency

range. The unity-gain voltage reference structure also makes its

output noise independent from the output voltage setting when

V_OUTsetting is less than V_REFvoltage.

The low noise buck regulator enables the device to power up noise

sensitive signal chain products directly with excellent output noise

performance, ~25 μV rms from 10 Hz to 100 kHz, which is similar

or even better than traditional low dropout regulators (LDOs).

PSM Mode

The additional LC filter is still required because the fundamental

switching output ripple and its harmonic affects signal chain

performance and likely generates unexpected spurs. This

additional LC filter is typically relatively small due to the high

switching frequency operation of the buck regulator in the

ADP5014.

To achieve higher efficiency, the buck regulators in the

ADP5014 smoothly transition to variable frequency PSM mode

operation when the output load falls below the PSM current

threshold. When the output voltage falls below regulation, the

buck regulator enters PWM mode for a few oscillator cycles

until the voltage increases to within regulation. During the idle

time between bursts, the MOSFET switch turns off, and the

output capacitor supplies all the output current.

INTERNAL REFERENCE (VREF)

The ADP5014 provides an accurate, low noise, 2.0 V reference

voltage. One 0.47 μF ceramic capacitor must be connected

between VREF and ground. A larger value of capacitance provides

better noise suppression.

The PSM mode comparator monitors the internal compensation

node, which represents the peak inductor current information.

The average PSM mode current threshold depends on the input

voltage (V_IN), the output voltage (V_OUT), the inductor, and the

output capacitor. Because the output voltage occasionally falls

below regulation and then recovers, the output voltage ripple in

PSM mode is larger than the ripple in the forced PWM mode of

operation under light load conditions.

The VREF reference circuitry is mainly designed for internal use

and has very limited output load capacity (<1 mA); therefore,

check the load capability requirements if VREF is used for other

purposes.

ADJUSTABLE OUTPUT VOLTAGE

The ADP5014 provides adjustable output voltage settings via

the external resistor divider. To minimize output noise and

maintain the loop unity-gain, the device provides the reference

input path to the error amplifier input with the integrated low-

frequency filter for each channel. Use an external resistor

divider to set the desired output voltage. Figure 28 shows the

adjustable output voltage diagram.

FPWM and Automatic PWM/PSM Modes

The buck regulators can be configured to always operate in FPWM

mode using the CFG2 configuration pin. In forced PWM mode,

the regulator continues to operate at a fixed frequency even when

the output current is below the PWM/PSM threshold. In PWM

mode, the efficiency is lower compared to PSM mode under light

load conditions. The low-side MOSFET remains on when the

inductor current falls to less than 0 A, causing the ADP5014 to

enter continuous conduction mode (CCM).

PVINx

SWx

VOUTx

COUTx

VREF

BUCK

VFBx

The buck regulators can be configured to operate in automatic

PWM or PSM mode using the CFG2 configuration pin. In

automatic PWM/PSM mode, the buck regulators operate in

either PWM mode or PSM mode, depending on the output

current. When the average output current falls below the

PWM/PSM threshold, the buck regulator enters PSM mode

R

A

R

TOP

VSETx

B

R

BOT

Figure 28. Adjustable Output Voltage Configuration

Rev. A | Page 14 of 34

Data Sheet

ADP5014

FUNCTION CONFIGURATIONS (CFG1 AND CFG2)

The CFG2 pin can be used to program the operation mode

(FPWM or PWM/PSM mode), the enable mode (manual mode

or sequence mode), the timer (×1 or ×8), and GPIO

functionalities (PWRGD, SYNC-IN, CLK-OUT, UVO) for all

channels. Table 7 provides the values of the resistors needed to

set different functionality in the CFG2 pin.

The ADP5014 include CFG1 and CFG2 pins to decode the

function configurations for all channels. The CFG1 pin has a

logic status of 8 that is decoded by connecting one resistor to

ground, whereas the CFG2 pin has a logic status of 16, decoded by

connecting one resistor to ground. This decoder circuitry only

works in the initiation stage of the ADP5014; therefore, the

configurations cannot be changed in operation. Typically, the

chip initiation takes less than 1 ms before the enabled regulator

starts switching.

The R_CFG1and R_CFG2resistors must have 1% tolerance to ensure

the correct decoding result.

Table 7. Configuration by the CFG2 Pin

The CFG1 pin can be used to program the load output capability

and parallel operation for all channels. Table 6 provides the

values of the resistors needed to set different functionality in the

CFG1 pin.

R_CFG2

(kΩ)

0

Enable

Mode

Operation

Timer Mode

GPIO

Manual

×1

×8

×1

×8

FPWM

PSM

PWRGD

SYNC-IN

CLK-OUT

PWRGD

SYNC-IN

CLK-OUT

PWRGD

UVO

10

Manual

12.1

14.7

Float

17.8

21.5

26.1

31.6

38.3

46.4

56.2

68.1

82.5

100

121

Manual

Table 6. Configuration by the CFG1 Pin

Output Capability

Manual

FPWM

PSM

R_CFG1(kΩ) Channel 1 Channel 2 Channel3 Channel 4

Manual

0

4 A

2 A

1 A

2 A

1 A

2 A

1 A

2 A

1 A

2 A

Manual

10

4 A

Manual

12.1

14.7

17.8

21.5

26.1

31.6

4 A

Sequence

FPWM

PSM

2 A

SYNC-IN

CLK-OUT

UVO

2 A

Parallel 8A

4 A

Parallel 8 A 2 A

4 A

Parallel 4 A Parallel 4 A

FPWM

PSM

UVO

Parallel 8 A Parallel 8 A Parallel 4 A Parallel 4 A

SYNC-IN

CLK-OUT

UVO

Rev. A | Page 15 of 34

ADP5014

Data Sheet

CHANNEL 1 CURRENT

CHANNEL 2 CURRENT

PARALLEL OPERATION

The ADP5014 supports 2-phase parallel operation of Channel 1

and Channel 2 to provide a single output with up to 8 A of

current, and two-phase parallel operation of Channel 3 and

Channel 4 to provide a single output with up to 4 A of current.

To configure a 2-phase single output in parallel operation,

perform the following steps (see Figure 29). Use the CFG1 pin

to select parallel operation as specified in Table 7.



Leave the COMP2 pin (or COMP4 pin) open.

Use the VSET1 and FB1 pin (or VSET3 and FB3 pin) to set

the output voltage.

0

2

4

6

8



Connect the FB2 and VSET2 pin (or FB4 pin and VSET4)

to ground (FB2 is ignored). Connect the EN2/DL12 pin (or

EN4/DL34 pin) to ground in manual enable mode (EN2 is

ignored). Note that the EN2/DL12 pin is for the delay timer

configuration in sequence enable mode.

TOTAL OUTPUT LOAD (A)

Figure 30. Current Balance in Parallel Output Configuration, V_IN= 5 V,

V_OUT= 1.2 V, f_SW= 1.2 MHz, FPWM Mode

MANUAL/SEQUENCE MODE

The ADP5014 features two enable modes using the CFG2 pin

configuration. The manual mode has individual precision

enable pins to enable each regulator manually. Alternatively,

the sequence mode has one grouped precision enable signal

with a programmable power-up and power-down delay timer on

each rail.

PVIN1

VIN

VOUT

(UP TO 8A)

PVIN2

CFG1

L1

SW1

FB1

CH1

BUCK

(4A)

VREF

VSET1

The enable pin (EN1 to EN4) functionality is different in

manual mode and sequence mode. Note that throughout this

data sheet, multifunction pins, such as EN1/ENALL, are referred to

by either the entire pin name or by a single function of the pin, for

example, EN1, when only that format is relevant. Figure 31 and

Table 8 show the pin mapping in different enable modes.

CH2

BUCK

(4A)

VSET2

L2

SW2

FB2

COMP1

COMP2

EN1

EN2

Figure 29. Parallel Operation for Channel 1 and Channel 2

If some channels are unused, pull down the corresponding

PVINx and ENx pin to ground and leave the SWx, COMPx,

VSETx, and FBx pins floating.

The following considerations apply when two channels are

operating in the parallel configuration:

MANUAL ENABLE

SEQUENCE ENABLE

MODE



The input voltages for both channels are the same.

Both channels are operating in forced PWM mode.

Do not support sequence mode.

VOUT1 ENALL

VOUT1

VOUT2

VOUT3

EN1

EN2

EN3

EN4

CHANNEL 1

CHANNEL 2

CHANNEL 3

CHANNEL 1

CHANNEL 2

CHANNEL 3

CHANNEL 4

DL12

VOUT2

The current balance in parallel configuration is well regulated

by the internal control loop. Figure 30 shows the typical current

balance matching in the parallel output configuration.

VOUT3

DL34

VOUT4

GPIO

VOUT4

CHANNEL 4

+

UV

GPIO

0.6V

–

Figure 31. Pin Configuration in Different Enable Modes

Table 8. Pin Functionality in Different Enable Modes

Pin Name

Manual Enable Mode

Sequence Enable Mode

EN1/ENALL (Pin 17)

EN2/DL12 (Pin 16)

EN3/UV (Pin 13)

EN4/DL34 (Pin 12)

EN1—enable pin for Channel 1

EN2—enable pin for Channel 2

EN3—enable pin for Channel 3

EN4—enable pin for Channel 4

ENALL—grouped enable pin for all four channels

DL12—delay timer setting for Channel 1 and Channel 2

UV—undervoltage comparator input

DL34—delay timer setting for Channel 3 and Channel 4

Rev. A | Page 16 of 34

Data Sheet

ADP5014

Manual Mode (Precision Enable)

Sequence Mode

In manual mode, the ADP5014 has an individual precision

enable pin for each regulator. The enable control pin (ENx)

features a precision enable circuit with a 0.6 V reference

voltage. When the voltage at the ENx pin is greater than 0.6 V

(typical), the regulator is enabled. When the ENx pin voltage

falls below 0.57 V (typical), the regulator is disabled. To force

the regulator to automatically start up when input power is

applied, connect the enable pin to the input.

In sequence mode, all channels in the ADP5014 turn on and off

under the control of the internal sequencer, which is triggered

by the ENALL pin. The DL12 and DL34 pins set the predefined

delay timer.

The ENALL pin features precision enable circuitry with a 0.6 V

turn on threshold and internal pull-down current source.

When the ENALL pin goes above the 0.6 V precision threshold,

all channels controlled by the sequencer begin a soft start after

the delay time specified by the DL12 and DL34 pin configuration.

Similarly, when the ENALL pin falls below 0.57 V precision

threshold, the channels turns off after the delay time specified

by DL12 and DL34 pin configurations.

The precision enable pin has an internal pull-down current

source (4 μA) that provides a default turn off when the enable

pin is left open. When the enable pin exceeds 0.6 V (typical),

the regulator is enabled and the internal pull-down current

source at the enable pin decreases to 1 μA. The decrease in the

current source allows the ratio of the external resistor divider to

program the UVLO threshold to monitor either the input

voltage or the output voltage while using the absolute value of

external resistor divider to program the hysteresis window.

Figure 32 shows the precision enable diagram.

Figure 33 shows the logical states of each channel and does not

show soft start and discharge ramps. Although the output

discharge switch helps to discharge the output capacitor quickly,

the discharge ramps on the output of each channel are still

decided by many different factors, including the output

capacitance, system load, and the ramps of input supply.

DL12 configures the delay timer for Channel 1 and Channel 2 by

connecting one resistor to ground. Similarly, DL34 configures the

delay timer for Channel 3 and Channel 4 (see Table 9). In parallel

operation, the slave channel (Channel 2 or Channel 4) always

follows up with the delay timer configuration of the master

channel; therefore, Channel 2 follows Channel 1, while Channel 4

follows Channel 3. The delay timer decoder circuitry only works

in the initiation stage of the ADP5014; therefore, the delay

timer does not change in operation.

R

TOP_EN

EN_CMP

+

0.6V

–

R

BOT_EN

1µA

3µA

Figure 32. Precision Enable Diagram for One Channel

ENALL

t_{DIS_DLY1}

t_{DIS_DLY2}

t_{DIS_DLY3}

t_{DIS_DLY4}

t_{EN_DLY1}

ON

CHANNEL1

CHANNEL2

OFF

t_{EN_DLY2}

t_{EN_DLY3}

t_{EN_DLY4}

CHANNEL3

CHANNEL4

Figure 33. Power-Up/Power-Down in Sequence Enable Mode

Rev. A | Page 17 of 34

ADP5014

Data Sheet

Table 10. Power-Up and Power-Down Timer

Table 9. Setting Sequence Timer in the DL12 and DL34 Pins

Sequence

Order

Power-Up Delay Timer

Power-Down Delay

Timer (t_{DIS_DLYx}

R_DL12

(or R_DL34

(kΩ)

(t_{EN_DLYx}

)

Channel 1 Sequence

(or Channel 3)

Channel 2 Sequence

(or Channel 4)

First Order

0 ms

36 ms (288 ms at

×8 option)

10

First order

Second

Order

Third Order

6 ms (48 ms at ×8 option)

24 ms (192 ms at

×8 option)

12 ms (96 ms at

×8 option)

0

First order

Second order

Third order

Fourth order

First order

Second order

Third order

Fourth order

First order

Second order

Third order

Fourth order

First order

Second order

Third order

Fourth order

12.1

14.7

17.8

21.5

26.1

31.6

38.3

46.4

56.2

Float

68.1

82.5

100

121

12 ms (96 ms at ×8

option)

18 ms (144 ms at ×8

option)

Second order

Third order

Fourth order

Fourth

Order

0 ms

GENERAL PURPOSE INPUT/OUTPUT (GPIO)

The ADP5014 includes one GPIO pin which can be configured

for different functionalities, such as PWRGD, synchronization

clock input (SYNC-IN), CLK-OUT, or UVO.

The PWRGD and UVO output functionalities have the open-

drain output after the initiation.

The CLK-OUT output functionality features a push/pull output,

enabling it to drive other regulators after initiation.

OSCILLATOR

Note that the R_DL12and R_DL34resistors must have 1 % tolerance

to ensure the correct decoding result.

The switching frequency (f_SW) of the ADP5014 can be set to a

value from 500 kHz to 2.5 MHz by connecting a resistor from

the RT pin to ground. Calculate the value of the RT resistor

(R_RT) as follows:

The power-up and power-down delay timer for all channels is

designed in an opposite manner to meet typical system

sequence requirements, as described below:

R

_RT(kΩ) = 100,000/f_SW(kHz)

•

First order sequence means the channel is configured as

the first to be powered up, and is shut down last.

Figure 34 shows the typical relationship between f_SWand the RT

resistor. The adjustable frequency allows users to make decisions

based on the trade-off between efficiency and the size of the

solution.

Second order sequence means the channel is configured as

the second to be powered up and is shut down third.

Third order sequence means the channel is configured as

the third to be powered up and is shut down second.

Fourth order sequence means the channel is configured as

the fourth to be powered up and is shut down first.

2700

2400

2100

1800

1500

1200

900

If a longer sequence timer is required, the delay time for all

channels can be increased by 8 times (×8 option) using the

CFG2 pin. Table 10 shows the power-up and power-down timer

configurations.

In sequence enable mode, the device performs the following

actions in fault conditions:

600

•

During individual fault conditions, such as overcurrent

hiccup, OVP, or PVINx, UVLO shuts down and powers up

the corresponding channel immediately without the

sequence delay.

300

20

60

100

140

180

220

RT RESISTOR (kΩ)

Figure 34. Switching Frequency vs. RT Resistor

•

TSD fault shuts down all channels immediately without the

sequence delay, but occurs after the defined power-up

sequence for the recovery.

An AVIN UVLO fault shuts down all channels immediately

without any sequence delay, but occurs after the defined

power-up sequence for the recovery after the device

reinitiation.

Rev. A | Page 18 of 34

Data Sheet

ADP5014

Phase Shift

POWER-GOOD FUNCTION

By default, the phase shift between Channel 1 and Channel 2 and

between Channel 3 and Channel 4 is 180° (see Figure 35). This

value provides the benefits of out of phase operation by reducing

the input ripple current and lowering the grounding noise.

The ADP5014 GPIO pin can be configured as an open-drain

power-good output (PWRGD pin) that becomes active high

when the selected buck regulators are operating normally.

A high status in the PWRGD pin indicates that the regulated

output voltage of the buck regulator is above 90% (typical) of its

nominal output. When the regulated output voltage of the buck

regulator falls below 87% (typical) of its nominal output for a

delay time greater than approximately 50 µs, the status of the

PWRGD pin is set to low.

0° REFERENCE

CH 1

180° PHASE SHIFT

CH 2

0° REFERENCE

The output of the PWRGD pin is the logical AND of the internal

PWRGD signals on an individual channel. An internal PWRGD

signal on an individual channel must be high for a validation

time of 2 ms (typical) timer before the PWRGD pin goes high.

This validation timer can be increased by 8 times (×8 option)

using the CFG2 pin configuration; if one internal PWRGD fails,

the PWRGD pin goes low with no delay.

CH 3

180° PHASE SHIFT

CH 4

Figure 35. Phase Shift Diagram, Four Buck Regulators

SYNCHRONIZATION INPUT/OUTPUT

The GPIO pin can be configured as the synchronization clock

input by using the CFG2 pin (see Table 7), and the switching

frequency of the ADP5014 can be synchronized to an external

clock with a frequency range from 500 kHz to 2.5 MHz. The

ADP5014 automatically detects the presence of an external

clock applied to the GPIO pin, and the switching frequency

transitions smoothly to the frequency of the external clock.

When the external clock signal stops, the device automatically

switches back to the internal clock and continues to operate.

UV COMPARATOR (SEQUENCE MODE ONLY)

In sequence mode, the EN3/UV pin is used as the UVO input

(UV pin), while the ADP5014 GPIO pin can be configured as

an open-drain UVO via CFG2 pin configuration. The UV

comparator is not related to the channel enabling and is only

used for monitoring purposes. For example, it can be used to

monitor any output voltage to create a power-good signal in

sequence mode.

Similar to the precision enable functionality, this UVO features

the same precise 0.6 V reference voltage with the 1 µA or 4 µA

pull-down hysteresis current. Using the ratio of external resistor

divider to program the UVLO threshold allows monitoring

either input voltage or output voltage while using the absolute

value of the external resistor divider to program the hysteresis

window. The UV pin is connected to the input supply if it is not

intended for use. Figure 37 shows the UVO diagram.

The internal switching frequency set by the RT pin must be

programmed to a value that is close to the external clock value

for successful synchronization; the suggested frequency

difference is less than 15% in typical applications.

The GPIO pin can be configured as a push/pull synchronization

clock output by CFG2 (refer to Table 7). A positive clock pulse

with a 50% duty cycle is generated at the GPIO pin with a

frequency equal to the internal switching frequency set by the

RT pin.

PVIN

Figure 36 shows two ADP5014 devices configured for frequency

synchronization mode: one ADP5014 device is configured as

the clock output to synchronize another ADP5014 device.

R

TOP

UV

(CLOCK MASTER)

(SLAVE)

+

UVO

0.6V

–

GPIO

(CLK-OUT) (SYNC-IN)

R

BOT

1µA

3µA

CFG2

CFG

R1

R2

ADP5014

DEVICE 1

ADP5014

DEVICE 2

Figure 37. Undervoltage Comparator Diagram (in Sequence Mode Only)

Figure 36. Two ADP5014 Devices Configured for Synchronization Mode

In the configuration shown in Figure 36, the phase shift

between Channel 1 of the first ADP5014 device and Channel 1

of the second ADP5014 device is 0˚.

Rev. A | Page 19 of 34

ADP5014

Data Sheet

SOFT START

SHORT-CIRCUIT PROTECTION (SCP)

The buck regulators in the ADP5014 include soft start circuitry

that ramps the output voltage in a controlled manner during

startup, thereby limiting the inrush current. The soft start time

for all channels is typically fixed at 2 ms. The soft start time for

all channels can be increased by eight times using the CFG2 pin

configuration.

The buck regulators in the ADP5014 include a hiccup mode for

OCP. When the peak inductor current reaches the current-limit

threshold, the high-side MOSFET turns off and the low-side

MOSFET turns on until the next cycle.

When hiccup mode is active, the overcurrent fault counter is

incremented. If the overcurrent fault counter reaches 15 and

overflows (indicating a short-circuit condition), both the high-side

and low-side MOSFETs are turned off. The buck regulator

remains in hiccup mode for a period equal to seven soft start

cycles and then attempts to restart from soft start. If the short-

circuit fault has cleared, the regulator resumes normal operation;

otherwise, it reenters hiccup mode after the soft start.

STARTUP WITH PRECHARGED OUTPUT

The buck regulators in the ADP5014 include a precharged

startup feature to protect the low-side FETs from damage

during startup. If the output voltage is precharged before the

regulator is turned on, the regulator prevents reverse inductor

current, which discharges the output capacitor, until the

internal soft start reference voltage exceeds the precharged

voltage on a feedback (FBx) pin.

Hiccup detection is masked during the initial soft start cycle to

enable startup of the buck regulator under heavy load conditions.

Careful design and proper component selection are required to

ensure the buck regulator recovers from hiccup mode under

heavy loads.

CURRENT-LIMIT PROTECTION

The buck regulators in the ADP5014 include peak current-limit

protection circuitry to limit the amount of positive current

flowing through the high-side MOSFET switch. The peak

current limit on the power switch limits the amount of current

that can flow from the input to the output. The programmable

current-limit threshold feature allows the use of small size

inductors for low current applications.

In parallel operation, the overcurrent protection in either

channel triggers both master and slave channels entering and

exiting the hiccup protection together.

OVERVOLTAGE PROTECTION

The ADP5014 includes an overvoltage protection feature to

protect the regulator against an output short to a higher voltage

supply, or when a strong load disconnect transient occurs. If the

feedback voltage increases to 1.15 × VSETx, the internal high-

side and low-side MOSFETs are turned off until the voltage at

the FBx pin decreases to 1.1 × VSETx At that time, the

ADP5014 resumes normal operation.

To configure different output load capability, connect a resistor

from the CFG1 pin to ground according to Table 6 which lists

different output current capability settings for all channels.

The buck regulators in the ADP5014 include negative current-

limit protection circuitry to limit certain amounts of negative

current flowing through the low-side MOSFET switch.

UNDERVOLTAGE LOCKOUT

FREQUENCY FOLD BACK

UVLO circuitry monitors the input voltage level of each buck

regulator, including the analog input pin in the ADP5014. If

any input voltage (PVINx pin) falls below 2.40 V (typical), the

corresponding channel is turned off. After the input voltage rises

above 2.65 V (typical), the soft start period is initiated, and the

corresponding channel is enabled when the ENx pin is high.

The buck regulators in the ADP5014 include frequency fold

back to prevent output current runaway when a hard short

occurs on the output. Frequency fold back is implemented as

follows:

•

If the voltage at the FBx pin falls below half of the target

output voltage, the switching frequency is reduced by half.

If the voltage at the FBx pin falls again to below one-fourth

of the target output voltage, the switching frequency is

reduced by half of its current value again, equaling one-

fourth of f_SW.

A UVLO condition on the AVIN pin has a higher priority than

a UVLO condition on individual channels, which means the

AVIN pin supply must be available before individual channels

can be operated.

•

The ADP5014 supports separate input voltages for buck

regulators. This means that the input voltages for each

individual buck regulator can be connected to different supply

voltages, as long as its input voltage (PVINx pin) and its AVIN pin

voltage are above its UVLO threshold.

The reduced switching frequency allows more time for the

inductor current to decrease, but also increases the ripple

current during peak current regulation. The reduced switching

frequency results in a reduction in average current and prevents

output current runaway.

Rev. A | Page 20 of 34

Data Sheet

ADP5014

ACTIVE OUTPUT DISCHARGE SWITCH

THERMAL SHUTDOWN

Each buck regulator in the ADP5014 integrates a discharge

switch from the switching node to ground. This switch is turned on

when its associated regulator is disabled, which helps discharge

the output capacitor quickly. The typical value of the discharge

switch is 85 Ω for Channel 1 to Channel 4.

If the ADP5014 junction temperature exceeds 150°C, the thermal

shutdown circuit turns off the IC except for the internal linear

regulator. Extreme junction temperatures can be the result of

high current operation, poor circuit board design, or high ambient

temperature. A 15°C hysteresis is included so that the ADP5014

does not return to operation after thermal shutdown until the

on-chip temperature falls below 135°C. When the device exits

thermal shutdown, a soft start is initiated for each enabled channel.

Rev. A | Page 21 of 34

ADP5014

Data Sheet

APPLICATIONS INFORMATION

The equation for the output voltage setting is as follows:

ADIsimPOWER DESIGN TOOL

V

_OUT= V_REF× (1 + (R_TOP/R_BOT))

The ADP5014 is supported by the ADIsimPower™ design tool

set. ADIsimPower is a collection of tools that produce complete

power designs optimized for a specific design goal. The tools

enable the user to generate a full schematic and bill of materials

and to calculate performance in minutes. ADIsimPower can

optimize designs for cost, area, efficiency, and device count

while considering the operating conditions and limitations of the

IC and all real external components. The ADIsimPower tool can

be found at http://www.analog.com/ADIsimPower; the user

can request an unpopulated board through the tool.

where:

V

R

_OUTis the output voltage.

_REFis the 2.0 V accurate low noise reference voltage.

_TOPis the feedback resistor from V_OUTto FB.

_BOTis the feedback resistor from FB to ground.

VOLTAGE CONVERSION LIMITATIONS

For a given input voltage, lower limitations on the output voltage

exist due to the minimum on time and the minimum off time.

The minimum output voltage for a given input voltage and

switching frequency is limited by the minimum on time. The

minimum on time for each channel is 60 ns (typical). The

minimum on time increases at higher junction temperatures.

PROGRAMMING THE OUTPUT VOLTAGE

The output voltage of the ADP5014 is externally set by a resistive

voltage divider from the VREF pin to the VSETx pin and a

resistive voltage divider from the output voltage to the FBx pin.

To limit the degradation of the output voltage accuracy due to

VSETx and FBx bias current, ensure the value of the bottom

resistor in the dividers is not too large.

Note that in FPWM mode, the output voltage potentially

exceeds the nominal output voltage when the minimum on

time limit is reached. Careful switching frequency selection is

required to avoid this problem.

The ADP5014 provides adjustable output voltage settings. Use

the resistor divider from the accurate internal V_REFreference

voltage (VREF pin) to set the desired output voltage and

directly tie the FBx pin to the output when the desired output

voltage setting is less than the V_REFvoltage, as shown in Figure 38.

The equation for the output voltage setting is

The minimum output voltage in CCM mode for a given input

voltage and switching frequency is calculated using the

following equation:

V

_{OUT_MIN}= V_IN× t_{MIN_ON}× f_SW− (R_DSON1− R_DSON2) ×

_{OUT_MIN}× t_{MIN_ON}× f_SW− (R_DSON2+ R_L) × I_{OUT_MIN}

where:

_{OUT_MIN}is the minimum output voltage.

_{MIN_ON}is the minimum on time.

_SWis the switching frequency.

I

(1)

V

_OUT= V_REF× (R₂/(R₁+R₂))

V

t

f

where:

V

_OUTis the output voltage.

_REFis the 2.0 V accurate low noise reference voltage.

R

_DSON1is the high-side MOSFET on resistance.

_DSON2is the low-side MOSFET on resistance.

R₂is the resistor from VSETx to ground.

R₁is the resistor from VSETx to V_REF

.

I

_{OUT_MIN}is the minimum output current.

If the desired output voltage exceeds the V_REFvoltage, use an

external resistor divider from the output to the FBx pin to set

the desired output voltage, and tie VSETx to VREF directly, as

shown in Figure 39.

R_Lis the resistance of the output inductor.

VREF

ADP5014

INTERNAL

REFERENCE 2.0V

R1

VSETx

FBx

R2

COMPx

+

L

VOUTx

C

SWx

EA

–

Figure 38. Configure the Output Voltage when V_OUTx≤ V_REF

VREF

ADP5014

INTERNAL

REFERENCE 2.0V

L

VOUTx

C

SWx

FBx

VSETx

R

TOP

+

EA

–

COMPx

R

BOT

Figure 39. Configure the Output Voltage when V_OUTX> V_REF

Rev. A | Page 22 of 34

Data Sheet

ADP5014

The maximum output voltage for a given input voltage and

switching frequency is limited by the minimum off time or the

maximum duty cycle. The minimum off time for each channel

is 50 ns (typical).

INDUCTOR SELECTION

The inductor value is determined by the operating frequency,

input voltage, output voltage, and inductor ripple current. Using

a small inductor yields faster transient response but degrades

efficiency due to the larger inductor ripple current. Using a large

inductor value yields a smaller ripple current and better efficiency,

but results in slower transient response. Therefore, a trade-off

must be made between the transient response and efficiency. As

a guideline, the inductor ripple current, ΔI_L, is typically set to a

value from 30% to 40% of the maximum load current. The

inductor value is calculated using the following equation:

The maximum output voltage for a given input voltage and

switching frequency is calculated using the following equation:

V

_{OUT_MAX}= V_IN× (1 − t_{MIN_OFF}× f_SW) − (R_DSON1− R_DSON2) ×

_{OUT_MAX}× (1 − t_{MIN_OFF}× f_SW) − (R_DSON2+ R_L) × I_{OUT_MAX}(2)

where:

_{OUT_MAX}is the maximum output voltage.

_{MIN_OFF}is the minimum off time.

_SWis the switching frequency.

I

V

t

f

L = [(V_IN− V_OUT) × D]/(ΔI_L× f_SW)

R

_DSON1is the high-side MOSFET on resistance.

where:

R

_DSON2is the low-side MOSFET on resistance.

V_INis the input voltage.

I

_{OUT_MAX}is the maximum output current.

V

_OUTis the output voltage.

R_Lis the resistance of the output inductor.

D is the duty cycle (D = V_OUT/V_IN).

ΔI_Lis the inductor ripple current.

As shown in Equation 1 and Equation 2, reducing the switching

frequency eases the minimum on time and off time limitations.

f

_SWis the switching frequency.

The ADP5014 has internal slope compensation in the current

loop to prevent subharmonic oscillations when the duty cycle is

greater than 50%.The inductor peak current is calculated using

the following equation:

CURRENT-LIMIT SETTING

The ADP5014 has two selectable current-limit thresholds for

each channel. Ensure that the selected current-limit value is

larger than the peak current of the inductor, I_PEAK. See Table 6

for the current-limit configuration for each channel.

I

_PEAK= I_OUT+ (ΔI_L/2)

The saturation current of the inductor must be larger than the

peak inductor current. For ferrite core inductors with a fast

saturation characteristic, the saturation current rating of the

inductor are higher than the current-limit threshold of the buck

regulator to prevent the inductor from becoming saturated.

SOFT START SETTING

The buck regulators in the ADP5014 include soft start circuitry

that ramps the output voltage in a controlled manner during

startup, thereby limiting the inrush current. To set the soft start

time to a value of 2 ms or 16 ms, connect a resistor from the

CFG2 pin to the ground (see the Soft Start section).

The rms current of the inductor is calculated using the

following equation:

2

∆I_L

12

2

I_RMS

=

I_OUT

+

Shielded ferrite core materials are recommended for low core

loss and low electromagnetic interference (EMI). Table 11 lists

the recommended inductors.

Table 11. Recommended Inductors

Vendor

Part No.

Value (µH)

0.6

1.0

1.5

2.2

I_SAT(A)

10.4

8.7

7.1

5.6

I_RMS(A)

11.7

9.6

7.5

5.5

DCR (mΩ)

9.5

13.3

21.5

35.2

30

35

50

70

Size (mm)

4 × 4

Coilcraft

XAL4020-601

XAL4020-102

XAL4020-152

XAL4020-222

TOKO

Wurth

DFE252012P-R68M

DFE252012P-1R0P

DFE252012P-1R5P

DFE252012P-2R2P

744383560068

74438356010

74438356015

74438356022

0.68

1.0

1.5

5.3

4.8

3.9

3.4

4.1

3.8

3.0

2.6

2.5 × 2.0

4.1 × 4.1

2.2

0.68

1

1.5

9.4

9.0

7.8

6.2

8.2

7.2

5.8

4.7

7.5

12

15

29

2.2

Rev. A | Page 23 of 34

ADP5014

Data Sheet

INPUT CAPACITOR SELECTION

OUTPUT CAPACITOR SELECTION

The input decoupling capacitor attenuates high frequency noise

on the input and acts as an energy reservoir. This capacitor is a

ceramic capacitor and must be placed close to the PVINx pins.

The loop composed of the input capacitor, the high-side MOSFET,

and the low-side MOSFET must be kept as small as possible.

The voltage rating of the input capacitor must be greater than

the maximum input voltage. The rms current rating of the

input capacitor (I_{CIN_rms})is larger than the following equation:

The selected output capacitor affects both the output voltage

ripple and the loop dynamics of the regulator. For example, during

load step transients on the output, when the load is suddenly

increased, the output capacitor supplies the load until the

control loop can ramp up the inductor current, causing an

undershoot of the output voltage.

The output capacitance required to meet the voltage droop

requirement (C_{OUT_UV}) is calculated using the following equation:

I_{CIN_rms}= I_OUT×

D (1  D)

K_UVI_STEP²L

C_{OUT _UV}



where D is the duty cycle (D = V_OUT/V_IN).

2



V_IN V_OUT V_{OUT _UV}



PROGRAMMING THE UVLO INPUT

where:

_UVis a factor (typically set to 2).

ΔI_STEPis the load step.

K

The precision enable input can be used to program the UVLO

threshold of the input voltage, as shown in Figure 32.

ΔV_{OUT_UV}is the allowable undershoot on the output voltage.

The precision turn on threshold is 0.6 V. Use the following

Another example of the effect of the output capacitor on the loop

dynamics of the regulator is when the load is suddenly removed

from the output. The energy stored in the inductor rushes into

the output capacitor, causing an overshoot of the output voltage.

equations to calculate R_{TOP_EN}and R_{BOT_EN}

_{TOP_EN}= (0.57 V × V_{IN_RISING}− 0.6 × V_{IN_FALLING})/(0.57 V ×

4 μA − 0.6 × 1 μA)

_{BOT_EN}= (0.6 V × R_{TOP_EN})/(V_{IN_RISING}– R_{TOP_EN}× 4 μA − 0.6 V)

where:

_{TOP_EN}is the resistor from PVINx to ENx.

:

R

The output capacitance required to meet the overshoot

requirement (C_{OUT_UV}) is calculated using the following equation:

R

K_OVI_STEP²L

V

_{IN_RISING}is the V_INrising threshold.

C_{OUT _OV}



2



V_OUTV_{OUT_OV}



 V_OUT

V

_{IN_FALLING}is the V_INfalling threshold.

R

_{BOT_EN}is the resistor from ENx to ground.

where:

_OVis a factor (typically set to 2).

ΔI_STEPis the load step.

K

COMPENSATION COMPONENTS DESIGN

For the peak current-mode control architecture, the power stage

can be simplified as a voltage controlled current source that

supplies current to the output capacitor and load resistor. The

simplified loop is composed of one domain pole and a zero

contributed by the ESR of the output capacitor. The control to

output transfer function (G_vd) is shown in the following equations:

ΔV_{OUT_OV}is the allowable overshoot on the output voltage.

The output voltage ripple is determined by the equivalent series

resistance (ESR) of the output capacitor and its capacitance

value. Use the following equation to select a capacitor that can

meet the output ripple requirements:

I_L













s

C_{OUT _ RIPPLE}



1 

8  f_SWV_{OUT _ RIPPLE}

2   f_z

V

_OUT(s)

G

_vd(s) 

 A_VI R 

V_COMP(s)

V_{OUT _ RIPPLE}





s





R_ESR











2  f _p

I_L

where:

ΔV_{OUT_RIPPLE}is the allowable output voltage ripple.

_ESRis the ESR of the output capacitor.

1

f_z

2R_ESRC_OUT

R

1

Select the largest output capacitance given by C_{OUT_UV}, C_{OUT_OV}

and C_{OUT_RIPPLE}to meet both load transient and output ripple

requirements.

,

f_p

2



RR_ESRC_OUT



where:

The selected output capacitor voltage rating must be greater

than the output voltage. The minimum rms current rating of

the output capacitor (I_{COUT_rms}) is determined by the following

equation:

A_VI= 16.67A/V for Channel 1 or Channel 2, and 8.33 A/V for

Channel 3 or Channel 4.

R is the load resistance.

f_zis the frequency of the zero.

C

R

_OUTis the output capacitance.

_ESRis the equivalent series resistance of the output capacitor.

f_pis the frequency of the pole.

I_L

12

I_{COUT_rms}

=

Rev. A | Page 24 of 34

Data Sheet

ADP5014

The ADP5014 uses a transconductance amplifier as the error

amplifier to compensate the system. Figure 40 shows the

simplified peak current-mode control small signal circuit.

Power Switch Conduction Loss (P_COND

)

Power switch conduction losses are caused by the flow of output

current through both the high-side and low-side power switches,

each of which has on resistance (R_DS(ON).

V

OUT

R

TOP

Use the following equation to estimate the power switch

conduction loss:

V

C

R

COMP

OUT

–

g_m

+

–

A

VI

2

P

_COND= (R_{DS(ON)_HS}× D + R_{DS(ON)_LS}× (1 − D)) × I_OUT

R

BOT

R

C

CP

where:

ESR

C

R

_{DS(ON)_HS}is the high-side MOSFET on resistance.

_{DS(ON)_LS}is the low-side MOSFET on resistance.

D is the duty cycle (D = V_OUT/V_IN).

Figure 40. Simplified Peak Current-Mode Control Small Signal Circuit

Switching Loss (P_SW)

The compensation components, R_Cand C_C, contribute a zero

and the optional C_CPand R_Ccontribute an optional pole.

Switching losses are associated with the current drawn by the

driver to turn the power devices on and off at the switching

frequency. Each time a power device gate is turned on or off,

the driver transfers a charge from the input supply to the gate,

and then from the gate to ground. Use the following equation to

estimate the switching loss:

The closed-loop transfer (T_V(s)) equation is as follows:

1+ R_C× C_C× s

R_C×C_C×C_CP

R_BOT

_BOT+ R_TOPC_C+ C_CP

−g_m

T_V(s) =

×

×G_vd(s)







R



s × 1+

× s





C_C+ C_CP

P

_SW= (C_{GATE_HS}+ C_{GATE_LS}) × V_IN²× f_SW





The following procedure shows how to select the compensation

components—R_C, C_C, and C_CP,—for ceramic output capacitor

applications.

where:

C_{GATE_HS}is the gate capacitance of the high-side switch.

_{GATE_LS}is the gate capacitance of the low-side switch.

C

1. Determine the cross frequency (f_C). Generally, f_Cis between

f_SW/12 and f_SW/6.

2. R_Ccan be calculated using the following equation:

f

_SWis the switching frequency.

Transition Loss (P_TRAN

)

Transition losses occur because the high-side switch cannot

turn on or off instantaneously. During a switch node transition,

the power switch provides all the inductor current. The source

to drain voltage of the power switch is half the input voltage,

resulting in power loss. Transition losses increase with both

load and input voltage and occur twice for each switching cycle.

Use the following equation to estimate the transition loss:

2 × π×V_OUT×C_OUT× f_C

R_C

=

VSETx × g_m× A_VI

3. Place the compensation zero at the domain pole (f_P).

C_Ccan be determined as follows:

(

R + R_ESR× C_OUT

)

C_C=

R_C

_CPis optional. It can be used to cancel the zero caused by

the ESR of the output capacitor.

P

_TRAN= 0.5 × V_IN× I_OUT× (t_R+ t_F) × f_SW

4.

C

where:

t_Ris the rise time of the switch node.

t_Fis the fall time of the switch node.

R

_ESR×C_OUT

C_CP

=

Thermal Shutdown

R_C

When the ADP5014 operates under a heavy load in a high

ambient temperature, the power loss can cause the junction

temperature to exceed the maximum junction temperature of

125°C. If the junction temperature exceeds 150°C, the regulator

enters thermal shutdown and recovers when the junction

temperature falls below 135°C.

POWER DISSIPATION

The total power dissipation in the ADP5014 (P_D) simplifies to

P_D= P_BUCK1+ P_BUCK2+ P_BUCK3+ P_BUCK4

Buck Regulator Power Dissipation

The power dissipation (P_LOSS) for each buck regulator includes

power switch conductive losses (P_COND), switch losses (P_SW), and

transition losses (P_TRAN). Other sources of power dissipation exist,

but these sources are generally less significant at the high output

currents of the application thermal limit.

Use the following equation to estimate the power dissipation of

the buck regulator:

P

_LOSS= P_COND+ P_SW+ P_TRAN

Rev. A | Page 25 of 34

ADP5014

Data Sheet

ambient temperature of the package (see Table 4). Thermal

JUNCTION TEMPERATURE

performance is directly linked to PCB design and operating

environment. Careful attention to PCB thermal design is

required.

P_Dis the power dissipation in the package.An important factor

to consider is that the thermal resistance value is based on a

4-layer, 4 inch × 3 inch PCB with 2.5 oz of copper, as specified

in the JEDEC standard, whereas real world applications can use

PCBs with different dimensions and a different number of

layers.

The junction temperature of the die is the sum of the ambient

temperature of the environment and the temperature rise of the

package due to power dissipation, as shown in the following

equation:

T_J= T_A+ T_R

where:

T_Jis the junction temperature.

T_Ais the ambient temperature.

T_Ris the rise in temperature of the package due to power

dissipation.

It is important to maximize the amount of copper used to

remove heat from the device. Copper exposed to air dissipates

heat better than copper used in the inner layers. The exposed

pad is connected to the ground plane with several vias.

The rise in temperature of the package is directly proportional

to the power dissipation in the package. The proportionality

constant for this relationship is the thermal resistance from the

junction of the die to the ambient temperature, as shown in the

following equation:

T_R= θ_JA× P_D

where:

T_Ris the rise in temperature of the package.

θ_JAis the thermal resistance from the junction of the die to the

Rev. A | Page 26 of 34

Data Sheet

ADP5014

DESIGN EXAMPLES

This section provides an example of the step by step design

procedures and the external components required for Channel 1.

Table 12 lists the design requirements for this example.

To set the output voltage to 1.2 V, choose the following resistor

values: R1 = 6.65 kΩ, and R2 = 10 kΩ.

SETTING THE CONFIGUATIONS (CFG1 AND CFG2)

Table 12. Example Design Requirements for Channel 1

The CFG1 pin can be used to program the load output

capability and parallel operation for all channels. For this

example, choose R_CFG1= 0 kΩ. For more information, see the

configuration in Function Configurations (CFG1 and CFG2).

Parameter

Specification

Input Voltage

Output Voltage

Output Current

Output Ripple

Load Transient

V_PVIN1= 5 V 5%

V_OUT1= 1.2 V

I_OUT1= 4 A

ΔV_{OUT1_RIPPLE}= 5 mV in CCM mode

5%, at 20% to 80% load transient, 1 A/µs

The CFG2 pin can be used to program the operation mode

(FPWM or PWM/PSM mode), the enable mode (manual mode

or sequence mode), the timer (×1 or ×8), and GPIO functionalities

(PWRGD, SYNC-IN, CLK-OUT, UVO) for all channels. For

this example, choose R_CFG2= 0 kΩ. For more information, see the

configuration in Function Configurations (CFG1 and CFG2).

Although this example shows step by step design procedures for

Channel 1, the procedures apply to all other buck regulator

channels (Channel 2 to Channel 4).

SELECTING THE INDUCTOR

SETTING THE SWITCHING FREQUENCY

The peak-to-peak inductor ripple current, ΔI_L, is set to 30% of

the maximum output current. Use the following equation to

estimate the value of the inductor (L):

The first step when setting the switching frequency is to determine

the switching frequency for the ADP5014 design. In general,

higher switching frequencies produce a smaller solution size

due to the lower component values required, whereas lower

switching frequencies result in higher conversion efficiency due

to lower switching losses.

(V_IN− V_OUT) ×D

L =

∆I_L× f_SW

where:

V_IN= 5 V.

The switching frequency of the ADP5014 can be set to a value

from 500 kHz to 2.5 MHz by connecting a resistor from the RT

pin to ground. The selected resistor allows users to make

decisions based on the trade-off between efficiency and solution

size. For more information, see the Oscillator section.

V

_OUT= 1.2 V.

D is the duty cycle (D = V_OUT/V_IN= 0.24).

ΔI_L= 30% × 4 A = 1.2 A.

f

_SW= 1.2 MHz.

However, the highest supported switching frequency must be

assessed by checking the voltage conversion limitations

enforced by the minimum on time and the minimum off time

(see the Voltage Conversion Limitations section).

The resulting value for L is 0.63 µH. The closest standard

inductor value is 0.8 µH; therefore, the inductor ripple current,

ΔI_L1, is 0.95 A.

The inductor peak current is calculated using the following

equation:

In this design example, a switching frequency of 1.2 MHz

achieves a good combination of small solution size and high

conversion efficiency. To set the switching frequency to

1.2 MHz, use the following equation to calculate the resistor

value, R_RT:

I

_PEAK= I_OUT+ (ΔI_L/2)

The calculated peak current for the inductor is 4.48 A.

The rms current of the inductor can be calculated using the

following equation:

R

_RT(kΩ) = (100,000/f_SW(kHz))

According to this equation, select standard resistor R_RT

82.5 kΩ.

=

2

∆I_L

12

2

I_RMS

=

I_OUT

+

SETTING THE OUTPUT VOLTAGE

The rms current of the inductor is approximately 4.01 A.

Therefore, an inductor with a minimum rms current rating of

4.01 A and a minimum saturation current rating of 4.48 A is

required. However, to prevent the inductor from reaching its

saturation point in current-limit conditions, it is recommended

that the inductor saturation current be higher than the maximum

peak current limit, typically 6 A, for reliable operation.

Because the desired output voltage setting is less than V_REF

voltage, use the resistor divider from the accurate internal

VREF reference voltage to set the desired output voltage and

directly tie the feedback pin (FB1) to the output (see Figure 38).

Select a 10 kΩ bottom resistor (R2) and then calculate the top

resistor using the following equation:

R1 = R2 × ((V_REF− V_OUT)/V_OUT

)

Based on these requirements and recommendations, the

COILCRAFT XAL5030-801MEB, with a direct current

resistance (DCR) of 5.14 mΩ, is selected for this design.

where:

V

_OUTis the output voltage.

_REFis 2.0 V for Channel 1 to Channel 4.

Rev. A | Page 27 of 34

ADP5014

Data Sheet

120

100

80

120

100

80

SELECTING THE OUTPUT CAPACITOR

The output capacitor must meet the output voltage ripple and

load transient requirements. To meet the output voltage ripple

requirement, use the following equation to calculate the ESR

and capacitance:

60

40

20

0

∆I_L

C_{OUT _ RIPPLE}

=

–20

–40

–60

–80

–100

–120

–20

–40

–60

–80

–100

–120

8 × f_SW× ∆V_{OUT _ RIPPLE}

∆V_{OUT _ RIPPLE}

∆I_L

R_ESR

=

CROSS FREQUENCY = 132kHz

PHASE MARGIN = 56°

The calculated capacitance, C_{OUT_RIPPLE}, is 19.8 µF, and the

calculated R_ESRis 5 mΩ.

1k

10k

100k

FREQUENCY (Hz)

1M

Figure 41. Bode Plot for 1.2 V Output

To meet the 5% overshoot and undershoot requirements,

use the following equations to calculate the capacitance:

K_UV× ∆I_STEP²× L

C_{OUT _UV}

=

2×

(

V_IN− V_OUT× ∆V_{OUT _UV}

)

1

K_OV× ∆I_STEP²× L

C_{OUT _OV}

2

(

V_OUT+ ∆V_{OUT_OV}

)

− V_OUT

For estimation purposes, use K_OV= K_UV= 2; therefore,

_{OUT_OV}= 62.4 µF and C_{OUT_UV}= 20.2 µF.

C

The ESR of the output capacitor must be less than 5 mΩ,

and the output capacitance must be greater than 62.4 µF. It is

recommended that two ceramic capacitors be used (47 µF, X5R,

6.3 V), such as the GRM21BR60J476ME15 from Murata with

an ESR of 2 mΩ.

4

B

CH1 5.00mV

M100µs

25.8%

A CH4

2.16A

W

T

CH4 2A Ω

Figure 42. Selecting the Input Capacitor

DESIGNING THE COMPENSATION NETWORK

For the input capacitor, select a ceramic capacitor with a

minimum value of 10 µF. The input capacitor is placed close to

the PVINx pin. In this example, one ceramic capacitor of 10 µF,

X5R, 16 V is recommended.

For better load transient and stability performance, set the cross

frequency, f_C, to f_SW/10. In this example, f_SWis set to 1.2 MHz;

therefore, f_Cis set to 120 kHz.

For the 1.2 V output rail, the 47 μF ceramic output capacitor has

a derated value of 32 µF.

LOW NOISE OUTPUT DESIGN

The ADP5014 optimizes many analog blocks and uses new unity-

gain reference architecture to achieve lower output noise in low-

frequency range. When the system design needs the low noise

output of ADP5014 , the device enables powering up the signal

chain products directly without LDOs. In this scenario, adding

an additional LC filter is highly recommended after the main

LC filter to filter the fundamental switching ripple and its

harmonic. This is because the switching ripples may generate

unexpected noise spurs for the noises sensitive signal chain

devices. Because this additional inductor filter may generate

voltage drop at the load, the inductor with small DCR is

recommended to minimize the voltage drop, especially for high

current applications.

2 × π ×1.2 V× 2 ×32µF×120 kHz

R_C=

C_C=

= 3.62 k Ω

= 5.32 nF

1.2 V × 800µs ×16.67A/V

(

0.3Ω + 0.001 Ω × 2 × 32µF

)

3.62 k Ω

0.001 Ω × 2 ×32 µF

3.62 k Ω

C_CP

=

= 17.7 pF

Choose standard components: R_C= 3.57 kΩ and C_C= 5.6 nF.

_CPis optional.

C

Figure 41 shows the bode plot for the 1.2 V output rail. The

cross frequency is 132 kHz, and the phase margin is 56°. The

load transient waveform is shown in Figure 42.

Figure 43 and Figure 44 show the ADP5014 noise spectral

density measurement from a 10 Hz to 10 MHz frequency range

and integrated rms noise from a 10 Hz to 1 MHz frequency

range, compared to the ADP1740 as another traditional, 2 A,

low noise linear regulator.

Rev. A | Page 28 of 34

Data Sheet

ADP5014

10k

50

45

40

35

30

25

20

15

10

5

ADP5014

ADP1740

ADP5014

ADP1740

1k

100

10

1

0.1

10

0

10

100

1k

10k

100k

1M

10M

100

1k

10k

100k

1M

FREQUENCY (Hz)

Figure 43. ADP5014 Noise Spectral Density Measurement, V_IN= 5 V, V_OUT1

1.3 V, I_OUT1= 0.5 A, f_SW= 1.2 MHz, L₁= 0.8 μH, C_OUT= 47 μF × 3, L_FILTER= 1 μH,

C_FILTER= 22 μF × 2

=

Figure 44. ADP5014 Integrated RMS Noise, V_IN= 5 V, V_OUT1= 1.3 V, I_OUT1= 0.5 A,

f_SW= 1.2 MHz, L₁= 0.8 μH, C_OUT= 47 μF × 3, L_FILTER= 1 μH, C_FILTER= 22 μF × 2

Rev. A | Page 29 of 34

ADP5014

Data Sheet

PCB LAYOUT RECOMMENDATIONS

Good circuit board layout is essential to obtain the best

performance from the ADP5014 (see Figure 45). Poor layout can

affect the regulation and stability of the device, as well as the

EMI and electromagnetic compatibility (EMC) performance.

Refer to the following guidelines for a good PCB layout.

•

Maximize the amount of ground metal for the exposed pad,

and use as many vias as possible on the component side to

improve thermal dissipation.

Use a ground plane with several vias connecting to the

component side ground to further reduce noise

interference on sensitive circuit nodes.

•

Place the input capacitor, inductor, and output capacitor

close to the IC.

•

Place the decoupling capacitors close to the VREF pin.

Place the RC filter close to the AVIN pin.

•

Use short, thick traces to connect the input capacitors

to the PVINx pins, and use dedicated power ground to

connect the input and output capacitor grounds to

minimize the connection length.

Place the frequency setting resistor close to the RT pin.

Place the V_REFresistor divider close to the VSETx and the

feedback resistor divider close to the FBx pin. In addition,

keep the VSETx and FBx traces away from the high current

traces and the switch node to avoid noise pickup.

Use size 0402 or 0603 resistors and capacitors to achieve

the smallest possible footprint solution on boards where

space is limited.

•

Use several high current vias, if required, to connect

PVINx, PGNDx, or SWx to other power planes.

Use short, thick traces to connect the inductors to the

SWx pins and the output capacitors.

Ensure that the high current loop traces are as short and wide

as possible.

•

R0402

47µF

6.5V/XR5

0805

VSET4 VSET3 VREF VSET2 VSET1 RT

FB3

AVIN

FB1 COMP1 PVIN1

PVIN1 30

1

2

3

4

5

6

7

8

9

VOUT1

29

SW1

COMP3

PVIN3

SW3

47µF

6.3V/XR5

0805

SW1 28

PGND1 27

PGND1 26

PGND2 25

47µF

6.3V/XR5

0603

PGND3

PGND4

SW4

ADP5014

6mm × 6mm

47µF

6.3V/XR5

0603

PGND2

24

SW2 23

PVIN4

COMP4

47µF

6.3V/XR5

0805

SW2

22

PVIN2 21

10 FB4

EN4/

EN2/ EN1/

GPIO DL34 EN3/UV CFG2 CFG1 DL12 ENALL FB2 COMP2 PVIN2

VOUT2

47µF

6.3V/XR5

0805

R0402

Figure 45. Typical PCB Layout for the ADP5014

Rev. A | Page 30 of 34

Data Sheet

ADP5014

TYPICAL APPLICATION CIRCUITS

ADP5014

VREF

0.47µF

RT

OSC

REF

82.5kΩ

EN1/ENALL

EN2/DL12

VREF

CFG1

0Ω

CFG2 31.6kΩ

0Ω

EN3/UV

LOGIC DECODER

EN4/DL34

GPIO

FB1

26.1kΩ

AVIN

5.0V

PVIN1

C2

C1

SW1

10µF

1µF

L1

CH 1

BUCK

(2A/4A)

VOUT1

1.2V/4A

VCORE

0.8µH

VREF

SW1

C3

47µF

C4

47µF

C5

47µF

VSET1

13.3kΩ

PGND1

20kΩ

FPGA

COMP1

PGND1

20kΩ

4.32kΩ

10nF

FB2

PVIN2

4.99kΩ

L2

0.8µH

AUXILIARY

VOLTAGE

SW2

C6

10µF

CH 2

BUCK

(2A/4A)

PVIN2

VSET2

VOUT2

2.5V/2A

VREF

10nF

SW2

C7

47µF

C8

47µF

BANK 0

BANK 1

PGND2

I/Os

BANK 2

COMP2

PGND2

4.32kΩ

PVIN3

L3

SW3

FB3

VOUT3

1.5V/2A

I/Os

BANK 3

C9

1.5µH

10µF

C10

47µF

CH 3

BUCK

(1A/2A)

VREF

VSET3

6.65kΩ

20kΩ

10nF

PGND3

DDR

TERM. LDO

DDR3 MEMORY

FLASH MEMORY

COMP3

4.32kΩ

PVIN4

L4

VOUT4

3.3V/2A

SW4

FB4

C11

10µF

1.5µH

C12

47µF

CH 4

BUCK

(1A/2A)

VREF

VSET4

13kΩ

20kΩ

PGND4

COMP4

6.04kΩ

10nF

AGND

EXPOSED PAD

ENALL

2ms

36ms

24ms

1.2V

6ms

2.5V/1.5V

3.3V

12ms

Figure 46. Typical Field Programmable Gate Array (FPGA) Application, 1.2 MHz Switching Frequency, Sequence Enable Mode

Rev. A | Page 31 of 34

ADP5014

Data Sheet

ADP5014

VREF

0.47µF

RT

OSC

REF

82.5kΩ

VREF

CFG1

EN1/ENALL

EN2/DL12

0Ω

CFG2 31.6kΩ

17.8kΩ

EN3/UV

LOGIC DECODER

EN4/DL34

GPIO

FB1

56.2kΩ

AVIN

5.1kΩ

RF TRANSCEIVER

5.0V

PVIN1

C2

3.3nF

VOUT1

C1

L1

1µH

L5

220nH

SW1

10µF

1µF

CH 1

BUCK

(2A/4A)

1.3V/3000mA

1.3V ANALOG

VREF

SW1

C3

47µF

C4

C5

47µF

C6

47µF

VSET1

10.7kΩ

47µF

PGND1

0.1Ω

1.3V VDD_JESD

20kΩ

COMP1

PGND1

FB2

4.32kΩ

10nF

5.1kΩ

PVIN2

3.3nF

C7

L6

220nH

SW2

L2

1µH

CH 2

BUCK

(2A/4A)

10µF

PVIN2

VSET2

1.3V/1500mA

VOUT2

VREF

1.3V DIGITAL

10.7kΩ

SW2

PGND2

C8

47µF

C9

47µF

C10

47µF

C11

47µF

20kΩ

0.1Ω

COMP2

PGND2

4.32kΩ

10nF

L3

PVIN3

VSET3

1.5µH

SW3

FB3

VOUT3

3.3V/600mA

3.3V VDD_GPO

C12

10µF

C13

47µF

CH 3

BUCK

(1A/2A)

VREF

18nF

13kΩ

20kΩ

COMP3

PGND3

6.04kΩ

PVIN4

VSET4

1.8V LVDS/CMOS

1.8V TX

C14

10µF

L4

1.5µH

L8

220nH

CH 4

BUCK

(1A/2A)

VREF

1.8V/600mA

SW4

VOUT4

2.21kΩ

20kΩ

C15

47µF

C16

47µF

C17

47µF

FB4

COMP4

PGND4

0.1Ω

3.3nF

5.1kΩ

4.32kΩ

15nF

AGND

EXPOSED PAD

ENALL

2ms

36ms

24ms

1.3V DIG

1.3V ANA

6ms

3.3V VDD/

1.8V TX

12ms

Figure 47. Typical RF Transceiver Application, 1.2 MHz Switching Frequency, Sequence Enable Mode

Rev. A | Page 32 of 34

Data Sheet

ADP5014

FACTORY PROGRAMMABLE OPTIONS

FACTORY DEFAULT OPTIONS

Table 13 lists the factory default options programmed into the ADP5014 when the device is ordered (see the Ordering Guide). To order

the device with options other than the default options, contact your local Analog Devices sales or distribution representative.

Table 13. Factory Default Options

Option

Default Value

Channel 1 Output Voltage

Channel 2 Output Voltage

Channel 3 Output Voltage

Channel 4 Output Voltage

PWRGD Pin Output

Adjustable output

Monitor all Channel 4 outputs (enabled by the CFG2 configuration)

Enabled for all four buck regulators

Hiccup protection enabled for overcurrent events

Output Discharge Function

Hiccup Detection

Rev. A | Page 33 of 34

ADP5014

Data Sheet

OUTLINE DIMENSIONS

DETAIL A

(JEDEC 95)

6.10

6.00 SQ

5.90

0.30

0.23

0.18

PIN 1

INDICATOR

AREA

PIN 1

40

INDICATOR AR EA OP TIONS

31

(SEE DETAIL A)

30

1

0.50

BSC

4.45

EXPOSED

PAD

4.30 SQ

4.25

21

20

10

11

0.45

0.40

0.35

0.20 MIN

TOP VIEW

SIDE VIEW

BOTTOM VIEW

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

0.80

0.75

0.70

0.05 MAX

0.02 NOM

SECTION OF THIS DATA SHEET.

COPLANARITY

0.08

0.20 REF

SEATING

PLANE

COMPLIANT TO JEDEC STANDARDS MO-220-WJJD-5

Figure 48. 40-Lead Lead Frame Chip Scale Package [LFCSP]

6 mm × 6 mm Body, and 0.75 mm Package Height

(CP-40-10)

Dimensions shown in millimeters

ORDERING GUIDE

Model¹

Temperature Range

−40°C to +125°C

Package Description

Package Option²

CP-40-10

ADP5014ACPZ-R7

ADP5014-EVALZ

40-Lead Lead Frame Chip Scale Package [LFCSP]

Evaluation Board

¹Z = RoHS Compliant Part.

²Table 13 lists the factory default options for the device. For a list of factory programmable options, see the Factory Programmable Options section. To order a device

with options other than the default values, contact your local Analog Devices sales or distribution representative.

registered trademarks are the property of their respective owners.

D15496-0-8/19(A)

Rev. A | Page 34 of 34


型号：	ADP5014
厂家：	ADI
描述：	Integrated Power Solution with Quad Low Noise Buck Regulators
文件：	总34页 (文件大小：827K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADP5014 [ADI]

相关型号：

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ADP5014ACPZ-R7

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ADP5020ACPZ-R7

ADP5020CP-EVALZ

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ADP5022ACBZ-1-R7

ADP5022ACBZ-2-R7

ADP5022ACBZ-4-R7

ADP5023

ADP5023ACPZ-1-R7

ADP5023ACPZ-R7