ADP5020ACPZ-R7 [ADI]
Power Management Unit for Imaging Modules; 成像模块的电源管理单元
| 型号： | ADP5020ACPZ-R7 |
| 厂家： | 
ADI |
| 描述： | Power Management Unit for Imaging Modules |
| 文件： | 总28页 (文件大小：933K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Power Management Unit
for Imaging Modules
ADP5020
TYPICAL APPLICATIONS CIRCUIT
FEATURES
V
IN
2.4V TO 5.5V
Input voltage range: 2.4 V to 5.5 V
Low standby current: 1 μA
Switching frequency: 3 MHz
I2C interface
Synchronous Buck 1 regulator: 600 mA
Synchronous Buck 2 regulator: 250 mA
Low dropout regulator (LDO): 150 mA
Internal compensation
SW1
VDD1
VDD2
VDD3
VDDA
10µF
2.2µH
V
OUT1
2.5V TO 3.7V
VOUT1
VOUT1
10µF
PGND1
V
OUT2
ADP5020
2.2µH
1.1V TO 1.8V
SW2
Internal soft start
Thermal shutdown
1µF
4.7µF
VOUT2
V
DD_IO
1.7V TO 3.6V
VDD_IO
PGND2
VOUT3
20-lead 4 mm × 4 mm LFCSP
V
OUT3
1.8V TO 3.3V
10kΩ 10kΩ
0.1µF
APPLICATIONS
Digital cameras, handsets
Mobile TVs
1µF
SDA
SCL
EXT. FREQ
9.6/19.2MHz
SYNC
XSHTDN
EN/GPIO
DGND
AGND
Figure 1.
GENERAL DESCRIPTION
The ADP5020 provides a highly integrated power solution that
includes all of the power circuits necessary for a digital imaging
module. It comprises two step-down dc-to-dc converters, one
LDO, and a power sequence controller. All dc-to-dc converters
integrate power pMOSFETs and nMOSFETs, making the system
simpler and more compact and reducing the cost. The ADP5020
has digitally programmed output voltages and buck converters
that can source up to 600 mA. A fixed frequency operation of
3 MHz enables the use of tiny inductors and capacitors. The buck
converters use a voltage mode, constant-frequency PWM control
scheme, and the synchronous rectification is implemented to
reduce the power loss. The Buck 1 regulator operates at up to
93% efficiency.
The ADP5020 provides high performance, reduces component
count and size, and is lower in cost when compared to conven-
tional designs.
The ADP5020 runs on input voltage from 2.4 V to 5.5 V and
supports one-cell lithium-ion (Li+) batteries. The high perfor-
mance LDO maximizes noise suppression. The ADP5020 can be
activated via an I2C® interface or through a dedicated enable input.
During logic-controlled shutdown, the input is disconnected
from the output source, and the part draws 1 μA typical from
the input source. Other key features include undervoltage lockout
to prevent deep-battery discharge and soft start to prevent input
current overshoot at startup. The ADP5020 is available in a
20-lead LFCSP.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2009 Analog Devices, Inc. All rights reserved.
ADP5020
TABLE OF CONTENTS
Features .............................................................................................. 1
Undervoltage Lockout ............................................................... 13
Thermal Shutdown .................................................................... 13
Control Registers............................................................................ 14
Device Address ........................................................................... 14
Register Map ............................................................................... 14
Register Descriptions................................................................. 14
Power-Up/Power-Down Sequence............................................... 17
Sequencer .................................................................................... 17
Default Power-On Sequence with EN Pin .............................. 17
Power-On Sequence Using the I2C Interface.............................. 19
Power-Up/Power-Down State Flow......................................... 20
Applications Information.............................................................. 21
Power Good Status..................................................................... 21
XSHTDN Logic .......................................................................... 21
Components Selection............................................................... 21
LDO Input Filter......................................................................... 22
Layout Recommendations............................................................. 23
Applications Schematic ............................................................. 23
PCB Board Layout Recommendations.................................... 24
External Component List.......................................................... 24
Outline Dimensions....................................................................... 25
Ordering Guide .......................................................................... 25
Applications....................................................................................... 1
Typical Applications Circuit............................................................ 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Functional Block Diagram .............................................................. 3
Specifications..................................................................................... 4
Switching Specifications .............................................................. 5
DC-to-DC Conversion Specifications, Buck 1 Regulator....... 5
DC-to-DC Conversion Specifications, Buck 2 Regulator....... 6
VOUT3 Specifications, Low Dropout (LDO) Regulator ........ 6
I2C Timing Specifications............................................................ 7
Absolute Maximum Ratings............................................................ 8
Thermal Resistance ...................................................................... 8
ESD Caution.................................................................................. 8
Pin Configuration and Function Descriptions............................. 9
Typical Performance Characteristics ........................................... 10
Theory of Operation ...................................................................... 13
Circuit Operation ....................................................................... 13
Internal Compensation.............................................................. 13
Current Limiting and Short-Circuit Protection..................... 13
Synchronization.......................................................................... 13
I2C Interface ................................................................................ 13
REVISION HISTORY
4/09—Revision 0: Initial Version
Rev. 0 | Page 2 of 28
ADP5020
FUNCTIONAL BLOCK DIAGRAM
VDD3 VDD2 VDD1
VDDA
UVLO
SW1
RESET
XSHTDN
BUCK 1
VOUT1
VOUT1
PGND1
SCL
2
I C
SDA
SW2
BUCK 2
VDD_IO
CONTROL
LOGIC
VOUT2
PGND2
EN/GPIO
SYNC
THERMAL
SHUTDOWN
LDO
VOUT3
BUCK1_EN
SEQUENCER
BUCK2_EN
LDO_EN
HOUSE-
KEEPING
VDDA
DGND
AGND
Figure 2.
Rev. 0 | Page 3 of 28
ADP5020
SPECIFICATIONS
TJ = −40°C to +125°C, VDDx = 3.6 V, VDD_IO = 1.8 V, unless otherwise noted.
Table 1.
Parameter
Symbol Conditions
Min
Typ
Max
Unit
OPERATING RANGE
VDDx Operating Voltage Range
Logic I/O Operating Voltage Range1
EN, SDA, SCL CHARACTERISTICS
Low Level Input Voltage
High Level Input Voltage
INPUT LOGIC CURRENT
XSHTDN, EN/GPIO
VDD
VDD_IO
2.4
1.7
5.5
3.6
V
V
VIL
VIH
0.3 × VDD_IO
V
V
0.7 × VDD_IO
−1
ILK
Internal pull-down, 1 MΩ
+6
μA
Low Level Output Voltage
High Level Output Voltage
OUTPUT LOGIC LEAKAGE CURRENT
UNDERVOLTAGE LOCKOUT THRESHOLD
Falling
VOL
VOH
ILK
IRST = +3 mA
IRST = −3 mA
0.2 × VDD_IO
1
V
V
0.8 × VDD_IO
μA
VUVLOF
VUVLOR
Referenced to VDDA
Referenced to VDDA
1.8
1.0
2.0
2.2
V
V
Rising
2.4
1.7
POWER-ON RESET THRESHOLD
Falling
Rising
VPORF
VPORR
Referenced to VDDA
Referenced to VDDA
VDD > POR levels
1.4
1.6
50
1
V
V
UVLO GLITCH DEBOUNCE TIME
SHUTDOWN OUTPUT DURATION2
POWER GOOD (POK) ACTIVATION DELAY TIME3
EN to First Regulator
First to Second Regulator
Second to Third Regulator
NO LOAD CURRENT CHARACTERISTICS
Standby Current
μs
ms
tXSHTDN
XSHTDN line driven low
tREG1
tREG2
tREG3
5
5
5
ms
ms
ms
IQ(STNBY)
ILOCK
IQ
EN = 0
EN = 0, VDDA < VUVLOF
ILOAD = 0 mA
1
1
10
5
1
15
μA
μA
mA
Lockout Current
Operating Quiescent Current, Switching4
THERMAL CHARACTERISTICS
Thermal Shutdown, TJ Rising
Thermal Shutdown Hysteresis
HOUSEKEEPING BLOCK
Power Good Threshold
TSD
150
30
°C
°C
VPG
70
80
90
%
1 The VDD_IO voltage must be less than or equal to the level on the VDDx supply lines.
2 Shutdown output duration is automatic when using the EN pin. To get this delay when using I2C, FORCE_XS must be set to 1.
3 Activation delays apply only when the device is activated through the EN pin or the EN_ALL bit (Address 0x03[4]); the sequencer controls the turning on of the
regulators.
4 The quiescent current is calculated as though all regulators are powered up.
Rev. 0 | Page 4 of 28
ADP5020
SWITCHING SPECIFICATIONS
Table 2.
Parameter
Symbol Conditions
Min
Typ
Max
Unit
SWITCHING FREQUENCY
CH1
CH2
fSW1
fSW2
Sync disabled
Sync disabled
2.5
2.5
3
3
3.6
3.6
MHz
MHz
SYNC CLOCK DIVIDER RATIO
RATIODIV SYNC_9P6 = 1
RATIODIV SYNC_19P2 = 1
3
6
SYNC CHARACTERISTICS
Frequency Range
fSYNC1
fSYNC2
fSYNCDUTY
9.6
19.2
50
MHz
MHz
%
Frequency Duty Cycle
Signal
40
60
DC Coupling Level
Low Level Input Voltage
High Level Input Voltage
DC Coupling
AC Coupling Level
AC Coupling Capacitor
Input Current
VIL
VIH
VSYNC
VCAC-PP
0.3 × VDD_IO
V
V
V
V
nF
μA
0.7 × VDD_IO
0
0.5
VDD_IO
VDD_IO
Sine wave, peak-to-peak
SYNC_9P6 = 1, or SYNC_19P2 = 1
1.0
10
50
ISYNC
DC-TO-DC CONVERSION SPECIFICATIONS, BUCK 1 REGULATOR
Table 3.
Parameter
Symbol Conditions
Min
Typ
Max
Unit
OUTPUT VOLTAGE
Range1
Initial Accuracy
VOUT1
3-bit range
TA = 25°C, VDD12, VOUT1 = 3.3 V, ILOAD = 20 mA
VDD13, ILOAD = 50 mA to 600 mA
2.5
−1
−5
3.7
+1
+4
V
%
%
Total Accuracy
VOUT1 REGULATION
Load Regulation
Line Regulation
ILOAD = 20 mA to 600 mA
VDDA = 1.8 V, VDD1
0.2
0.15
%
%
2, 3
CURRENT
Maximum Output Current
Quiescent Current
POWER
IBK1MAX
IQBK1
VDD13, VOUT1 = 2.5 V to 3.7 V
ILOAD = 0 mA
600
6
mA
mA
4
Low-Side Power nMOSFET
High-Side Power pMOSFET
SWITCH CURRENT LIMIT
MINIMUM ON TIME
MAXIMUM DUTY CYCLE
SOFT START TIME
COUT DISCHARGE SWITCH ON RESISTANCE
RDSON1
RDSON1
ICL1
ID = 400 mA
ID = 400 mA
175
250
1.2
55
250
400
1.6
mΩ
mΩ
A
0.8
0.7
tMIN1
DMAX1
tSS1
ns
88
95
%
1.4
1
ms
kΩ
RDIS1
1.3
1 See Table 13 (the BUCK1_VSEL register, Address 0x01) for details.
2 VDD1 = 3.1 V to 5.5 V, ILOAD is less than 200 mA. For tight regulation, the supply voltage must be 0.6 V higher than the output voltage.
3 VDD1 = 3.7 V to 5.5 V, ILOAD is more than 200 mA. For tight regulation, the supply voltage must be 1.2 V higher than the output voltage.
Rev. 0 | Page 5 of 28
ADP5020
DC-TO-DC CONVERSION SPECIFICATIONS, BUCK 2 REGULATOR
Table 4.
Parameter
Symbol
Conditions
Min Typ
Max
Unit
OUTPUT VOLTAGE
Adjustable Range1
Initial Accuracy
Total Accuracy
Load Regulation
VOUT2
4-bit range
1.1
1.8
+1
+4
V
TA = 25°C, VDD2 = 3.6 V, VOUT2 = 1.2 V, ILOAD = 20 mA −1
VDD2 = 2.5 V to 5 V, ILOAD = 10 mA to 250 mA
ILOAD = 10 mA to 250 mA
%
%
%
%
−5
0.2
0.15
Line Regulation
VDDA = 1.8 V, VDD2 = 2.5 V to 5 V
CURRENT
Maximum Output Current
Quiescent Current
POWER
IBK2MAX
IQBK2
250
6.5
mA
mA
ILOAD = 0 mA
4
Low-Side Power nMOSFET
High-Side Power pMOSFET
SWITCH CURRENT LIMIT
MINIMUM ON TIME
MAXIMUM DUTY CYCLE
SOFT START TIME
RDSON2
RDSON2
ICL2
ID = 200 mA
ID = 200 mA
240
300
330
450
850
mΩ
mΩ
mA
ns
360 630
55
tMIN2
DMAX2
tSS2
87.5
90
%
900
μs
COUT DISCHARGE SWITCH ON RESISTANCE
RDIS2
0.7
1
1.3
kΩ
1 See Table 14 (the BUCK2_LDO_VSEL register, Address 0x02) for details.
VOUT3 SPECIFICATIONS, LOW DROPOUT (LDO) REGULATOR
Table 5.
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
OUTPUT VOLTAGE
Adjustable Range1
Initial Accuracy
VOUT3
100 mV step, 4-bit range
1.8
−1.5
−5
3.3
+1.5
+4
0.75
0.30
V
%
%
%
%
TA = 25°C, VDD3 = 3.6 V, VOUT3 = 1.8 V, ILOAD = 10 mA
VDD3 = 2.5 V to 5 V, ILOAD = 0 mA to 150 mA
ILOAD = 10 mA to 100 mA
Total Accuracy
Load Regulation
Line Regulation
0.45
0.15
ILOAD = 100 mA2
CURRENT
Maximum Output Current
Dropout Voltage
Quiescent Current
Short-Circuit Current Limit
Power Supply Rejection Ratio
ILDOMAX
VLDODROP
IQ
150
100
85
mA
mV
μA
At 100 mA, VOUT3 = 3.3 V
ILOAD = 0 mA
70
45
400
200
0.7
600
mA
PSRR
f = 1 kHz, VDD3 = 5 V, VOUT3 = 3.3 V, ILOAD = 50 mA
f = 10 kHz, VDD3 = 5 V, VOUT3 = 3.3 V, ILOAD = 50 mA
47
44
70
1
dB
dB
μs
SOFT START TIME
tSS2
COUT DISCHARGE SWITCH ON RESISTANCE
RDIS8
1.3
kΩ
1 See Table 14 (the BUCK_LDO_VSEL register, Address 0x02) for details.
2 VDD3 > VOUT3 + LDODROP
.
Rev. 0 | Page 6 of 28
ADP5020
I2C TIMING SPECIFICATIONS
Table 6.
Parameter
Min
Max
Unit
kHz
μs
Description
fSCL
tHIGH
400
SCL clock frequency
SCL high time
0.6
tLOW
1.3
μs
SCL low time
tSU,DAT
tHD,DAT
100
0
ns
μs
Data setup time
Data hold time
1
0.9
tSU,STA
tHD,STA
tBUF
tSU,STO
tRISE
tFALL
0.6
0.6
1.3
0.6
20 + 0.1CB
20 + 0.1CB
0
μs
μs
μs
μs
ns
ns
ns
pF
Setup time for repeated start
Hold time for start/repeated start
Bus free time between a stop condition and a start condition
Setup time for stop condition
Rise time of SCL/SDA
Fall time of SCL/SDA
Pulse width of suppressed spike
Capacitive load for each bus line
300
300
50
tSP
CB
2
400
1 A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the VIHMIN of the SCL signal) to bridge the undefined region of the SCL falling edge.
2 CB is the total capacitance of one bus line in picofarads (pF).
Timing Diagram
SDA
tBUF
tFALL
tFALL
tLOW
tRISE
tSP tRISE
tSU,DAT
tHD,STA
SCL
tHD,DAT
tSU,STA
tSU,STO
tHIGH
S
Sr
P
S
S = START CONDITION
Sr = START REPEATED CONDITION
P = STOP CONDITION
Figure 3. I2C Interface Timing Diagram
Rev. 0 | Page 7 of 28
ADP5020
ABSOLUTE MAXIMUM RATINGS
Table 7.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Parameter
Rating
VDD1, VDD2, VDD3
SW1, SW2
VOUT1, VOUT2, VOUT3
VDD_IO
EN, SCL, SDA, SYNC, XSHTDN
Operating Temperature Range
Ambient
−0.3 V to +6 V
−0.3 V to +6 V
−0.3 V to +6 V
−0.3V to +3.6 V
−0.3 V to VDD_IO + 0.3 V
Table 8. Thermal Resistance
Package Type
θJA
θJC
Unit
20-Lead LFCSP (CP-20-4)
47.4
4.3
°C/W
Thermal Data
−40°C to +85°C
−40°C to +125°C
−65°C to +150°C
260°C
260°C
215°C
Junction-to-ambient thermal resistance (θJA) of the package is
based on modeling and calculation using a 4-layer board. The
junction-to-ambient thermal resistance is highly dependent on
the application and board layout. In applications where high maxi-
mum power dissipation exists, attention to thermal board design
is required. The value of θJA may vary, depending on PCB material,
layout, and environmental conditions. The specified value of θJA
is based on a 4-layer, 4 in × 3 in, 2 1/2 oz copper board, as per
JEDEC standards. For more information, see the AN-772
Application Note, A Design and Manufacturing Guide for the
Lead Frame Chip Scale Package (LFCSP).
Junction
Storage Temperature Range
Lead Temperature
Soldering (10 sec)
Vapor Phase (60 sec)
Infrared (15 sec)
220°C
VESD
Machine Model Range
Human Body Model Range
Charged Device Model
−200 V to +200 V
−2000 V to +2000 V
750 V
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
The ADP5020 can be damaged when the junction temperature
(TJ) limits are exceeded. Monitoring the ambient temperature
does not guarantee that TJ is within the specified temperature
limits. In applications with high power dissipation and poor
thermal resistance, the maximum ambient temperature may
have to be derated. In applications having moderate power dis-
sipation and low PCB thermal resistance, the maximum ambient
temperature can exceed the maximum limit as long as the junction
temperature is within specification limits. The TJ of the device is
dependent on the ambient temperature (TA), the power dissipation
(PD) of the device, and the junction-to-ambient thermal resistance
of the package (θJA). Maximum TJ is calculated from TA and PD
using the following formula:
TJ = TA + (PD × θJA)
Rev. 0 | Page 8 of 28
ADP5020
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
VOUT1 15
VOUT1 14
VDD3 13
1
2
3
4
5
PGND2
VOUT2
VDDA
AGND
SYNC
PIN 1
INDICATOR
ADP5020
BOTTOM VIEW
(Not to Scale)
PGND2
VOUT2
VDDA
AGND
SYNC
1
2
3
4
5
15 VOUT1
14
13
VOUT1
VDD3
VOUT3 12
EN/GPIO 11
ADP5020
TOP VIEW
(Not to Scale)
EXPOSED PAD
12 VOUT3
11 EN/GPIO
NOTES
1. EXPOSED PAD SHOULD BE CONNECTED
TO PGND1 AND PGND2.
Figure 4. Pin Configuration (Bottom View)
Figure 5. Pin Configuration (Top View)
Table 9. Pin Function Descriptions
Pin No. Mnemonic Description
1
2
3
4
5
PGND2
VOUT2
VDDA
AGND
SYNC
Power Ground Buck 2.
Feedback Buck 2.
Supply Voltage Internal Analog Circuit.
Analog Ground.
Frequency Synchronization. Connect to an external 19.2 MHz or 9.6 MHz clock signal to synchronize the
internal oscillator.
6
DGND
SDA
Digital Ground.
I2C Data.
7
8
SCL
I2C Clock.
9
VDD_IO
XSHTDN
EN/GPIO
Supply Voltage for Internal Logic Inputs/Outputs.
10
11
Shutdown Output, Active Low.
After power-on reset, this pin is defined as enable (EN). To enable active high, the I2C command can program
this pin to be an output (GPIO). A weak pull-down resistor is enabled when the pin operates as EN.
12
VOUT3
VDD3
Regulated Output Voltage from LDO.
Supply Voltage LDO.
13
14, 15
16
VOUT1
PGND1
SW1
Feedback/Driver Buck 1 Output.
Power Ground Buck 1.
17
Switch Pin Buck 1.
18
VDD1
Supply Voltage Buck 1.
19
VDD2
Supply Voltage Buck 2.
20
SW2
Switch Pin Buck 2.
EPAD
Exposed paddle
Exposed pad should be connected to PGND1 and PGND2.
Rev. 0 | Page 9 of 28
ADP5020
TYPICAL PERFORMANCE CHARACTERISTICS
VIN = 4.5 V, VOUT1 = 2.8 V, VOUT2 = VOUT3 = 1.8 V, IOUT = 100 mA, C4 = C1 = 10 μF, C2 = 4.7 μF, C3 = 1 μF, TJ = 25°C, unless otherwise noted.
3.5
95
3.3V
3.0V
2.8V
90
85
3.0
2.5
2.0
1.5
2.5V
2.0V
1.8V
V
V
V
V
V
V
V
(2.5V)
(2.8V)
(2.9V)
(3.0V)
(3.2V)
(3.3V)
(3.7V)
80
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
75
70
1.0
0
30
60
90
120
150
0
100
200
300
400
500
600
LOAD CURRENT (mA)
LOAD CURRENT (mA)
Figure 6. LDO Load Regulation
Figure 9. Buck 1, Efficiency vs. Load Current
LDO OUTPUT = 20mV/DIV
= 100mA/DIV
BUCK 1 OUTPUT = 100mV/DIV
I = 100mA/DIV
LOAD
I
LOAD
TIME = 100µs/DIV
TIME = 100µs/DIV
LDO
I
LOAD
Figure 7. LDO Load Transient
Figure 10. Buck 1 Load Transient Response
3.8
3.6
3.4
3.2
3.0
2.8
2.6
2.4
2.2
0
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
0
V
(1.8V)
OUT8
V
V
(3.7V)
(3.3V)
OUT7
OUT6
V
V
V
V
V
V
V
(1.7V)
(1.6V)
(1.5V)
(1.4V)
(1.3V)
(1.2V)
(1.1V)
OUT7
OUT6
OUT5
OUT4
OUT3
OUT2
OUT1
V
(3.2V)
(2.9V)
OUT5
V
OUT3
V
(3.0V)
OUT4
V
(2.8V)
(2.5V)
OUT2
V
OUT1
0
100
200
300
400
500
600
0
50
100
150
200
250
300
LOAD CURRENT (mA)
LOAD CURRENT (mA)
Figure 8. Buck 1 Load Regulation
Figure 11. Buck 2 Load Regulation
Rev. 0 | Page 10 of 28
ADP5020
VIN = 4.5 V, VOUT1 = 2.8 V, VOUT2 = VOUT3 = 1.8 V, IOUT = 100 mA, C4 = C1 = 10 μF, C2 = 4.7 μF, C3 = 1 μF, TJ = 25°C, unless otherwise noted.
0.90
BUCK 1 OUTPUT = 2V/DIV
BUCK 2 OUTPUT = 1V/DIV
0.85
0.80
0.75
0.70
0.65
0.60
0.55
0.50
TIME = 5ms/DIV
EFF1 (1.1V)
EFF2 (1.2V)
EFF3 (1.3V)
EFF4 (1.4V)
EFF5 (1.5V)
EFF6 (1.6V)
EFF7 (1.7V)
EFF8 (1.8V)
0
50
100
150
200
250
300
LOAD CURRENT (mA)
Figure 12. Buck 2 Efficiency vs. Load Current
Figure 15. Startup Sequence of the Three Regulators, Set by Default
BUCK 2 OUTPUT = 50mV/DIV
BUCK 2 OUTPUT = 1V/DIV
SW2 OUTPUT = 2V/DIV
TIME = 500µs/DIV
I
= 100mA/DIV
LOAD
TIME = 100µs/DIV
BUCK 2
BUCK 2
I
LOAD
SW2
Figure 13. Buck 2 Load Transient Response
Figure 16. Buck 2 Enable Startup
1.2
1.0
0.8
0.6
BUCK 1 OUTPUT = 1V/DIV
SW1 OUTPUT = 2V/DIV
TIME = 500µs/DIV
I
I
I
(µA) @ –40°C
(µA) @ +25°C
(µA) @ +125°C
SHTDN
SHTDN
SHTDN
0.4
0.2
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
INPUT VOLTAGE (V)
Figure 14. Shutdown Current vs. Input Voltage
Figure 17. Buck 1 Enable Startup
Rev. 0 | Page 11 of 28
ADP5020
VIN = 4.5 V, VOUT1 = 2.8 V, VOUT2 = VOUT3 = 1.8 V, IOUT = 100 mA, C4 = C1 = 10 μF, C2 =4.7 μF, C3 = 1 μF, TJ = 25°C, unless otherwise noted.
LDO OUTPUT = 1V/DIV
TIME = 50µs/DIV
SW2
LDO
BUCK 2 OUTPUT = 20mV/DIV
SW2 = 5V/DIV
TIME = 100ns/DIV
BUCK 2
Figure 18. LDO Startup
Figure 20. Buck 2 Switching Node Voltage and
Output Ripple Voltage
BUCK 1 OUTPUT = 2V/DIV
BUCK 2 OUTPUT = 1V/DIV
LDO OUTPUT = 1V/DIV
SW1
ENABLE OUTPUT = 2V/DIV
TIME = 5ms/DIV
BUCK 1
LDO
BUCK 1 OUTPUT = 20mV/DIV
SW1 = 5V/DIV
TIME = 100ns/DIV
BUCK 2
BUCK 1
ENABLE
Figure 19. Buck 1 Switching Node Voltage and
Output Ripple Voltage
Figure 21. Three Regulators Turned Off by Sequencer
Rev. 0 | Page 12 of 28
ADP5020
THEORY OF OPERATION
The I2C timing specifications are shown in Table 6, and the I2C
interface timing diagram is shown in Figure 3. The 7-bit slave
address of the ADP5020 is shown in Table 10.
CIRCUIT OPERATION
The buck converters use pMOSFET as the upper switch and
nMOSFET as a synchronous rectifier. This synchronous recti-
fication maintains high efficiency for a wide input and output
voltage range. The voltage mode control architecture, which
features a high frequency bandwidth, provides a fast load and
line transient response. The Buck 1 regulator can deliver up to
600 mA with very tight regulation. To minimize cross conduction
and maximize efficiency, an antishoot-through circuit is imple-
mented in the gate driver. The two switching regulators operate
out of phase, reducing input ripple voltage and current.
UNDERVOLTAGE LOCKOUT
The undervoltage lockout block contains the UVLO detector
circuits for the battery voltage level. It also contains the status
registers that are required to allow the external application
processor to determine the status of the power supplies. The
most important function of the UVLO circuit is to prevent
converter operation if the supply voltage is too low. The UVLO
falling condition (when the battery voltage decreases from the
operating range level) is set to a typical value of 2.0 V, whereas the
UVLO rising condition (when the supply voltage increases from
zero) is typically 2.2 V.
INTERNAL COMPENSATION
The ADP5020 contains an internal compensation network. The
compensation circuit is designed to make the synchronous buck
converter stable over the input line, output load, and temperature
with specified output capacitors and inductors. In addition, the
high bandwidth control loop design allows for fast load and line
transient response.
THERMAL SHUTDOWN
The thermal shutdown block (TSD) prevents device damage
if the die temperature reaches a level greater than 150°C. When
the thermal shutdown limit is reached, the regulator disables
the outputs, while waiting for the die to cool down (typically, to
30°C below the thermal shutdown threshold). There are two
distinct conditions to be considered when recovering from
a thermal shutdown condition:
CURRENT LIMITING AND SHORT-CIRCUIT
PROTECTION
Both buck converters and the LDO have a current limit feature
that allows the ADP5020 to protect itself and any external compo-
nents during overload and short-circuit conditions. The upper
switch pMOSFET turns off if peak current exceeds the limit.
The nMOSFET is turned on for a longer period until inductor
current drops to 0 A to prevent thermal runaway.
•
The EN pin is low. If the EN pin is low and the device is
operating in I2C command mode, the outputs remain
disabled until the application processor initializes the
parameters and performs the sequencing of the regulators.
The application processor can sense a generic failure con-
dition by detecting a missing acknowledge bit following an
I2C command. When a thermal shutdown condition occurs,
Bit 0 (TSD) in the OPERATIONAL_CONTROL register
(Address 0x04) is latched to 1 so that the processor can
recognize the origin of the failure when resuming from
a fault condition. When the TSD bit is set, the application
processor must clear this bit to activate the regulators. If
the TSD bit is not cleared, writing to the regulator enable
bits, Bits[7:4] (BK1_EN, BK2_EN, LDO_EN, and EN_ALL),
in the REG_CONTROL_STATUS register (Address 0x03)
has no effect. The application processor can also force Bit 0
(TSD) to 1. In this case, the operation proceeds as though
a thermal shutdown condition has occurred.
SYNCHRONIZATION
The device has several methods of synchronizing an external
clock with the switching regulators. If the external clock is
9.6 MHz, Bit 6 (SYNC_9P6) in the OPERATIONAL_CONTROL
register (Address 0x04) must be set to 1, and Bit 5 (SYNC_19P2)
must be set to 0. This operation divides the external clock by 3
before it is applied to the switching regulator clock. If the external
clock is 19.2 MHz, Bit 5 (SYNC_19P2) in Address 0x04 must be
set to 1, and Bit 6 (SYNC_9P6) must be set to 0. This opera-tion
divides the external clock by 6 before it is applied to the
switching regulator clock. The synchronous clock can be dc- or
ac-coupled onto the SYNC pin. For ac coupling, Bit 4 (SYNC_AC)
in Address 0x04 is set to 1; for dc coupling, Bit 4 is set to 0.
Operational control is performed by I2C writing to Register 0x04.
•
The EN pin is high. If the EN pin is high, the device resumes
operation automatically from a thermal shutdown condition.
The device resumes performing the predefined regulator
sequence without processor intervention. Bit 0 (TSD) in the
OPERATIONAL_CONTROL register (Address 0x04) is set
to indicate that a thermal shutdown has occurred, and it is
not possible to activate the regulators using an I2C com-
mand unless the host sets the TSD bit to 0.
I2C INTERFACE
An internal register can be accessed using a synchronous
serial interface that implements the standard I2C interface. The
ADP5020 behaves as a slave device, communicating at normal
speed (100 kHz) or fast speed (400 kHz).
Rev. 0 | Page 13 of 28
ADP5020
CONTROL REGISTERS
DEVICE ADDRESS
Following a start condition, the bus master must send the address
of the slave it is accessing. The slave address for the ADP5020 is
shown in Table 10. The Bit 0 defines the operation to be per-
formed. When this bit is set to Logic 1, a read operation is
selected. When this bit is set to Logic 0, a write operation is
selected.
Table 10. Slave Address
Bit 7
ADR6
0
Bit 6
ADR5
0
Bit 5
ADR4
1
Bit 4
ADR3
0
Bit 3
ADR2
1
Bit 2
ADR1
0
Bit 1
ADR0
0
Bit 0
R/W
1 or 0
REGISTER MAP
Table 11.
Address
0x00
0x01
Register Name
Revision
BUCK1_VSEL
BUCK2_LDO_VSEL
D7
D6
MAJ[2:0]
D5
D4
D3
MIN[2:0]
D2
D1
D0
OPT[1:0]
BK1_VSEL[2:0]
LDO_VSEL[3:0]
Reserved[7:3]
BK2_VSEL[3:0]
0x02
0x03
REG_CONTROL_STATUS
BK1_EN
BK2_EN
LDO_EN
EN_ALL BK1_
PGOOD
BK1_
BK2_
PGOOD
LDO_
PGOOD
FORCE_XS
0x04
0x05
TSD
OPERATIONAL_CONTROL Reserved SYNC_9P6 SYNC_19P2 SYNC_
AC
BK2_
LDO_
XSHTDN XSHTDN XSHTDN
EN_CONTROL
Reserved[7:2]
ENO_HIZ_
BAR
ENO_DRV
0x06 to
0x0F
Reserved
REGISTER DESCRIPTIONS
User Accessible Registers
Table 12. Revision Register, Address 0x00
Bit
Bit Name
Access
Default
Description
[7:5] MAJ[2:0]
[4:2] MIN[2:0]
[1:0] OPT[1:0]
R
R
R
N/A
N/A
N/A
Major revision bits. Used to electronically ID the device version.
Minor revision bits. Used to electronically ID the device version.
Option bits. Used to electronically ID the option (multiple options on same device family).
Table 13. BUCK1_VSEL Register, Address 0x01
Bit
Bit Name
Access
Default
Description
[7:3] Reserved
N/A
N/A
Reserved.
[2:0] BK1_VSEL[2:0]
R/W
Fuse
Sets the voltage output level of the Buck 1 regulator. Preloads on power-up with values
stored in fuses. Note that this value can be edited by the user in an application.
000 = 2.5 V.
001 = 2.8 V.
010 = 2.9 V.
011 = 3.0 V.
100 = 3.2 V.
101 = 3.3 V (default).
110 = 3.7 V.
111 = reserved.
Rev. 0 | Page 14 of 28
ADP5020
Table 14. BUCK2_LDO_VSEL Register, Address 0x02
Bit
Bit Name
Access
Default
Description
[7:4] BK2_VSEL[3:0]
R/W
Fuse
Sets the voltage output level of the Buck 2 regulator. Preloads on power-up with values
stored in fuses. Note that this value can be edited by a user in an application.
0000 = 1.1 V.
0001 = 1.1 V.
0010 = 1.1 V.
0011 = 1.1 V.
0100 = 1.1 V.
0101 = 1.1 V.
0110 = 1.1 V.
0111 = 1.1 V.
1000 = 1.1 V.
1001 = 1.2 V (default).
1010 = 1.3 V.
1011 = 1.4 V.
1100 = 1.5 V.
1101 = 1.6 V.
1110 = 1.7 V.
1111 = 1.8 V.
[3:0] LDO_VSEL[3:0]
R/W
Fuse
Sets the voltage output level of the LDO regulator. Preloads on power-up with values
stored in fuses. Note that this value can be edited by the user in an application.
0000 = 1.8 V (default).
0001 = 1.9 V.
0010 = 2.0 V.
0011 = 2.1 V.
0100 = 2.2 V.
0101 = 2.3 V.
0110 = 2.4 V.
0111 = 2.5 V.
1000 = 2.6 V.
1001 = 2.7 V.
1010 = 2.8 V.
1011 = 2.9 V.
1100 = 3.0 V.
1101 = 3.1 V.
1110 = 3.2 V.
1111 = 3.3 V.
Rev. 0 | Page 15 of 28
ADP5020
Table 15. REG_CONTROL_STATUS Register, Address 0x03
Bit Bit Name
Access
Default
Description
7
6
5
4
BK1_EN
BK2_EN
LDO_EN
EN_ALL
R/W
0
0
0
0
1 = turns on the Buck 1 regulator. If the EN pin is high, the sequencer is ignored.
1 = turns on the Buck 2 regulator. If the EN pin is high, the sequencer is ignored.
1 = turns on the LDO regulator. If the EN pin is high, the sequencer is ignored.
R/W
R/W
R/W
1 = turns on all regulators, following sequencer programming. BK1_EN, BK2_EN, and
LDO_EN must all be set to 0 for this bit to function.
3
2
1
0
BK1_PGOOD
BK2_PGOOD
LDO_PGOOD
FORCE_XS
R
0
0
0
0
Power good status for Buck 1.
1 = power good (POK).
0 = fail.
R
Power good status for Buck 2.
1 = power good (POK).
0 = fail.
R
Power good status for LDO.
1 = power good (POK).
0 = fail.
R/W
1 = the XSHTDN pin is controlled by the power good signals.
0 = the XSHTDN pin is held low unless the EN pin is high, regardless of regulator status.
If EN is high, this bit is ignored in controlling the XSHTDN pin (acts as if FORCE_XS = 1).
Table 16. OPERATIONAL_CONTROL Register, Address 0x04
Bit Bit Name
Access
Default
Description
7
6
Reserved
SYNC_9P61
N/A
N/A
Reserved.
R/W
0
1 = a 9.6 MHz clock is on the SYNC pin. The SYNC frequency is divided by 3 and used as
clock frequency for switching regulators.
5
SYNC_19P21
R/W
0
1 = a 19.2 MHz clock is on the SYNC pin. The SYNC frequency is divided by 6 and used as
clock frequency for switching regulators.
1 for both SYNC_9P6 and SYNC_19P2 = invalid setting.
0 for both SYNC_9P6 and SYNC_19P2 = clock synchronization is disabled, and the device
operates with the 3 MHz internal clock.
4
3
2
1
0
SYNC_AC1
BK1_XSHTDN
BK2_XSHTDN
LDO_XSHTDN
TSD
R/W
R/W
R/W
R/W
R/W
0
1 = the ac path is used for the SYNC input.
0 = the dc path is used (default).
Fuse
Fuse
Fuse
0
0 = power good for Buck 1 must be high for XSHTDN to go high (default).
1 = Buck 1 power good is ignored.
0 = power good for Buck 2 must be high for XSHTDN to go high (default).
1 = Buck 2 power good is ignored.
0 = LDO power good must be high for XSHTDN to go high (default).
1 = LDO power good is ignored.
Shows a latched status of a thermal shutdown (TSD) event.
1 = TSD is active.
Must be cleared to 0 by user program to enable the regulators. If this bit remains set to 1,
regulator activation is inhibited, as in a thermal shutdown event.
1 The SYNC selection bits (SYNC_AC, SYNC_9P6, and SYNC_19P2) cannot be changed while a switching regulator is running.
Table 17. EN_CONTROL Register, Address 0x05
Bit
Bit Name
Access
Default Description
[7:2] Reserved
N/A
N/A
0
Reserved.
1
0
ENO_HIZ_BAR
ENO_DRV
R/W
0 = the EN/GPIO pin is in high impedance, and the EN function is selected.
1 = GPIO output is selected, and the EN function is ignored.
Active only when ENO_HIZ_BAR = 1 (GPIO).
0 = GPIO output is set to low.
R/W
0
1 = GPIO output is set to high.
Rev. 0 | Page 16 of 28
ADP5020
POWER-UP/POWER-DOWN SEQUENCE
SEQUENCER
DEFAULT POWER-ON SEQUENCE WITH EN PIN
The sequencer is enabled after a low-to-high transition of the
enable pin (EN). When EN is low or programmed as an output, the
sequencing is controlled and timed by the application processor
via the I2C commands.
Figure 22 shows the default regulator sequencing after a low-to-
high transition of the EN pin. The regulator order is factory
programmed and can be changed for specific applications. The
power good signal (POK) turns to high if the regulator voltage
is ≥80% of the target voltage. The second regulator checks the
POK signal of the first regulator and waits the preset delay time
(tREG2) before turning on. In addition to changing the regulator
order, it is also possible to disable the unused regulator. Additional
fuses allow disabling of the association between XSHTDN genera-
tion and the POK signal for a specific regulator. The power good
signal of an unused regulator must be masked, via dedicated fuse
and user registers, to prevent the XSHTDN output from being
forced low. A host processor controller, connected to the I2C bus,
can override the masking fuses by accessing the following bits in
the OPERATIONAL_CONTROL register (Address 0x04): Bit 3
(BK1_XSHTDN, for Buck 1), Bit 2 (BK2_XSHTDN, for Buck 2),
and Bit 3 (LDO_XSHTDN, for LDO). Writing 0 to these register
bits requires that power good be true to release the XSHTDN pin
to high. Writing 1 to these bits causes the regu-lator state to be
ignored, and XSHTDN must depend on the active and
unmasked regulators.
Each regulator inside the ADP5020 is controlled by the
sequencer block. The sequencer is factory programmed with
a default turn-on sequence that determines the activation order of
the regulators. The default activation order is listed as follows:
1. Buck 1
2. LDO
3. Buck 2
A low-to-high transition of the EN pin, when programmed
as an input, or an I2C command setting Bit 4 (EN_ALL) in the
REG_CONTROL_STATUS register (Address 0x03), starts the
sequencer.
The activation delay for the first regulator is determined by the
turn-on delay of the band gap, oscillator, and other internal
circuits. Therefore, the first regulator cannot be activated before
a typical 5 ms delay time has elapsed. Delays between the first
and second regulator and from the second to third regulator are
hard coded to a specific time (tREG1, tREG2, and tREG3). The delay
time starts from the moment a regulator has reached the power
good threshold (see Figure 22).
The regulators can also be activated individually via the I2C
commands. The host specifies which regulator is to be turned
on or off by setting or clearing the following selection bits in the
REG_CONTROL_STATUS register (Address 0x03): Bit 7
(BK1_EN), Bit 6 (BK2_EN), or Bit 5 (LDO_EN). When the
regulators are individually activated by I2C commands, the auto
sequencing is disabled and the host controls the turn-on and
turn-off timing (see Figure 26).
EN
tREG1
POK
BUCK 1
tREG2
POK
LDO
tREG3
BUCK 2
POK
tXSHTDN
XSHTDN
Figure 22. Automatic Sequencing with EN Low-to-High Transition
Rev. 0 | Page 17 of 28
ADP5020
Activation Waveforms
VDDx
POR
V
UVLOR
INTERNAL
POR
EN
2
EN_
ALL = 1
I C SEQUENCER
REGISTERS
EN_
ALL = 0
2
I C BUS
PROGRAMMING
tREG1
POK
BUCK 1
LDO
tREG2
POK
tREG3
POK
BUCK 2
tXSHTDN
XSHTDN
Figure 23. Regulators Are Activated by I2C Command
VDDx
POR
INTERNAL
POR
EN
2
I C SEQUENCER
REGISTERS
2
I C BUS
PROGRAMMING
tREG1
POK
BUCK 1
LDO
tREG2
POK
tREG3
POK
BUCK 2
tXSHTDN
XSHTDN
Figure 24. Activation Command Using the EN Pin
When activated through the EN pin, the sequencer is affected
only by the I2C commands that set or clear the regulator power
good masking bits: Bit 3 (BK1_XSHTDN), Bit 2 (BK2_XSHTDN),
and Bit 1 (LDO_XSHTDN) in the OPERATIONAL_CONTROL
register (Address 0x04). See the Default Power-On Sequence with
EN Pin section for more information. The sequence order of the
regulators is factory programmed through fuses, but the delays
between the regulators (tREG1, tREG2, and tREG3) are fixed and cannot
be changed.
The EN_ALL bit (Bit 4) in the REG_CONTROL_STATUS regi-ster
(Address 0x03) has the same functionality as the EN pin. The
sequencer has an antiglitch function that allows it to ignore supply
voltage dip if glitch time is less than 50 μs (see Figure 25).
Rev. 0 | Page 18 of 28
ADP5020
POWER-ON SEQUENCE USING THE I2C INTERFACE
1. Buck 1
2. LDO
3. Buck 2
When the EN pin is low, the regulator sequence is controlled by
the application processor sending I2C commands to control the
activation. When Bit 4 (EN_ALL) in the REG_CONTROL_
STATUS register (Address 0x03) is set to 1, the regulator sequence
is as follows:
This sequence can be factory programmed through fuses.
Unused regulators can also be fuse programmed to be turned
off during sequencing.
VDDx
V
POR
UVLOR
V
UVLOF
<50µs
INTERNAL
POR
EN
2
I C SET/CLEAR
xxx_XSHTDN BITS
2
I C BUS
tREG1
tREG2
BUCK 1
LDO
tREG3
tXSHTDN
BUCK 2
XSHTDN
Figure 25. Activation and Power Failure Conditions
EN
BK1_EN,
LDO_EN,
BK2_EN = 0
BK1_EN
= 1
LD0_EN
= 1
BK2_EN
= 1
FORCE_XS
= 1
FORCE_XS
= 0
2
I C BUS
BUCK 1
LDO
BUCK 2
XSHTDN
Figure 26. Individual Activation Through I2C Commands
Rev. 0 | Page 19 of 28
ADP5020
The application processor, together with the regulator power
good signal, controls the XSHTDN pin, as shown in Table 18.
After a regulator is enabled and no failure condition is detected
(power good = 1 in Bits[3:1] of the REG_CONTROL_STATUS
register, Address 0x03), the level of the XSHTDN pin is con-
trolled by Bit 0 (FORCE_XS) in the REG_CONTROL_STATUS
register. Therefore, the application processor can write to this
register to gain control over the XSHTDN pin. However, if the
EN signal is high, the level on the XSHTDN pin depends on the
power good condition of the regulator.
POWER-UP/POWER-DOWN STATE FLOW
When the device is enabled, the UVLO circuit constantly monitors
the supply voltage. If the supply voltage falls below the VUVLOF
threshold, typically 2.0 V, the regulators are immediately turned
off. All the internal analog circuits are then disabled to save power,
except the power-on reset (POR) circuit, which detects if the supply
voltage is dropping. If the supply voltage is higher than the POR
threshold, the POR circuit keeps the logic circuits operating
properly and retains the internal values of the registers. This
POR threshold is set to approximately 1.4 V.
Table 18. Truth Table
If the supply voltage goes below the VUVLOR threshold, but not
below the POR threshold, the registers are preserved. If the supply
voltage returns to the normal operating level (above VUVLOR),
a new activation does not require initialization of the registers.
However, if the supply voltage goes below the POR level, the
device is held in reset state. When the input voltage resumes the
proper operating level, the host controller must reload the registers.
EN
Pin
Power
Good
XSHTDN
FORCE_XS Pin
I2C Regulator Enable
0
0
0
0
1
1
0
1
1
1
X1
X1
0
X1
0
1
1
0
X1
0
0
0
1
1
0
0
1
1
X1
X1
The additional current required to keep the POR monitoring
circuits alive during UVLO is estimated to be approximately 1 μA.
1 X = don’t care.
NO POWER
VDDx > V
POR
LEVEL
INTERNAL
RESET
VDDx < V
POR
VDDx < V
POR
EN = LOW
STAND BY
2
EN = LOW AND 1 C OFF
COMMAND
OR VDDx < V
UVLOF
EN = HIGH
2
I C
2
COMMANDS
EN = LOW OR I C OFF
NORMAL
OPERATION
DEVICE ENABLED
(EN_ALL OR EN = HIGH)
COMMAND
OR VDDx < V
UVLOF
TSD
STARTUP
SEQUENCER
SEQUENCE
END, AND ALL REGULATIONS ARE
POWER GOOD
Figure 27. State Flow
Rev. 0 | Page 20 of 28
ADP5020
APPLICATIONS INFORMATION
POWER GOOD STATUS
Peak inductor current is calculated in the following equation:
I
LMAX = IOUT + 0.5 × r × IOUT
(2)
The ADP5020 constantly monitors the operating conditions.
When a regulator is activated, it checks if the output voltage
level is above 80% (the power good threshold) of the nominal
level for that output. If the output voltage does not reach the
power good threshold, one of the three power good status bits in
the REG_CONTROL_STATUS register (Address 0x03) is cleared.
If the output voltage reaches the power good threshold, one of
the power good status bits in the REG_CONTROL_STATUS
register is set to 1. The REG_CONTROL_STATUS register
contains the following three power good bits: BK1_PGOOD for
the Buck 1 output (Bit 3), BK2_PGOOD for the Buck 2 output
(Bit 2), and LDO_PGOOD for the LDO output (Bit 1).
The calculated minimum Buck 2 inductor value is 2.2 μH. The
maximum peak inductor current is 325 mA. A ceramic inductor
such as the Taiyo Yuden BRL2012T2R2M, with a 600 mA satu-
ration current in a 2 mm × 1.2 mm × 1 mm package, can be used.
For the Buck 1 converter, the calculated minimum inductance is
2.2 μH, with maximum peak current of 690 mA. A ceramic
inductor such as the Taiyo Yuden BRL2518T2R2M, with a 1 A
saturation current in a 2.5 mm × 1.8 mm × 1.2 mm package, is
recommended.
Input Capacitor Selection
The input capacitors are used to decouple the parasitic inductance
of input wires to the converters and to reduce the input ripple
voltage and the switching ac current flow to the battery rail. The
capacitors are selected to support the maximum input operating
voltage and the maximum rms current. The capacitance must also
be large enough to ensure input stability and suppress input ripple.
ESR should as small as possible to decouple the noise. MLCC
ceramic capacitors are a good choice for battery-powered appli-
cations because of their high capacitance, small size, and low ESR.
A 10 μF ceramic capacitor (for example, the JMK107BJ106MA-T
from Taiyo Yuden) is recommended.
XSHTDN LOGIC
In addition to the power good information for each enabled
regulator, an XSHTDN signal is generated, as shown in Table 18. If
one or more regulators are unused in a specific application, the
masking bits for the disabled regulator, which are fuse pro-
grammable and I2C programmable after device startup, must be
set to 1 to mask the status of the power good signal. Besides having
the masking bits predefined through factory-programmed fuses
(necessary only for operation with the EN signal), the ADP5020
provides three masking bits that are accessible through the I2C
interface. These bits are located in the OPERATIONAL_
Output Capacitor Selection
CONTROL register (Address 0x04), where the BK1_XSHTDN
bit (Bit 3) is the mask (if set to 1) for Buck 1, the BK2_XSHTDN bit
(Bit 2) is the mask (if set to 1) for Buck 2, and the LDO_
XSHTDN bit (Bit 3) is the mask (if set to 1) for the LDO. Addi-
tional failures that are verified are the input (VDDA) undervoltage
condition, as described in the Undervoltage Lockout section; and
an overtemperature condition of the die, as described in the
Thermal Shutdown section. As soon as one of these conditions
occurs, the active regulators are immediately turned off, and the
XSHTDN pin is set to 0.
Output capacitor selection should be based on the following three
factors:
•
Maximizing the control loop bandwidth of the converter
with the LC filter
•
•
Minimizing the output voltage ripple
Minimizing the size of the capacitor
Note that the output ripple is the combination of several factors,
including the inductor ripple current (ΔIL), the ESR and ESL
output capacitors, and the capacitor impedance at the switching
frequency.
COMPONENTS SELECTION
Buck Inductor
In buck converters, the output ripple can be calculated as
follows:
The buck inductor is chosen to meet output ripple current and
ripple voltage requirements with minimum size. The fast load
transient response and wide frequency bandwidth are also impor-
tant factors for inductor selection. The minimum inductance of the
buck converter is derived from the following equation:
⎛
⎜
⎜
⎝
⎞
⎟
⎟
⎠
1
ΔVOUTRIPPLE = ΔIL
ESR +
+ 4 × ESL × fSW
8 × fSW ×COUT
ΔIL = r × IOUT
(VINMAX −VOUT )×VOUT
Capacitor manufacturer data sheets show the ESR and ESL
value. In real-life applications, the ripple voltage may be higher
because the equations provided in this data sheet do not consider
parameters such as board/package parasitic inductance and
capacitance. The minimum recommended capacitance is no less
than 4.0 μF for Buck 1, 2.0 μF for Buck 2, and 0.4 μF for the
LDO.
LMINBUCK
=
(1)
VINMAX × fSW ×r × IOUT
where:
V
V
INMAX is the maximum input supply voltage.
OUT is the regulator output voltage in the buck converter.
f
SW is the converter switching frequency.
r is the inductor ripple factor, which is selected as 30%.
Rev. 0 | Page 21 of 28
ADP5020
ADP5020
LDO INPUT FILTER
SW1
To improve the LDO input-to-output ripple suppression in the
critical switching frequency range of the buck converters, it may be
necessary to add an LC filter tuned to 1 MHz, as shown in
Figure 28. Additional tests and simulation must be performed
to assess if this filter is necessary.
VBATT
C1
10µF
L1
2.2µH
BUCK 1
VOUT1
VOUT1
3.3V
C6
10µF
LDO
INPUT FILTER
The filter resonance frequency is determined by the following
equation:
L3
VDD3
1
f
=
(3)
C8
0.1µF
LC
LDO
2×π× L3 × C8
VOUT3
2.8V
where L3 = 250 nH, assuming that fLC = 1 MHz and C8 = 100 nF.
The inductor must be able to withstand the LDO load current,
including the overload condition, which is limited to 400 mA.
C3
1µF
Figure 28. Optional LDO Input Filter
Rev. 0 | Page 22 of 28
ADP5020
LAYOUT RECOMMENDATIONS
APPLICATIONS SCHEMATIC
ADP5020
VDD1
VDD2
VBATT
C4
10µF
SW1
GND
L1
2.2µH
VOUT1
VOUT1
PGND1
+VIS
–VIS
C1
10µF
VDD3
VDDA
C6
1.0µF
L2
2.2µH
+V
SW2
CORE
VOUT2
C2
4.7µF
VDD_IO
VDDIO
C5
0.1µF
PGND2
VOUT3
–V
CORE
R1
10kΩ
R2
10kΩ
+VIO
–VIO
C3
1.0µF
SDA
SCL
SDA
SCL
SYNC
SYNC
EN/GPIO
GPIO/EN
XSHTDN
XSHTDN
DGND
AGND
Figure 29. Schematic for Camera Module Applications
Rev. 0 | Page 23 of 28
ADP5020
•
The power and analog ground planes are recommended to
keep the noise low. Use one layer for power ground and one
layer for analog ground. Tie the power and analog grounds
at a single point.
Use wide traces to connect the inductor and the input and
output capacitors.
Add the L3 inductor and the C8 capacitor, if needed, to
improve the LDO noise rejection at the switching fre-
quency of the Buck 1 regulator (3 MHz) because the LDO
PSRR typically degrades at higher frequencies. If switching
noise is not an issue, remove the L3 inductor.
PCB BOARD LAYOUT RECOMMENDATIONS
•
Place the input and output capacitors, C1, C2, C3, C4, and
C5, as close as possible to the respective ADP5020 pin, and
make the grounding connection to the ADP5020 ground
pins as short as possible.
•
•
•
•
Connect C3, C5, and C6 to the analog ground, and connect
C1, C2, and C4 to the power ground.
Place the L1 and L2 inductors as close as possible to the
respective output pins.
EXTERNAL COMPONENT LIST
Table 19. Recommended External Components List
Reference
Designator Description
Size
Proposed Vendor
Murata
Taiyo Yuden
Murata
Murata
Murata
Vendor Part No.
GRM188R60J106M
JMK107BJ106MA
GRM188R60J475K
GRM155R60J105K
GRM155R61A104K
GRM155R60J105K
BRL2518T2R2M
C1, C4
C1, C4
C2
C3
C5
C6
L1
L2
R1, R2
10 μF, X5R, 6.3 V, 20%
0603
0603
0603
0603
0402
0603
10 μF, X5R, 6.3 V, 20%
4.7 μF, X5R, 6.3 V, 10%
1.0 μF, X5R, 6.3 V, 10%
0.1 μF, X5R, 10 V, 10%
1.0 μF, X5R, 6.3 V, 10%
2.2 μH, DCR = 0.13 Ω, IDC = 1 A
Murata
2.5 mm × 1.8 mm × 1.2 mm
Taiyo Yuden
Taiyo Yuden
KOA Speer Electronics
2.2 μH, DCR = 0.23 Ω, IDC = 0.53 A 2.0 mm × 1.2 mm × 1.0 mm
10 kΩ, 1%, thick film resistor 0402
BRL2012T2R2M
RK73H1ETTP1002F
Rev. 0 | Page 24 of 28
ADP5020
OUTLINE DIMENSIONS
0.60 MAX
4.00
BSC SQ
0.60 MAX
PIN 1
INDICATOR
15
16
20
1
5
0.50
BSC
2.65
2.50 SQ
2.35
PIN 1
INDICATOR
3.75
BSC SQ
EXPOSED
PAD
(BOTTOM VIEW)
10
11
6
0.50
0.40
0.30
0.25 MIN
TOP VIEW
0.80 MAX
0.65 TYP
12° MAX
1.00
0.85
0.80
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 REF
SECTION OF THIS DATA SHEET.
0.30
0.23
0.18
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-1
Figure 30. 20-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
4 mm × 4 mm Body, Very Thin Quad
(CP-20-4)
Dimensions shown in millimeters
ORDERING GUIDE
Model
Temperature Range
−40°C to +85°C
Package Description
20-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
Evaluation Board
Package Option
CP-20-4
ADP5020ACPZ-R71
ADP5020CP-EVALZ1
1 Z = RoHS Compliant Part.
Rev. 0 | Page 25 of 28
ADP5020
NOTES
Rev. 0 | Page 26 of 28
ADP5020
NOTES
Rev. 0 | Page 27 of 28
ADP5020
NOTES
©2009 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07774-0-5/09(0)
Rev. 0 | Page 28 of 28
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