ADP5071CP-EVALZ [ADI]
Independent Positive and Negative Outputs;型号: | ADP5071CP-EVALZ |
厂家: | ADI |
描述: | Independent Positive and Negative Outputs |
文件: | 总28页 (文件大小:1002K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
2 A/1.2 A DC-to-DC Switching Regulator with
Independent Positive and Negative Outputs
Data Sheet
ADP5071
FEATURES
TYPICAL APPLICATION CIRCUIT
Wide input supply voltage range: 2.85 V to 15 V
Generates well regulated, independently resistor
programmable VPOS and VNEG outputs
Boost regulator to generate VPOS output
Adjustable positive output to 39 V
ADP5071
SS
INBK
R
C1
L1
D1
COMP1
V
POS
C
C1
SW1
FB1
EN1
C
R
VREG
FT1
VREG
Integrated 2.0 A main switch
C
OUT1
R
FB1
Optional single-ended primary-inductor converter
(SEPIC) configuration for automatic step-up/step-down
Inverting regulator to generate VNEG output
Adjustable negative output to VIN − 39 V
Integrated 1.2 A main switch
True shutdown for both positive and negative outputs
1.2 MHz/2.4 MHz switching frequency with optional external
frequency synchronization from 1.0 MHz to 2.6 MHz
Resistor programmable soft start timer
PVIN1
PVIN2
PVINSYS
V
IN
PGND
VREF
C
IN1
C
VREF
EN2
R
FB2
C
OUT2
R
C2
FB2
COMP2
R
FT2
C
C2
SYNC/FREQ
SLEW
SW2
V
NEG
D2
SEQ
AGND
L2
Slew rate control for lower system noise
Individual precision enable and flexible start-up sequence
control for symmetric start, VPOS first, or VNEG first
Out-of-phase operation
Figure 1.
UVLO, OCP, OVP, and TSD protection
4 mm × 4 mm, 20-lead LFCSP and 20-lead TSSOP
−40°C to +125°C junction temperature range
Supported by the ADIsimPower tool set
APPLICATIONS
Bipolar amplifiers, ADCs, DACs, and multiplexers
Charge-coupled device (CCD) bias supply
Optical module supply
RF power amplifier (PA) bias
GENERAL DESCRIPTION
The ADP5071 is a dual high performance dc-to-dc regulator that
generates independently regulated positive and negative rails.
The ADP5071 includes a fixed internal or resistor programmable
soft start timer to prevent inrush current at power-up. During
shutdown, both regulators completely disconnect the loads from
the input supply to provide a true shutdown.
The input voltage range of 2.85 V to 15 V supports a wide variety of
applications. The integrated main switch in both regulators enables
generation of an adjustable positive output voltage up to +39 V
and a negative output voltage down to −39 V below input voltage.
Other key safety features in the ADP5071 include overcurrent
protection (OCP), overvoltage protection (OVP), thermal
shutdown (TSD), and input undervoltage lockout (UVLO).
The ADP5071 operates at a pin selected 1.2 MHz/2.4 MHz
switching frequency. The ADP5071 can synchronize with an
external oscillator from 1.0 MHz to 2.6 MHz to ease noise
filtering in sensitive applications. Both regulators implement
programmable slew rate control circuitry for the MOSFET
driver stage to reduce electromagnetic interference (EMI).
The ADP5071 is available in a 20-lead LFCSP or in a 20-lead
TSSOP and is rated for a −40°C to +125°C junction temperature
range.
Table 1. Family Models
Model
Boost Switch (A)
Inverter Switch (A)
Flexible start-up sequencing is provided with the options of
manual enable, simultaneous mode, positive supply first, and
negative supply first.
ADP5070
ADP5071
1.0
2.0
0.6
1.2
Rev. A
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rightsof third parties that may result fromits use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks andregisteredtrademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Technical Support
©2015 Analog Devices, Inc. All rights reserved.
www.analog.com
ADP5071* Product Page Quick Links
Last Content Update: 11/01/2016
Comparable Parts
Reference Materials
View a parametric search of comparable parts
Press
• Bias Generation and Level Setting Made Easy with
Multiple Range, User Programmable Voltage Output D/A
Converter
Evaluation Kits
• ADP5070/ADP5071 Evaluation Board
Design Resources
• ADP5071 Material Declaration
• PCN-PDN Information
• Quality And Reliability
• Symbols and Footprints
Documentation
Application Notes
• AN-1366: Using the ADP5070/ADP5071 to Create Positive
and Negative Voltage Rails when VOUT < VIN
• AN-1368: Ferrite Bead Demystified
Data Sheet
Discussions
View all ADP5071 EngineerZone Discussions
• ADP5071: 2 A/1.2 A DC-to-DC Switching Regulator with
Independent Positive and Negative Outputs Data Sheet
User Guides
Sample and Buy
Visit the product page to see pricing options
• UG-758: Evaluating the ADP5070CP/ADP5071CP LFCSP
DC-to-DC Switching Regulators/Converters
• UG-848: Evaluating the ADP5070RE/ADP5071RE TSSOP
DC-to-DC Switching Regulators/Converters
Technical Support
Submit a technical question or find your regional support
number
Tools and Simulations
• ADIsimPower™ Voltage Regulator Design Tool
• ADP507x Design Tool
* This page was dynamically generated by Analog Devices, Inc. and inserted into this data sheet. Note: Dynamic changes to
the content on this page does not constitute a change to the revision number of the product data sheet. This content may be
frequently modified.
ADP5071
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Soft Start ...................................................................................... 15
Slew Rate Control....................................................................... 15
Current-Limit Protection ............................................................ 15
Overvoltage Protection.............................................................. 15
Thermal Shutdown .................................................................... 15
Start-Up Sequence...................................................................... 15
Applications Information .............................................................. 17
ADIsimPower Design Tool ....................................................... 17
Component Selection ................................................................ 17
Loop Compensation .................................................................. 20
Common Applications .............................................................. 22
Super Low Noise With Optional LDOs................................... 24
SEPIC Step-Up/Step-Down Operation ................................... 25
Layout Considerations............................................................... 26
Outline Dimensions....................................................................... 27
Ordering Guide .......................................................................... 27
Applications....................................................................................... 1
Typical Application Circuit ............................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 5
Thermal Resistance ...................................................................... 5
ESD Caution.................................................................................. 5
Pin Configurations and Function Descriptions ........................... 6
Typical Performance Characteristics ............................................. 8
Theory of Operation ...................................................................... 14
PWM Mode................................................................................. 14
PSM Mode................................................................................... 14
Undervoltage Lockout (UVLO) ............................................... 14
Oscillator and Synchronization................................................ 14
Internal Regulators..................................................................... 14
Precision Enabling...................................................................... 15
REVISION HISTORY
6/15—Rev. 0 to Rev. A
Added 20-Lead TSSOP ......................................................Universal
Change to Pull-Down Resistance Parameter, Table 2.................. 3
Changes to Table 3 and Table 4....................................................... 5
Added Figure 3, Renumbered Sequentially .................................. 6
Changes to Figure 37 Caption to Figure 39 Caption ................. 13
Changes to Internal Regulators Section ...................................... 14
Change to Soft Start Section.......................................................... 15
Changes to Component Selection Section.................................. 17
Changes to Output Capacitors Section, Soft Start Resistor Section,
and Diodes Section......................................................................... 18
Changes to Figure 52 Caption....................................................... 26
Added Figure 53.............................................................................. 26
Updated Outline Dimensions....................................................... 27
Changes to Ordering Guide .......................................................... 27
2/15—Revision 0: Initial Version
Rev. A | Page 2 of 27
Data Sheet
ADP5071
SPECIFICATIONS
PVIN1 = PVIN2 = PVINSYS = 2.85 V to 15 V, VPOS = 15 V, VNEG = −15 V, fSW = 1200 kHz, TJ = −40°C to +125°C for minimum/maximum
specifications, and TA = 25°C for typical specifications, unless otherwise noted.
Table 2.
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions/Comments
INPUT SUPPLY VOLTAGE RANGE
QUIESCENT CURRENT
VIN
2.85
15
V
PVIN1, PVIN2, PVINSYS
Operating Quiescent Current
PVIN1, PVIN2, PVINSYS (Total)
IQ
3.5
5
4.0
10
mA
µA
No switching, EN1 = EN2 = high,
PVIN1 = PVIN2 = PVINSYS = 5 V
No switching, EN1 = EN2 = low,
PVIN1 = PVIN2 = PVINSYS = 5 V
Shutdown Current
ISHDN
UVLO
System UVLO Threshold
Rising
Falling
PVINSYS
VUVLO_RISING
VUVLO_FALLING
VHYS_1
2.8
2.55
0.25
2.85
V
V
V
2.5
Hysteresis
OSCILLATOR CIRCUIT
Switching Frequency
fSW
1.130
2.240
1.200
2.400
1.270
2.560
MHz
MHz
SYNC/FREQ = low
SYNC/FREQ = high (connect to
VREG)
SYNC/FREQ Input
Input Clock Range
fSYNC
1.000
100
100
2.600
1.3
MHz
ns
ns
V
Input Clock Minimum On Pulse Width
Input Clock Minimum Off Pulse Width
Input Clock High Logic
Input Clock Low Logic
tSYNC_MIN_ON
tSYNC_MIN_OFF
VH (SYNC)
VL (SYNC)
0.4
V
PRECISION ENABLING (EN1, EN2)
High Level Threshold
Low Level Threshold
VTH_H
VTH_L
VTH_S
1.125
1.025
0.4
1.15
1.05
1.175
1.075
V
V
V
Shutdown Mode
Internal circuitry disabled to
achieve ISHDN
Pull-Down Resistance
INTERNAL REGULATOR
VREG Output Voltage
BOOST REGULATOR
REN
1.48
4.25
0.8
MΩ
V
VREG
VFB1
Feedback Voltage
V
Feedback Voltage Accuracy
−0.5
−1.5
+0.5
+1.5
0.1
%
%
µA
V
TJ = 25°C
TJ = −40°C to +125°C
Feedback Bias Current
Overvoltage Protection Threshold
Load Regulation
IFB1
VOV1
∆VFB1/ILOAD1
∆VFB1/VPVIN1
0.86
0.0003
0.002
At FB1 pin
%/mA ILOAD11 = 5 mA to 150 mA
1
Line Regulation
%/V
VPVIN1 = 2.85 V to 14.5 V, ILOAD1
50 mA
=
Error Amplifier (EA) Transconductance
Power FET On Resistance
Power FET Maximum Drain Source Voltage VDS (MAX) BOOST
Input Disconnect Switch On Resistance
Current-Limit Threshold
Minimum On Time
gM1
RDS (ON) BOOST
270
2.0
300
175
39
210
2.2
50
330
2.4
µA/V
mΩ
V
mΩ
A
RDS (ON) INBK
ILIM (BOOST)
ns
Minimum Off Time
25
ns
Rev. A | Page 3 of 27
ADP5071
Data Sheet
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions/Comments
INVERTING REGULATOR
Reference Voltage
VREF
1.60
V
Reference Voltage Accuracy
−0.5
−1.5
+0.5
+1.5
%
%
V
TJ = 25°C
TJ = −40°C to +125°C
Feedback Voltage
VREF − VFB2
0.8
Feedback Voltage Accuracy
−0.5
−1.5
+0.5
+1.5
0.1
%
%
µA
V
TJ = 25°C
TJ = −40°C to +125°C
Feedback Bias Current
Overvoltage Protection Threshold
IFB2
VOV2
0.74
At FB2 pin after soft start has
completed
Load Regulation
Line Regulation
∆(VREF − VFB2)/
ILOAD2
∆(VREF − VFB2)/
VPVIN2
0.0004
0.003
%/mA ILOAD21 = 5 mA to 75 mA
1
%/V
VPVIN2 = 2.85 V to 14.5 V, ILOAD2 =
25 mA
EA Transconductance
Power FET On Resistance
Power FET Maximum Drain Source Voltage VDS (MAX) INVERTER
gM2
RDS (ON) INVERTER
270
300
350
39
330
µA/V
mΩ
V
Current-Limit Threshold
Minimum On Time
Minimum Off Time
SOFT START
ILIM (INVERTER)
1200
1320
60
50
1440
mA
ns
ns
Soft Start Timer for Boost and Inverting
Regulators
tSS
4
ms
SS = open
32
8 × tSS
ms
ms
SS resistor = 50 kΩ to GND
Hiccup Time
THERMAL SHUTDOWN
Threshold
tHICCUP
TSHDN
THYS
150
15
°C
°C
Hysteresis
1 ILOADx is the current through a resistive load connected across the output capacitor (where x is 1 for the boost regulator load and 2 for the inverting regulator load).
Rev. A | Page 4 of 27
Data Sheet
ADP5071
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 3.
θJA and ΨJT are based on a 4-layer printed circuit board (PCB)
(two signal and two power planes) with nine thermal vias
connecting the exposed pad to the ground plane as recommended
in the Layout Considerations section. θJC is measured at the top
of the package and is independent of the PCB. The ΨJT value is
more appropriate for calculating junction to case temperature in
the application.
Parameter
Rating
PVIN1, PVIN2, PVINSYS
INBK
SW1
SW2
PGND, AGND
VREG
−0.3 V to +18 V
−0.3 V to PVIN1 + 0.3 V
−0.3 V to +40 V
PVIN2 − 40 V to PVIN2 + 0.3 V
−0.3 V to +0.3 V
−0.3 V to lower of PVINSYS +
0.3 V or +6 V
Table 4. Thermal Resistance
EN1, EN2, FB1, FB2, SYNC/FREQ −0.3 V to +6 V
COMP1, COMP2, SLEW, SS,
SEQ, VREF
Operating Junction
Temperature Range
Package Type
20-Lead LFCSP
20-Lead TSSOP
θJA
θJC
ΨJT
Unit
°C/W
°C/W
−0.3 V to VREG + 0.3 V
60.2
58.5
36.5
35.0
0.63
0.60
−40°C to +125°C
Storage Temperature Range
Soldering Conditions
−65°C to +150°C
JEDEC J-STD-020
ESD CAUTION
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Rev. A | Page 5 of 27
ADP5071
Data Sheet
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
20 SW2
PGND
SW1
1
2
19 PVIN2
18 PVINSYS
17 PVIN1
16 VREG
15 AGND
INBK
3
SYNC/FREQ
SEQ
4
15 PVIN1
14 VREG
13 AGND
12 VREF
11 FB2
INBK
SYNC/FREQ
SEQ
1
2
3
4
5
ADP5071
5
TOP VIEW
ADP5071
SLEW
FB1
6
TOP VIEW
(Not to Scale)
SLEW
7
14
13
VREF
FB2
FB1
COMP1
EN1
8
9
12 COMP2
11 EN2
SS
10
NOTES
NOTES
1. EXPOSED PAD. CONNECT THE EXPOSED PAD TO AGND.
1. EXPOSED PAD. CONNECT THE EXPOSED PAD TO AGND.
Figure 2. 20-Lead LFCSP Pin Configuration
Figure 3. 20-Lead TSSOP Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
LFCSP TSSOP Mnemonic Description
1
2
3
4
INBK
Input Disconnect Switch Output for the Boost Regulator.
SYNC/FREQ Frequency Setting and Synchronization Input. To set the switching frequency to 2.4 MHz, pull the SYNC/FREQ
pin high. To set the switching frequency to 1.2 MHz, pull the SYNC/FREQ pin low. To synchronize the
switching frequency, connect the SYNC/FREQ pin to an external clock.
3
4
5
6
SEQ
Start-Up Sequence Control. For manual VPOS/VNEG startup using an individual precision enabling pin, leave
the SEQ pin open. For simultaneous VPOS/VNEG startup when the EN2 pin rises, connect the SEQ pin to VREG
(the EN1 pin can be used to enable the internal references early, if required). For a sequenced startup, pull the
SEQ pin low. Either EN1 or EN2 can be used, and the corresponding supply is the first in sequence; hold
the other enable pin low.
Driver Stage Slew Rate Control. The SLEW pin sets the slew rate for the SW1 and SW2 drivers. For the
fastest slew rate (best efficiency), leave the SLEW pin open. For normal slew rate, connect the SLEW pin to
VREG. For the slowest slew rate (best noise performance), connect the SLEW pin to AGND.
SLEW
5
7
FB1
Feedback Input for the Boost Regulator. Connect a resistor divider between the positive side of the boost
regulator output capacitor and AGND to program the output voltage.
6
8
COMP1
EN1
Error Amplifier Compensation for the Boost Regulator. Connect the compensation network between this
pin and AGND.
Boost Regulator Precision Enable. The EN1 pin is compared to an internal precision reference to enable
the boost regulator output.
7
9
8
10
11
12
13
14
SS
Soft Start Programming. Leave the SS pin open to obtain the fastest soft start time. To program a slower
soft start time, connect a resistor between the SS pin and AGND.
Inverting Regulator Precision Enable. The EN2 pin is compared to an internal precision reference to enable
the inverting regulator output.
Error Amplifier Compensation for the Inverting Regulator. Connect the compensation network between
this pin and AGND.
Feedback Input for the Inverting Regulator. Connect a resistor divider between the negative side of the
inverting regulator output capacitor and VREF to program the output voltage.
9
EN2
10
11
12
COMP2
FB2
VREF
Inverting Regulator Reference Output. Connect a 1.0 μF ceramic filter capacitor between the VREF pin and
AGND.
13
14
15
16
17
15
16
17
18
19
AGND
VREG
PVIN1
PVINSYS
PVIN2
Analog Ground.
Internal Regulator Output. Connect a 1.0 μF ceramic filter capacitor between the VREG pin and AGND.
Power Input for the Boost Regulator.
System Power Supply for the ADP5071.
Power Input for the Inverting Regulator.
Rev. A | Page 6 of 27
Data Sheet
ADP5071
Pin No.
LFCSP TSSOP Mnemonic Description
18
19
20
20
1
2
SW2
PGND
SW1
Switching Node for the Inverting Regulator.
Power Ground for the Boost and Inverting Regulators.
Switching Node for the Boost Regulator.
EPAD
Exposed Pad. Connect the exposed pad to AGND.
Rev. A | Page 7 of 27
ADP5071
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
Typical performance characteristics are generated using the standard bill of materials for each input/output combination listed in Table 9,
Table 10, and Table 11.
1200
1000
800
600
400
200
0
1000
800
600
400
200
0
V
V
V
V
V
V
= 3.3V, L = 3.3µH
= 3.3V, L = 4.7µH
= 5V, L = 3.3µH
= 5V, L = 4.7µH
= 12V, L = 10µH
= 15V, L = 10µH
V
V
V
V
V
V
V
V
= 3.3V, L = 4.7µH
= 5V, L = 6.8µH
= 5V, L = 10µH
= 12V, L = 6.8µH
= 12V, L = 15µH
= 15V, L = 10µH
= 3.3V, L = 6.8µH
= 15V, L = 22µH
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
–40
–30
–20
NEG
–10
0
0
10
20
30
40
50
V
(V)
V
(V)
POS
Figure 4. Boost Regulator Maximum Output Current, fSW = 1.2 MHz,
A = 25°C, Based on Target of 70% ILIM (BOOST)
Figure 7. Inverting Regulator Maximum Output Current, fSW = 1.2 MHz,
A = 25°C, Based on Target of 70% ILIM (INVERTER)
T
T
700
600
500
400
300
200
100
0
1000
800
600
400
200
0
V
V
V
V
V
V
= 3.3V, L = 3.3µH
V
V
V
V
V
V
V
= 3.3V, L = 2.2µH
= 5V, L = 3.3µH
= 5V, L = 4.7µH
= 12V, L = 6.8µH
= 15V, L = 10µH
= 12V, L = 3.3µH
= 15V, L = 4.7µH
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
= 3.3V, L = 4.7µH
= 5V, L = 2.2µH
= 5V, L = 4.7µH
= 12V, L = 4.7µH
= 15V, L = 6.8µH
–40
–30
–20
NEG
–10
0
0
10
20
30
40
50
V
(V)
V
(V)
POS
Figure 5. Boost Regulator Maximum Output Current, fSW = 2.4 MHz,
A = 25°C, Based on Target of 70% ILIM (BOOST)
Figure 8. Inverting Regulator Maximum Output Current, fSW = 2.4 MHz,
A = 25°C, Based on Target of 70% ILIM (INVERTER)
T
T
100
80
60
40
20
0
100
80
60
40
20
0
V
V
= 3.3V, 1.2MHz
= 3.3V, 2.4MHz
V
V
= 3.3V, 1.2MHz
= 3.3V, 2.4MHz
IN
IN
IN
IN
0.001
0.01
0.1
1
0.001
0.01
0.1
1
LOAD (A)
LOAD (A)
Figure 6. Boost Regulator Efficiency vs. Current Load, VIN = 3.3 V,
POS = 5 V, TA = 25°C
Figure 9. Inverting Regulator Efficiency vs. Current Load, VIN = 3.3 V,
NEG = −5 V, TA = 25°C
V
V
Rev. A | Page 8 of 27
Data Sheet
ADP5071
100
80
60
40
20
100
80
60
40
20
0
V
V
V
V
= 3.3V, 1.2MHz
= 3.3V, 2.4MHz
= 5V, 1.2MHz
= 5V, 2.4MHz
V
V
V
V
= 3.3V, 1.2MHz
IN
IN
IN
IN
IN
IN
IN
IN
= 3.3V, 2.4MHz
= 5V, 1.2MHz
= 5V, 2.4MHz
0
0.001
0.01
0.1
1
0.001
0.01
0.1
1
LOAD (A)
LOAD (A)
Figure 10. Boost Regulator Efficiency vs. Current Load, VPOS = 9 V, TA = 25°C
Figure 13. Inverting Regulator Efficiency vs. Current Load, VNEG = −9 V,
TA = 25°C
100
100
80
60
40
20
80
60
40
20
V
V
V
V
= 3.3V, 1.2MHz
= 3.3V, 2.4MHz
= 5V, 1.2MHz
= 5V, 2.4MHz
V
V
V
V
= 3.3V, 1.2MHz
= 3.3V, 2.4MHz
= 5V, 1.2MHz
= 5V, 2.4MHz
IN
IN
IN
IN
IN
IN
IN
IN
0
0
0.001
0.01
0.1
1
0.001
0.01
0.1
1
LOAD (A)
LOAD (A)
Figure 11. Boost Regulator Efficiency vs. Current Load, VPOS = 15 V,
Figure 14. Inverting Regulator Efficiency vs. Current Load, VNEG = −15 V,
T
A = 25°C
T
A = 25°C
100
80
60
40
20
0
100
80
60
40
20
0
V
V
= 5V, 1.2MHz
= 5V, 2.4MHz
V
V
= 5V, 1.2MHz
= 5V, 2.4MHz
IN
IN
IN
IN
0.001
0.01
0.1
1
0.001
0.01
0.1
1
LOAD (A)
LOAD (A)
Figure 12. Boost Regulator Efficiency vs. Current Load, VPOS = 34 V,
A = 25°C
Figure 15. Inverting Regulator Efficiency vs. Current Load, VNEG = −34 V,
A = 25°C
T
T
Rev. A | Page 9 of 27
ADP5071
Data Sheet
100
80
60
40
20
100
80
60
40
20
0
T
T
T
= +125°C
= +25°C
= –40°C
T
T
T
= +125°C
= +25°C
= –40°C
A
A
A
A
A
A
0
0.001
0.01
0.1
1
0.001
0.01
0.1
1
LOAD (A)
LOAD (A)
Figure 16. Boost Regulator Efficiency over Temperature,
Figure 19. Inverting Regulator Efficiency over Temperature,
IN = 5 V, VNEG = −15 V, fSW = 1.2 MHz
VIN = 5 V, VPOS = 15 V, fSW = 1.2 MHz
V
0.5
0.3
0.5
0.3
0.1
0.1
–0.1
–0.3
–0.5
–0.1
–0.3
–0.5
V
V
V
ACCURACY
ACCURACY
ACCURACY
OUT
REF
FB2
V
ACCURACY
ACCURACY
OUT
V
FB1
15
0
5
10
(V)
20
0
5
10
(V)
15
20
V
V
IN
IN
Figure 17. Boost Regulator Line Regulation, VPOS = 15 V,
SW = 1.2 MHz, 15 mA Load, TA = 25°C
Figure 20. Inverting Regulator Line Regulation, VNEG = −15 V,
SW = 1.2 MHz, 15 mA Load, TA = 25°C
f
f
0.5
0.3
0.5
0.3
0.1
0.1
–0.1
–0.3
–0.5
–0.1
–0.3
–0.5
1.2MHz
2.4MHz
1.2MHz
2.4MHz
0
0.1
0.2
0.3
0.4
0.5
0
0.05
0.10
0.15
LOAD (A)
LOAD (A)
Figure 18. Boost Regulator Load Regulation, VIN = 5 V, VPOS = 15 V
Figure 21. Inverting Regulator Load Regulation, VIN = 5 V, VNEG = −15 V
Rev. A | Page 10 of 27
Data Sheet
ADP5071
0.5
0.5
0.3
0.3
0.1
0.1
–0.1
–0.3
–0.1
–0.3
–0.5
–0.5
0
0.05
0.10
0.15
0.20
–0.05
0.05
0.15
0.25
0.35
0.45
INVERTING REGULATOR LOAD (A)
BOOST REGULATOR LOAD (A)
Figure 22. Cross Regulation, Boost Regulator VFB1 Regulation over Inverting
Regulator Current Load, VIN = 5 V, VPOS = 15 V, VNEG = −15 V,
Figure 25. Cross Regulation, Inverting Regulator VFB2 Regulation over Boost
Regulator Current Load, VIN = 5 V, VPOS = 15 V, VNEG = −15 V,
f
SW = 2.4 MHz, TA = 25°C, Boost Regulator Run in Continuous Conduction
Mode with Fixed Load for Test
f
SW = 2.4 MHz, TA = 25°C, Inverting Regulator Run in Continuous Conduction
Mode with Fixed Load for Test
1.44
2.40
T
T
T
= +125°C
= +25°C
= –40°C
T
T
T
= +125°C
= +25°C
= –40°C
A
A
A
A
A
A
2.35
2.30
2.25
2.20
2.15
2.10
2.05
2.00
1.40
1.36
1.32
1.28
1.22
1.20
0
5
10
(V)
15
20
0
2
4
6
8
10
12
14
16
V
V
(V)
IN
IN
Figure 23. Boost Regulator Current Limit (ILIMIT) vs. Input Voltage (VIN
over Temperature
)
Figure 26. Inverting Regulator Current Limit (ILIMIT) vs. Input Voltage (VIN
over Temperature
)
1.27
2.54
T
T
T
= +125°C
= +25°C
= –40°C
T
T
T
= +125°C
= +25°C
= –40°C
A
A
A
A
A
A
1.25
1.23
1.21
1.19
1.17
1.15
1.13
2.49
2.44
2.39
2.34
2.29
2.24
0
2
4
6
8
10
12
14
16
0
2
4
6
8
10
12
14
16
V
(V)
V
(V)
IN
IN
Figure 24. Oscillator Frequency vs. Input Voltage (VIN) over Temperature,
SYNC/FREQ Pin = High
Figure 27. Oscillator Frequency vs. Input Voltage (VIN) over Temperature,
SYNC/FREQ Pin = Low
Rev. A | Page 11 of 27
ADP5071
Data Sheet
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
14
12
10
8
6
4
T
T
T
= +125°C
= +25°C
= –40°C
A
A
A
2
T
T
T
= +125°C
= +25°C
= –40°C
A
A
A
0
2
4
6
8
10
12
14
16
0
0
2
4
6
8
10
12
14
16
V
(V)
IN
V
(V)
IN
Figure 31. Operating Quiescent Current vs. Input Voltage (VIN) over
Temperature, Both ENx Pins On
Figure 28. Shutdown Quiescent Current vs. Input Voltage (VIN) over
Temperature, Both ENx Pins Below Shutdown Threshold
T
T
V
IN
V
IN
V
NEG
2
1
V
POS
2
1
V
FB2
V
3
FB1
3
B
B
CH1 1V
CH3 5mV
CH2 100mV
W
4.00ms
14.0ms
CH1
5.0V
W
W
B
B
CH1 1.0V
CH3 5.0mV
CH2 100mV
4.00ms
W
CH1
5.00V
B
W
T
B
T
14.0ms
W
Figure 32. Inverting Regulator Line Transient, VIN = 4.5 V to 5.5 V Step,
Figure 29. Boost Regulator Line Transient, VIN = 4.5 V to 5.5 V Step,
VNEG = −15 V, RLOAD2 = 300 Ω, fSW = 2.4 MHz, TA = 25°C
VPOS = 15 V, RLOAD1 = 300 Ω, fSW = 2.4 MHz, TA = 25°C
T
T
I
LOAD1
I
LOAD2
V
1
2
NEG
2
1
V
POS
V
FB2
3
V
FB1
3
B
CH1 10mA
CH3 5mV
CH2 50mV
W
4.00ms
13.0ms
CH1
50mA
W
B
CH1 20mA
CH3 25mV
CH2 50mV
W
4.00ms
CH1
137mA
B
W
T
B
T
13.160ms
Figure 33. Inverting Regulator Load Transient, VIN = 5 V Step, VNEG = −15 V,
LOAD2 = 35 mA to 45 mA Step, fSW = 2.4 MHz, TA = 25°C
Figure 30. Boost Regulator Load Transient, VIN = 5 V Step, VPOS = 15 V,
LOAD1 = 120 mA to 150 mA Step, fSW = 2.4 MHz, TA = 25°C
I
I
Rev. A | Page 12 of 27
Data Sheet
ADP5071
T
T
I
INDUCTOR
I
INDUCTOR
1
1
2
SW2
SW1
2
3
V
V
NEG
POS
3
B
B
B
B
CH2 5V Ω
CH1 200mA
CH3 500mV
CH2 2.5V Ω
2.0µs
34.6%
CH1
0.0A
CH1 100mA
CH3 500mV
2.0µs
17.4%
CH1
0A
W
B
W
W
B
W
T
T
W
W
Figure 34. Boost Regulator Skip Mode Operation Showing Inductor Current
(IINDUCTOR), Switch Node Voltage, and Output Ripple, VIN = 5 V,
Figure 37. Inverting Regulator Skip Mode Operation Showing Inductor
Current (IINDUCTOR), Switch Node Voltage, and Output Ripple, VIN = 5 V,
VPOS = 15 V, ILOAD1 = 4 mA, fSW = 2.4 MHz, TA = 25°C
VNEG = −5 V, ILOAD2 = 1 mA, fSW = 2.4 MHz, TA = 25°C
T
T
I
INDUCTOR
SW2
I
INDUCTOR
SW1
1
1
2
2
3
V
V
POS
NEG
3
B
B
B
B
CH2 5.0V Ω
CH1 200mA
CH3 500mV
CH2 2.5V Ω
100ns
34.6%
CH1
152mA
CH1 100mA
CH3 500mV
100ns
W
CH1
80mA
W
B
W
W
B
T
T 17.4%
W
W
Figure 35. Boost Regulator Discontinuous Conduction Mode Operation
Showing Inductor Current (IINDUCTOR), Switch Node Voltage, and Output
Ripple, VIN = 5 V, VPOS = 15 V, ILOAD1 = 35 mA, fSW = 2.4 MHz, TA = 25°C
Figure 38. Inverting Regulator Discontinuous Conduction Mode Operation
Showing Inductor Current (IINDUCTOR), Switch Node Voltage, and Output Ripple,
VIN = 5 V, VNEG = −5 V, ILOAD2 = 6 mA, fSW = 2.4 MHz, TA = 25°C
T
T
I
INDUCTOR
1
1
2
I
INDUCTOR
SW2
SW1
2
3
V
NEG
3
V
POS
B
B
B
B
CH2 5V Ω
CH1 200mA
CH3 500mV
CH2 2.5V Ω
100ns
CH1
152mA
CH1 100mA
CH3 500mV
100ns
17.4%s
CH1
172mA
W
B
W
W
B
W
T
34.6%
T
W
W
Figure 39. Inverting Regulator Continuous Conduction Mode Operation
Showing Inductor Current (IINDUCTOR), Switch Node Voltage, and Output
Ripple, VIN = 5 V, VNEG = −5 V, ILOAD2 = 35 mA, fSW = 2.4 MHz, TA = 25°C
Figure 36. Boost Regulator Continuous Conduction Mode Operation
Showing Inductor Current (IINDUCTOR), Switch Node Voltage, and Output
Ripple, VIN = 5 V, VPOS = 15 V, ILOAD1 = 90 mA, fSW = 2.4 MHz, TA = 25°C
Rev. A | Page 13 of 27
ADP5071
Data Sheet
THEORY OF OPERATION
V
IN
CVREG
PVIN1
SYNC/FREQ
PVINSYS
VREG
PVIN2
C
IN
CURRENT SENSE
INVERTER
INBK SWITCH
CONTROL
HV
REGULATOR
INBK
PWM CONTROL
D2
SW2
L2
L1
EN1
EN2
SLEW
HV
BAND GAP
D1
C
V
OUT2
OUT1
SW1
SLEW
C
OUT1
PLL
BOOST PWM
CONTROL
R
FT1
ERROR
AMP
R
REF2
FT2
+
–
OSCILLATOR
PGND
FB1
FB2
CURRENT
SENSE
BOOST_ENABLE
SEQUENCE
CONTROL
R
FB2
ERROR
AMP
–
+
INVERTER_ENABLE
VREF
REF_1V6
REF1
R
REF1
THERMAL
SHUTDOWN
FB1
COMP1
C
VREF
VREG
4µA
COMP2
UVLO
R
C1
REFERENCE
GENERATOR
START-UP
TIMERS
R
C2
REF2
FB1
OVP
REF_1V6
FB2
C
C1
C
C2
SLEW
EN1
EN2 SEQ
SS
AGND
R
(OPTIONAL)
SS
Figure 40. Functional Block Diagram
A phase-locked loop (PLL)-based oscillator generates the internal
clock and offers a choice of two internally generated frequency
options or external clock synchronization. The switching frequency
is configured using the SYNC/FREQ pin options shown in Table 6.
PWM MODE
The boost and inverting regulators in the ADP5071 operate at a
fixed frequency set by an internal oscillator. At the start of each
oscillator cycle, the MOSFET switch turns on, applying a positive
voltage across the inductor. The inductor current increases until
the current sense signal crosses the peak inductor current threshold
that turns off the MOSFET switch; this threshold is set by the error
amplifier output. During the MOSFET off time, the inductor
current declines through the external diode until the next
oscillator clock pulse starts a new cycle. It regulates the output
voltage by adjusting the peak inductor current threshold.
For external synchronization, connect the SYNC/FREQ pin to a
suitable clock source. The PLL locks to an input clock within
the range specified by fSYNC
.
Table 6. SYNC/FREQ Pin Options
SYNC/FREQ Pin
High
Switching Frequency
2.4 MHz
Low
1.2 MHz
PSM MODE
External Clock
1 × clock frequency
During light load operation, the regulators can skip pulses to
maintain output voltage regulation. Skipping pulses increases
the device efficiency.
INTERNAL REGULATORS
The internal VREG regulator in the ADP5071 provides a stable
power supply for the internal circuitry. The VREG supply can be
used to provide a logic high signal for device configuration pins but
must not be used to supply external circuitry.
UNDERVOLTAGE LOCKOUT (UVLO)
The undervoltage lockout circuitry monitors the PVINSYS pin
voltage level. If the input voltage drops below the VUVLO_FALLING
threshold, both regulators turn off. After the PVINSYS pin voltage
rises above the VUVLO_RISING threshold, the soft start period initiates,
and the regulators are enabled.
The VREF regulator provides a reference voltage for the inverting
regulator feedback network to ensure a positive feedback voltage on
the FB2 pin.
OSCILLATOR AND SYNCHRONIZATION
A current-limit circuit is included for both regulators to protect the
circuit from accidental loading.
The ADP5071 initiates the drive of the boost regulator SW1 pin
and the inverting regulator SW2 pin 180° out of phase to reduce
peak current consumption and noise.
Rev. A | Page 14 of 27
Data Sheet
ADP5071
PRECISION ENABLING
CURRENT-LIMIT PROTECTION
The ADP5071 has an individual enable pin for the boost and
inverting regulators: EN1 and EN2. The enable pins feature a
precision enable circuit with an accurate reference voltage. This
reference allows the ADP5071 to be sequenced easily from other
supplies. It can also be used as a programmable UVLO input by
using a resistor divider.
The boost and inverting regulators in the ADP5071 include
current-limit protection circuitry to limit the amount of forward
current through the MOSFET switch.
When the peak inductor current exceeds the overcurrent limit
threshold for a number of clock cycles during an overload or
short-circuit condition, the regulator enters hiccup mode. The
regulator stops switching and then restarts with a new soft start
cycle after tHICCUP and repeats until the overcurrent condition is
removed.
The enable pins have an internal pull-down resistor that defaults
each regulator to off when the pin is floating.
When the voltage at the enable pins is greater than the VTH_H
reference level, the regulator is enabled.
OVERVOLTAGE PROTECTION
An overvoltage protection mechanism is present on the FB1
and FB2 pins for the boost and inverting regulators.
SOFT START
Each regulator in the ADP5071 includes soft start circuitry that
ramps the output voltage in a controlled manner during startup,
thereby limiting the inrush current. The soft start time is internally
set to the fastest rate when the SS pin is open.
On the boost regulator, when the voltage on the FB1 pin exceeds
the VOV1 threshold, the switching on SW1 stops until the voltage
falls below the threshold again. This functionality is permanently
enabled on this regulator.
Connecting a resistor between SS and AGND allows the adjust-
ment of the soft start delay. The delay length is common to both
regulators.
On the inverting regulator, when the voltage on the FB2 pin
drops below the VOV2 threshold, the switching stops until the
voltage rises above the threshold. This functionality is enabled
after the soft start period has elapsed.
SLEW RATE CONTROL
The ADP5071 employs programmable output driver slew rate
control circuitry. This circuitry reduces the slew rate of the
switching node as shown in Figure 41, resulting in reduced
ringing and lower EMI. To program the slew rate, connect the
SLEW pin to the VREG pin for normal mode, to the AGND pin
for slow mode, or leave it open for fast mode. This configuration
allows the use of an open-drain output from a noise sensitive
device to switch the slew rate from fast to slow, for example,
during analog-to-digital converter (ADC) sampling.
THERMAL SHUTDOWN
In the event that the ADP5071 junction temperature rises above
T
SHDN, the thermal shutdown circuit turns off the IC. Extreme
junction temperatures can be the result of prolonged high current
operation, poor circuit board design, and/or high ambient temper-
ature. Hysteresis is included so that when thermal shutdown occurs,
the ADP5071 does not return to operation until the on-chip
temperature drops below TSHDN minus THYS. When resuming from
thermal shutdown, a soft start is performed on each enabled
channel.
Note that slew rate control causes a trade-off between efficiency
and low EMI.
START-UP SEQUENCE
The ADP5071 implements a flexible start-up sequence to meet
different system requirements. Three different enabling modes
can be implemented via the SEQ pin, as explained in Table 7.
FASTEST
SLOWEST
Table 7. SEQ Pin Settings
SEQ Pin
Open
VREG
Low
Description
Manual enable mode
Simultaneous enable mode
Sequential enable mode
To configure the manual enable mode, leave the SEQ pin open.
The boost and inverting regulators are controlled separately from
their respective precision enable pins.
Figure 41. Switching Node at Various Slew Rate Settings
Rev. A | Page 15 of 27
ADP5071
Data Sheet
V
POS
To configure the simultaneous enable mode, connect the SEQ pin
to the VREG pin. Both regulators power up simultaneously
when the EN2 pin is taken high. The EN1 pin enable can be
used to enable the internal references ahead of enabling the
outputs, if desired. The simultaneous enable mode timing is
shown in Figure 42.
V
IN
DISCONNECT
SWITCH TURN ON
TIME
V
POS
V
V
NEG
1. V
POS
FOLLOWED BY V
NEG
V
(SEQ = LOW, EN1 = HIGH, EN2 = LOW)
IN
DISCONNECT
SWITCH TURN ON
POS
TIME
V
IN
DISCONNECT
SWITCH TURN ON
V
NEG
TIME
SIMULTANEOUS ENABLE MODE
(SEQ = HIGH, EN2 = HIGH)
Figure 42. Simultaneous Enable Mode
V
NEG
To configure the sequential enable mode, pull the SEQ pin low.
In this mode, either VPOS or VNEG can be enabled first by using
the respective EN1 pin or EN2 pin. Keep the other pin low. The
secondary supply is enabled when the primary supply completes
soft start and its feedback voltage reaches approximately 85% of
the target value. The sequential enable mode timing is shown in
Figure 43.
2. V
NEG
FOLLOWED BY V
POS
(SEQ = LOW, EN2 = HIGH, EN1 = LOW)
SEQUENTIAL ENABLE MODE
Figure 43. Sequential Enable Mode
Rev. A | Page 16 of 27
Data Sheet
ADP5071
APPLICATIONS INFORMATION
Set the positive output for the boost regulator by
ADIsimPOWER DESIGN TOOL
The ADP5071 is supported by the ADIsimPower design toolset.
ADIsimPower is a collection of tools that produce complete
power designs optimized to a specific design goal. These tools
allow the user to generate a full schematic, bill of materials, and
calculate performance in minutes. ADIsimPower can optimize
designs for cost, area, efficiency, and parts count while taking
into consideration the operating conditions and limitations of
the IC and all real external components. The ADIsimPower tool
can be found at www.analog.com/adisimpower, and the user
can request an unpopulated board through the tool.
R
FT1
VPOS = VFB1 × 1+
RFB1
where:
V
V
R
R
POS is the positive output voltage.
FB1 is the FB1 reference voltage.
FT1 is the feedback resistor from VPOS to FB1.
FB1 is the feedback resistor from FB1 to AGND.
Set the negative output for the inverting regulator by
R
FT2
FB2
COMPONENT SELECTION
Feedback Resistors
VNEG = VFB2
where:
V
V
R
R
V
−
(
VREF −VFB2
)
R
The ADP5071 provides an adjustable output voltage for both boost
and inverting regulators. An external resistor divider sets the output
voltage where the divider output must equal the appropriate
feedback reference voltage, VFB1 or VFB2. To limit the output voltage
accuracy degradation due to feedback bias current, ensure that the
NEG is the negative output voltage.
FB2 is the FB2 reference voltage.
FT2 is the feedback resistor from VNEG to FB2.
FB2 is the feedback resistor from FB2 to VREF.
REF is the VREF pin reference voltage.
current through the divider is at least 10 times IFB1 or IFB2
.
Table 8. Recommended Feedback Resistor Values
Boost/SEPIC Regulator
Inverting Regulator
Calculated
Desired Output
Voltage (V)
Calculated
RFT1 (MΩ)
0.143
0.316
0.357
0.432
0.604
1.24
1.4
2.1
2.43
2.15
RFB1 (kΩ)
115
115
115
102
115
121
100
137
137
100
107
107
100
137
Output Voltage (V)
RFT2 (MΩ)
0.332
0.475
0.523
0.715
1.15
1.62
1.15
2.8
2.32
RFB2 (kΩ)
Output Voltage (V)
1.8
3
3.3
4.2
5
1.795
2.998
3.283
4.188
5.002
8.998
12.000
13.063
14.990
18.000
19.865
23.903
30.000
35.253
102
100
102
115
158
133
71.5
162
118
113
113
102
107
−1.804
−3.000
−3.302
−4.174
−5.023
−8.944
−12.067
−13.027
−14.929
−18.103
−20.014
−23.984
−30.004
−34.748
9
12
13
15
18
20
24
30
35
2.67
2.94
3.16
4.12
2.55
3.09
3.65
5.9
5.11
115
Rev. A | Page 17 of 27
ADP5071
Data Sheet
Output Capacitors
VREF Capacitor
Higher output capacitor values reduce the output voltage ripple
and improve load transient response. When choosing this value,
it is also important to account for the loss of capacitance due to
the output voltage dc bias.
A 1.0 µF ceramic capacitor (CVREF) is required between the VREF
pin and AGND.
Soft Start Resistor
A resistor can be connected between the SS pin and the AGND pin
to increase the soft start time. The soft start time can be set by the
resistor between 4 ms (268 kΩ) and 32 ms (50 kΩ). Leaving the
SS pin open selects the fastest time of 4 ms. Figure 44 shows the
behavior of this operation. Calculate the soft start time using the
following formula:
Ceramic capacitors are manufactured with a variety of dielectrics,
each with a different behavior over temperature and applied
voltage. Capacitors must have a dielectric adequate to ensure the
minimum capacitance over the necessary temperature range and
dc bias conditions. X5R or X7R dielectrics with a voltage rating of
25 V or 50 V (depending on output) are recommended for best
performance. Y5V and Z5U dielectrics are not recommended
for use with any dc-to-dc converter because of their poor
temperature and dc bias characteristics.
t
SS = 38.4 × 10−3 − 1.28 × 10−7 × RSS (Ω)
where 50 kΩ ≤ RSS ≤ 268 kΩ.
SOFT START
TIMER
Calculate the worst-case capacitance accounting for capacitor
variation over temperature, component tolerance, and voltage
using the following equation:
32ms
C
EFFECTIVE = CNOMINAL × (1 − TEMPCO) × (1 − DCBIASCO) ×
(1 − Tolerance)
where:
4ms
SS PIN OPEN
R1
SOFT START
RESISTOR
CEFFECTIVE is the effective capacitance at the operating voltage.
CNOMINAL is the nominal data sheet capacitance.
R2
Figure 44. Soft Start Behavior
TEMPCO is the worst-case capacitor temperature coefficient.
DCBIASCO is the dc bias derating at the output voltage.
Tolerance is the worst-case component tolerance.
Diodes
A Schottky diode with low junction capacitance is recommended
for D1 and D2. At higher output voltages and especially at higher
switching frequencies, the junction capacitance is a significant
contributor to efficiency. Higher capacitance diodes also generate
more switching noise. As a guide, a diode with less than 40 pF
junction capacitance is preferred when the output voltage is
above 5 V.
To guarantee the performance of the device, it is imperative that
the effects of dc bias, temperature, and tolerances on the
behavior of the capacitors be evaluated for each application.
Capacitors with lower effective series resistance (ESR) and
effective series inductance (ESL) are preferred to minimize
output voltage ripple.
Inductor Selection for the Boost Regulator
Note that the use of large output capacitors can require a slower
soft start to prevent current limit during startup. A 10 µF capacitor
is suggested as a good balance between performance and size.
The inductor stores energy during the on time of the power
switch, and transfers that energy to the output through the
output rectifier during the off time. To balance the tradeoffs
between small inductor current ripple and efficiency, inductance
values in the range of 1 µH to 22 µH are recommended. In general,
lower inductance values have higher saturation current and
lower series resistance for a given physical size. However, lower
inductance results in a higher peak current that can lead to reduced
efficiency and greater input and/or output ripple and noise. A
peak-to-peak inductor ripple current close to 30% of the maximum
dc input current for the application typically yields an optimal
compromise.
Input Capacitor
Higher value input capacitors help to reduce the input voltage
ripple and improve transient response.
To minimize supply noise, place the input capacitor as close as
possible to the PVINSYS pin, PVIN1 pin, and PVIN2 pin. A low
ESR capacitor is recommended.
The effective capacitance needed for stability is a minimum of 10 µF.
If the power pins are individually decoupled, it is recommended
to use an effective minimum of a 5.6 µF capacitor on the PVIN1
and PVIN2 pins and a 3.3 µF capacitor on the PVINSYS pin. The
minimum values specified exclude dc bias, temperature, and
tolerance effects that are application dependent and must be
taken into consideration.
VREG Capacitor
A 1.0 µF ceramic capacitor (CVREG) is required between the VREG
pin and AGND.
Rev. A | Page 18 of 27
Data Sheet
ADP5071
For the inductor ripple current in continuous conduction mode
(CCM) operation, the input (VIN) and output (VPOS) voltages
determine the switch duty cycle (DUTY1) by the following
equation:
Inductor Selection for the Inverting Regulator
The inductor stores energy during the on time of the power
switch, and transfers that energy to the output through the
output rectifier during the off time. To balance the tradeoffs
between small inductor current ripple and efficiency, inductance
values in the range of 1 µH to 22 µH are recommended. In
general, lower inductance values have higher saturation current
and lower series resistance for a given physical size. However,
lower inductance results in a higher peak current that can lead
to reduced efficiency and greater input and/or output ripple and
noise. A peak-to-peak inductor ripple current close to 30% of
the maximum dc current in the inductor typically yields an
optimal compromise.
DIODE1
V
POS −VIN +V
DUTY =
1
VPOS +VDIODE1
where VDIODE1 is the forward voltage drop of the Schottky diode
(D1).
The dc input current in CCM (IIN) can be determined by the
following equation:
IOUT1
(1− DUTY )
IIN
=
For the inductor ripple current in continuous conduction mode
(CCM) operation, the input (VIN) and output (VNEG) voltages
determine the switch duty cycle (DUTY2) by the following
equation:
1
Using the duty cycle (DUTY1) and switching frequency (fSW),
determine the on time (tON1) using the following equation:
DUTY
fSW
1
tON1
=
|VNEG | + VDIODE2
DUTY
=
2
VIN + |VNEG | + V
DIODE2
The inductor ripple current (∆IL1) in steady state is calculated by
VIN ×tON1
where VDIODE2 is the forward voltage drop of the Schottky diode
(D2).
∆IL1
=
L1
The dc current in the inductor in CCM (IL2) can be determined
by the following equation:
Solve for the inductance value (L1) using the following equation:
VIN × tON1
L1 =
IOUT2
(1− DUTY )
IL2
=
∆IL1
2
Assuming an inductor ripple current of 30% of the maximum
dc input current results in
Using the duty cycle (DUTY2) and switching frequency (fSW),
determine the on time (tON2) by the following equation:
VIN × tON1 × (1− DUTY
1)
DUTY
fSW
2
L1 =
tON2
=
× OUT1
Ensure that the peak inductor current (the maximum input
current plus half the inductor ripple current) is below the rated
saturation current of the inductor. Likewise, ensure that the
maximum rated rms current of the inductor is greater than the
maximum dc input current to the regulator.
The inductor ripple current (∆IL2) in steady state is calculated by
VIN ×tON2
∆IL2
=
L2
Solve for the inductance value (L2) by the following equation:
When the ADP5071 boost regulator is operated in CCM at duty
cycles greater than 50%, slope compensation is required to stabilize
the current mode loop. This slope compensation is built in to
the ADP5071 For stable current mode operation, ensure that
the selected inductance is equal to or greater than the minimum
calculated inductance, LMIN1, for the application parameters in
the following equation:
VIN × tON2
L2 =
∆IL2
Assuming an inductor ripple current of 30% of the maximum
dc current in the inductor results in
VIN × tON2 ×(1− DUTY )
2
L2 =
×OUT2
0.13
(1 − DUTY )
(µH)
Ensure that the peak inductor current (the maximum input current
plus half the inductor ripple current) is below the rated saturation
current of the inductor. Likewise, ensure that the maximum rated
rms current of the inductor is greater than the maximum dc
input current to the regulator.
L1 > LMIN1 =VIN ×
− 0.16
1
Table 10 suggests a series of inductors to use with the ADP5071
boost regulator.
Rev. A | Page 19 of 27
ADP5071
Data Sheet
When the ADP5071 inverting regulator is operated in CCM at
duty cycles greater than 50%, slope compensation is required to
stabilize the current mode loop. For stable current mode operation,
ensure that the selected inductance is equal to or greater than
the minimum calculated inductance, LMIN2, for the application
parameters in the following equation:
G
CS1 is the current sense transconductance gain (the inductor
current divided by the voltage at COMP1), which is internally
set by the ADP5071and is 12.5 A/V.
ZOUT1 is the impedance of the load in parallel with the output
capacitor.
To determine the crossover frequency (fC1), it is important to
note that, at that frequency, the compensation impedance (ZCOMP1
is dominated by a resistor (RC1), and the output impedance (ZOUT1
is dominated by the impedance of an output capacitor (COUT1).
Therefore, when solving for the crossover frequency, the equation
(by definition of the crossover frequency) is simplified to
)
)
0.13
(1 − DUTY
(µH)
L2 > LMIN2 =VIN ×
− 0.16
2
)
Table 11 suggests a series of inductors to use with the ADP5071
inverting regulator.
VFB1 VIN
VPOS VPOS
LOOP COMPENSATION
AVL1
=
×
×GM1 × RC1 ×GCS1 ×
The ADP5071 uses external components to compensate the
regulator loop, allowing the optimization of the loop dynamics
for a given application. It is recommended to use the ADIsimPower
tool to calculate compensation components.
1
=1
2π × fC1 ×COUT1
where fC1 is the crossover frequency.
Boost Regulator
To solve for RC1, use the following equation:
The boost converter produces an undesirable right half plane
zero in the regulation feedback loop. This feedback loop requires
compensating the regulator such that the crossover frequency
occurs well below the frequency of the right half plane zero. The
right half plane zero is determined by the following equation:
2
2π × fC1 ×COUT1 ×(VPOS
)
RC1
=
VFB1 ×VIN ×GM1 ×GCS1
where GCS1 = 12.5 A /V.
2
Using typical values for VFB1 and GM1 results in
R
LOAD1(1− DUTY
1)
fZ1(RHP) =
where:
2
2094 × fC1 ×COUT1 ×(VPOS
)
π ×
RC1
=
VIN
fZ1(RHP) is the right half plane zero frequency.
LOAD1 is the equivalent load resistance or the output voltage
divided by the load current.
For better accuracy, it is recommended to use the value of output
capacitance, COUT1, expected for the dc bias conditions under
which it operates under in the calculation for RC1.
R
DIODE1
V
POS −VIN +V
After the compensation resistor is known, set the zero formed
by the compensation capacitor and resistor to one-fourth of the
crossover frequency, or
DUTY =
1
VPOS +VDIODE1
where VDIODE1 is the forward voltage drop of the Schottky
2
diode (D1).
CC1
=
π × fC1 × RC1
To stabilize the regulator, ensure that the regulator crossover
frequency is less than or equal to one-tenth of the right half
plane zero frequency.
where CC1 is the compensation capacitor value.
ERROR
AMPLIFIER
FB1
The boost regulator loop gain is
COMP1
g
M1
REF1
VFB1 VIN
VPOS VPOS
R
C1
AVL1
=
×
× GM1 × ROUT1||ZCOMP1 × GCS1 × ZOUT1
C
B1
C
C1
where:
A
V
V
V
G
VL1 is the loop gain.
Figure 45. Compensation Components
FB1 is the feedback regulation voltage
POS is the regulated positive output voltage.
IN is the input voltage.
The capacitor, CB1, is chosen to cancel the zero introduced by
the output capacitor ESR. Solve for CB1 as follows:
M1 is the error amplifier transconductance gain.
ESR × COUT1
CB1 =
R
Z
OUT1 is the output impedance of the error amplifier and is 33 MΩ.
COMP1 is the impedance of the series RC network from
RC1
COMP1 to AGND.
Rev. A | Page 20 of 27
Data Sheet
ADP5071
For low ESR output capacitance such as with a ceramic capacitor,
To determine the crossover frequency, it is important to note
that, at that frequency, the compensation impedance (ZCOMP2) is
C
B1 is optional. For optimal transient performance, RC1 and CC1
may need to be adjusted by observing the load transient response
of the ADP5071. For most applications, RC1 must be within the
range of 1 kΩ to 200 kΩ, and CC1 must be within the range of
1 nF to 68 nF.
dominated by a resistor, RC2, and the output impedance (ZOUT2
)
is dominated by the impedance of the output capacitor, COUT2
.
Therefore, when solving for the crossover frequency, the equation
(by definition of the crossover frequency) is simplified to
Inverting Regulator
VFB2
VIN
A
=
×
× GM2 ×
VL2
|VNEG| (VIN + 2 ×|VNEG|)
The inverting converter, like the boost converter, produces an
undesirable right half plane zero in the regulation feedback loop.
This feedback loop requires compensating the regulator such that
the crossover frequency occurs well below the frequency of the
right half plane zero. The right half plane zero frequency is
determined by the following equation:
1
RC2 × GCS 2 ×
=1
2π × fC2 × COUT2
where fC2 is the crossover frequency.
To solve for RC2, use the following equation:
2
RLOAD2(1− DUTY
2π × L2 × DUTY
2
)
2π × fC2 × COUT2 ×|VNEG|×(VIN + (2 ×|VNEG|)
VFB2 ×VIN × GM2 × GCS2
fZ2(RHP) =
RC2 =
2
where:
fZ2(RHP) is the right half plane zero frequency.
LOAD2 is the equivalent load resistance or the output voltage
divided by the load current.
where GCS2 = 12.5 A /V.
Using typical values for VFB2 and GM2 results in
R
2094× fC2 ×COUT2×|VNEG|× (VIN + (2 ×|VNEG|)
RC2
=
VIN
|VNEG|+VDIODE2
VIN +|VNEG|+ V
DUTY =
2
For better accuracy, it is recommended to use the value of output
capacitance, COUT2, expected under the dc bias conditions that it
operates under in the calculation for RC2.
DIODE2
where VDIODE2 is the forward voltage drop of the Schottky diode
(D2).
After the compensation resistor is known, set the zero formed
by the CC2 and RC2 to one-fourth of the crossover frequency, or
To stabilize the regulator, ensure that the regulator crossover
frequency is less than or equal to one-tenth of the right half
plane zero frequency.
2
CC2 =
π × fC2 × RC2
The inverting regulator loop gain is
where CC2 is the compensation capacitor.
VFB2
VIN
ERROR
A
=
×
× GM2 ×
VL2
AMPLIFIER
FB2
|VNEG
|
(VIN + 2 × |VNEG|)
COMP2
g
M2
REF2
R
C2
C
B2
ROUT2||ZCOMP2 × GCS2 × ZOUT2
where:
C
C2
A
V
V
V
G
VL2 is the loop gain.
FB2 is the feedback regulation voltage.
NEG is the regulated negative output voltage.
IN is the input voltage.
Figure 46. Compensation Component
The capacitor, CB2, is chosen to cancel the zero introduced by
output capacitance, ESR.
M2 is the error amplifier transconductance gain.
Solve for CB2 as follows:
R
Z
OUT2 is the output impedance of the error amplifier and is 33 MΩ.
COMP2 is the impedance of the series RC network from COMP2
ESR × COUT2
CB2 =
to AGND.
CS2 is the current sense transconductance gain (the inductor
RC2
For low ESR output capacitance, such as with a ceramic capacitor,
B2 is optional. For optimal transient performance, RC2 and CC2
may need to be adjusted by observing the load transient response
of the ADP5071. For most applications, RC2 must be within the
range of 1 kΩ to 200 kΩ, and CC2 must be within the range of
1 nF to 68 nF.
G
current divided by the voltage at COMP2), which is internally
set by the ADP5071 and is 12.5 A/V.
C
ZOUT2 is the impedance of the load in parallel with the output
capacitor.
Rev. A | Page 21 of 27
ADP5071
Data Sheet
Figure 47 shows the schematic referenced by Table 9 through
Table 11 with example component values for +5 V to 15 V
generation. Table 9 shows the components common to all of the
COMMON APPLICATIONS
Table 9 through Table 11 list a number of common component
selections for typical VIN and VOUT conditions. These have been
bench tested and provide an off the shelf solution. Note that when
pairing a boost and inverting regulator bill of materials, choose
the same VIN and switching frequency. To optimize components
for an application, it is recommend to use the ADIsimPower
toolset.
V
IN and VOUT conditions.
Table 9. Recommended Common Components Selections
REF Value Part Number
CIN1 10 µF TMK316B7106KL-TD
Manufacturer
Taiyo Yuden
CVREG 1 µF
CVREF 1 μF
GRM188R71A105KA61D Murata
GRM188R71A105KA61D Murata
ADP5071
R
5.6kΩ
L1
3.3µH
SS
INBK
C1
V
+15V
D1
DFLS240
POS
COMP1
C
47nF
C1
SW1
FB1
EN1
R
FT1
2.43MΩ
C
OUT1
VREG
10µF
R
C
FB1
VREG
137kΩ
1µF
PVIN1
PVIN2
PVINSYS
V
+5V
IN
PGND
VREF
C
IN1
10µF
C
VREF
1µF
EN2
R
FB2
C
R
12kΩ
OUT2
C2
118kΩ
10µF
FB2
COMP2
R
FT2
C
C2
47nF
2.32MΩ
SYNC/FREQ
SLEW
SW2
V
NEG
D2
SEQ
–15V
AGND
DFLS240
L2
6.8µH
Figure 47. Typical +5 V to 15 V Application
Rev. A | Page 22 of 27
Data Sheet
ADP5071
Table 10. Recommended Boost Regulator Components
VIN VPOS Freq.
(V) (V) (MHz) (µH) Part
L1
L1, Coilcraft®
COUT1
(µF)
D1, Diodes,
Inc. Part
RFT1
(MΩ)
RFB1
(kΩ)
CC1
(nF)
RC1
(kΩ)
COUT1, Murata Part
3.3
3.3
3.3
3.3
3.3 15
3.3 15
3.3 24
3.3 24
3.3 34
3.3 34
5
5
5
5
5
5
5
5
5
5
9
9
1.2
2.4
1.2
2.4
1.2
2.4
1.2
2.4
1.2
2.4
1.2
2.4
1.2
2.4
1.2
2.4
1.2
2.4
1.2
2.4
2.2
1
XAL4020-222ME_
XAL4020-102ME_
XAL4020-222ME_
XAL4020-152ME_
XAL4030-332ME_
XAL4020-152ME_
XAL4030-332ME_
XAL4030-332ME_
XAL4030-472ME_
XAL4030-472ME_
XAL4030-332ME_
XAL4020-152ME_
XAL4030-332ME_
XAL4020-222ME_
XAL4030-472ME_
XAL4030-332ME_
XAL4030-472ME_
XAL4030-472ME_
XAL4030-682ME_
XAL4030-332ME_
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
GRM32ER71H106KA12L DFLS240L
GRM32ER71H106KA12L DFLS240L
GRM32ER71H106KA12L DFLS240
GRM32ER71H106KA12L DFLS240
GRM32ER71H106KA12L DFLS240
GRM32ER71H106KA12L DFLS240
GRM32ER71H106KA12L DFLS240
GRM32ER71H106KA12L DFLS240
GRM32ER71H106KA12L DFLS240
GRM32ER71H106KA12L DFLS240
GRM32ER71H106KA12L DFLS240
GRM32ER71H106KA12L DFLS240
GRM32ER71H106KA12L DFLS240
GRM32ER71H106KA12L DFLS240
GRM32ER71H106KA12L DFLS240
GRM32ER71H106KA12L DFLS240
GRM32ER71H106KA12L DFLS240
GRM32ER71H106KA12L DFLS240
GRM32ER71H106KA12L DFLS240
GRM32ER71H106KA12L DFLS240
0.604
0.604
1.24
1.24
2.43
2.43
3.09
3.09
4.22
4.22
1.24
1.24
2.43
2.43
3.09
3.09
4.22
4.22
3.09
3.09
115
115
121
121
137
137
107
107
102
102
121
121
137
137
107
107
102
102
107
107
47
47
47
47
47
47
47
47
47
47
47
47
47
47
47
47
47
47
47
47
4.7
4.7
3.3
3.3
14
14
18
18
33
2.2
1.5
3.3
1.5
3.3
3.3
4.7
4.7
3.3
1.5
3.3
2.2
4.7
3.3
4.7
4.7
6.8
3.3
33
9
9
1.8
2.2
5.6
8.2
10
10
12
12
4.7
4.7
15
15
24
24
34
34
24
24
12
12
Table 11. Recommended Inverting Regulator Components
VIN VNEG Freq.
L2
(MHz) (µH) L2, Coilcraft Part
COUT2
(µF)
D2, Diodes,
Inc. Part
RFT2
(MΩ)
RFB2
(kΩ)
CC2
(nF)
RC2
(kΩ)
(V) (V)
3.3 −5
3.3 −5
3.3 −9
3.3 −9
COUT2, Murata Part
1.2
2.4
1.2
2.4
3.3
2.2
4.7
2.2
4.7
2.2
4.7
3.3
6.8
4.7
6.8
3.3
6.8
3.3
10
XAL4030-332ME_
XAL4020-222ME_
XAL4030-472ME_
XAL4020-222ME_
XAL4030-472ME_
XAL4020-222ME_
XAL4030-472ME_
XAL4030-332ME_
XAL4030-682ME_
XAL4030-472ME_
XAL4030-682ME_
XAL4030-332ME_
XAL4030-682ME_
XAL4030-332ME_
XAL4040-103ME_
XAL4030-472ME_
XAL4040-103ME_
XAL4030-472ME_
XAL4040-153ME_
XAL4030-682ME_
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
10
GRM32ER71H106KA12L DFLS240L
GRM32ER71H106KA12L DFLS240L
GRM32ER71H106KA12L DFLS240
GRM32ER71H106KA12L DFLS240
GRM32ER71H106KA12L DFLS240
GRM32ER71H106KA12L DFLS240
GRM32ER71H106KA12L DFLS240
GRM32ER71H106KA12L DFLS240
GRM32ER71H106KA12L DFLS240
GRM32ER71H106KA12L DFLS240
GRM32ER71H106KA12L DFLS240
GRM32ER71H106KA12L DFLS240
GRM32ER71H106KA12L DFLS240
GRM32ER71H106KA12L DFLS240
GRM32ER71H106KA12L DFLS240
GRM32ER71H106KA12L DFLS240
GRM32ER71H106KA12L DFLS240
GRM32ER71H106KA12L DFLS240
GRM32ER71H106KA12L DFLS240
GRM32ER71H106KA12L DFLS240
1.15
1.15
1.62
1.62
2.32
2.32
3.16
3.16
4.99
4.99
1.62
1.62
2.32
2.32
3.16
3.16
4.99
4.99
3.16
3.16
158
158
133
133
118
118
102
102
115
115
133
133
118
118
102
102
115
115
102
102
47
47
47
47
47
47
47
47
47
47
47
47
68
47
47
47
47
47
47
47
8.2
8.2
10
15
18
18
39
47
33
33
5.6
5.6
12
12
27
27
39
39
15
15
3.3 −15 1.2
3.3 −15 2.4
3.3 −24 1.2
3.3 −24 2.4
3.3 −34 1.2
3.3 −34 2.4
5
5
−9
−9
1.2
2.4
5
5
5
5
5
5
12
12
−15 1.2
−15 2.4
−24 1.2
−24 2.4
−34 1.2
−34 2.4
−24 1.2
−24 2.4
4.7
10
4.7
15
6.8
Rev. A | Page 23 of 27
ADP5071
Data Sheet
SUPER LOW NOISE WITH OPTIONAL LDOS
Low dropout regulators (LDOs) can be added to the ADP5071
output to provide super low noise supplies for high performance
ADCs, digital-to-analog converters (DACs), and other precision
applications. Table 12 shows recommended companion devices,
and Figure 48 shows a typical application schematic for 15 V
generation from a +5 V supply.
ADP5071
R
5.6kΩ
L1
3.3µH
SS
INBK
C1
D1
COMP1
ADP7142
VIN VOUT
DFLS240
V
= +15V
POS
C
+16V
C
1µF
C1
SW1
FB1
47nF
R
20kΩ
C
1µF
EN1
FT3
NR3
IN3
R
C
FT1
2.15MΩ
OUT3
ADJ
(5V)
2.2µF
C
R
R
1kΩ
OUT1
10µF
FB3
NR3
VREG
R
10kΩ
C
FB1
VREG
EN
SS
113kΩ
1µF
PVIN1
PVIN2
PVINSYS
GND
V
IN
PGND
VREF
C
1nF
+5V
C
SS3
IN1
10µF
C
VREF
1µF
ADP7182
EN VOUT
V
= –15V
NEG
EN2
C
R
OUT2
10µF
FB2
R
R
FT4
52.3kΩ
C
C2
NR4
47µF
100kΩ
C
OUT4
12kΩ
FB2
2.2µF
ADJ
COMP2
R
R
FT2
2.1MΩ
R
5.9kΩ
FB4
NR4
C
C2
SYNC/FREQ
SLEW
5.9kΩ
–16V
47nF
SW2
VIN
GND
C
IN4
D2
DFLS240
SEQ
2.2µF
AGND
L2
6.8µH
Figure 48. Super Low Noise 15 V Generation with Post Regulation by the ADP7142 (+40 V, +200 mA, Low Noise LDO) and ADP7182 (−28 V, −200 mA, Low Noise LDO)
Table 12. Recommended LDOs for Super Low Noise Operation
Parameter
VIN Range
Fixed VOUT
Adjustable VOUT
IOUT
IQ at No Load
ISHDN Typical
Soft Start
PGOOD
ADP7102
3.3 V to 20 V
1.5 V to 9 V
1.22 V to 19 V
300 mA
400 µA
40 µA
No
Yes
ADP7104
3.3 V to 20 V
1.5 V to 9 V
1.22 V to 19 V
500 mA
400 µA
40 µA
No
Yes
ADP7105
3.3 V to 20 V
1.8 V, 3.3 V, 5 V
1.22 V to 19 V
500 mA
400 µA
40 µA
Yes
Yes
ADP7118
2.7 V to 20 V
1.2 V to 5 V
1.2 V to 19 V
200 mA
50 µA
2 µA
Yes
No
ADP7142
2.7 V to 40 V
1.2 V to 5 V
1.2 V to 39 V
200 mA
50 µA
2 µA
Yes
No
ADP7182
−2.7 V to −28 V
−1.8 V to −5 V
−1.22 V to−27 V
−200 mA
−33 µA
−2 µA
No
No
Noise (Fixed), 10 Hz 15 µV rms
to 100 kHz
15 µV rms
15 µV rms
11 µV rms
11 µV rms
18 µV rms
PSRR (100 kHz)
PSRR (1 MHz)
Package
60 dB
40 dB
8-lead LFCSP,
8-lead SOIC
60 dB
40 dB
8-lead LFCSP,
8-lead SOIC
60 dB
40 dB
8-lead LFCSP,
8-lead SOIC
68 dB
50 dB
6-lead LFCSP,
8-lead SOIC,
5-lead TSOT
68 dB
50 dB
6-lead LFCSP,
8-lead SOIC,
5-lead TSOT
45 dB
45 dB
6-lead LFCSP, 8-lead
LFCSP, 5-lead TSOT
Rev. A | Page 24 of 27
Data Sheet
ADP5071
SEPIC STEP-UP/STEP-DOWN OPERATION
SEPIC operation allows the positive output channel to produce
a voltage higher or lower than VIN. Both standalone and coupled
inductors are supported for this application. SEPIC designs are
supported in the ADIsimPower toolset.
ADP5071
SS
INBK
STANDALONE OR
L1A
L1B
D1
COUPLED-INDUCTOR
R
C1
COMP1
+5V/400mA
C
C1
SW1
FB1
EN1
C
S1
C
R
VREG
FT1
VREG
C
OUT1
R
FB1
1µF
PVIN1
V
= +12V
PVIN2
PVINSYS
IN
PGND
VREF
C
IN1
10µF
C
VREF
EN2
1µF
R
FB2
C
OUT2
R
C2
FB2
COMP2
R
FT2
C
C2
SYNC/FREQ
SLEW
SW2
–5V/400mA
D2
SEQ
AGND
L2
Figure 49. SEPIC Application for +12 V in to 5 V Output Generation
Rev. A | Page 25 of 27
ADP5071
Data Sheet
LAYOUT CONSIDERATIONS
Layout is important for all switching regulators but is particularly
important for regulators with high switching frequencies. To
achieve high efficiency, good regulation, good stability, and low
noise, a well-designed PCB layout is required. Follow these
guidelines when designing PCBs:
•
Keep the input bypass capacitor, CIN1, close to the PVIN1 pin,
the PVIN2 pin, and the PVINSYS pin. Route each of these
pins individually to the pad of this capacitor to minimize noise
coupling between the power inputs rather than connecting the
three pins at the device. A separate capacitor can be used on
the PVINSYS pin for the best noise performance.
•
•
Keep the high current paths as short as possible. These
paths include the connections between CIN1, L1, L2, D1,
D2, COUT1, COUT2, and PGND and their connections to
the ADP5071.
Keep AGND and PGND separate on the top layer of the
board. This separation avoids pollution of AGND with
switching noise. Do not connect PGND to the EPAD on
the top layer of the layout. Connect both AGND and PGND
to the board ground plane with vias. Ideally, connect PGND
to the plane at a point between the input and output
capacitors. Connect the EPAD on its own to this ground
layer with vias and connect AGND as near to the pin as
possible between the CVREF and CVREG capacitors.
Keep high current traces as short and wide as possible to
minimize parasitic series inductance, which causes spiking
and electromagnetic interference (EMI).
Figure 50. Suggested LFCSP Layout; Vias Connected to the PCB Ground
Plane, Not to Scale
•
•
Avoid routing high impedance traces near any node con-
nected to the SW1 and SW2 pins or near Inductors L1and
L2 to prevent radiated switching noise injection.
•
•
Place the feedback resistors as close to the FB1 and FB2 pins as
possible to prevent high frequency switching noise injection.
Place the top of the upper feedback resistors, RFT1 and RFT2,
or route traces to them from as close as possible to the top
of COUT1 and COUT2 for optimum output voltage sensing.
Place the compensation components as close as possible
to COMP1 and COMP2. Do not share vias to the ground
plane with the feedback resistors to avoid coupling high
frequency noise into the sensitive COMP1 and COMP2 pins.
Place the CVREF and CVREG capacitors as close to the
VREG and VREF pins as possible. Ensure that short traces
•
•
Figure 51. Suggested TSSOP Layout; Vias Connected to the PCB Ground
Plane, Not to Scale
are used between VREF and RFB2
.
Rev. A | Page 26 of 27
Data Sheet
ADP5071
OUTLINE DIMENSIONS
4.10
4.00 SQ
3.90
0.30
0.25
0.18
PIN 1
INDICATOR
PIN 1
INDICATOR
16
15
20
0.50
BSC
1
EXPOSED
PAD
2.75
2.60 SQ
2.35
11
5
6
BOTTOM VIEW
10
0.50
0.40
0.30
0.25 MIN
TOP VIEW
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.80
0.75
0.70
0.05 MAX
0.02 NOM
COPLANARITY
0.08
SECTION OF THIS DATA SHEET.
SEATING
PLANE
0.20 REF
COMPLIANT TO JEDEC STANDARDS MO-220-WGGD.
Figure 52. 20-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
4 mm × 4 mm Body, Very Very Thin Quad
(CP-20-8)
Dimensions shown in millimeters
4.25
4.20
4.15
6.60
6.50
6.40
20
11
3.05
3.00
2.95
4.50
4.40
4.30
EXPOSED
PAD
(Pins Up)
TOP
VIEW
6.40
BSC
1
10
BOTTOM VIEW
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.65 BSC
1.05
1.00
0.80
1.20 MAX
SECTION OF THIS DATA SHEET.
8°
0°
0.20
0.09
0.15
0.05
0.30
0.19
0.75
0.60
0.45
SEATING
PLANE
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-153-ACT
Figure 53. 20-Lead Thin Shrink Small Outline With Exposed Pad [TSSOP_EP]
(RE-20-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
ADP5071ACPZ
ADP5071ACPZ-R7
ADP5071AREZ
ADP5071AREZ-R7
ADP5071CP-EVALZ
ADP5071RE-EVALZ
Temperature Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Package Description
Package Option
20-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
20-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
20-Lead Thin Shrink Small Outline With Exposed Pad [TSSOP_EP]
20-Lead Thin Shrink Small Outline With Exposed Pad [TSSOP_EP]
Evaluation Board for the LFCSP_WQ
CP-20-8
CP-20-8
RE-20-1
RE-20-1
Evaluation Board for the TSSOP_EP
1 Z = RoHS Compliant Part.
©2015 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D12069-0-6/15(A)
Rev. A | Page 27 of 27
相关型号:
ADP5072CB-EVALZ
1 A/0.6 A DC to DC Switching Regulator Independent Positive and Negative Outputs
ADI
©2020 ICPDF网 联系我们和版权申明