ADRV9008BBCZ-1REEL_技术文档

Integrated Dual RF Receivers

ADRV9008-1

In addition to automatic gain control (AGC), the ADRV9008-1 also

features flexible external gain control modes, allowing dynamic

gain control.

Data Sheet

FEATURES

Dual receivers

Maximum receiver bandwidth: 200 MHz

Fully integrated, fractional-N, RF synthesizers

Fully integrated clock synthesizer

Multichip phase synchronization for RF LO and baseband clocks

JESD204B datapath interface

The received signals are digitized with a set of four, high dynamic

range, continuous time, sigma-delta (Σ-Δ) ADCs that provide

inherent antialiasing. The combination of the direct conversion

architecture (which does not suffer from out of band image

mixing) and the lack of aliasing reduces the requirements of the RF

filters compared to the requirements of traditional intermediate

frequency (IF) receivers.

Tuning range (center frequency): 75 MHz to 6000 MHz

APPLICATIONS

3G/4G/5G FDD, macrocell base stations

Wideband active antenna systems

Massive multiple input, multiple output (MIMO)

Phased array radar

Electronic warfare

Military communications

The fully integrated phase-locked loop (PLL) provides high

performance, low power, fractional-N, RF synthesis for the

receiver signal paths. An additional synthesizer generates the

clocks needed for the converters, digital circuits, and serial

interface. A multichip synchronization mechanism synchronizes

the phase of the RF local oscillator (LO) and baseband clocks

between multiple ADRV9008-1 chips. The ADRV9008-1 features

the isolation that high performance base station applications

require. All voltage controlled oscillators (VCOs) and loop

filter components are integrated.

Portable test equipment

GENERAL DESCRIPTION

The ADRV9008-1 is a highly integrated, dual radio frequency (RF),

agile receiver offering integrated synthesizers and digital signal

processing functions. The IC delivers a versatile combination of

high performance and low power consumption required by

3G/4G/5G macrocell, frequency division duplex (FDD), base

station applications.

The high speed JESD204B interface supports up to 12.288 Gbps

lane rates, resulting in a single lane per receiver in the widest

bandwidth mode. The interface also supports interleaved mode

for lower bandwidths, reducing the total number of high speed

data interface lanes to one. Both fixed and floating point data

formats are supported. The floating point format allows internal

AGC to be invisible to the demodulator device.

The receive path consists of two independent, wide bandwidth,

direct conversion receivers with state-of-the-art dynamic range.

The complete receive subsystem includes automatic and manual

attenuation control, dc offset correction, quadrature error

correction (QEC), and digital filtering, eliminating the need for

these functions in the digital baseband. RF front-end control and

several auxiliary functions, such as analog-to-digital converters

(ADCs), digital-to-analog converters (DACs), and general-purpose

input/outputs (GPIOs) for the power amplifier (PA), are also

integrated.

The core of the ADRV9008-1 can be powered directly from

1.3 V and 1.8 V regulators and is controlled via a standard 4-wire

serial port. Comprehensive power-down modes are included to

minimize power consumption during normal use. The

ADRV9008-1 is packaged in a 12 mm × 12 mm, 196-ball chip

scale ball grid array (CSP_BGA).

Rev. 0

Document Feedback

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rightsof third parties that may result fromits use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks andregisteredtrademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Technical Support

www.analog.com

ADRV9008-1

Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

Theory of Operation ...................................................................... 47

Receivers...................................................................................... 47

Clock Input.................................................................................. 47

Synthesizers................................................................................. 47

SPI................................................................................................. 47

JTAG Boundary Scan................................................................. 47

Power Supply Sequence............................................................. 47

GPIO_x Pins ............................................................................... 48

Auxiliary Converters.................................................................. 48

JESD204B Data Interface .......................................................... 48

Applications Information.............................................................. 49

PCB Layout and Power Supply Recommendations............... 49

PCB Material and Stackup Selection ....................................... 49

Fanout and Trace Space Guidelines......................................... 51

Component Placement and Routing Guidelines ................... 52

RF and JESD204B Transmission Line Layout ........................ 58

Isolation Techniques Used on the ADRV9008-1W/PCBZ... 60

RF Port Interface Information.................................................. 61

Outline Dimensions....................................................................... 68

Ordering Guide .......................................................................... 68

Applications....................................................................................... 1

General Description......................................................................... 1

Revision History ............................................................................... 2

Functional Block Diagram .............................................................. 3

Specifications..................................................................................... 4

Current and Power Consumption Specifications..................... 8

Timing Diagrams.......................................................................... 9

Absolute Maximum Ratings.......................................................... 10

Reflow Profile.............................................................................. 10

Thermal Management ............................................................... 10

Thermal Resistance .................................................................... 10

ESD Caution................................................................................ 10

Pin Configuration and Function Descriptions........................... 11

Typical Performance Characteristics ........................................... 17

75 MHz to 525 MHz Band ........................................................ 17

650 MHz to 3000 MHz Band.................................................... 25

3400 MHz to 4800 MHz Band.................................................. 33

5100 MHz to 5900 MHz Band.................................................. 40

Receiver Input Impedance......................................................... 45

Terminology .................................................................................... 46

REVISION HISTORY

9/2018—Revision 0: Initial Version

Rev. 0 | Page 2 of 68

Data Sheet

ADRV9008-1

FUNCTIONAL BLOCK DIAGRAM

ADRV9008-1

Rx2

RX1_IN+

SYNCIN0±

SYNCIN1±

Rx1

RX1_IN–

RX2_IN+

ADC

SERDOUT0±

SERDOUT1±

SERDOUT2±

SERDOUT3±

LPF

RX2_IN–

DIGITAL

PROCESSING

SYSREF_IN±

DECIMATION

pFIR

GP_INTERRUPT

RX1_ENABLE

RX2_ENABLE

RESET

TEST

SCLK

AGC

DC OFFSET

QEC

JESD204B

CIF/RIF

RF_EXT_LO_I/O+

RF_EXT_LO_I/O–

RF LO

SYNTHESIZER

Arm

Cortex-M3

CS

SDO

SDIO

GPIOs, AUXILIARY ADCs,

AND AUXILIARY DACs

REF_CLK_IN +

REF_CLK_IN –

CLOCK

GENERATION

GPIO_3p3_x

GPIO_x

AUXADC_x

Figure 1.

Rev. 0 | Page 3 of 68

ADRV9008-1

Data Sheet

SPECIFICATIONS

Electrical characteristics at VDDA1P3¹= 1.3 V, VDDD1P3_DIG = 1.3 V, T_J= full operating temperature range, and LO frequency (f_LO) =

1800 MHz, unless otherwise noted. The specifications in Table 1 are not de-embedded. Refer to the Typical Performance Characteristics

section for input/output circuit path loss. The device configuration profile for the 75 MHz to 525 MHz frequency range is as follows:

receiver = 50 MHz bandwidth (inphase quadrature (I/Q) rate = 61.44 MHz), JESD204B rate = 9.8304 GSPS, and device clock = 245.76 MHz.

Unless otherwise specified, the device configuration for all other frequency ranges is as follows: receiver = 200 MHz bandwidth (I/Q rate =

245.76 MHz), JESD204B rate = 9.8304 GSPS, and device clock = 245.76 MHz.

Table 1.

Parameter

Symbol Min

Typ

Max

Unit

Test Conditions/Comments

RECEIVERS

Center Frequency

Gain Range

Analog Gain Step

75

6000

MHz

dB

30

0.5

1

Attenuator steps from 0 dB to 6 dB

Attenuator steps from 6 dB to 30 dB

dB

Bandwidth Ripple

0.5

dB

200 MHz bandwidth, compensated by

programmable finite impulse response (FIR)

filter

0.2

dB

Any 20 MHz bandwidth span, compensated

by programmable FIR filter

Receiver (Rx) Bandwidth

Receiver Alias Band

Rejection

200

MHz

dB

80

Due to digital filters

Maximum Useable Input

Level

P_HIGH

0 dB attenuation, increases decibel

for decibel with attenuation, continuous

wave (CW) = 1800 MHz, corresponds to

−1 dBFS at ADC

−11

−10.2

−9.5

dBm

75 MHz < f ≤ 3000 MHz

3000 MHz < f ≤ 4800 MHz

4800 MHz < f ≤ 6000 MHz

0 dB attenuation, at receiver port

75 MHz < f ≤ 600 MHz

Noise Figure

Ripple

NF

11.5

12

13

15.2

1.8

dB

600 MHz < f ≤ 3000 MHz

3000 MHz < f ≤ 4800 MHz

4800 MHz < f ≤ 6000 MHz

At band edge maximum bandwidth mode

Input Third-Order Intercept

Point

IIP3

Difference Product

12

dBm

75 MHz < f ≤ 600 MHz, (P_HIGH− 12) dB per

tone; 600 MHz < f ≤ 6000 MHz, (P_HIGH− 10) dB

per tone; two tones near band edge

75 MHz < f ≤ 600 MHz, (P_HIGH− 12) dB per

tone; 600 MHz < f ≤ 6000 MHz, (P_HIGH− 10) dB

per tone; two tones at bandwidth/6 offset

from the LO

Sum Product

Third-Order Harmonic

Distortion

HD3

75 MHz < f ≤ 600 MHz, (P_HIGH− 6) dB; 600

MHz < f ≤ 6000 MHz, (P_HIGH− 4) dB; CW tone

at bandwidth/6 offset from the LO

−65

−66

−62

dBc

75 MHz < f ≤ 600 MHz

600 MHz < f ≤ 4800 MHz

4800 MHz < f ≤ 6000 MHz

Rev. 0 | Page 4 of 68

Data Sheet

ADRV9008-1

Parameter

Symbol Min

Typ

Max

Unit

Test Conditions/Comments

Second-Order Input

Intermodulation

Intercept Point

IIP2

62

dBm

75 MHz < f ≤ 600 MHz, (P_HIGH− 12) dB per

tone; 600 MHz < f ≤ 6000 MHz, (P_HIGH− 10) dB

per tone; 0 dB attenuation, complex

Image Rejection

75

dB

QEC active, within 200 MHz receiver

bandwidth

Input Impedance

Receiver to Receiver

Isolation

100

77

Ω

dB

Differential (see Figure 168)

75 MHz < f ≤ 600 MHz

65

61

dB

600 MHz < f ≤ 4800 MHz

4800 MHz < f ≤ 6000 MHz

Receiver Band Spurs

Referenced to RF Input at

Maximum Gain

−95

dBm

No more than one spur at this level per

10 MHz of receiver bandwidth

Receiver LO Leakage at

Receiver Input at

Maximum Gain

Leakage decreases decibel for decibel with

attenuation for first 12 dB

−70

−65

dBm

75 MHz < f ≤ 600 MHz

600 MHz < f ≤ 3000 MHz

3000 MHz < f ≤ 6000 MHz

LO SYNTHESIZER

LO Frequency Step

2.3

Hz

1.5 GHz to 2.8 GHz, 76.8 MHz phase

frequency detector (PFD) frequency

LO Spur

Integrated Phase Noise

75 MHz LO

1900 MHz LO

3800 MHz LO

−85

dBc

Excludes integer boundary spurs

2 kHz to 18 MHz

Narrow PLL loop bandwidth (50 kHz)

Wide PLL loop bandwidth (300 kHz)

0.014

0.2

0.36

0.54

°rms

5900 MHz LO

Spot Phase Noise

75 MHz LO

Narrow PLL loop bandwidth

10 kHz Offset

100 kHz Offset

1 MHz Offset

10 MHz Offset

1900 MHz LO

−126.5

−132.8

−150.1

−150.7

dBc/Hz

Narrow PLL loop bandwidth

100 kHz Offset

200 kHz Offset

400 kHz Offset

600 kHz Offset

800 kHz Offset

1.2 MHz Offset

1.8 MHz Offset

6 MHz Offset

−100

−115

−120

−129

−132

−135

−140

−150

−153

dBc/Hz

10 MHz Offset

3800 MHz LO

Wide PLL loop bandwidth

100 kHz Offset

1.2 MHz Offset

10 MHz Offset

5900 MHz LO

−104

−125

−145

dBc/Hz

100 kHz Offset

1.2 MHz Offset

10 MHz Offset

LO PHASE SYNCHRONIZATION

−99

−119.7

−135.4

dBc/Hz

Change in LO delay per temperature

change

Phase Deviation

1.6

ps/°C

Rev. 0 | Page 5 of 68

ADRV9008-1

Data Sheet

Parameter

Symbol Min

Typ

Max

Unit

Test Conditions/Comments

EXTERNAL LO INPUT

Input Frequency

f_EXTLO

300

0

8000

12

MHz

Input frequency must be 2× the desired LO

frequency

50 Ω matching at the source

f_EXTLO≤ 2 GHz, add 0.5 dBm/GHz above

2 GHz

f_EXTLO= 8 GHz

Input Signal Power

dBm

3

6

dBm

External LO Input Signal

Differential

To ensure adequate QEC

Phase Error

3.6

1

2

ps

dB

%

Amplitude Error

Duty Cycle Error

Even Order Harmonics

CLOCK SYNTHESIZER

Integrated Phase Noise

1966.08 MHz LO

Spot Phase Noise

1966.08 MHz

−50

dBc

1 kHz to 100 MHz

PLL optimized for close in phase noise

0.4

°rms

100 kHz Offset

1 MHz Offset

10 MHz Offset

−109

−129

−149

dBc/Hz

REFERENCE CLOCK

(REF_CLK_IN )

Frequency Range

Signal Level

10

0.3

1000

2.0

MHz

V p-p

AC-coupled, common-mode voltage (V_CM) =

618 mV, use <1 V p-p input clock for best

spurious performance

AUXILIARY CONVERTERS

ADC

Resolution

12

Bits

Input Voltage

Minimum

Maximum

0.05

V

VDDA_

3P3 −

0.05

DAC

Resolution

Output Voltage

Minimum

Maximum

10

Bits

Includes four offset levels

0.7

V

1 V V_REF

2.5 V V_REF

VDDA_

3P3 −

0.3

Output Drive Capability

10

mA

DIGITAL SPECIFICATIONS

(CMOS): SERIAL PERIPHERAL

INTERFACE (SPI), GPIO_x

Logic Inputs

Input Voltage

High Level

VDD_

INTERFACE

× 0.8

VDD_

INTERFACE

V

Low Level

0

VDD_

INTERFACE

× 0.2

Input Current

High Level

−10

+10

μA

Rev. 0 | Page 6 of 68

Data Sheet

ADRV9008-1

Parameter

Low Level

Symbol Min

Typ

Max

Unit

Test Conditions/Comments

−10

+10

μA

Logic Outputs

Output Voltage

High Level

VDD_

V

INTERFACE

× 0.8

Low Level

VDD_

V

INTERFACE

× 0.2

Drive Capability

3

mA

DIGITAL SPECIFICATIONS

(CMOS): GPIO_3p3_x

Logic Inputs

Input Voltage

High Level

VDDA_

3P3 × 0.8

0

VDDA_3P3

V

Low Level

VDDA_

3P3 × 0.2

Input Current

High Level

Low Level

−10

+10

μA

Logic Outputs

Output Voltage

High Level

VDDA_

V

3P3 × 0.8

Low Level

VDDA_

V

3P3 × 0.2

Drive Capability

4

mA

DIGITAL SPECIFICATIONS, LOW

VOLTAGE DIFFERENTIAL

SIGNALING (LVDS)

Logic Inputs (SYSREF_IN ,

SYNCINx )

Input Voltage Range

Input Differential Voltage

Threshold

825

−100

1675

+100

mV

Each differential input in the pair

Receiver Differential

Input Impedance

100

Ω

Internal termination enabled

SPI TIMING

See the UG-1295 for more information

SCLK Period

t_CP

t_MP

t_SC

20

10

3

ns

SCLK Pulse Width

CS Setup to First SCLK

Rising Edge

Last SCLK Falling Edge to CS t_HC

Hold

0

2

0

3

ns

SDIO Data Input Setup to

SCLK

t_S

SDIO Data Input Hold to

SCLK

t_H

SCLK Rising Edge to Output t_CO

Data Delay (3-Wire Mode

or 4-Wire Mode)

8

Bus Turnaround Time, Read

After Baseband Processor

(BBP) Drives Last Address

Bit

t_HZM

t_H

t_CO

ns

Rev. 0 | Page 7 of 68

ADRV9008-1

Data Sheet

Parameter

Symbol Min

Typ

Max

Unit

Test Conditions/Comments

Bus Turnaround Time, Read

After ADRV9008-1 Drives

Last Data Bit

t_HZS

0

t_CO

ns

JESD204B DATA OUTPUT

TIMING

AC-coupled

Unit Interval

Data Rate Per Channel (NRZ)

Rise Time

UI

81.38

3125

24

320

12288

ps

Mbps

ps

t_R

t_F

39.5

39.4

20% to 80% in 100 Ω load

AC-coupled

Fall Time

24

ps

Output Common-Mode

Voltage

V_CM

0

1.8

V

Differential Output Voltage

Short-Circuit Current

Differential Termination

Impedance

V_DIFF

I_DSHORT

360

−100

80

600

770

+100

120

mV

mA

Ω

94.2

Total Jitter

Uncorrelated Bounded

High Probability Jitter

Duty Cycle Distortion

SYSREF_IN Setup Time to

REF_CLK_IN

15.13

0.56

ps

Bit error rate (BER) = 10⁻¹⁵

UBHPJ

DCD

0.369

ps

ns

2.5

See Figure 2

SYSREF_IN Hold Time to

REF_CLK_IN

−1.5

ns

See Figure 2

Latency

t_{LAT_FRM}

REF_CLK_IN = 245.76 MHz

89.4

Clock

cycles

Receiver bandwidth = 200 MHz, IQ rate =

245.76 MHz, lane rate = 9830.4 MHz,

M = 2, L = 2, N = 16, S = 1

364.18

ns

¹VDDA1P3 refers to all analog 1.3 V supplies, including VDDA1P3_RF_SYNTH, VDDA1P3_BB, VDDA1P3_RX_RF, VDDA1P3_RF_VCO_LDO, VDDA1P3_RF_LO,

VDDA1P3_SER, VDDA1P3_CLOCK_SYNTH, VDDA1P3_CLOCK_VCO_LDO, VDDA1P3_AUX_SYNTH, and VDDA1P3_AUX_VCO_LDO.

CURRENT AND POWER CONSUMPTION SPECIFICATIONS

Table 2.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

SUPPLY CHARACTERISTICS

VDDA1P3¹Analog Supply

VDDD1P3_DIG Supply

VDDA1P8_AN Supply

VDDA1P8_BB Supply

VDD_INTERFACE Supply

VDDA_3P3 Supply

1.267

1.71

1.3

1.8

3.3

1.33

1.89

2.625

3.465

V

CMOS and LVDS supply, 1.8 V to 2.5 V nominal range

3.135

POSITIVE SUPPLY CURRENT

200 MHz Receiver Bandwidth

VDDA1P3¹Analog Supply

VDDD1P3_DIG Supply

VDDA1P8_AN Supply

VDDA1P8_BB Supply

VDD_INTERFACE Supply

VDDA_3P3 Supply

LO at 2600 MHz

Two receivers enabled

1645

984

0.4

68

8

3

mA

Receiver QEC active

No Auxiliary DAC x or AUXADC_x enabled (if enabled,

AUXADC_x adds 2.7 mA, and each Auxiliary DAC x

adds 1.5 mA)

Total Power Dissipation

3.57

W

Typical supply voltages, receiver QEC active

¹VDDA1P3 refers to all analog 1.3 V supplies, including VDDA1P3_RF_SYNTH, VDDA1P3_BB, VDDA1P3_RX_RF, VDDA1P3_RX, VDDA1P3_RF_VCO_LDO,

VDDA1P3_RF_LO, VDDA1P3_SER, VDDA1P3_CLOCK_SYNTH, VDDA1P3_CLOCK_VCO_LDO, VDDA1P3_AUX_SYNTH, and VDDA1P3_AUX_VCO_LDO.

Rev. 0 | Page 8 of 68

Data Sheet

ADRV9008-1

TIMING DIAGRAMS

AT DEVICE PINS

REF_CLK_IN± DELAY

IN REFERENCE TO SYSREF_IN±

AT DEVICE CORE

t’_Ht’_H

t_H

t_S

t’_S

REF_CLK_IN±

t_H= –1.5ns

t_S= +2.5ns

CLK DELAY = 2ns

t’_H= +0.5ns

t’_S= +0.5ns

NOTES

1. t_HAND t_SARE THE HOLD AND SETUP TIMES FOR THE REF_CLK_IN± PINS. t’_HAND t’_SREFER TO THE

DELAYED HOLD AND SETUP TIMES AT THE DEVICE CORE IN REFERENCE TO THE SYSREF_N± SIGNALS

DUE TO AN INTERNAL BUFFER THAT THE SIGNAL PASSES THROUGH.

Figure 2. SYSREF_IN Setup and Hold Timing

t_H

t_S

REF_CLK_IN±

SYSREF_IN±

t_H= –1.5ns

t_S= +2.5ns

VALID SYSREF

INVALID SYSREF

Figure 3. SYSREF_IN Setup and Hold Timing Examples, Relative to Device Clock

Rev. 0 | Page 9 of 68

ADRV9008-1

Data Sheet

ABSOLUTE MAXIMUM RATINGS

exposed die package to provide the customer with the most

Table 3.

effective method of controlling the die temperature. The exposed

die allows cooling of the die directly. Figure 4 shows the profile

view of the device mounted to a user printed circuit board (PCB)

and a heat sink (typically the aluminum case) to keep the junction

(exposed die) below the maximum junction temperature shown

in Table 3. The device is designed for a lifetime of 10 years when

operating at the maximum junction temperature.

Parameter

Rating

VDDA1P3¹to VSSA

VDDD1P3_DIG to VSSD

VDD_INTERFACE to VSSA

VDDA_3P3 to VSSA

−0.3 V to +1.4 V

−0.3 V to +3.0 V

−0.3 V to +3.9 V

−0.3 V to VDD_

INTERFACE + 0.3 V

VDD_INTERFACE Logic Inputs and

Outputs to VSSD

JESD204B Logic Outputs to VSSA

Input Current to Any Pin Except

Supplies

Maximum Input Power into RF Port

Maximum Junction Temperature

Storage Temperature Range

−0.3 V to VDDA1P3_SER

10 mA

THERMAL RESISTANCE

θ_JAis specified for the worst-case conditions, that is, a device

soldered in a circuit board for surface-mount packages. Thermal

resistance data for the ADRV9008-1 mounted on both a JEDEC

2S2P test board and a 10-layer Analog Devices, Inc., evaluation

board is listed in Table 4. Do not exceed the absolute maximum

junction temperature rating in Table 3. Ten-layer PCB entries

refer to the 10-layer Analog Devices evaluation board, which

more accurately reflects the PCB used in customer applications.

23 dBm (peak)

110°C

−65°C to +150°C

¹VDDA1P3 refers to all analog 1.3 V supplies, including VDDA1P3_RF_SYNTH,

VDDA1P3_BB, VDDA1P3_RX_RF, VDDA1P3_RX, VDDA1P3_RF_VCO_LDO,

VDDA1P3_RF_LO, VDDA1P3_CLOCK_SYNTH, VDDA1P3_CLOCK_SYNTH, and

VDDA1P3_CLOCK_VCO_LDO.

Stresses at or above those listed under Absolute Maximum

Ratings may cause permanent damage to the product. This is a

stress rating only; functional operation of the product at these

or any other conditions above those indicated in the operational

section of this specification is not implied. Operation beyond

the maximum operating conditions for extended periods may

affect product reliability.

Table 4. Thermal Resistance^{1, 2}

Package Type

θ_JA

θ_{JC_TOP}

θ_JB

Ψ_JT

Ψ_JB

Unit

BC-196-13

21.1

0.04

4.9

0.3

4.9

°C/W

¹For the θ_JCtest, 100 µm thermal interface material (TIM) is used. TIM is

assumed to have 3.6 thermal conductivity watts/(meter × Kelvin).

²Using enhanced heat removal techniques such as PCB, heat sink, and airflow

improves the thermal resistance values.

REFLOW PROFILE

ESD CAUTION

The ADRV9008-1 reflow profile is in accordance with the

JEDEC JESD204B criteria for Pb-free devices. The maximum

reflow temperature is 260°C.

THERMAL MANAGEMENT

The ADRV9008-1 is a high power device that can dissipate over

3 W depending on the user application and configuration.

Because of the power dissipation, the ADRV9008-1 uses an

CUSTOMER CASE (HEAT SINK)

CUSTOMER THERMAL FILLER

SILICON (DIE)

IC PROFILE

PACKAGE SUBSTRATE

CUSTOMER PCB

Figure 4. Typical Thermal Management Solution

Rev. 0 | Page 10 of 68

Data Sheet

ADRV9008-1

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

1

2

3

4

5

6

7

8

9

10

11

12

13

14

A

B

C

D

E

F

VSSA

RX2_IN+

RX2_IN–

VSSA

RX1_IN+

RX1_IN–

VSSA

VDDA1P3_

RX_RF

RF_EXT_

LO_I/O–

RF_EXT_

LO_I/O+

VSSA

VDDA_3P3

VSSA

VDDA1P3_

AUX_VCO_

LDO

VDDA1P3_ VDDA1P3_RF_ VDDA1P1_

RF_VCO_LDO VCO_LDO

VDDA1P3_

RF_LO

RF_VCO

VSSA

GPIO_3p3_0 GPIO_3p3_3 VDDA1P3_RX

GPIO_3p3_9

RBIAS

VDDA1P1_

AUX_VCO

GPIO_3p3_1 GPIO_3p3_4

VSSA

TEST

VSSA

GPIO_3p3_8 GPIO_3p3_10

AUX_SYNTH_

OUT

GPIO_3p3_2 GPIO_3p3_5 GPIO_3p3_6 VDDA1P8_BB VDDA1P3_BB

REF_CLK_IN+

VSSA

AUXADC_3 VDDA1P8_AN GPIO_3p3_7 GPIO_3p3_11

REF_CLK_IN–

VSSA

DNC

VSSA

AUXADC_0

VSSA

AUXADC_1

VSSA

SDO

AUXADC_2

VSSA

DNC

VDDA1P3_

CLOCK_

SYNTH

VDDA1P3_

RF_SYNTH

RF_SYNTH_

VTUNE

VDDA1P3_

AUX_SYNTH

G

H

J

VSSA

SDIO

SCLK

GPIO_12

GPIO_13

GPIO_14

GPIO_15

GPIO_16

GPIO_11

GPIO_10

GPIO_9

GPIO_8

GP_

INTERRUPT

DNC

GPIO_18

RESET

DNC

GPIO_2

GPIO_1

GPIO_0

K

L

VSSA

SYSREF_IN+ SYSREF_IN–

GPIO_5

GPIO_6

GPIO_4

GPIO_7

VSSD

CS

VSSA

GPIO_3

VSSD

VDDD1P3_

DIG

VDDA1P3_

SER

VDDA1P3_

SER

VDDD1P3_

DIG

SYNCIN1–

SYNCIN0–

SYNCIN1+

SYNCIN0+

VSSD

GPIO_17

VDDA1P1_

CLOCK_VCO

VDD_

INTERFACE

VDDA1P3_

SER

VDDA1P3_

SER

M

N

P

RX1_ENABLE

RX2_ENABLE

VSSA

VSSD

VDDA1P3_

CLOCK_

VCO_LDO

VDDA1P3_

SER

VDDA1P3_

SER

VDDA1P3_

SER

VDDA1P3_

SER

VDDA1P3_

SER

VDDA1P3_

SER

SERDOUT3– SERDOUT3+ SERDOUT2– SERDOUT2+

VSSA

AUX_SYNTH_

VTUNE

VDDA1P3_

SER

VDDA1P3_

SER

VDDA1P3_

SER

VDDA1P3_

SER

VDDA1P3_

SER

VDDA1P3_

SER

SERDOUT0+

VSSA

SERDOUT1– SERDOUT1+ SERDOUT0–

VSSA

ADRV9008-1

Figure 5. Pin Configuration

Table 5. Pin Function Descriptions

Pin No.

Type

Mnemonic

Description

Analog Supply Voltage (V_SS).

A1 to A4, A7, A8, A11 to A14, B2

to B6, B9 to B14, C4, C9, C11,

D3 to D9, D11, D12, E6, E9, F1,

F2, F5 to F10, F12 to F14, G1

to G4, G6, G10 to G14, H2 to

H10, H13, J2, J13, K1, K2, K13,

K14, L1, L2, M2, M9, N2, N7,

N14, P2, P3, P10

Input

VSSA

Rev. 0 | Page 11 of 68

ADRV9008-1

Data Sheet

Pin No.

Type

Mnemonic

Description

A5, A6

Input

RX2_IN+, RX2_IN−

Differential Input for Receiver 1. When unused, connect these

pins to ground.

A9, A10

Input

RX1_IN+, RX1_IN−

VDDA1P3_RX_RF

RF_EXT_LO_I/O−,

RF_EXT_LO_I/O+

Differential Input for Receiver 2. When unused, connect these

pins to ground.

Receiver Mixer Supply.

Differential External LO Input/Output. If these pins are used

for external LO, the input frequency must be 2× the desired

carrier frequency. When unused, do not connect these pins.

B1

B7, B8

Input

C1

C2

Input/

output

GPIO_3p3_0

GPIO Pin Referenced to 3.3 V Supply. The alternate function is

Auxiliary DAC 4. Because this pin contains an input stage, the

voltage on the pin must be controlled. When unused, this pin

can be tied to ground through a resistor to safeguard against

misconfiguration, or this pin can be left floating, programmed as

an output, and driven low.

GPIO Pin Referenced to 3.3 V Supply. Because this pin contains

an input stage, the voltage on the pin must be controlled. When

unused, this pin can be tied to ground through a resistor to

safeguard against misconfiguration, or this pin can be left

floating, programmed as an output, and driven low.

Input/

output

GPIO_3p3_3

C3

Input

VDDA1P3_RX

1.3 V Supply for Receiver Baseband Circuits, Transimpedance

Amplifier (TIA), Baseband Filters, and Auxiliary DACs.

RF VCO Low Dropout (LDO) Supply Inputs. Connect Pin C5 to

Pin C6. Use a separate trace to a common supply point.

C5, C6

VDDA1P3_RF_VCO_LDO

C7

C8

Input

VDDA1P1_RF_VCO

VDDA1P3_RF_LO

1.1 V VCO Supply. Decouple this pin with 1 µF.

1.3 V LO Generator for RF Synthesizer. This pin is sensitive to

aggressors.

C10

C12

Input

VDDA1P3_AUX_VCO_LDO

VDDA_3P3

1.3 V Supply.

General-Purpose Output Pull-Up Voltage and Auxiliary DAC

Supply Voltage.

C13

Input/

output

GPIO_3p3_9

GPIO Pin Referenced to 3.3 V Supply. The alternative function

is Auxiliary DAC 9. Because this pin contains an input stage,

the voltage on the pin must be controlled. When unused, this

pin can be tied to ground through a resistor to safeguard

against misconfiguration, or this pin can be left floating,

programmed as an output, and driven low.

C14

D1

Input/

output

RBIAS

Bias Resistor. Tie this pin to ground using a 14.3 kΩ resistor.

This pin generates an internal current based on an external

1% resistor.

GPIO Pin Referenced to 3.3 V Supply. The alternative function

is Auxiliary DAC 5. Because this pin contains an input stage,

the voltage on the pin must be controlled. When unused, this

pin can be tied to ground through a resistor to safeguard

against misconfiguration, or this pin can be left floating,

programmed as an output, and driven low.

Input/

output

GPIO_3p3_1

D2

Input/

output

GPIO_3p3_4

GPIO Pin Referenced to 3.3 V Supply. The alternative function

is Auxiliary DAC 6. Because this pin contains an input stage,

the voltage on the pin must be controlled. When unused, this

pin can be tied to ground through a resistor to safeguard

against misconfiguration, or this pin can be left floating,

programmed as an output, and driven low.

D10

D13

Input

Input/

output

VDDA1P1_AUX_VCO

GPIO_3p3_8

1.1 V VCO Supply. Decouple with 1 µF.

GPIO Pin Referenced to 3.3 V Supply. The alternative function

is Auxiliary DAC 1. Because this pin contains an input stage,

the voltage on the pin must be controlled. When unused, this

pin can be tied to ground through a resistor to safeguard

against misconfiguration, or this pin can be left floating,

programmed as an output, and driven low.

Rev. 0 | Page 12 of 68

Data Sheet

ADRV9008-1

Pin No.

Type

Mnemonic

Description

D14

Input/

output

GPIO_3p3_10

GPIO Pin Referenced to 3.3 V Supply. The alternative function

is Auxiliary DAC 0. Because this pin contains an input stage,

the voltage on the pin must be controlled. When unused, this

pin can be tied to ground through a resistor to safeguard

against misconfiguration, or this pin can be left floating,

programmed as an output, and driven low.

E1

E2

Input/

output

GPIO_3p3_2

GPIO_3p3_5

GPIO Pin Referenced to 3.3 V Supply. Because this pin contains

an input stage, the voltage on the pin must be controlled.

When unused, this pin can be tied to ground through a resistor

to safeguard against misconfiguration, or this pin can be left

floating, programmed as an output, and driven low.

GPIO Pin Referenced to 3.3 V Supply. The alternative function

is Auxiliary DAC 7. Because this pin contains an input stage,

the voltage on the pin must be controlled. When unused, this

pin can be tied to ground through a resistor to safeguard

against misconfiguration, or this pin can be left floating,

programmed as an output, and driven low.

Input/

output

E3

Input/

output

GPIO_3p3_6

GPIO Pin Referenced to 3.3 V Supply. The alternative function

is Auxiliary DAC 8. Because this pin contains an input stage,

the voltage on the pin must be controlled. When unused, this

pin can be tied to ground through a resistor to safeguard

against misconfiguration, or this pin can be left floating,

programmed as an output, and driven low.

E4

E5

E7, E8

Input

VDDA1P8_BB

VDDA1P3_BB

REF_CLK_IN+, REF_CLK_IN−

1.8 V Supply for the ADC and DAC.

1.3 V Supply for the ADC, DAC, and Auxiliary ADCs.

Device Clock Differential Input.

E10

Output AUX_SYNTH_OUT

Auxiliary PLL Output. When unused, do not connect this pin.

E11, F3, F4, F11

Input

AUXADC_0 to AUXADC_3

Auxiliary ADC Input. When unused, connect these pins to ground

with a pull-down resistor, or connect directly to ground.

E12

E13

Input

Input/

output

VDDA1P8_AN

GPIO_3p3_7

1.8 V Bias Supply for Analog Circuitry.

GPIO Pin Referenced to 3.3 V Supply. The alternative function

is Auxiliary DAC 2. Because this pin contains an input stage,

the voltage on the pin must be controlled. When unused, this

pin can be tied to ground through a resistor to safeguard

against misconfiguration, or this pin can be left floating,

programmed as an output, and driven low.

E14

Input/

output

GPIO_3p3_11

GPIO Pin Referenced to 3.3 V Supply. The alternative function

is Auxiliary DAC 3. Because this pin contains an input stage,

the voltage on the pin must be controlled. When unused, this

pin can be tied to ground through a resistor to safeguard

against misconfiguration, or this pin can be left floating,

programmed as outputs, and driven low.

G5

G7

Input

VDDA1P3_CLOCK_SYNTH

VDDA1P3_RF_SYNTH

VDDA1P3_AUX_SYNTH

1.3 V Supply Input for Clock Synthesizer. Use a separate trace

on the PCB back to a common supply point.

1.3 V RF Synthesizer Supply Input. This pin is sensitive to

aggressors.

1.3 V Auxiliary Synthesizer Supply Input.

RF Synthesizer V_TUNEOutput.

Do Not Connect. Do not connect these pins.

Digital GPIO, 1.8 V to 2.5 V. Because this pin contains an input

stage, the voltage on the pin must be controlled. When

unused, this pin can be tied to ground through a resistor to

safeguard against misconfiguration, or it can be left floating,

programmed as an output, and driven low.

G8

G9

Output RF_SYNTH_VTUNE

DNC¹

Input/

output

H1, J1, H14, J14

H11

DNC

GPIO_12

H12

Input/

output

GPIO_11

Digital GPIO, 1.8 V to 2.5 V. Because this pin contains an input

stage, the voltage on the pin must be controlled. When

unused, this pin can be tied to ground through a resistor to

safeguard against misconfiguration, or it can be left floating,

programmed as an output, and driven low.

Rev. 0 | Page 13 of 68

ADRV9008-1

Data Sheet

Pin No.

Type

Mnemonic

Description

J3

Input/

output

GPIO_18

Digital GPIO, 1.8 V to 2.5 V. The joint test action group (JTAG)

function is test clock (TCLK). Because this pin contains an input

stage, the voltage on the pin must be controlled. When

unused, this pin can be tied to ground through a resistor to

safeguard against misconfiguration, or it can be left floating,

programmed as an output, and driven low.

J4

J5

Input

RESET

Active Low Chip Reset.

Output GP_INTERRUPT

General-Purpose Digital Interrupt Output Signal. When

unused, do not connect this pin.

J6

J7

Input

TEST

Pin Used for JTAG Boundary Scan. When unused, connect this

pin to ground.

Input/

output

GPIO_2

Digital GPIO, 1.8 V to 2.5 V. The user sets the JTAG function to

0. Because this pin contains an input stage, the voltage on the

pin must be controlled. When unused, this pin can be tied to

ground through a resistor to safeguard against misconfiguration,

or it can be left floating, programmed as an output, and

driven low.

J8

J9

Input/

output

GPIO_1

SDIO

Digital GPIO, 1.8 V to 2.5 V. The user sets the JTAG function to 0.

Because this pin contains an input stage, the voltage on the pin

must be controlled. When unused, this pin can be tied to ground

through a resistor to safeguard against misconfiguration, or it can

be left floating, programmed as an output, and driven low.

Input/

output

Serial Data Input in 4-Wire Mode or Input/Output in 3-Wire

Mode.

J10

J11

Output SDO

Serial Data Output. In SPI 3-Wire mode, do not connect this pin.

Input/

GPIO_13

Digital GPIO, 1.8 V to 2.5 V. Because this pin contains an input

stage, the voltage on the pin must be controlled. When

unused, this pin can be tied to ground through a resistor to

safeguard against misconfiguration, or it can be left floating,

programmed as an output, and driven low.

output

J12

Input/

output

GPIO_10

Digital GPIO, 1.8 V to 2.5 V. Because this pin contains an input

stage, the voltage on the pin must be controlled. When

unused, this pin can be tied to ground through a resistor to

safeguard against misconfiguration, or it can be left floating,

programmed as an output, and driven low.

K3, K4

K5

Input

Input/

output

SYSREF_IN+, SYSREF_IN−

GPIO_5

LVDS Input.

Digital GPIO, 1.8 V to 2.5 V. The JTAG function is test data

output (TDO). Because this pin contains an input stage, the

voltage on the pin must be controlled. When unused, this pin

can be tied to ground through a resistor to safeguard against

misconfiguration, or it can be left floating, programmed as an

output, and driven low.

K6

Input/

output

GPIO_4

Digital GPIO, 1.8 V to 2.5 V. The JTAG function is test rest (TRST).

Because this pin contains an input stage, the voltage on the

pin must be controlled. When unused, this pin can be tied to

ground through a resistor to safeguard against

misconfiguration, or it can be left floating, programmed as an

output, and driven low.

K7

K8

Input/

output

GPIO_3

GPIO_0

Digital GPIO, 1.8 V to 2.5 V. The user sets the JTAG function to 1.

Because this pin contains an input stage, the voltage on the pin

must be controlled. When unused, this pin can be tied to ground

through a resistor to safeguard against misconfiguration, or it can

be left floating, programmed as an output, and driven low.

Digital GPIO, 1.8 V to 2.5 V. The user sets the JTAG function to 1.

Because this pin contains an input stage, the voltage on the pin

must be controlled. When unused, this pin can be tied to ground

through a resistor to safeguard against misconfiguration, or it can

be left floating, programmed as an output, and driven low.

Input/

output

K9

K10

Input

SCLK

CS

Serial Data Bus Clock.

Serial Data Bus Chip Select, Active Low.

Rev. 0 | Page 14 of 68

Data Sheet

ADRV9008-1

Pin No.

Type

Mnemonic

Description

K11

Input/

output

GPIO_14

Digital GPIO, 1.8 V to 2.5 V. Because this pin contains an input

stage, the voltage on the pin must be controlled. When

unused, this pin can be tied to ground through a resistor to

safeguard against misconfiguration, or it can be left floating,

programmed as an output, and driven low.

K12

Input/

output

GPIO_9

Digital GPIO, 1.8 V to 2.5 V. Because this pin contains an input

stage, the voltage on the pin must be controlled. When

unused, this pin can be tied to ground through a resistor to

safeguard against misconfiguration, or it can be left floating,

programmed as an output, and driven low.

L3, L4

L5

Input

SYNCIN1−, SYNCIN1+

GPIO_6

LVDS Input. When unused, connect these pins to ground with a

pull-down resistor, or connect directly to ground.

Input/

output

Digital GPIO, 1.8 V to 2.5 V. The JTAG function is test data input

(TDI). Because this pin contains an input stage, the voltage on

the pin must be controlled. When unused, this pin can be tied

to ground through a resistor to safeguard against

misconfiguration, or it can be left floating, programmed as an

output, and driven low.

L6

Input/

output

GPIO_7

Digital GPIO, 1.8 V to 2.5 V. The JTAG function is test mode

select input (TMS). Because this pin contains an input stage,

the voltage on the pin must be controlled. When unused, this

pin can be tied to ground through a resistor to safeguard

against misconfiguration, or it can be left floating, programmed

as an output, and driven low.

L7, L10, M6, M8

L8, L9

Input

VSSD

VDDD1P3_DIG

Digital V_SS.

1.3 V Digital Core. Connect Pin L8 to Pin L9. Use a separate

trace to a common supply point.

L11

Input/

output

GPIO_15

Digital GPIO, 1.8 V to 2.5 V. Because this pin contains an input

stage, the voltage on the pin must be controlled. When

unused, this pin can be tied to ground through a resistor to

safeguard against misconfiguration, or it can be left floating,

programmed as an output, and driven low.

L12

Input/

output

GPIO_8

Digital GPIO, 1.8 V to 2.5 V. Because this pin contains an input

stage, the voltage on the pin must be controlled. When

unused, this pin can be tied to ground through a resistor to

safeguard against misconfiguration, or it can be left floating,

programmed as an output, and driven low.

L13, L14, M13, M14, N8 to N13,

P8, P9, P11 to P14

Input

VDDA1P3_SER

1.3 V Supply for JESD204B Serializer.

M1

M3, M4

Input

VDDA1P1_CLOCK_VCO

SYNCIN0−, SYNCIN0+

1.1 V VCO Supply. Decouple this pin with 1 µF.

JESD204B Receiver Channel 0. These pins form the synchro-

nization signal associated with receiver channel data on the

JESD204B interface. When unused, connect these pins to ground

with a pull-down resistor, or connect directly to ground.

M5

Input

RX1_ENABLE

RX2_ENABLE

GPIO_17

Receiver 1 Enable Pin. When unused, connect this pin to ground

with a pull-down resistor, or connect directly to ground.

Receiver 2 Enable Pin. When unused, connect this pin to ground

with a pull-down resistor, or connect directly to ground.

Digital GPIO, 1.8 V to 2.5 V. Because this pin contains an input

stage, the voltage on the pin must be controlled. When

unused, this pin can be tied to ground through a resistor to

safeguard against misconfiguration, or it can be left floating,

programmed as an output, and driven low.

M7

M10

Input/

output

M11

Input/

output

GPIO_16

Digital GPIO, 1.8 V to 2.5 V. Because this pin contains an input

stage, the voltage on the pin must be controlled. When

unused, this pin can be tied to ground through a resistor to

safeguard against misconfiguration, or it can be left floating,

programmed as an output, and driven low.

M12

N1

Input

VDD_INTERFACE

Input/Output Interface Supply, 1.8 V to 2.5 V.

VDDA1P3_CLOCK_VCO_LDO 1.3 V Supply. Use a separate trace to a common supply point.

Rev. 0 | Page 15 of 68

ADRV9008-1

Data Sheet

Pin No.

Type

Mnemonic

Description

N3, N4

Output SERDOUT3−, SERDOUT3+

RF Current Mode Logic (CML) Differential Output 3. When

unused, do not connect these pins.

N5, N6

Output SERDOUT2−, SERDOUT2+

RF CML Differential Output 2. When unused, do not connect

these pins.

P1

Output AUX_SYNTH_VTUNE

Auxiliary Synthesizer V_TUNEOutput.

P4, P5

Output SERDOUT1−, SERDOUT1+

RF CML Differential Output 1. When unused, do not connect

these pins.

P6, P7

Output SERDOUT0−, SERDOUT0+

RF CML Differential Output 0. When unused, do not connect

these pins.

¹DNC means do not connect.

Rev. 0 | Page 16 of 68

Data Sheet

ADRV9008-1

TYPICAL PERFORMANCE CHARACTERISTICS

The temperature settings refer to the die temperature.

75 MHz TO 525 MHz BAND

0

45

40

35

30

25

20

15

10

5

–10

+110°C

+25°C

–40°C

+110°C

+25°C

–40°C

–20

–30

–40

–50

–60

–70

–80

–90

–100

0

75

125

175

225

275

325

375

425

475

525

0

2

4

6

8

10

12

14

16

18

20

RECEIVER LO FREQUENCY (MHz)

RECEIVER ATTENUATION (dB)

Figure 6. Receiver LO Leakage vs. Receiver LO Frequency, 75 MHz, 300 MHz,

525 MHz; Receiver Attenuation = 0 dB, RF Bandwidth = 50 MHz,

Sample Rate = 61.44 MSPS

Figure 9. Receiver Noise Figure vs. Receiver Attenuation, LO = 525 MHz,

RF Bandwidth = 50 MHz, Sample Rate = 61.44 MSPS,

Integration Bandwidth = 1 MHz to 25 MHz

45

20

18

40

+110°C

+25°C

–40°C

+25°C

–40°C

16

35

14

30

25

20

15

10

5

12

10

8

6

4

2

0

75

0

2

4

6

8

10

12

14

16

18

20

175

275

375

475

RECEIVER ATTENUATION (dB)

RECEIVER LO FREQUENCY (MHz)

Figure 7. Receiver Noise Figure vs. Receiver Attenuation, LO = 75 MHz,

RF Bandwidth = 50 MHz, Sample Rate = 61.44 MSPS,

Integration Bandwidth = 1 MHz to 25 MHz

Figure 10. Receiver Noise Figure vs. Receiver LO Frequency, Receiver

Attenuation = 0 dB, RF Bandwidth = 50 MHz, Sample Rate = 61.44 MSPS,

Integration Bandwidth = 25 MHz

45

20

40

+110°C

+25°C

–40°C

+110°C

+25°C

–40°C

18

16

14

12

10

8

35

30

25

20

15

10

5

0

2

4

6

8

10

12

14

16

18

20

–25

–15

–5

5

15

25

RECEIVER ATTENUATION (dB)

RECEIVER OFFSET FREQUENCY FROM LO (75MHz)

Figure 8. Receiver Noise Figure vs. Receiver Attenuation, LO = 300 MHz,

RF Bandwidth = 50 MHz, Sample Rate = 61.44 MSPS,

Integration Bandwidth = 1 MHz to 25 MHz

Figure 11. Receiver Noise Figure vs. Receiver Offset Frequency from LO,

Integration Bandwidth = 200 kHz, LO = 75 MHz

Rev. 0 | Page 17 of 68

ADRV9008-1

Data Sheet

20

18

16

14

12

10

8

110

100

90

+110°C

+25°C

–40°C

80

70

+110°C (SUM)

+25°C (SUM)

–40°C (SUM)

+110°C (DIFF)

+25°C (DIFF)

–40°C (DIFF)

60

50

0

2

4

6

8

10 12 14 16 18 20 22 24 26 28 30

–25

–15

–5

5

15

25

RECEIVER ATTENUATION (dB)

RECEIVER OFFSET FREQUENCY FROM LO (300MHz)

Figure 15. Receiver IIP2 vs. Receiver Attenuation, LO = 300 MHz, Tones Placed

at 310 MHz and 311 MHz, −23.5 dBm Plus Attenuation

Figure 12. Receiver Noise Figure vs. Receiver Offset Frequency from LO,

Integration Bandwidth = 200 kHz, LO = 300 MHz

80

75

70

65

20

+110°C

+25°C

–40°C

18

16

14

12

10

8

60

+110°C (SUM)

+25°C (SUM)

–40°C (SUM)

+110°C (DIFF)

+25°C (DIFF)

–40°C (DIFF)

55

50

45

40

–25

–15

–5

5

15

25

80.0

81.0

82.5

83.5

87.5

88.5

90.0

91.0

92.5

93.5

75

95.0

96.0

97.5

98.5

100.0 102.5

101.0 103.5

RECEIVER OFFSET FREQUENCY FROM LO (525MHz)

SWEPT PASS BAND FREQUENCY (MHz)

Figure 13. Receiver Noise Figure vs. Receiver Offset Frequency from LO,

Integration Bandwidth = 200 kHz, LO = 525 MHz

Figure 16. Receiver IIP2 Sum and Difference Across Bandwidth vs. Swept Pass

Band Frequency, Receiver Attenuation = 0 dB, LO = 75 MHz, 10 Tone Pairs,

−23.5 dBm Each

100

95

90

85

80

75

80

75

70

65

60

+110°C (SUM)

70

+25°C (SUM)

–40°C (SUM)

+110°C (DIFF)

+25°C (DIFF)

–40°C (DIFF)

55

50

45

40

+110°C (SUM)

+25°C (SUM)

–40°C (SUM)

+110°C (DIFF)

+25°C (DIFF)

–40°C (DIFF)

65

60

55

50

0

2

4

6

8

10 12 14 16 18 20 22 24 26 28 30

305.0 307.5 310.0 312.5 315.0 317.5 320.0 322.5 325.0 327.5

306.0 308.5 311.0 313.5 316.0 318.5 321.0 323.5 326.0 328.5

300

RECEIVER ATTENUATION (dB)

SWEPT PASS BAND FREQUENCY (MHz)

Figure 14. Receiver IIP2 vs. Receiver Attenuation, LO = 75 MHz,

Tones Placed at 82.5 MHz and 83.5 MHz, −23.5 dBm Plus Attenuation

Figure 17. Receiver IIP2 Sum and Difference Across Bandwidth vs. Swept Pass

Band Frequency, Receiver Attenuation = 0 dB, LO = 300 MHz, 10 Tone pairs,

−23.5 dBm Each

Rev. 0 | Page 18 of 68

Data Sheet

ADRV9008-1

110

25

20

15

10

5

Rx1 (SUM) = +110°C

Rx1 (DIFF) = +110°C

Rx1 (SUM) = +25°C

Rx1 (DIFF) = +25°C

Rx1 (SUM) = –40°C

Rx1 (DIFF) = –40°C

100

90

80

70

60

50

Rx1 = +110°C

Rx1 = +25°C

Rx1 = –40°C

Rx2 = +110°C

Rx2 = +25°C

Rx2 = –40°C

Rx2 (SUM) = +110°C

Rx2 (DIFF) = +110°C

Rx2 (SUM) = +25°C

Rx2 (DIFF) = +25°C

Rx2 (SUM) = –40°C

Rx2 (DIFF) = –40°C

0

5

10

15

20

25

30

305.0 307.5 310.0 312.5 315.0 317.5 320.0 322.5 325.0 327.5

306.0 308.5 311.0 313.5 316.0 318.5 321.0 323.5 326.0 328.5

RECEIVER ATTENUATION (dB)

SWEPT PASS BAND FREQUENCY (MHz)

Figure 18. Receiver IIP2 vs. Receiver Attenuation, LO = 75 MHz, Tones Placed at

77 MHz and 97 MHz, −23.5 dBm Plus Attenuation

Figure 21. Receiver IIP3, Receiver Attenuation = 0 dB, LO = 300 MHz, Tone 2 =

Tone 1 + 1 MHz, −21 dBm Each, Swept Across Pass Band

80

50

45

40

35

30

25

Rx1 (SUM) = +110°C

Rx1 (DIFF) = +110°C

Rx1 (SUM) = +25°C

Rx1 (DIFF) = +25°C

Rx1 (SUM) = –40°C

Rx1 (DIFF) = –40°C

75

70

65

60

55

50

45

40

20

15

10

5

Rx1 = +110°C

Rx1 = +25°C

Rx1 = –40°C

Rx2 = +110°C

Rx2 = +25°C

Rx2 = –40°C

Rx2 (SUM) = +110°C

Rx2 (DIFF) = +110°C

Rx2 (SUM) = +25°C

Rx2 (DIFF) = +25°C

Rx2 (SUM) = –40°C

Rx2 (DIFF) = –40°C

0

5

10

20

25

30

35

79.5

77.0

82.0

77.0

84.5

77.0

87.0

77.0

89.5

77.0

92.0

77.0

94.5

77.0

97.0

77.0

99.5

77.0

ATTENUATION (dB)

SWEPT PASS BAND FREQUENCY (MHz)

Figure 22. Receiver IIP3 vs. Attenuation, LO = 300 MHz, Tone 1 = 302 MHz,

Tone 2 = 322 MHz, −19 dBm Plus Attenuation

Figure 19. Receiver IIP2 Sum and Difference Across Bandwidth vs. Swept Pass

Band Frequency, Receiver Attenuation = 0 dB, LO = 75 MHz, Tone 1 =

77 MHz, Tone 2 Swept, −23.5 dBm Each

25

20

15

50

45

40

35

30

25

20

15

10

5

10

5

Rx1 = +110°C

Rx1 = +25°C

Rx1 = –40°C

Rx2 = +110°C

Rx2 = +25°C

Rx2 = –40°C

Rx1 = +110°C

Rx1 = +25°C

Rx1 = –40°C

Rx2 = +110°C

Rx2 = +25°C

Rx2 = –40°C

0

5

10

15

20

25

30

302.0 302.0 302.0 302.0 302.0 302.0 302.0 302.0 302.0 302.0

304.5 307.0 309.5 312.0 314.5 317.0 319.5 322.0 324.5 327.0

ATTENUATION (dB)

SWEPT PASS BAND FREQUENCY (MHz)

Figure 23. Receiver IIP3 vs. Swept Pass Band Frequency, Receiver Attenuation =

0 dB, LO = 300 MHz, Tone 1 = 302 MHz, Tone 2 Swept Across Pass Band, −19 dBm

Each

Figure 20. Receiver IIP3 vs. Attenuation, LO = 300 MHz, Tone 1 = 325 MHz,

Tone 2 = 326 MHz, −21 dBm Plus Attenuation

Rev. 0 | Page 19 of 68

ADRV9008-1

Data Sheet

–10

0

–20

+110°C

+25°C

–40°C

+110°C

+25°C

–40°C

–30

–40

–50

–60

–70

–80

–90

–100

–120

–100

–110

–25 –20 –15 –10

–5

0

5

10

15

20

25

0

5

10

15

20

25

30

BASEBAND FREQUENCY OFFSET

ATTENUATOR SETTING (dB)

Figure 24. Receiver Image vs. Baseband Frequency Offset,

Attenuation = 0 dB, RF Bandwidth = 50 MHz, Tracking Calibration Active,

Sample Rate = 61.44 MSPS, LO = 75 MHz

Figure 27. Receiver Image vs. Attenuator Setting, RF Bandwidth = 25 MHz,

Tracking Calibration Active, Sample Rate = 61.44 MSPS, LO = 75 MHz,

Baseband Frequency = 25 MHz

–10

0

–20

+110°C

–20

+25°C

–40°C

–40

+25°C

–40°C

–30

–40

–60

–50

–60

–70

–80

–90

–100

–120

–100

–110

–25 –20 –15 –10

–5

0

5

10

15

20

25

0

5

10

15

20

25

30

BASEBAND FREQUENCY OFFSET

ATTENUATOR SETTING (dB)

Figure 25. Receiver Image vs. Baseband Frequency Offset,

Attenuation = 0 dB, RF Bandwidth = 50 MHz, Tracking Calibration Active,

Sample Rate = 61.44 MSPS, LO = 300 MHz

Figure 28. Receiver Image vs. Attenuator Setting, RF Bandwidth = 25 MHz,

Tracking Calibration Active, Sample Rate = 61.44 MSPS, LO = 325 MHz,

Baseband Frequency = 25 MHz

–10

25

–20

20

+110°C

+25°C

–30

–40°C

–40

–40°C

15

10

5

–50

–60

–70

0

–80

–5

–10

–15

–90

–100

–110

–25 –20 –15 –10

–5

0

5

10

15

20

25

0

5

10

15

20

25

30

BASEBAND FREQUENCY OFFSET

RECEIVER ATTENUATOR SETTING (dB)

Figure 26. Receiver Image vs. Baseband Frequency Offset,

Attenuation = 0 dB, RF Bandwidth = 50 MHz, Tracking Calibration Active,

Sample Rate = 61.44 MSPS, LO = 525 MHz

Figure 29. Receiver Gain vs. Receiver Attenuator Setting,

RF Bandwidth = 50 MHz, Sample Rate = 61.44 MSPS, LO = 75 MHz

Rev. 0 | Page 20 of 68

Data Sheet

ADRV9008-1

25

20

15

10

5

0.5

0.4

+110°C

+25°C

–40°C

+110°C

+25°C

–40°C

0.3

0.2

0.1

0

–0.1

–0.2

–0.3

–0.4

–0.5

0

–5

–10

–15

0

5

10

15

20

25

30

0

3

6

9

12

15

18

21

24

27

30

RECEIVER ATTENUATOR SETTING (dB)

Figure 33. Receiver Gain Step Error vs. Receiver Attenuator Setting,

LO = 75 MHz

Figure 30. Receiver Gain vs. Receiver Attenuator Setting,

RF Bandwidth = 50 MHz, Sample Rate = 61.44 MSPS, LO = 325 MHz

25

0.5

0.4

20

+110°C

+25°C

–40°C

+25°C

–40°C

0.3

0.2

15

10

5

0.1

0

–0.1

–0.2

–0.3

–0.4

–0.5

0

–5

–10

–15

0

3

6

9

12

15

18

21

24

27

30

0

5

10

15

20

25

30

RECEIVER ATTENUATOR SETTING (dB)

Figure 34. Receiver Gain Step Error vs. Receiver Attenuator Setting,

LO = 325 MHz

Figure 31. Receiver Gain vs. Receiver Attenuator Setting,

RF Bandwidth = 50 MHz, Sample Rate = 61.44 MSPS, LO = 525 MHz

0.5

24

0.4

+110°C

+25°C

–40°C

+110°C

+25°C

–40°C

0.3

0.2

22

20

18

16

14

12

10

0.1

0

–0.1

–0.2

–0.3

–0.4

–0.5

0

3

6

9

12

15

18

21

24

27

30

75

125

175

225

275

320

375

425

475

525

RECEIVER ATTENUATOR SETTING (dB)

LO FREQUENCY (MHz)

Figure 35. Receiver Gain Step Error vs. Receiver Attenuator Setting,

LO = 525 MHz

Figure 32. Receiver Gain vs. LO Frequency,

RF Bandwidth = 50 MHz, Sample Rate = 61.44 MSPS

Rev. 0 | Page 21 of 68

ADRV9008-1

Data Sheet

0.5

0.4

–70

–75

0.3

+110°C

+25°C

–40°C

0.2

–80

0.1

0

–85

–0.1

–0.2

–0.3

–90

–0.4

–0.5

–0.6

–0.7

–0.8

–0.9

–1.0

I RIPPLE = +110°C

I RIPPLE = +25°C

I RIPPLE = –40°C

Q RIPPLE = +110°C

Q RIPPLE = +25°C

Q RIPPLE = –40°C

–95

–100

–105

–110

0

5

10

15

20

25

30

RECEIVER ATTENUATOR SETTING (dB)

BASEBAND OFFSET FREQUENCY (MHz)

Figure 39. Receiver DC Offset vs. Receiver Attenuator Setting, LO = 525 MHz

Figure 36. Normalized Receiver Baseband Flatness vs. Baseband Offset

Frequency (Receiver Flatness), LO = 75 MHz

–50

–30

ATTN = 15 +110°C

ATTN = 15 +25°C

–40

+110°C

–60

ATTN = 15 –40°C

ATTN = 0 +110°C

ATTN = 0 +25°C

ATTN = 0 –40°C

–50

+25°C

–40°C

–60

–70

–80

–90

–100

–110

–120

–130

–140

–150

–90

–100

–110

75

125

175

225

275

325

375

425

475

525

–30

–20

–10

0

10

20

30

RECEIVER LO FREQUENCY (MHz)

BASEBAND FREQUENCY OFFSET AND ATTENUATION (MHz)

Figure 37. Receiver DC Offset vs. Receiver LO Frequency

Figure 40. Receiver Second-Order Harmonic Distortion (HD2) Left vs.

Baseband Frequency Offset and Attenuation, Tone Level = −21 dBm at

Attenuation = 0 dB, X-Axis Is Baseband Frequency Offset of Fundamental

Tone, Not Frequency of HD2 Product (HD2 Product is 2× Baseband

Frequency), HD2 Canceller Disabled, LO = 75MHz

–30

–70

–75

ATTN = 15 +110°C

ATTN = 15 +25°C

ATTN = 15 –40°C

ATTN = 0 +110°C

ATTN = 0 +25°C

ATTN = 0 –40°C

–40

+110°C

+25°C

–40°C

–50

–80

–60

–70

–85

–80

–90

–100

–110

–120

–130

–140

–150

–95

–100

–105

–110

0

5

10

15

20

25

30

–30

–20

–10

0

10

20

30

BASEBAND FREQUENCY OFFSET AND ATTENUATION (MHz)

RECEIVER ATTENUATOR SETTING (dB)

Figure 41. Receiver HD2 Left vs. Baseband Frequency Offset and Attenuation,

Tone Level −21 dBm at Attenuation = 0 dB, X-Axis Is Baseband Frequency

Offset of Fundamental Tone, Not Frequency of HD2 Product (HD2 Product Is

2× Baseband Frequency), HD2 Canceller Disabled, LO = 300 MHz

Figure 38. Receiver DC Offset vs. Receiver Attenuator Setting,

LO = 75 MHz

Rev. 0 | Page 22 of 68

Data Sheet

ADRV9008-1

–30

–10

–30

ATTN = 15 +110°C

+110°C Rx2 (RIGHT)

+110°C Rx1 (RIGHT)

+25°C Rx2 (RIGHT)

+25°C Rx1 (RIGHT)

–40°C Rx2 (RIGHT)

–40°C Rx1 (RIGHT)

+110°C Rx2 (LEFT)

–40

–50

ATTN = 15 +25°C

ATTN = 15 –40°C

ATTN = 0 +110°C

ATTN = 0 +25°C

ATTN = 0 –40°C

+110°C Rx1 (LEFT)

+25°C Rx2 (LEFT)

+25°C Rx1 (LEFT)

–40°C Rx2 (LEFT)

–40°C Rx1 (LEFT)

–60

–50

–70

–80

–70

–90

–100

–110

–120

–130

–140

–150

–110

–130

–150

–30

–20

–10

0

10

20

30

–25

–20

–15

–10

–5

5

10

15

20

25

BASEBAND FREQUENCY OFFSET AND ATTENUATION (MHz)

525

FREQUENCY OFFSET FROM LO (MHz)

Figure 45. Receiver HD3, Left and Right vs. Frequency Offset from LO, Tone

Level −17 dBm at Attenuation = 0 dB, LO = 525 MHz

Figure 42. Receiver HD2 Left vs. Baseband Frequency Offset and Attenuation,

Tone Level −21 dBm at Attenuation = 0 dB, X-Axis Is Baseband Frequency

Offset of Fundamental Tone, Not Frequency of HD2 Product (HD2 Product Is

2× Baseband Frequency), HD2 Canceller Disabled, LO = 525 MHz

0

–10

+110°C Rx2 (RIGHT)

+110°C Rx1 (RIGHT)

+25°C Rx2 (RIGHT)

+25°C Rx1 (RIGHT)

–40°C Rx2 (RIGHT)

–40°C Rx1 (RIGHT)

+110°C Rx2 (LEFT)

+110°C Rx1 (LEFT)

+25°C Rx2 (LEFT)

+25°C Rx1 (LEFT)

–40°C Rx2 (LEFT)

–40°C Rx1 (LEFT)

–5

+110°C

+25°C

–40°C

–30

–50

–10

–15

–20

–25

–30

–35

–40

–45

–50

–70

–90

–110

–130

–150

–65

–55

–45

–35

–25

–15

–5

5

–25

–20

–15

–10

–5

5

10

15

20

25

LTE 20MHz RF INPUT POWER (dBm)

75

FREQUENCY OFFSET FROM LO AND ATTENUATION (MHz)

Figure 43. Receiver HD3, Left and Right vs. Frequency Offset from LO and

Attenuation, Tone Level = −16 dBm at Attenuation = 0 dB, LO = 75 MHz

Figure 46. Receiver Error Vector Magnitude (EVM) vs. LTE 20 MHz RF Input

Power, LTE 20 MHz RF Signal, LO = 75 MHz, Default AGC Settings

–10

0

+110°C Rx2 (RIGHT)

+110°C Rx1 (RIGHT)

+25°C Rx2 (RIGHT)

+25°C Rx1 (RIGHT)

–40°C Rx2 (RIGHT)

–40°C Rx1 (RIGHT)

+110°C Rx2 (LEFT)

+110°C Rx1 (LEFT)

+25°C Rx2 (LEFT)

+25°C Rx1 (LEFT)

–40°C Rx2 (LEFT)

–40°C Rx1 (LEFT)

–5

+110°C

+25°C

–40°C

–30

–50

–10

–15

–20

–25

–30

–35

–40

–45

–50

–70

–90

–110

–130

–150

–65

–55

–45

–35

–25

–15

–5

5

–25

–20

–15

–10

–5

5

10

15

20

25

300

LTE 20MHz RF INPUT POWER (dBm)

FREQUENCY OFFSET FROM LO (MHz)

Figure 44. Receiver HD3, Left and Right vs. Frequency Offset from LO, Tone

Level −17 dBm at Attenuation = 0 dB, LO = 300 MHz

Figure 47. Receiver EVM vs. LTE 20 MHz RF Input Power, LTE 20 MHz RF

Signal, LO = 300 MHz, Default AGC Settings

Rev. 0 | Page 23 of 68

ADRV9008-1

Data Sheet

–80

–85

–90

0

100Hz = –99.81dBc/Hz

1kHz = –108.20dBc/Hz

10kHz = –114.24dBc/Hz

100kHz = –120.82dBc/Hz

1MHz = –147.16dBc/Hz

10MHz = –152.38dBc/Hz

100MHz = –152.51dBc/Hz

–5

+110°C

+25°C

–40°C

–95

–10

–15

–20

–25

–30

–35

–40

–45

–50

–100

–105

–110

–115

–120

–125

–130

–135

–140

–145

–150

–155

–160

–165

–170

–65

–55

–45

–35

–25

–15

–5

5

100

1k

10k

100k

1M

10M

100M

LTE 20MHz RF INPUT POWER (dBm)

FREQUENCY (Hz)

Figure 51. LO Phase Noise vs. Frequency Offset, LO = 300 MHz, PLL Loop

Bandwidth = 50 kHz

Figure 48. Receiver EVM vs. LTE 20 MHz RF Input Power,

LTE 20 MHz RF Signal, LO = 525 MHz, Default AGC Settings

–80

0

100Hz = –95.48dBc/Hz

–85

1kHz

= –103.55dBc/Hz

10

–90

–95

10kHz = –109.36dBc/Hz

100kHz = –116.28dBc/Hz

1MHz = –144.62dBc/Hz

10MHz = –152.33dBc/Hz

100MHz = –152.85dBc/Hz

Rx1 TO Rx2

Rx2 TO Rx1

20

30

–100

–105

–110

–115

–120

–125

–130

–135

–140

–145

–150

–155

–160

–165

–170

40

50

60

70

80

90

100

0

100

200

300

400

500

600

100

1k

10k

100k

1M

10M

100M

LO FREQUENCY (MHz)

FREQUENCY (Hz)

Figure 49. Receiver to Receiver Isolation vs. LO Frequency,

Baseband Frequency = 10 MHz

Figure 52. LO Phase Noise vs. Frequency Offset, LO = 525 MHz, PLL Loop

Bandwidth = 50 kHz

–80

–85

–90

100Hz = –110.00dBc/Hz

1kHz = –120.75dBc/Hz

10kHz = –126.54dBc/Hz

100kHz = –132.76dBc/Hz

1MHz = –150.09dBc/Hz

10MHz = –151.09dBc/Hz

100MHz = –150.74dBc/Hz

–95

–100

–105

–110

–115

–120

–125

–130

–135

–140

–145

–150

–155

–160

–165

–170

100

1k

10k

100k

1M

10M

100M

FREQUENCY (Hz)

Figure 50. LO Phase Noise vs. Frequency Offset, LO = 75 MHz, PLL Loop

Bandwidth = 50 kHz

Rev. 0 | Page 24 of 68

Data Sheet

ADRV9008-1

650 MHz TO 3000 MHz BAND

45

40

35

30

25

20

15

10

5

0

–0.25

–0.50

–0.75

–1.00

–1.25

–1.50

–1.75

–2.00

–2.25

–2.50

–2.75

–3.00

+110°C

+25°C

–40°C

0

2

4

6

8

10

12

14

16

18

20

ATTENUATION (dB)

LO FREQUENCY (MHz)

Figure 53. Receiver Off Chip Matching Circuit Path Loss vs. LO Frequency,

Can Be Used for De-Embedding Performance Data

Figure 56. Receiver Noise Figure vs. Attenuation, LO = 1850 MHz,

200 MHz Bandwidth, Sample Rate = 245.76 MSPS,

Integration Bandwidth = 500 kHz to 100 MHz

0

45

+110°C

+25°C

–40°C

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

+110°C

+25°C

–40°C

40

35

30

25

20

15

10

5

0

2

4

6

8

10

12

14

16

18

20

RECEIVER ATTENUATION (dB)

RECEIVER LO FREQUENCY (MHz)

Figure 57. Receiver Noise Figure vs. Receiver Attenuation, 2850 MHz LO,

RF Bandwidth = 200 MHz, Sample Rate = 245.76 MSPS,

Integration Bandwidth = 500 kHz to 100 MHz

Figure 54. Receiver LO Leakage vs. Receiver LO Frequency, Receiver

Attenuation = 0 dB, RF Bandwidth = 200 MHz,

Sample Rate = 245.76 MSPS

20

18

16

14

12

10

45

40

35

30

25

20

15

10

5

+110°C

+25°C

–40°C

8

+110°C

+25°C

–40°C

6

4

2

0

2

4

6

8

10

12

14

16

18

20

ATTENUATION (dB)

RECEIVER LO FREQUENCY (MHz)

Figure 55. Receiver Noise Figure vs. Attenuation, LO = 650 MHz, RF

Bandwidth = 200 MHz, Sample Rate = 245.76 MSPS, Integration Bandwidth =

500 kHz to 100 MHz

Figure 58. Receiver Noise Figure vs. Receiver LO Frequency,

Receiver Attenuation = 0 dB, RF Bandwidth = 200 MHz,

Sample Rate = 245.76 MSPS, Integration Bandwidth = 100 MHz

Rev. 0 | Page 25 of 68

ADRV9008-1

Data Sheet

40

35

30

25

20

15

10

5

20

–40°C

+25°C

+110°C

–40°C

+25°C

+110°C

18

16

14

12

10

8

0

–20

–15

–10

–5

0

5

10

–100 –80 –60 –40 –20

0

20

40

60

80

100

CW OUT OF BAND BLOCKER LEVEL (dBm)

RECEIVER OFFSET FREQUENCY FROM LO (650MHz)

Figure 59. Receiver Noise Figure vs. Receiver Offset Frequency from LO, Integration

Bandwidth = 200 kHz, LO = 650 MHz

Figure 62. Receiver Noise Figure vs. CW Out of Band Blocker Level, LO =

1685 MHz, Blocker = 2085 MHz

20

110

–40°C

–40°C (SUM)

–40°C (DIFF)

+25°C (SUM)

+25°C

+110°C

18

16

14

12

10

8

100

+25°C (DIFF)

+110°C (SUM)

+110°C (DIFF)

90

80

70

60

50

–80 –60 –40 –20

0

20

40

60

80

100

–100

0

2

4

6

8

10 12 14 16 18 20 22 24 26 28 30

RECEIVER OFFSET FREQUENCY FROM LO (1850MHz)

RECEIVER ATTENUATION (dB)

Figure 60. Receiver Noise Figure vs. Receiver Offset Frequency from LO, Integration

Bandwidth = 200 kHz, LO = 1850 MHz

Figure 63. Receiver IIP2 vs. Receiver Attenuation, LO = 1800 MHz, Tones

Placed at 1845 MHz and 1846 MHz, −21 dBm Each at Attenuation = 0 dB

20

80

75

70

65

60

–40°C

+25°C

+110°C

18

16

14

12

10

8

55

–40°C (SUM)

–40°C (DIFF)

+25°C (SUM)

+25°C (DIFF)

+110°C (SUM)

+110°C (DIFF)

50

45

40

–100 –80 –60 –40 –20

0

20

40

60

80

100

806

805

826

825

846

845

866

865

886

885

906

905

RECEIVER OFFSET FREQUENCY FROM LO (2850MHz)

800

SWEPT PASS BAND FREQUENCY (MHz)

Figure 64. Receiver IIP2 Sum and Difference Across Bandwidth vs. Swept Pass

Band Frequency, Receiver Attenuation = 0 dB, LO = 800 MHz, Six Tone Pairs,

−21 dBm Each

Figure 61. Receiver Noise Figure vs. Receiver Offset Frequency from LO, Integration

Bandwidth = 200 kHz, LO = 2850 MHz

Rev. 0 | Page 26 of 68

Data Sheet

ADRV9008-1

80

75

70

65

60

55

50

45

40

100

95

90

85

80

75

70

65

60

55

50

RX1 +110°C MAX OF IIP2_SUM_CF

RX1 +110°C MAX OF IIP2_DIF_CF

RX2 +110°C MAX OF IIP2_SUM_CF

RX2 +110°C MAX OF IIP2_DIF_CF

RX1 +25°C MAX OF IIP2_SUM_CF

RX1 +25°C MAX OF IIP2_DIF_CF

RX2 +25°C MAX OF IIP2_SUM_CF

RX2 +25°C MAX OF IIP2_DIF_CF

RX1 –40°C MAX OF IIP2_SUM_CF

RX1 –40°C MAX OF IIP2_DIF_CF

RX2 –40°C MAX OF IIP2_SUM_CF

RX2 –40°C MAX OF IIP2_DIF_CF

–40°C (SUM)

–40°C (DIFF)

+25°C (SUM)

+25°C (DIFF)

+110°C (SUM)

+110°C (DIFF)

1806

1805

1826

1825

1846

1845

1866

1865

1886

1885

1906

1905

1800

SWEPT PASS BAND FREQUENCY (MHz)

TONE1 = 802MHz, TONE2 = SWEPT ACROSS PASSBAND

ATTENUATOR = 0

Figure 65. Receiver IIP2 Sum and Difference Across Bandwidth vs. Swept Pass

Band Frequency, Receiver Attenuation = 0 dB, LO = 1800 MHz, Six Tone Pairs,

−21 dBm Each

Figure 68. Receiver IIP2 Sum and Difference Across Bandwidth, Receiver

Attenuation = 0 dB, LO = 800 MHz, Tone 1 = 802 MHz, Tone 2 Swept,

−21 dBm Each, IIP2_SUM_CF and IIP2_DIF_CF Indicate Sum and Difference

Products

100

80

75

70

65

60

Rx1 –40°C MAX OF IIP2_SUM_CF

Rx1 –40°C MAX OF IIP2_DIF_CF

95

Rx1 +25°C MAX OF IIP2_SUM_CF

Rx1 +25°C MAX OF IIP2_DIF_CF

90

85

80

75

70

65

60

55

50

Rx1 +110°C MAX OF IIP2_SUM_CF

Rx1 +110°C MAX OF IIP2_DIF_CF

Rx2 –40°C MAX OF IIP2_SUM_CF

Rx2 –40°C MAX OF IIP2_DIF_CF

Rx2 +25°C MAX OF IIP2_SUM_CF

Rx2 +25°C MAX OF IIP2_DIF_CF

Rx2 +110°C MAX OF IIP2_SUM_CF

Rx2 +110°C MAX OF IIP2_DIF_CF

55

–40°C (SUM)

50

45

40

–40°C (DIFF)

+25°C (SUM)

+25°C (DIFF)

+110°C (SUM)

+110°C (DIFF)

1807 1817 1827 1837 1847 1857 1867 1877 1887 1897 1907

2906

2905

2926

2925

2946

2945

2966

2965

2986

2985

3006

3005

SWEPT PASS BAND FREQUENCY (MHz)

Figure 66. Receiver IIP2 Sum and Difference Across Bandwidth vs. Swept Pass

Band Frequency, Receiver Attenuation = 0 dB, LO = 2900 MHz, Six Tone Pairs,

−21 dBm Each

Figure 69. Receiver IIP2 Sum and Difference Across Bandwidth vs. Swept Pass

Band Frequency, Receiver Attenuation = 0 dB, LO = 1800 MHz, Tone 1 =

1802 MHz, Tone 2 Swept, −21 dBm Each, IIP2_SUM_CF and IIP2_DIF_CF

Indicate Sum and Difference Products

100

R

X

1 +110°C MAX OF IIP2_SUM_CF

1 +110°C MAX OF IIP2_DIF_CF

2 +110°C MAX OF IIP2_SUM_CF

2 +110°C MAX OF IIP2_DIF_CF

Rx1 –40°C (SUM)

Rx1 –40°C (DIF)

95

90

85

80

75

70

65

60

55

50

Rx1 +25°C (SUM)

Rx1 +25°C (DIF)

90

Rx1 +110°C (SUM)

Rx1 +110°C (DIF)

85

80

75

70

65

60

55

50

Rx2 –40°C (SUM)

Rx2 –40°C (DIF)

Rx2 +110°C (SUM)

Rx2 +110°C (DIF)

R

X1 +25°C MAX OF IIP2_SUM_CF

X1 +25°C MAX OF IIP2_DIF_CF

X2 +25°C MAX OF IIP2_SUM_CF

X2 +25°C MAX OF IIP2_DIF_CF

X1 –40°C MAX OF IIP2_SUM_CF

X1 –40°C MAX OF IIP2_DIF_CF

X2 –40°C MAX OF IIP2_SUM_CF

X2 –40°C MAX OF IIP2_DIF_CF

2907 2917 2927 2937 2947 2957 2967 2977 2987 2997 3007

0

2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 25.0 27.5 30.0

TONE1 = 1802MHz, TONE2 = 1892MHz

ATTENUATOR = SWEPT

SWEPT PASS BAND FREQUENCY (MHz)

Figure 67. Receiver IIP2, LO = 1800 MHz, Tones Placed at 1802 MHz and

1892 MHz, −21 dBm Each at Attenuation = 0 dB, IIP2_SUM_CF and IIP2_DIF_CF

Indicate Sum and Difference Products

Figure 70. Receiver IIP2 Sum and Difference Across Bandwidth vs. Swept Pass

Band Frequency, Receiver Attenuation = 0 dB, LO = 2900 MHz, Tone 1 =

2902 MHz, Tone 2 Swept, −21 dBm Each

Rev. 0 | Page 27 of 68

ADRV9008-1

Data Sheet

45

25

20

15

10

5

Rx1 –40°C

Rx1 +25°C

Rx1 +110°C

Rx2 –40°C

Rx2 +25°C

Rx2 +110°C

Rx1 –40°C

Rx1 +25°C

Rx1 +110°C

Rx2 –40°C

Rx2 +25°C

Rx2 +110°C

40

35

30

25

20

15

10

5

0

2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 25.0 27.5 30.0

ATTENUATION (dB)

2905 2915 2925 2935 2945 2955 2965 2975 2985 2995 3005 3015 3025

2906 2916 2926 2936 2946 2956 2966 2976 2986 2996 3006 3016 3026

SWEPT PASS BAND FREQUENCY (MHz)

Figure 71. Receiver IIP3 vs. Attenuation, LO = 1800 MHz, Tone 1 = 1890 MHz,

Tone 2 = 1891 MHz, −21 dBm Each at Attenuation = 0 dB

Figure 74. Receiver IIP3 vs. Swept Pass Band Frequency, Receiver Attenuation =

0 dB, LO = 2900 MHz, Tone 2 = Tone 1 + 1 MHz, −21 dBm Each,

Swept Across Pass Band

30

60

Rx1 –40°C

Rx1 +25°C

Rx1 +110°C

Rx1 –40°C

Rx1 +25°C

Rx1 +110°C

Rx2 –40°C

50

25

Rx2 +25°C

Rx2 +110°C

Rx2 +25°C

Rx2 +110°C

20

15

10

5

40

30

20

10

0

2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 25.0 27.5 30.0

ATTENUATION (dB)

805 815 825 835 845 855 865 875 885 895 905 915 925

806 816 826 836 846 856 866 876 886 896 906 916 926

SWEPT PASS BAND FREQUENCY (MHz)

Figure 72. Receiver IIP3 vs. Swept Pass Band Frequency, Receiver Attenuation =

0 dB, LO = 800 MHz, Tone 2 = Tone 1 + 1 MHz, −21 dBm Each,

Swept Across Pass Band

Figure 75. Receiver IIP3 vs. Attenuation, LO = 1800 MHz, Tone 1 = 1802 MHz,

Tone 2 = 1892 MHz, −21 dBm Each at Attenuation = 0 dB

30

Rx1 –40°C

Rx1 +25°C

Rx1 +110°C

Rx1 –40°C

Rx1 +25°C

Rx1 +110°C

25

Rx2 –40°C

25

Rx2 +25°C

Rx2 +110°C

Rx2 +25°C

Rx2 +110°C

20

15

10

5

20

15

10

5

0

807 817 827 837 847 857 867 877 887 897 907

0

SWEPT PASS BAND FREQUENCY (MHz)

1805 1815 1825 1835 1845 1855 1865 1875 1885 1895 1905 1915 1925

1806 1816 1826 1836 1846 1856 1866 1876 1886 1896 1906 1916 1926

SWEPT PASS BAND FREQUENCY (MHz)

Figure 73. Receiver IIP3 vs. Swept Pass Band Frequency, Receiver Attenuation =

0 dB, LO = 1800 MHz, Tone 2 = Tone 1 + 1 MHz, −21 dBm Each,

Swept Across Pass Band

Figure 76. Receiver IIP3 vs. Swept Pass Band Frequency, Receiver Attenuation =

0 dB, LO = 800 MHz, Tone 1 = 802 MHz, Tone 2 Swept Across Pass Band,

−21 dBm Each

Rev. 0 | Page 28 of 68

Data Sheet

ADRV9008-1

0

–20

30

25

20

15

10

5

–40°C

+25°C

+110°C

Rx1 –40°C

Rx1 +25°C

Rx1 +110°C

Rx2 –40°C

Rx2 +25°C

Rx2 +110°C

–40

–60

–80

–100

0

1807 1817 1827 1837 1847 1857 1867 1877 1887 1897 1907

–120

SWEPT PASS BAND FREQUENCY (MHz)

–100

–75

–50

–25

0

25

50

75

100

BASEBAND FREQUENCY OFFSET (Hz)

Figure 77. Receiver IIP3 vs. Swept Pass Band Frequency, Receiver Attenuation =

0 dB, LO = 1800 MHz, Tone 1 = 1802 MHz, Tone 2 Swept Across Pass Band,

−21 dBm Each

Figure 80. Receiver Image vs. Baseband Frequency Offset,

Attenuation = 0 dB, RF Bandwidth = 200 MHz, Tracking Calibration Active,

Sample Rate = 245.76 MSPS, LO = 1850 MHz

30

25

20

15

0

–40°C

+25°C

+110°C

–20

–40

–60

10

–80

Rx1 –40°C

5

0

Rx1 +25°C

Rx1 +110°C

Rx2 –40°C

Rx2 +110°C

–100

–120

2907 2917 2927 2937 2947 2957 2967 2977 2987 2997 3007

–100

–75

–50

–25

0

25

50

75

100

BASEBAND FREQUENCY OFFSET (Hz)

SWEPT PASS BAND FREQUENCY (MHz)

Figure 78. Receiver IIP3 vs. Swept Pass Band Frequency, Receiver Attenuation =

0 dB, LO = 2900 MHz, Tone 1 = 2902 MHz, Tone 2 Swept Across Pass Band,

−21 dBm Each

Figure 81. Receiver Image vs. Baseband Frequency Offset,

Attenuation = 0 dB, RF Bandwidth = 200 MHz, Tracking Calibration Active,

Sample Rate = 245.76 MSPS, LO = 2850 MHz

0

–40°C

+25°C

+110°C

–40°C

+25°C

+110°C

–20

–40

–20

–40

–60

–80

–100

–120

–100

–75

–50

–25

0

25

50

75

100

0

2.5

5.0

7.5

10.0

12.5

15.0

BASEBAND FREQUENCY OFFSET (Hz)

ATTENUATOR SETTING (dB)

Figure 79. Receiver Image vs. Baseband Frequency Offset,

Attenuation = 0 dB, 200 MHz RF Bandwidth, Tracking Calibration Active,

Sample Rate = 245.76 MSPS, LO = 650 MHz

Figure 82. Receiver Image vs. Attenuator Setting,

RF Bandwidth = 200 MHz, Tracking Calibration Active,

Sample Rate = 245.76 MSPS, LO = 1850 MHz

Rev. 0 | Page 29 of 68

ADRV9008-1

Data Sheet

25

20

15

10

5

0.10

0.05

0

–40°C

+25°C

+110°C

–0.05

–0.10

–0.15

–0.20

–0.25

–0.30

–0.35

–0.40

–0.45

–0.50

–0.55

–0.60

–0.65

–0.70

–0.75

–0.80

–0.85

–0.90

–0.95

–1.00

0

NORMALIZED I RIPPLE

NORMALIZED Q RIPPLE

–5

–10

–15

0

5

10

15

20

25

30

RECEIVER ATTENUATION (dB)

BASEBAND OFFSET FREQUENCY (MHz)

Figure 83. Receiver Gain vs. Receiver Attenuation, RF Bandwidth = 20 MHz,

Sample Rate = 245.76 MSPS, LO = 1850 MHz

Figure 86. Normalized Receiver Baseband Flatness vs. Baseband Offset

Frequency, LO = 2600 MHz

24

–70

–40°C

+25°C

+110°C

–75

–40°C

+25°C

+110°C

22

20

–80

–85

–90

–95

18

16

14

12

–100

10

650 850 1050 1250 1450 1650 1850 2050 2250 2450 2650 2850

RECEIVER LO FREQUENCY (MHz)

LO FREQUENCY (MHz)

Figure 84. Receiver Gain vs. LO Frequency, RF Bandwidth = 20 MHz, Sample

Rate = 245.76 MSPS

Figure 87. Receiver DC Offset vs. Receiver LO Frequency

–70

0.5

–40°C

+25°C

0.4

+110°C

–75

–80

0.3

0.2

0.1

–85

0

–0.1

–0.2

–0.3

–0.4

–0.5

–90

–95

–100

0

5

10

15

20

25

30

0

5

10

15

20

25

30

RECEIVER ATTENUATOR SETTING (dB)

Figure 88. Receiver DC Offset vs. Receiver Attenuator Setting, LO = 1850 MHz

Figure 85. Receiver Gain Step Error vs. Receiver Attenuator Setting over

Temperature

Rev. 0 | Page 30 of 68

Data Sheet

ADRV9008-1

–30

10

–10

ATTN = 15 –40°C

Rx1 –40°C HD3 (LEFT)

Rx1 –40°C HD3 (RIGHT)

Rx1 +25°C HD3 (LEFT)

Rx1 +25°C HD3 (RIGHT)

Rx1 +110°C HD3 (LEFT)

Rx1 +110°C HD3 (RIGHT)

Rx2 –40°C HD3 (LEFT)

Rx2 –40°C HD3 (RIGHT)

ATTN = 0 –40°C

ATTN = 15 +25°C

ATTN = 0 +25°C

ATTN = 15 +110°C

ATTN = 0 +110°C

–50

–70

–30

–50

–90

–70

–90

–110

–130

–150

–110

–130

–150

Rx2 +25°C HD3 (LEFT)

Rx2 +25°C HD3 (RIGHT)

Rx2 +110°C HD3 (LEFT)

Rx2 +110°C HD3 (RIGHT)

–60

–40

–20

0

20

40

60

–50

–40

–30

–20

–10

10

20

30

40

50

650

FREQUENCY OFFSET FROM LO (MHz)

BASEBAND FREQUENCY OFFSET AND ATTENUATION (MHz)

Figure 89. Receiver HD2 Left vs. Baseband Frequency Offset and Attenuation,

Tone Level = −15 dBm at Attenuation = 0 dB, HD2 Correction Configured for

Low-Side Optimization, X-Axis = Baseband Frequency Offset of Fundamental

Tone and Not the Frequency of the HD2 Product (HD2 Product = 2× Baseband

Frequency), LO = 650 MHz

Figure 92. Receiver HD3, Left and Right vs. Frequency Offset from LO, Tone

Level = −15 dBm at Attenuation = 0 dB, LO = 650 MHz

10

–30

Rx1 –40°C HD3 (LEFT)

Rx1 –40°C HD3 (RIGHT)

ATTN = 15 –40°C

ATTN = 0 –40°C

ATTN = 15 +25°C

–10

–30

Rx1 +25°C HD3 (LEFT)

Rx1 +25°C HD3 (RIGHT)

Rx1 +110°C HD3 (LEFT)

Rx1 +110°C HD3 (RIGHT)

Rx2 –40°C HD3 (LEFT)

Rx2 –40°C HD3 (RIGHT)

–50

ATTN = 0 +25°C

ATTN = 15 +110°C

ATTN = 0 +110°C

–70

–90

–50

–70

–90

–110

–130

–150

–110

–130

–150

Rx2 +25°C HD3 (LEFT)

Rx2 +25°C HD3 (RIGHT)

Rx2 +110°C HD3 (LEFT)

Rx2 +110°C HD3 (RIGHT)

–60

–40

–20

0

20

40

60

–50

–40

–30

–20

–10

1850

FREQUENCY OFFSET FROM LO (MHz)

10

20

30

40

50

BASEBAND FREQUENCY OFFSET AND ATTENUATION (MHz)

Figure 90. Receiver HD2 Left vs. Baseband Frequency Offset and Attenuation,

Tone Level = −15 dBm at Attenuation = 0 dB, HD2 Correction Configured for

Low-Side Optimization, X-Axis = Baseband Frequency Offset of the Fundamental

Tone and Not the Frequency of the HD2 Product (HD2 Product = 2× the Baseband

Frequency), LO = 1850 MHz

Figure 93. Receiver HD3, Left and Right vs. Frequency Offset from LO, Tone

Level = −15 dBm at Attenuation = 0 dB, LO = 1850 MHz

10

–30

–50

–70

–90

Rx1 –40°C HD3 (LEFT)

Rx1 –40°C HD3 (RIGHT)

–10

–30

Rx1 +25°C HD3 (LEFT)

Rx1 +25°C HD3 (RIGHT)

Rx1 +110°C HD3 (LEFT)

Rx1 +110°C HD3 (RIGHT)

Rx2 –40°C HD3 (LEFT)

Rx2 –40°C HD3 (RIGHT)

–50

–70

–90

–110

ATTN = 15dB, +110°C

ATTN = 0dB, +110°C

ATTN = 15dB, +25°C

ATTN = 0dB, +25°C

ATTN = 15dB, –40°C

ATTN = 0dB, –40°C

–110

–130

–150

–130

–150

Rx2 +25°C HD3 (LEFT)

Rx2 +25°C HD3 (RIGHT)

Rx2 +110°C HD3 (LEFT)

Rx2 +110°C HD3 (RIGHT)

–60

–40

–20

0

–20

–40

60

–50

–40

–30

–20

–10

2850

FREQUENCY OFFSET FROM LO (MHz)

10

20

30

40

50

BASEBAND FREQUENCY OFFSET AND ATTENUATION (MHz)

Figure 94. Receiver HD3, Left and Right vs. Frequency Offset from LO, Tone

Level = −15 dBm at Attenuation = 0 dB, LO = 2850 MHz

Figure 91. Receiver HD2 Left vs. Baseband Frequency Offset and Attenuation,

Tone Level = −15 dBm at Attenuation = 0 dB, HD2 Correction Configured for

Low-Side Optimization, X-Axis = Baseband Frequency Offset of the Fundamental

Tone and Not the Frequency of the HD2 Product (HD2 Product = 2× the Baseband

Frequency), LO = 2850 MHz

Rev. 0 | Page 31 of 68

ADRV9008-1

Data Sheet

10

0

–5

Rx1 –40°C HD3 (LEFT)

Rx1 –40°C HD3 (RIGHT)

Rx1 +25°C HD3 (LEFT)

Rx1 +25°C HD3 (RIGHT)

Rx1 +110°C HD3 (LEFT)

Rx1 +110°C HD3 (RIGHT)

Rx2 –40°C HD3 (LEFT)

Rx2 –40°C HD3 (RIGHT)

–40°C

+25°C

+110°C

–10

–15

–20

–25

–30

–35

–40

–45

–30

–50

–70

–90

–110

–130

–150

Rx2 +25°C HD3 (LEFT)

Rx2 +25°C HD3 (RIGHT)

Rx2 +110°C HD3 (LEFT)

Rx2 +110°C HD3 (RIGHT)

0 15 30 10 25 5 20 0 15 30 10 25 5 20 0 15 30 10 25 5 20 0 15 30

–50 –40 –30 –20 –10 10 20 30 40 50

1850

–65

–55

–45

–35

–25

–15

–5

5

LTE 20MHz RF INPUT POWER (dBm)

UPPER: RECEIVER ATTENUATION (dB)

LOWER: FREQUENCY OFFSET FROM LO (MHz)

Figure 98. Receiver EVM vs. LTE 20 MHz RF Input Power,

LTE 20 MHz RF Signal, LO = 2700 MHz

Figure 95. Receiver HD3, Left and Right vs. Receiver Attenuation and Frequency

Offset from LO, Baseband Tone Held Constant, Tone Level Increased 1 for 1 as

Attenuator is Swept from 0 dB to 30 dB, HD3 Right (High Side): Tone on Same Side

as HD3 Product; HD3 Left (Low Side): Tone on Opposite Side as HD3 Product,

CW Signal, LO = 1850 MHz, Tone Level = −15 dBm at Attenuation = 0 dB

0

10

20

30

40

50

60

70

80

90

–40°C

+25°C

+110°C

+25°C

–5

+110°C

–10

–15

–20

–25

–30

–35

–40

–45

–50

–65

–55

–45

–35

–25

–15

–5

5

LTE 20MHz RF INPUT POWER (dBm)

LO FREQUENCY (MHz)

Figure 96. Receiver EVM vs. LTE 20 MHz RF Input Power,

LTE 20 MHz RF Signal, LO = 600 MHz

Figure 99. Receiver to Receiver Isolation (dB) vs. LO Frequency (MHz)

0

–5

–70

–80

–40°C

+25°C

+110°C

–10

–15

–20

–25

–30

–35

–40

–45

–50

–90

–100

–110

–120

–130

–140

–150

–160

–170

–65

–55

–45

–35

–25

–15

–5

5

100

1k

10k

100k

1M

10M

100M

LTE 20MHz RF INPUT POWER (dBm)

FREQUENCY OFFSET (Hz)

Figure 100. LO Phase Noise vs. Frequency Offset, LO = 1900 MHz, Spectrum

Analyzer Limits Far Out Noise

Figure 97. Receiver EVM vs. LTE 20 MHz RF Input Power,

LTE 20 MHz RF Signal, LO = 1800 MHz

Rev. 0 | Page 32 of 68

Data Sheet

ADRV9008-1

3400 MHz TO 4800 MHz BAND

45

40

35

30

25

20

15

10

5

0

–0.2

–0.4

–0.6

–0.8

–1.0

–1.2

–1.4

–1.6

–1.8

–2.0

+110°C

+25°C

–40°C

0

2

4

6

8

10

12

14

16

18

20

3400

3600

3800

4000

4200

4400

4600

4800

5000

RECEIVER ATTENUATION (dB)

LO FREQUENCY (MHz)

Figure 101. Receiver Off Chip Matching Circuit Path Loss vs. LO Frequency

(Simulation), Can Be Used for De-Embedding Performance Data

Figure 104. Receiver Noise Figure vs. Receiver Attenuation,

LO = 4600 MHz, RF Bandwidth = 200 MHz, Sample Rate = 245.76 MSPS,

Integration Bandwidth = 500 kHz to 100 MHz

0

120

110

100

90

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

+110°C

+25°C

–40°C

80

70

60

50

IIP2 SUM +110°C

IIP2 SUM +25°C

IIP2 SUM –40°C

IIP2 DIFF +110°C

IIP2 DIFF +25°C

IIP2 DIFF –40°C

3600

4600

0

2

4

6

8

10 12 14 16 18 20 22 24 26 28 30

RECEIVER LO FREQUENCY (MHz)

RECEIVER ATTENUATION (dB)

Figure 102. Receiver LO Leakage from 3600 MHz to 4600 MHz, 0 dB Receiver

Attenuation, 200 MHz RF Bandwidth, 245.76 MSPS Sample Rate

Figure 105. Receiver IIP2 vs. Receiver Attenuation, LO = 3600 MHz, Tones

Placed at 3645 MHz and 3646 MHz, −21 dBm Plus Attenuation

45

110

100

90

+110°C

+25°C

–40°C

40

35

30

25

20

15

10

5

80

70

IIP2 SUM +110°C

IIP2 SUM +25°C

IIP2 SUM –40°C

IIP2 DIFF +110°C

IIP2 DIFF +25°C

60

IIP2 DIFF –40°C

10 12 14 16 18 20 22 24 26 28 30

RECEIVER ATTENUATION (dB)

0

50

0

2

4

6

8

10

12

14

16

18

20

0

2

4

6

8

RECEIVER ATTENUATION (dB)

Figure 103. Receiver Noise Figure vs. Receiver Attenuation,

LO = 3600 MHz, RF Bandwidth = 200 MHz, Sample Rate = 245.76 MSPS,

Integration Bandwidth = 500 kHz to 100 MHz

Figure 106. Receiver IIP2 vs. Receiver Attenuation, LO = 4600 MHz, Tones

Placed at 4645 MHz and 4646 MHz, −21 dBm Plus Attenuation

Rev. 0 | Page 33 of 68

ADRV9008-1

Data Sheet

80

75

70

65

60

55

50

45

40

100

95

90

85

80

75

70

65

60

55

50

IIP2 SUM +110°C

IIP2 SUM +25°C

IIP2 SUM –40°C

IIP2 DIFF +110°C

IIP2 DIFF +25°C

IIP2 DIFF –40°C

+110°C = Rx1 (DIFF)

+110°C = Rx1 (SUM)

+25°C = Rx1 (DIFF)

+25°C = Rx1 (SUM)

–40°C = Rx1 (DIFF)

–40°C = Rx1 (SUM)

+110°C = Rx2 (DIFF)

+110°C = Rx2 (SUM)

+25°C = Rx2 (DIFF)

+25°C = Rx2 (SUM)

–40°C = Rx2 (DIFF)

–40°C = Rx2 (SUM)

3606

3605

3626

3625

3646

3645

3666

3665

3686

3685

3706

3705

0

5

10

15

20

25

30

RECEIVER ATTENUATION

SWEPT PASS BAND FREQUENCY (MHz)

Figure 110. Receiver IIP2 vs. Receiver Attenuation, LO = 4600 MHz, Tones

Placed at 4602 MHz and 4692 MHz, −21 dBm Plus Attenuation

Figure 107. Receiver IIP2 Sum and Difference Across Bandwidth vs. Swept

Pass Band Frequency, Receiver Attenuation = 0 dB, LO = 3600 MHz,

Six Tone Pairs, −21 dBm Plus Attenuation Each

80

75

70

65

60

100

+110°C = Rx1 (DIFF)

+110°C = Rx1 (SUM)

+25°C = Rx1 (DIFF)

+25°C = Rx1 (SUM)

–40°C = Rx1 (DIFF)

–40°C = Rx1 (SUM)

+110°C = Rx2 (DIFF)

+110°C = Rx2 (SUM)

+25°C = Rx2 (DIFF)

+25°C = Rx2 (SUM)

–40°C = Rx2 (DIFF)

–40°C = Rx2 (SUM)

95

90

85

80

75

70

65

60

55

50

55

IIP2 SUM +110°C

50

45

40

IIP2 SUM +25°C

IIP2 SUM –40°C

IIP2 DIFF +110°C

IIP2 DIFF +25°C

IIP2 DIFF –40°C

3612 3622 3632 3642 3652 3662 3672 3682 3692 3702 3712

4606

4605

4626

4625

4646

4645

4666

4665

4686

4685

4706

4705

SWEPT PASS BAND FREQUENCY (MHz)

Figure 111. Receiver IIP2 Sum and Difference Across Bandwidth vs. Swept

Pass Band Frequency, Receiver Attenuation = 0 dB, LO = 3600 MHz,

Tone 1 = 3602 MHz, Tone 2 Swept, −21 dBm Each

Figure 108. Receiver IIP2 Sum and Difference Across Bandwidth vs. Swept

Pass Band Frequency, Receiver Attenuation = 0 dB, LO = 4600 MHz,

Six Tone Pairs, −21 dBm Each

100

95

90

85

80

75

70

Rx1 +110°C IIP2_SUM_CF

Rx1 +110°C IIP2_DIF_CF

Rx2 +110°C IIP2_SUM_CF

Rx2 +110°C IIP2_DIF_CF

Rx1 +25°C IIP2_SUM_CF

Rx1 +25°C IIP2_DIF_CF

Rx2 +25°C IIP2_SUM_CF

Rx2 +25°C IIP2_DIF_CF

Rx1 –40°C IIP2_SUM_CF

Rx1 –40°C IIP2_DIF_CF

Rx2 –40°C IIP2_SUM_CF

Rx2 –40°C IIP2_DIF_CF

95

90

85

80

75

70

65

60

55

50

40

+110°C = Rx1 (DIFF)

+110°C = Rx1 (SUM)

+25°C = Rx1 (DIFF)

+25°C = Rx1 (SUM)

–40°C = Rx1 (DIFF)

–40°C = Rx1 (SUM)

+110°C = Rx2 (DIFF)

+110°C = Rx2 (SUM)

+25°C = Rx2 (DIFF)

+25°C = Rx2 (SUM)

–40°C = Rx2 (DIFF)

–40°C = Rx2 (SUM)

65

60

55

50

Tone2

0

5

10

15

20

25

30

4612 4622 4632 4642 4652 4662 4672 4682 4692 4702 4712

RECEIVER ATTENUATION

SWEPT PASS BAND FREQUENCY (MHz)

Figure 112. Receiver IIP2 Sum and Difference Across Bandwidth vs. Swept

Pass Band Frequency, Receiver Attenuation = 0 dB, LO = 4600 MHz,

Tone 1 = 4602 MHz, Tone 2 Swept, −21 dBm Each, IIP2_SUM_CF and

IIP2_DIF_CF Indicate Sum and Difference Products

Figure 109. Receiver IIP2 vs. Receiver Attenuation, LO = 3600 MHz,

Tone 1 = 4602 MHz and Tone 2 = 4692 MHz, −21 dBm Plus Attenuation

Rev. 0 | Page 34 of 68

Data Sheet

ADRV9008-1

45

40

35

30

25

20

15

10

5

30

25

20

15

10

5

Rx1 = +110°C

Rx1 = +25°C

Rx1 = –40°C

Rx2 = +110°C

Rx2 = +25°C

Rx2 = –40°C

Rx1 = +110°C

Rx1 = +25°C

Rx1 = –40°C

Rx2 = +110°C

Rx2 = +25°C

Rx2 = –40°C

0

5

10

15

20

25

30

4605

4625

4626

4645

4646

4665

4666

4685

4686

4705

4706

ATTENUATION (dB)

4606

RECEIVER ATTENUATION (dB)

Figure 113. Receiver IIP3 vs. Attenuation, LO = 3600 MHz, Tone 1 = 3695 MHz,

Tone 2 = 3696 MHz, −21 dBm Plus Attenuation

Figure 116. Receiver IIP3 vs. Receiver Attenuation, Receiver Attenuation = 0 dB,

LO = 4600 MHz, Tone 2 = Tone 1 + 1 MHz,

−21 dBm Each, Swept Across Pass Band

50

45

40

35

30

25

45

40

35

30

25

20

Rx1 = +110°C

Rx1 = +25°C

Rx1 = –40°C

Rx2 = +110°C

Rx2 = +25°C

Rx2 = –40°C

15

10

5

Rx1 = +25°C

Rx1 = –40°C

Rx2 = +110°C

Rx2 = +25°C

Rx2 = –40°C

10

5

0

5

10

15

20

25

30

0

5

10

15

20

25

30

RECEIVER ATTENUATION (dB)

TONE 1 = 4695MHz TONE 2 = 4696MHz

RECEIVER ATTENUATION SWEPT (dB)

Figure 117. Receiver IIP3 vs. Receiver Attenuation, LO = 3600 MHz, Tone 1 =

3602 MHz, Tone 2 = 3692 MHz, −21 dBm Plus Attenuation

Figure 114. Receiver IIP3 vs. Receiver Attenuation Swept, LO = 4600 MHz,

Tone 1 = 4695 MHz, Tone 2 = 4696 MHz, −21 dBm Plus Attenuation

50

40

30

25

20

15

Rx1 = +110°C

20

Rx1 = +110°C

10

Rx1 = +25°C

Rx1 = –40°C

Rx2 = +110°C

Rx2 = +25°C

Rx2 = –40°C

Rx1 = +25°C

Rx1 = –40°C

Rx2 = +110°C

10

5

Rx2 = +25°C

Rx2 = –40°C

0

3605

3606

0

5

10

15

20

25

30

3625

3626

3645

3646

3665

3666

3685

3686

3705

3706

RECEIVER ATTENUATION (dB)

Figure 118. Receiver IIP3 vs. Receiver Attenuation, LO = 4600 MHz,

Tone 1 = 4602 MHz, Tone 2 = 4692 MHz, −21 dBm Plus Attenuation

Figure 115. Receiver IIP3 Across Bandwidth, Receiver Attenuation = 0 dB, LO =

3600 MHz, Tone 2 = Tone 1 + 1 MHz, −21 dBm Each,

Swept Across Pass Band

Rev. 0 | Page 35 of 68

ADRV9008-1

Data Sheet

35

30

25

20

15

0

–20

+110°C

+25°C

–40°C

–40

–60

Rx1 = +110°C

–80

Rx1 = +25°C

Rx1 = –40°C

Rx2 = +110°C

Rx2 = +25°C

Rx2 = –40°C

10

5

–100

0

3612

–120

3632

3652

3672

3692

3712

–100

–75

–50

–25

0

25

50

75

100

SWEPT PASS BAND FREQUENCY (MHz)

BASEBAND FREQUENCY OFFSET (MHz)

Figure 119. Receiver IIP3 Across Bandwidth vs. Swept Pass Band Frequency,

Receiver Attenuation = 0 dB, LO = 3600 MHz, Tone 1 = 3602 MHz, Tone 2 Swept

Across Pass Band, −21 dBm Each

Figure 122. Receiver Image vs. Baseband Frequency Offset, Attenuation =

0 dB, RF Bandwidth = 200 MHz, Tracking Calibration Active,

Sample Rate = 245.76 MSPS, LO = 4600 MHz

35

30

25

20

0

+110°C

+25°C

–40°C

–20

–40

–60

–80

15

Rx1 = +110°C

Rx1 = +25°C

Rx1 = –40°C

Rx2 = +110°C

Rx2 = +25°C

Rx2 = –40°C

10

5

–100

–120

0

4612

4632

4652

4672

4692

4712

0

5

10

15

20

25

30

SWEPT PASS BAND FREQUENCY (MHz)

ATTENUATOR SETTING (dB)

Figure 123. Receiver Image vs. Attenuator Setting, RF Bandwidth = 200 MHz,

Tracking Calibration Active, Sample Rate = 245.76 MSPS,

LO = 3600 MHz, Baseband Frequency= 10 MHz

Figure 120. Receiver IIP3 Across Bandwidth vs. Swept Pass Band Frequency,

Receiver Attenuation = 0 dB, LO = 4600 MHz,

Tone 1 = 4602 MHz, Tone 2 Swept Across Pass Band, −21 dBm Each

0

+110°C

+25°C

–40°C

+25°C

–40°C

–20

–40

–60

–80

–60

–80

–100

–120

–100

–120

–100

–75

–50

–25

0

25

50

75

100

0

5

10

15

20

25

30

BASEBAND FREQUENCY OFFSET (MHz)

ATTENUATOR SETTING (dB)

Figure 124. Receiver Image vs. Attenuator Setting, RF Bandwidth = 200 MHz,

Tracking Calibration Active, Sample Rate = 245.76 MSPS,

LO = 4600 MHz, Baseband Frequency = 10 MHz

Figure 121. Receiver Image vs. Baseband Frequency Offset, Attenuation =

0 dB, RF Bandwidth = 200 MHz, Tracking Calibration Active,

Sample Rate = 245.76 MSPS, LO = 3600 MHz

Rev. 0 | Page 36 of 68

Data Sheet

ADRV9008-1

25

20

15

10

5

0.5

0.4

+110°C

+25°C

–40°C

+110°C

+25°C

–40°C

0.3

0.2

0.1

0

–0.1

–0.2

–0.3

–0.4

–0.5

0

–5

–10

–15

0

5

10

15

20

25

30

0

5

10

15

20

25

30

RECEIVER ATTENUATION (dB)

RECEIVER ATTENUATOR SETTING (dB)

Figure 125. Receiver Gain vs. Receiver Attenuation, RF Bandwidth = 20 MHz,

Sample Rate = 245.76 MSPS, LO = 3600 MHz

Figure 128. Receiver Gain Step Error vs. Receiver Attenuator Setting,

LO = 3600 MHz

25

0.5

+110°C

+25°C

–40°C

+110°C

+25°C

–40°C

0.4

0.3

20

15

0.2

10

5

0.1

0

–0.1

–0.2

–0.3

–0.4

–0.5

0

–5

–10

–15

0

5

10

15

20

25

30

0

5

10

15

20

25

30

RECEIVER ATTENUATION (dB)

RECEIVER ATTENUATOR SETTING (dB)

Figure 126. Receiver Gain vs. Receiver Attenuation, RF Bandwidth = 20 MHz,

Sample Rate = 245.76 MSPS, LO = 4600 MHz

Figure 129. Receiver Gain Step Error vs. Receiver Attenuator Setting,

LO = 4600 MHz

24

–50

+110°C

+25°C

–40°C

+110°C

+25°C

–40°C

22

20

18

16

14

12

10

–60

–70

–80

–90

–100

–110

3400

3600

3800

4000

4200

4400

4600

4800

RECEIVER LO FREQUENCY (MHz)

LO FREQUENCY (MHz)

Figure 130. Receiver DC Offset vs. Receiver LO Frequency

Figure 127. Receiver Gain vs. LO Frequency, RF Bandwidth = 200 MHz,

Sample Rate = 245.76 MSPS

Rev. 0 | Page 37 of 68

ADRV9008-1

Data Sheet

–70

–30

–40

+110°C

+25°C

–40°C

–75

–50

–80

–60

–70

–85

–80

–90

–100

–110

–120

–130

–140

–150

–95

ATTN = 0 +110°C

ATTN = 0 +25°C

ATTN = 0 –40°C

ATTN = 15 +110°C

ATTN = 15 +25°C

ATTN = 15 –40°C

–100

–105

–110

0

5

10

15

20

25

30

–60

–40

–20

0

20

40

60

RECEIVER ATTENUATOR SETTING (dB)

BASEBAND FREQUENCY OFFSET AND ATTENUATION (MHz)

Figure 131. Receiver DC Offset vs. Receiver Attenuator Setting, LO = 3600 MHz

Figure 134. Receiver HD2, Left vs. Baseband Frequency Offset and

Attenuation, Tone Level = −15 dBm at Attenuation = 0 dB, X-Axis =

Baseband Frequency Offset of the Fundamental Tone, Not the Frequency of

the HD2 Product (HD2 Product = 2× the Baseband Frequency), HD2

Canceller Disabled, LO = 4600 MHz

–70

10

Rx1 = +110°C (RIGHT)

Rx1 = +110°C (LEFT)

Rx1 = +25°C (RIGHT)

Rx1 = +25°C (LEFT)

Rx1 = –40°C (RIGHT)

Rx1 = –40°C (LEFT)

Rx2 = +110°C (RIGHT)

Rx2 = +110°C (LEFT)

Rx2 = +25°C (RIGHT)

Rx2 = +25°C (LEFT)

Rx2 = –40°C (RIGHT)

Rx2 = –40°C (LEFT)

+110°C

+25°C

–40°C

–75

–80

–10

–30

–85

–90

–50

–70

–95

–90

–100

–105

–110

–130

–150

0

5

10

15

20

25

30

–50

–40

–30

–20

–10

3600

FREQUENCY OFFSET FROM LO (MHz)

10

20

30

40

50

RECEIVER ATTENUATOR SETTING (dB)

Figure 132. Receiver DC Offset vs. Receiver Attenuator Setting,

LO = 4600 MHz

Figure 135. Receiver HD3, Left and Right vs. Frequency Offset from LO, Tone

Level = −15 dBm at Attenuation = 0 dB, LO = 3600 MHz

–30

–40

–50

–60

–70

–80

–90

–100

10

Rx1 = +110°C (RIGHT)

Rx1 = +110°C (LEFT)

Rx1 = +25°C (RIGHT)

Rx1 = +25°C (LEFT)

Rx1 = –40°C (RIGHT)

Rx1 = –40°C (LEFT)

Rx2 = +110°C (RIGHT)

Rx2 = +110°C (LEFT)

Rx2 = +25°C (RIGHT)

Rx2 = +25°C (LEFT)

Rx2 = –40°C (RIGHT)

Rx2 = –40°C (LEFT)

–10

–30

–50

–70

–90

–110

–120

–130

–140

–150

ATTN = 0 +110°C

ATTN = 0 +25°C

ATTN = 0 –40°C

ATTN = 15 +110°C

ATTN = 15 +25°C

ATTN = 15 –40°C

–110

–130

–150

–60

–40

–20

0

20

40

60

–50

–40

–30

–20

–10

4600

FREQUENCY OFFSET FROM LO AND ATTENUATION (MHz)

10

20

30

40

50

BASEBAND FREQUENCY OFFSET AND ATTENUATION (MHz)

Figure 136. Receiver HD3, Left and Right vs. Frequency Offset from LO and

Attenuation, Tone Level = −15 dBm at Attenuation = 0 dB,

LO = 4600 MHz

Figure 133. Receiver HD2, Left vs. Baseband Frequency Offset and

Attenuation, Tone Level = −15 dBm at Attenuation = 0 dB, X-Axis =

Baseband Frequency Offset of the Fundamental Tone Not the Frequency of

the HD2 Product (HD2 Product = 2× the Baseband Frequency), HD2

Canceller Disabled, LO = 3600 MHz

Rev. 0 | Page 38 of 68

Data Sheet

ADRV9008-1

0

–5

0

10

20

30

40

50

60

70

80

90

Rx1 TO Rx2 ISOLATION

Rx2 TO Rx1 ISOLATION

+110°C

+25°C

–40°C

–10

–15

–20

–25

–30

–35

–40

–45

–50

–65

–55

–45

–35

–25

–15

–5

5

LTE 20MHz RF INPUT POWER (dBm)

LO FREQUENCY (MHz)

Figure 137. Receiver EVM vs. LTE 20 MHz RF Input Power, RF Signal =

LTE 20 MHz, LO = 3600 MHz, Default AGC Settings

Figure 139. Receiver to Receiver Isolation vs. LO Frequency

0

–70

–80

–90

+110°C

+25°C

–40°C

–5

–10

–15

–20

–25

–30

–35

–40

–45

–100

–110

–120

–130

–140

–150

–160

–170

–65

–55

–45

–35

–25

–15

–5

5

100

1k

10k

100k

1M

10M

100M

LTE 20MHz RF INPUT POWER (dBm)

FREQUENCY OFFSET (Hz)

Figure 138. Receiver EVM vs. LTE 20 MHz RF Input Power,

RF Signal = LTE 20 MHz, LO = 4600 MHz, Default AGC Settings

Figure 140. LO Phase Noise vs. Frequency Offset, LO = 3800 MHz, PLL Loop

Bandwidth = 300 kHz, Spectrum Analyzer Limits Far Out Noise

Rev. 0 | Page 39 of 68

ADRV9008-1

Data Sheet

5100 MHz TO 5900 MHz BAND

80

75

70

65

60

55

50

45

40

0

–0.20

–0.40

–0.60

–0.80

–1.00

–1.20

–1.40

–1.60

–1.80

–2.00

IIP2 SUM +110°C

IIP2 SUM +25°C

IIP2 SUM –40°C

IIP2 DIFF +110°C

IIP2 DIFF +25°C

IIP2 DIFF –40°C

5805

5806

5825

5826

5845

5846

5865

5866

5885

5886

5905

5906

5000

5200

5400

5600

5800

6000

SWEPT PASS BAND FREQUENCY (MHz)

LO FREQUENCY (MHz)

Figure 144. Receiver IIP2 Sum and Difference Across Bandwidth vs. Swept

Pass Band Frequency, Receiver Attenuation = 0 dB, LO = 5800 MHz,

Six Tone Pairs, −21 dBm Plus Attenuation Each

Figure 141. Receiver Off Chip Matching Circuit Path Loss vs. LO Frequency

(Simulation), Can Be Used for De-Embedding Performance Data

110

0

Rx1 IIP2 DIFF +110°C

Rx1 IIP2 SUM +110°C

Rx1 IIP2 DIFF +25°C

Rx1 IIP2 SUM +25°C

Rx1 IIP2 DIFF –40°C

Rx1 IIP2 SUM –40°C

+110°C

+25°C

–40°C

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

100

90

80

70

60

50

Rx2 IIP2 DIFF +110°C

Rx2 IIP2 SUM +110°C

Rx2 IIP2 DIFF +25°C

Rx2 IIP2 SUM +25°C

Rx2 IIP2 DIFF –40°C

Rx2 IIP2 SUM –40°C

0

5

10

15

20

25

30

5200

5300

5400

5500

5600

5700

5800

RECEIVER ATTENUATION

RECEIVER LO FREQUENCY (MHz)

Figure 142. Receiver LO Leakage vs. Receiver LO Frequency, 5200 MHz,

5500 MHz, and 5800 MHz, Receiver Attenuation = 0 dB, RF Bandwidth =

200 MHz, Sample Rate = 245.76 MSPS

Figure 145. Receiver IIP2 vs. Receiver Attenuation, LO = 5800 MHz, Tones

Placed at 5802 MHz and 5892 MHz, −21 dBm Plus Attenuation

110

80

IIP2 SUM +110°C

IIP2 SUM +25°C

IIP2 SUM –40°C

Rx1 IIP2 DIFF +110°C

Rx1 IIP2 SUM +110°C

Rx1 IIP2 DIFF +25°C

75

100

Rx1 IIP2 SUM +25°C

IIP2 DIFF +110°C

Rx1 IIP2 DIFF –40°C

Rx1 IIP2 SUM –40°C

IIP2 DIFF +25°C

IIP2 DIFF –40°C

90

70

65

60

80

70

60

50

55

Rx2 IIP2 DIFF +110°C

Rx2 IIP2 SUM +110°C

Rx2 IIP2 DIFF +25°C

Rx2 IIP2 SUM +25°C

Rx2 IIP2 DIFF –40°C

Rx2 IIP2 SUM –40°C

50

45

40

5802 5812 5822 5832 5842 5852 5862 5872 5882 5892 5902

0

2

4

6

8

10 12 14 16 18 20 22 24 26 28 30

ATTENUATION (dB)

5802 5802 5802 5802 5802 5802 5802 5802 5802 5802 5802

SWEPT PASS BAND FREQUENCY (MHz)

Figure 143. Receiver IIP2 vs. Attenuation, LO = 5800 MHz, Tones Placed at

5845 MHz and 5846 MHz, −21 dBm Plus Attenuation

Figure 146. Receiver IIP2 Sum and Difference Across Bandwidth vs. Swept

Pass Band Frequency, Receiver Attenuation = 0 dB, LO = 5800 MHz,

Tone 1 = 5802 MHz, Tone 2 Swept, −21 dBm Each

Rev. 0 | Page 40 of 68

Data Sheet

ADRV9008-1

45

40

35

30

25

20

15

10

5

30

25

20

15

10

5

Rx1 = +110°C

Rx1 = +25°C

Rx1 = –40°C

Rx2 = +110°C

Rx2 = +25°C

Rx2 = –40°C

Rx1 = +110°C

Rx1 = +25°C

Rx1 = –40°C

Rx2 = +110°C

Rx2 = +25°C

Rx2 = –40°C

0

5

10

15

20

25

30

5802 5802 5802 5802 5802 5802 5802 5802 5802 5802 5802 5802

5812 5822 5832 5842 5852 5862 5872 5882 5892 5902 5912 5922

RECEIVER ATTENUATION (dB)

SWEPT PASS BAND FREQUENCY (MHz)

Figure 147. Receiver IIP3 vs. Receiver Attenuation, LO = 5800 MHz, Tone 1 =

5895 MHz, Tone 2 = 5896 MHz, −21 dBm Plus Attenuation

Figure 150. Receiver IIP3 Across Bandwidth vs. Swept Pass Band Frequency,

Receiver Attenuation = 0 dB, LO = 5800 MHz, Tone 1 = 5802 MHz, Tone 2

Swept Across Pass Band, −21 dBm Each

30

–10

Rx1 = +110°C

Rx1 = +25°C

Rx1 = –40°C

Rx2 = +110°C

Rx2 = +25°C

Rx2 = –40°C

+110°C

+25°C

–40°C

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

25

20

15

10

5

0

5805 5815 5825 5835 5845 5855 5865 5875 5888 5895 5905 5915

5806 5816 5826 5836 5846 5856 5866 5876 5886 5896 5906 5916

–100

–75

–50

–25

0

25

50

75

100

SWEPT PASS BAND FREQUENCY (MHz)

BASEBAND FREQUENCY OFFSET (MHz)

Figure 151. Receiver Image vs. Baseband Frequency Offset, Attenuation =

0 dB, RF Bandwidth = 200 MHz, Tracking Calibration Active,

Sample Rate = 245.76 MSPS, LO = 5200 MHz

Figure 148. Receiver IIP3 vs. Swept Pass Band Frequency, Receiver

Attenuation = 0 dB, LO = 5800 MHz, Tone 2 = Tone 1 + 1 MHz, −21 dBm

Each, Swept Across Pass Band

60

–10

Rx1 = +110°C

Rx1 = +25°C

Rx1 = –40°C

Rx2 = +110°C

Rx2 = +25°C

Rx2 = –40°C

+110°C

+25°C

–40°C

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

50

40

30

20

10

0

5

10

15

20

25

30

–100

–75

–50

–25

0

25

50

75

100

RECEIVER ATTENUATION (dB)

BASEBAND FREQUENCY OFFSET (MHz)

Figure 152. Receiver Image vs. Baseband Frequency Offset, Attenuation =

0 dB, RF Bandwidth = 200 MHz, Tracking Calibration Active,

Sample Rate = 245.76 MSPS, LO = 5900 MHz

Figure 149. Receiver IIP3 vs. Receiver Attenuation, LO = 5800 MHz,

Tone 1 = 5802 MHz, Tone 2 = 5892 MHz, −21 dBm Plus Attenuation

Rev. 0 | Page 41 of 68

ADRV9008-1

Data Sheet

0

0.5

0.4

+110°C

+25°C

–40°C

+110°C

+25°C

–40°C

–20

0.3

0.2

–40

0.1

–60

0

–0.1

–0.2

–0.3

–0.4

–0.5

–80

–100

–120

0

2

10

15

20

25

30

0

2

10

15

20

25

30

ATTENUATOR SETTING (dB)

RECEIVER ATTENUATOR SETTING AND TEMPERATURE (dB)

Figure 153. Receiver Image vs. Attenuator Setting, RF Bandwidth = 200 MHz,

Tracking Calibration Active, Sample Rate = 245.76 MSPS,

LO = 5200 MHz, Baseband Frequency = 10 MHz

Figure 156. Receiver Gain Step Error vs. Receiver Attenuator Setting and

Temperature, LO = 5600 MHz

0

0.5

+110°C

+25°C

–40°C

+110°C

+25°C

–40°C

0.4

0.3

–20

0.2

–40

0.1

–60

–80

0

–0.1

–0.2

–0.3

–0.4

–0.5

–100

–120

0

2

10

15

20

25

30

0

2

10

15

20

25

30

ATTENUATOR SETTING (dB)

RECEIVER ATTENUATOR SETTING AND TEMPERATURE (dB)

Figure 154. Receiver Image vs. Attenuator Setting, RF Bandwidth = 200 MHz,

Tracking Calibration Active, Sample Rate = 245.76 MSPS,

LO = 5900MHz, Baseband Frequency = 10 MHz

Figure 157. Receiver Gain Step Error vs. Receiver Attenuator Setting and

Temperature, LO = 6000 MHz

0.5

0.4

+110°C

+25°C

–40°C

0.4

0.3

0.2

0.1

0.2

0

0.1

–0.1

–0.2

–0.3

–0.4

–0.5

0

–0.1

–0.2

–0.3

–0.4

–0.5

MAX OF NORMALIZED I RIPPLE –40°C

MAX OF NORMALIZED I RIPPLE +25°C

MAX OF NORMALIZED I RIPPLE +110°C

MAX OF NORMALIZED Q RIPPLE –40°C

MAX OF NORMALIZED Q RIPPLE +25°C

MAX OF NORMALIZED Q RIPPLE +110°C

–0.6

–0.7

–0.8

–0.9

–1.0

0

2

10

15

20

25

30

RECEIVER ATTENUATOR SETTING AND TEMPERATURE (dB)

BASEBAND FREQUENCY (MHz)

Figure 155. Receiver Gain Step Error vs. Receiver Attenuator Setting and

Temperature, LO = 5200 MHz

Figure 158. Normalized Receiver Baseband Flatness vs. Baseband Frequency

(Receiver Flatness)

Rev. 0 | Page 42 of 68

Data Sheet

ADRV9008-1

–30

–40

–10

–30

Rx2 = +110°C (LEFT)

Rx1 = +110°C (LEFT)

Rx2 = +25°C (LEFT)

Rx1 = +25°C (LEFT)

Rx2 = –40°C (LEFT)

Rx1 = –40°C (LEFT)

Rx2 = +110°C (RIGHT)

Rx1 = +110°C (RIGHT)

Rx2 = +25°C (RIGHT)

Rx1 = +25°C (RIGHT)

Rx2 = –40°C (RIGHT)

Rx1 = –40°C (RIGHT)

–50

–60

–50

–70

–80

–70

–90

–100

–110

–120

–130

–140

–150

ATTN = 15 +110°C

ATTN = 15 +25°C

ATTN = 15 –40°C

ATTN = 0 +110°C

ATTN = 0 +25°C

ATTN = 0 –40°C

–110

–130

–150

–60

–40

–20

0

20

40

60

–50

–40

–30

–20

–10

5900

FREQUENCY OFFSET FROM LO (MHz)

10

20

30

40

50

BASEBAND FREQUENCY OFFSET (MHz)

Figure 162. Receiver HD3, Left and Right vs. Frequency Offset from LO, Tone

Level = −15 dBm at Attenuation = 0 dB, LO = 5900 MHz

Figure 159. Receiver HD2 Left vs. Baseband Frequency Offset, Tone Level =

−15 dBm at Attenuation = 0 dB, X-Axis = Baseband Frequency Offset of the

Fundamental Tone Not the Frequency of the HD2 Product (HD2 Product = 2×

the Baseband Frequency), HD2 Canceller Disabled,

LO = 5200 MHz

0

–30

–40

–50

–60

–70

–80

–90

–100

+110°C

+25°C

–40°C

–5

–10

–15

–20

–25

–30

–35

–40

–45

–110

–120

–130

–140

–150

ATTN = 15 +110°C

ATTN = 15 +25°C

ATTN = 15 –40°C

ATTN = 0 +110°C

ATTN = 0 +25°C

ATTN = 0 –40°C

–65

–55

–45

–35

–25

–15

–5

5

–60

–40

–20

0

20

40

60

LTE 20MHz RF INPUT POWER (dBm)

BASEBAND FREQUENCY OFFSET (MHz)

Figure 163. Receiver EVM vs. LTE 20 MHz RF Input Power, LTE 20 MHz RF

Signal, LO = 5200 MHz, Default AGC Settings

Figure 160. Receiver HD2 Left vs. Baseband Frequency Offset, Tone Level =

−15 dBm at Attenuation = 0 dB, X-Axis = Baseband Frequency Offset of the

Fundamental Tone Not the Frequency of the HD2 Product (HD2 Product = 2×

the Baseband Frequency), HD2 Canceller Disabled,

LO = 5900 MHz

0

–10

Rx2 = +110°C (LEFT)

Rx1 = +110°C (LEFT)

Rx2 = +25°C (LEFT)

Rx1 = +25°C (LEFT)

Rx2 = –40°C (LEFT)

Rx1 = –40°C (LEFT)

Rx2 = +110°C (RIGHT)

Rx1 = +110°C (RIGHT)

Rx2 = +25°C (RIGHT)

Rx1 = +25°C (RIGHT)

Rx2 = –40°C (RIGHT)

Rx1 = –40°C (RIGHT)

+110°C

+25°C

–40°C

–5

–10

–30

–50

–15

–20

–25

–30

–35

–40

–45

–70

–90

–110

–130

–150

–65

–55

–45

–35

–25

–15

–5

5

–50

–40

–30

–20

–10

5200

FREQUENCY OFFSET FROM LO (MHz)

10

20

30

40

50

LTE 20MHz RF INPUT POWER (dBm)

Figure 161. Receiver HD3, Left and Right vs. Frequency Offset from LO, Tone

Level = −15 dBm at Attenuation = 0 dB, LO = 5200 MHz

Figure 164. Receiver EVM vs. LTE 20 MHz RF Input Power, LTE 20 MHz RF

Signal, LO = 5500 MHz, Default AGC Settings

Rev. 0 | Page 43 of 68

ADRV9008-1

Data Sheet

0

–20

–40

+110°C

+25°C

–40°C

–5

–10

–15

–20

–25

–30

–35

–40

–45

–60

–80

–100

–120

–140

–160

–180

100

1k

10k

100k

1M

10M

100M

–65

–55

–45

–35

–25

–15

–5

5

LTE 20MHz RF INPUT POWER (dBm)

FREQUENCY OFFSET (Hz)

Figure 165. Receiver EVM vs. LTE 20 MHz RF Input Power, LTE 20 MHz RF

Signal, LO = 5800 MHz, Default AGC Settings

Figure 167. LO Phase Noise vs. Frequency Offset, LO = 5900 MHz, PLL Loop

Bandwidth > 300 kHz, Spectrum Analyzer Limits Far Out Noise

0

Rx1 TO Rx2

Rx2 TO Rx1

10

20

30

40

50

60

70

80

90

100

5000 5100 5200 5300 5400 5500 5600 5700 5800 5900 6000

LO FREQUENCY (MHz)

Figure 166. Receiver to Receiver Isolation vs. LO Frequency

Rev. 0 | Page 44 of 68

Data Sheet

ADRV9008-1

RECEIVER INPUT IMPEDANCE

RX PORT SIMULATED IMPEDANCE: SEDZ

M20

M15

FREQUENCY = 3.000GHz

S (1,1) = 0.267 / –64.650

FREQUENCY = 100.0MHz

S (1,1) = 0.390 / –1.819

IMPEDANCE = 113.933 – j3.331

IMPEDANCE = 55.102 – j28.685

M21

M16

FREQUENCY = 4.000GHz

S (1,1) = 0.186 / –104.336

IMPEDANCE = 42.821 – j16.026

FREQUENCY = 300.0MHz

S (1,1) = 0.390 / –5.495

IMPEDANCE = 112.803 – j9.931

M23

M22

M17

M15

M16

M17

M18

FREQUENCY = 5.000GHz

S (1,1) = 0.164 / –173.106

IMPEDANCE = 35.977 – j1.455

FREQUENCY = 500.0MHz

S (1,1) = 0.388 / –9.198

IMPEDANCE = 110.398 – j16.107

M22

M21

M19

M20

M23

M18

FREQUENCY = 6.000GHz

S (1,1) = 0.266 / 130.063

IMPEDANCE = 32.890 + j14.399

FREQUENCY = 1.000GHz

S (1,1) = 0.377 / –18.643

IMPEDANCE = 100.377 – j28.250

M19

FREQUENCY = 2.000GHz

S (1,1) = 0.336 / –39.123

IMPEDANCE = 74.966 – j35.800

FREQUENCY (0Hz TO 6.000GHz)

Figure 168. Receiver Input Impedance, Series Equivalent Differential Impedance (SEDZ)

Rev. 0 | Page 45 of 68

ADRV9008-1

Data Sheet

TERMINOLOGY

Large Signal Bandwidth

Backoff

Large signal bandwidth, otherwise known as instantaneous

bandwidth or signal bandwidth, is the bandwidth over which

there are large signals. For example, for Band 42 LTE, the large

signal bandwidth is 200 MHz.

Backoff is the difference (in dB) between full-scale signal power

and the rms signal power.

P_HIGH

P_HIGHis the largest signal that can be applied without overloading

Occupied Bandwidth

the ADC for the receiver input. This input level results in slightly

less than full scale at the digital output because of the nature of the

continuous-time, Σ-Δ ADCs, which, for example, exhibit a soft

overload in contrast to the hard clipping of pipeline ADCs.

Occupied bandwidth is the total bandwidth of the active signals.

For example, three 20 MHz carriers have a 60 MHz occupied

bandwidth, regardless of the placement of the carriers within

the large signal bandwidth.

Rev. 0 | Page 46 of 68

Data Sheet

ADRV9008-1

THEORY OF OPERATION

The ADRV9008-1 is a highly integrated, RF, agile receiver

subsystem capable of configuration for a wide range of

applications. The device integrates all RF, mixed-signal, and

digital blocks necessary to provide all receiver functions in a

single device. Programmability allows the receiver to be adapted

for use in many TDD and 3G/4G/5G cellular standards. The

ADRV9008-1 contains two high speed links each for the receiver

chain. These links are JESD204B, Subclass 1 compliant.

Clock PLL

The ADRV9008-1 contains a PLL synthesizer that generates

all the baseband related clock signals and serialization/

deserialization (SERDES) clocks. This PLL is programmed

based on the data rate and sample rate requirements of the

system.

SPI

The ADRV9008-1 uses an SPI interface to communicate with

the BBP. This interface can be configured as a 4-wire interface

with a dedicated receiver port and transmitter port. The interface

can also be configured as a 3-wire interface with a bidirectional

data communications port. This bus allows the BBP to set all

device control parameters using a simple address data serial bus

protocol.

The ADRV9008-1 also provides tracking correction of dc offset

QEC errors to maintain high performance under varying temp-

eratures and input signal conditions. The device also includes test

modes that allow system designers to debug designs during

prototyping and optimize radio configurations.

RECEIVERS

The ADRV9008-1 receivers contain all the blocks necessary to

receive RF signals and convert them to digital data used by a BBP.

Each receiver can be configured as a direct conversion system

that supports up to a 200 MHz bandwidth. Each receiver contains

a programmable attenuator stage and matched I and Q mixers

that downconvert received signals to baseband for digitization.

Write commands follow a 24-bit format. The first five bits set

the bus direction and the number of bytes to transfer. The next

11 bits set the address where the data is written. The final eight

bits are the data transferred to the specific register address.

Read commands follow a similar format with the exception that

the first 16 bits are transferred on the SDIO pin and the final eight

bits are read from the ADRV9008-1, either on the SDO pin in

4-wire mode or on the SDIO pin in 3-wire mode.

Achieve gain control by using the on-chip AGC or by allowing

the BBP to make gain adjustments in a manual gain control

mode. Optimize performance by mapping each gain control

setting to specific attenuation levels at each adjustable gain block

in the receiver signal path. Additionally, each channel contains

independent receive signal strength indicator (RSSI) measurement

capability, dc offset tracking, and all circuitry necessary for self

calibration.

JTAG BOUNDARY SCAN

The ADRV9008-1 provides support for the JTAG boundary

scan. There are five dual-function pins associated with the

JTAG interface. These pins, listed in Figure 5, are used to access

the on-chip test access port. To enable the JTAG functionality,

set the GPIO_3 pin through the GPIO_0 pin to 1001 and pull

the TEST pin high.

The receivers include ADCs and adjustable sample rates that

produce data streams from the received signals. The signals can

be conditioned further by a series of decimation filters and a

programmable FIR filter with additional decimation settings. The

sample rate of each digital filter block is adjustable by changing

decimation factors to produce the desired output data rate.

POWER SUPPLY SEQUENCE

The ADRV9008-1 requires a specific power-up sequence to

avoid undesired power-up currents. In the optimal power-up

sequence, the VDDD1P3_DIG supply and the VDDA1P3_x supply

(VDDA1P3_x includes all 1.3 V domains) power up together

first. If these supplies cannot be powered up simultaneously, then

the VDDD1P3_DIG supply must power up first. Power up the

VDDA_3P3 supply, the VDDA1P8_x supply, and the

VDDA1P3_SER supply after powering up the 1.3 V supplies. The

VDD_INTERFACE supply can be powered up at any time. No

device damage occurs if this sequence is not followed, but failing to

follow this sequence may result in higher than expected power-up

CLOCK INPUT

The ADRV9008-1 requires a differential clock connected to the

REF_CLK_IN_x pins. The frequency of the clock input must be

between 10 MHz and 1000 MHz, and the frequency must have

low phase noise because this signal generates the RF LO and

internal sampling clocks.

SYNTHESIZERS

RF PLL

RESET

currents. Toggle the

signal after the power stabilizes, prior

to configuration. The power-down sequence is not critical. If a

power-down sequence is followed, remove the VDDD1P3_DIG

supply last to avoid any back biasing of the digital control lines.

The ADRV9008-1 contains a fractional-N PLL to generate the

RF LO for the signal paths. The PLL incorporates an internal

VCO and loop filter, requiring no external components. The

LOs on multiple chips can be phase synchronized to support

active antenna systems and beam forming applications.

Rev. 0 | Page 47 of 68

ADRV9008-1

Data Sheet

enabled, the auxiliary ADC is free running. The SPI reads provide

the last value latched at the ADC output. The auxiliary ADC can

also be multiplexed to a built in, diode-based temperature sensor.

GPIO_x PINS

The ADRV9008-1 provides nineteen 1.8 V to 2.5 V GPIO signals

that can be configured for numerous functions. When configured

as outputs, certain pins can provide real-time signal information to

the BBP, allowing the BBP to determine receiver performance. A

pointer register selects the information that is output to these pins.

Signals used for manual gain mode, calibration flags, state machine

states, and various receiver parameters are among the outputs that

can be monitored on these pins. Additionally, certain pins can be

configured as inputs and used for various functions, such as setting

the receiver gain in real time.

Auxiliary DAC x

The ADRV9008-1 contains 10 identical auxiliary DACs that can

be used for bias or other system functionality. The auxiliary

DACs are 10 bits, have an output voltage range of approximately

0.7 V to VDDA_3P3 − 0.3 V, and have a current drive of 10 mA.

JESD204B DATA INTERFACE

The digital data interface for the ADRV9008-1 uses JEDEC

JESD204B Subclass 1. The serial interface operates at speeds of

up to 12.288 Gbps. The benefits of the JESD204B interface

include a reduction in required board area for data interface

routing, resulting in smaller total system size. Four high speed

serial lanes are provided for the receiver. The ADRV9008-1

supports single-lane and dual-lane interfaces and supports fixed

and floating point data formats for receiver.

Twelve 3.3 V GPIO_x pins are also included on the device.

These pins provide control signals to external components.

AUXILIARY CONVERTERS

AUXADC_x

The ADRV9008-1 contains an auxiliary ADC that is multiplexed to

four input pins (AUXADC_x). The auxiliary ADC is 12 bits with

an input voltage range of 0.05 V to VDDA_3P3 − 0.05 V. When

Table 6. Example Receiver Interface Rates (Other Output Rates, Bandwidths, and JESD204B Lanes Also Supported)

Single-Channel Operation Dual-Channel Operation

JESD204B Lane Rate JESD204B Number JESD204B Lane Rate JESD204B Number

Output Rate

(MSPS)

Bandwidth (MHz)

(Mbps)

4915.2

6144

9830.4

4915.2

of Lanes

(Mbps)

9830.4

12288

9830.4

4915.2

of Lanes

80

122.88

153.6

245.76

1

2

1

2

4

100

200

FIR

FILTER

(DECIMATION

1, 2, 4)

RECEIVE

HALF-BAND

FILTER

3

RECEIVE

HALF-BAND

FILTER

2

RECEIVE

HALF-BAND

FILTER

1

DC

DIGITAL

GAIN

JESD204B

ADC

ESTIMATION

Figure 169. Receiver Datapath Filter Implementation

Rev. 0 | Page 48 of 68

Data Sheet

ADRV9008-1

APPLICATIONS INFORMATION

PCB LAYOUT AND POWER SUPPLY

RECOMMENDATIONS

13 are crucial to maintaining the RF signal integrity and,

ultimately, the ADRV9008-1 performance. Layer 3 and Layer 12

are used to route power supply domains. To keep the RF section

of the ADRV9008-1 isolated from the fast transients of the digital

section, the JESD204B interface lines are routed on Layer 5 and

Layer 10. These layers have impedance control set to a 100 Ω

differential. The remaining digital lines from ADRV9008-1 are

routed on Inner Layer 7 and Inner Layer 8. RF traces on the outer

layers must be a controlled impedance for optimal performance

of the device. The inner layers in this board use 0.5 ounce

copper or 1 ounce copper. The outer layers use 1.5 ounce

copper so that the RF traces are less prone to pealing. Ground

planes on this board are full copper floods with no splits except

for vias, through-hole components, and isolation structures.

The ground planes must route entirely to the edge of the PCB

under the Surface-Mount Type A (SMA) connectors to

maintain signal launch integrity. Power planes can be pulled

back from the board edge to decrease the risk of shorting from

the board edge.

Overview

The ADRV9008-1 is a highly integrated, RF, agile receiver with

significant signal conditioning integrated on one chip. Due to

the increased complexity of the device and its high pin count,

careful PCB layout is important to achieve optimal performance.

This data sheet provides a checklist of issues to look for and

guidelines on how to optimize the PCB to mitigate performance

issues. The goal of this data sheet is to help achieve optimal

performance of the ADRV9008-1 while reducing board layout

effort. This data sheet assumes that the reader is an experienced

analog and RF engineer with an understanding of RF PCB layout

and RF transmission lines. This data sheet discusses the following

issues and provides guidelines for system designers to achieve

optimal performance of the ADRV9008-1:

•

PCB material and stackup selection

Fanout and trace space layout guidelines

Component placement and routing guidelines

RF and JESD204B transmission line layout

Isolation techniques used on the ADRV9008-1W/PCBZ

Power management considerations

Unused pin instructions

PCB MATERIAL AND STACKUP SELECTION

Figure 170 shows the PCB stackup used for the ADRV9008-

1W/PCBZ. Table 7 and Table 8 list the single-ended and

differential impedance for the stackup shown in Figure 170. The

dielectric material used on the top and the bottom layers is 8

mil Rogers 4350B. The remaining dielectric layers are FR4-370

HR. The board design uses the Rogers laminate for the top and

the bottom layers for the low loss tangent at high frequencies.

The ground planes under the Rogers laminate (Layer 2 and

Layer 13) are the reference planes for the transmission lines

routed on the outer surfaces. These layers are solid copper

planes without any splits under the RF traces. Layer 2 and Layer

Figure 170. ADRV9008-1W/PCBZ Trace Impedance and Stackup

Rev. 0 | Page 49 of 68

ADRV9008-1

Data Sheet

Table 7. Evaluation Board Single-Ended Impedance and Stackup¹

Single-

Ended

Reference

Board

Copper Starting

Layer (%) Copper (oz.) Copper (oz.) Impedance

Designed Trace

Single-Ended

(Inches)

Finished Trace

Single-Ended

(Inches)

Finished

Single-Ended

Calculated

Impedance (Ω) Layers

1

2

3

4

5

6

7

8

N/A

65

50

65

50

65

50

65

50

65

50

65

0.5

1

0.5

1

0.5

1

0.5

1

0.5

1

0.5

1.71

1

0.5

1

0.5

1

50 Ω 10%

N/A

50 Ω 10%

N/A

50 Ω 10%

N/A

50 Ω 10%

N/A

0.0155

N/A

0.0045

N/A

0.0049

N/A

0.0045

N/A

0.0135

N/A

0.0042

N/A

0.0039

N/A

0.0039

N/A

49.97

N/A

49.79

N/A

50.05

N/A

49.88

N/A

2

N/A

4, 6

N/A

6, 9

N/A

9, 11

N/A

13

9

10

11

12

13

14

1

1.64

N/A

50 Ω 10%

N/A

0.0155

N/A

0.0135

N/A

49.97

¹N/A means not applicable.

Table 8. Evaluation Board Differential Impedance and Stackup¹

Gap Differential

Designed for Designed

Trace (Inches) Trace (Inches)

Gap Differential

for Finished

Trace (Inches) Trace (Inches)

Differential

Layer Impedance

Finished

Calculated

Differential

Reference Layers

Impedance (Ω)

99.55

50.11

N/A

99.95

N/A

100.51

N/A

100.80

N/A

1

100 Ω 10%

50 Ω 10%

N/A¹

0.008

0.0032

N/A

0.006

0.004

N/A

0.007

0.0304

N/A

0.007

0.0056

N/A

2

N/A

4, 6

N/A

6, 9

N/A

9, 11

N/A

13

3

N/A

4

N/A

5

6

100 Ω 10%

N/A

0.0036

N/A

0.0064

N/A

0.0034

N/A

0.0065

N/A

7

8

9

100 Ω 10%

N/A

0.0036

0.0038

N/A

0.0064

0.0062

N/A

0.0034

N/A

0.0066

N/A

10

11

12

13

14

100 Ω 10%

N/A

100 Ω 10%

50 Ω 10%

0.0036

N/A

0.008

0.032

0.0064

N/A

0.006

N/A

0.003

N/A

0.007

0.004

0.007

N/A

0.007

N/A

99.55

50.11

13

¹N/A means not applicable.

Rev. 0 | Page 50 of 68

Data Sheet

ADRV9008-1

The JESD204B interface signals are routed on two signal layers

that use impedance control (Layer 5 and Layer 10). The spacing

between the BGA pads is 17.5 mil. After the signal is on the inner

layers, a 3.6 mil trace (50 Ω) connects the JESD204B signal to the

field programmable gate array (FPGA) mezzanine card (FMC)

connector. The recommended BGA land pad size is 15 mil.

FANOUT AND TRACE SPACE GUIDELINES

The ADRV9008-1 uses a 196-ball chip scale ball grid array

(CSP_BGA), 12 mm × 12 mm package. The pitch between the

pins is 0.8 mm. This small pitch makes it impractical to route all

signals on a single layer. RF pins are placed on the outer edges

of the ADRV9008-1 package. The location of the pins helps route

the critical signals without a fanout via. Each digital signal is

routed from the BGA pad using a 4.5 mil trace. The trace is

connected to the BGA using a via in the pad structure. The signals

are buried in the inner layers of the board for routing to other parts

of the system.

Figure 171 shows the fanout scheme of the ADRV9008-1W/PCBZ.

As mentioned before, the ADRV9008-1W/PCBZ uses a via in

the pad technique. This routing approach can be used for the

ADRV9008-1 if there are no issues with manufacturing

capabilities.

4.5mil TRACE

AIR GAP = 17.5mil

JESD204B INTERFACE

TRACE WIDTH = 3.6mil

PAD SIZE = 15mil

VIA SIZE = 14mil

Figure 171. Trace Fanout Scheme on the ADRV9008-1W/PCBZ (PCB Layer Top and Layer 5 Enabled)

Rev. 0 | Page 51 of 68

ADRV9008-1

Data Sheet

Figure 170 shows the general directions in which each of the

signals must be routed so that they can be properly isolated

from noisy signals.

COMPONENT PLACEMENT AND ROUTING

GUIDELINES

The ADRV9008-1 receiver requires few external components to

function, but those that are used require careful placement and

routing to optimize performance. This section provides a

checklist for properly placing and routing critical signals and

components.

The receiver baluns and the matching circuits affect the overall

RF performance of the ADRV9008-1 receiver. Make every effort

to optimize the component selection and placement to avoid

performance degradation. The RF Routing Guidelines section

describes proper matching circuit placement and routing in

more detail. Refer to the RF Port Interface Information section

for more information.

Signals with Highest Routing Priority

RF lines and JESD204B interface signals are the signals that are

most critical and must be routed with the highest priority.

To achieve the desired level of isolation between RF signal paths,

use the technique described in the Isolation Techniques Used on

the ADRV9008-1W/PCBZ section in customer designs.

VSSA

RX2_IN+

VSSA

RX2_IN–

VSSA

RX1_IN+

VSSA

RX1_IN–

VSSA

VDDA1P3_

RX_RF

RF_EXT_

LO_I/O–

RF_EXT_

LO_I/O+

VDDA1P3_

AUX_VCO_

LDO

VDDA1P3_

RF_VCO_LDO

VDDA1P3_RF_

VCO_LDO

VDDA1P1_

RF_VCO

VDDA1P3_

RF_LO

GPIO_3p3_0

GPIO_3p3_1

GPIO_3p3_2

VSSA

GPIO_3p3_3

GPIO_3p3_4

GPIO_3p3_5

VSSA

VDDA1P3_RX

VSSA

VDDA_3P3

GPIO_3p3_9

GPIO_3p3_8

GPIO_3p3_7

VSSA

RBIAS

VDDA1P1_

AUX_VCO

VSSA

GPIO_3p3_10

GPIO_3p3_11

VSSA

AUX_SYNTH_

OUT

GPIO_3p3_6

AUXADC_0

VSSA

VDDA1P8_BB VDDA1P3_BB

REF_CLK_IN+

AUXADC_3

AUXADC_2

VSSA

VDDA1P8_AN

REF_CLK_IN–

VSSA

AUXADC_1

VSSA

SDO

VSSA

VDDA1P3_

CLOCK_

SYNTH

VDDA1P3_

RF_SYNTH

RF_SYNTH_

VTUNE

VDDA1P3_

AUX_SYNTH

VSSA

DNC

VSSA

SDIO

SCLK

GPIO_12

GPIO_13

GPIO_14

GPIO_15

GPIO_16

GPIO_11

GPIO_10

GPIO_9

VSSA

DNC

GP_

INTERRUPT

DNC

VSSA

GPIO_18

SYSREF_IN+

SYNCIN1–

SYNCIN0–

SERDOUT3–

VSSA

RESET

TEST

VSSA

DNC

GPIO_2

GPIO_1

GPIO_0

VSSA

SYSREF_IN–

SYNCIN1+

SYNCIN0+

SERDOUT3+

SERDOUT1–

GPIO_5

GPIO_6

GPIO_4

GPIO_7

VSSD

CS

VSSA

GPIO_3

VSSD

VDDD1P3_

DIG

VDDA1P3_

SER

VDDA1P3_

SER

VDDD1P3_

DIG

VSSA

VSSD

GPIO_17

GPIO_8

VDDA1P1_

CLOCK_VCO

VDD_

INTERFACE

VDDA1P3_

SER

VDDA1P3_

SER

VSSA

RX1_ENABLE

SERDOUT2–

SERDOUT1+

RX2_ENABLE

VSSA

VSSD

VDDA1P3_

CLOCK_

VCO_LDO

VDDA1P3_

SER

VDDA1P3_

SER

VDDA1P3_

SER

VDDA1P3_

SER

VDDA1P3_

SER

VDDA1P3_

SER

VSSA

SERDOUT2+

SERDOUT0–

VSSA

AUX_SYNTH_

VTUNE

VDDA1P3_

SER

VDDA1P3_

SER

VDDA1P3_

SER

VDDA1P3_

SER

VDDA1P3_

SER

VDDA1P3_

SER

SERDOUT0+

VSSA

Figure 172. RF Input/Output, REF_CLK_IN , and JESD204B Signal Routing Guidelines

Rev. 0 | Page 52 of 68

Data Sheet

ADRV9008-1

Figure 173 shows placement for ac coupling capacitors and a 100 Ω

termination resistor near the ADRV9008-1 REF_CLK_IN pins.

Shield the traces with ground flooding that is surrounded with vias

staggered along the edge of the trace pair. The trace pair creates

a shielded channel that shields the reference clock from any

interference from other signals. Refer to the ADRV9008-1W/PCBZ

layout and board support files included with the evaluation board

software for exact details.

The JESD204B Trace Routing Recommendations section

outlines recommendations for JESD204B interface routing.

Provide appropriate isolation between interface differential

pairs. The Isolation Between JESD204B Lines section provides

guidelines for optimizing isolation.

The RF_EXT_LO_I/O− pin (B7) and RF_EXT_LO_I/O+ pin

(B8) on the ADRV9008-1 are internally dc biased. If an external

LO is used, connect the LO to the device via ac coupling capacitors.

Route the JESD204B interface at the beginning of the PCB

design and with the same priority as the RF signals.

AC COUPLING

CAPS

100ΩTERMINATION

RESISTOR

TO

BGA BALLS

Figure 173. REF_CLK_IN Routing Recommendation

Rev. 0 | Page 53 of 68

ADRV9008-1

Data Sheet

Signals with Second Routing Priority

When the recommendation is to use a trace to connect power to

a particular domain, ensure that this trace is surrounded by

ground.

Power supply quality has a direct impact on overall system

performance. To achieve optimal performance, follow

recommendations for ADRV9008-1 power supply routing. The

following recommendations outline how to route different

power domains that can be connected together directly and to

the same supply, but are separated by a 0 Ω placeholder resistor

or ferrite bead.

Figure 174 shows an example of such traces routed on the

ADRV9008-1W/PCBZ on Layer 12. Each trace is separated

from any other signal by the ground plane and vias. Separating

the traces from other signals is essential to providing necessary

isolation between the ADRV9008-1 power domains.

Figure 174. Layout Example of Power Supply Domains Routed with Ground Shielding (Layer 12 to Power)

Rev. 0 | Page 54 of 68

Data Sheet

ADRV9008-1

Each power supply pin requires a 0.1 µF bypass capacitor near

the pin at a minimum. Place the ground side of the bypass

capacitor so that ground currents flow away from other power

pins and the bypass capacitors.

placed. The recommendation is to connect a ferrite bead between a

power plane and the ADRV9008-1 at a distance away from the

device. The ferrite bead and the reservoir capacitor provide stable

voltage to the ADRV9008-1 during operation by isolating the pin

or pins that the network is connected to from the power plane.

Then, shield this trace with ground and provide power to the

power pins on the ADRV9008-1. Place a 100 nF capacitor near the

power supply pin with the ground side of the bypass capacitor

placed so that ground currents flow away from other power

pins and the bypass capacitors.

For domains shown in Figure 175, like the domains powered

through a 0 Ω placeholder resistor or ferrite bead (FB), place the

0 Ω placeholder resistors or ferrite beads further away from the

device. Space 0 Ω placeholder resistors or ferrite beads apart from

each other to ensure the electric fields on the ferrite beads do not

influence each other. Figure 176 shows an example of how the

ferrite beads, reservoir capacitors, and decoupling capacitors are

TRACE THROUGH 0Ω RES. TO 1.3V ANALOG PLANE (AP)

MAINTAIN LOWEST POSSIBLE IMPEDANCE

TRACE THROUGH 0.1Ω RESISTOR TO AP

TRACE THROUGH 0Ω RESISTOR TO AP

VSSA

RX2_IN+

VSSA

RX2_IN–

VSSA

RX1_IN+

VSSA

RX1_IN–

VSSA

TRACE THROUGH

VDDA1P3_

RX_RF

RF_EXT_

LO_I/O–

RF_EXT_

LO_I/O+

0Ω TO AP

VDDA1P3_

AUX_VCO_

LDO

TRACE THROUGH

TRACE THROUGH FB

TO 3.3V PLANE

VDDA1P3_

RF_VCO_LDO

VDDA1P3_RF_

VCO_LDO

VDDA1P1_

RF_VCO

VDDA1P3_

RF_LO

0Ω TO AP

GPIO_3p3_0

GPIO_3p3_1

GPIO_3p3_2

VSSA

GPIO_3p3_3

GPIO_3p3_4

GPIO_3p3_5

VSSA

VDDA1P3_RX

VSSA

VDDA_3P3

GPIO_3p3_9

GPIO_3p3_8

GPIO_3p3_7

VSSA

RBIAS

TRACE THROUGH

VDDA1P1_

AUX_VCO

0Ω TO AP

VSSA

GPIO_3p3_10

GPIO_3p3_11

VSSA

TRACE THROUGH

0Ω TO 1.8V PLANE

TRACE THROUGH 0Ω

TO 1.8V PLANE

AUX_SYNTH_

OUT

GPIO_3p3_6

AUXADC_0

VSSA

VDDA1P8_BB VDDA1P3_BB

REF_CLK_IN+

AUXADC_3

AUXADC_2

VSSA

VDDA1P8_AN

REF_CLK_IN–

TRACE THROUGH

1Ω RESISTOR TO AP

VSSA

AUXADC_1

VSSA

SDO

VSSA

TRACE THROUGH 0Ω

TO PLANE

TRACE THROUGH

VDDA1P3_

CLOCK_

SYNTH

VDDA1P3_

RF_SYNTH

RF_SYNTH_

VTUNE

VDDA1P3_

AUX_SYNTH

0Ω TO AP

VSSA

DNC

VSSA

SDIO

SCLK

GPIO_12

GPIO_13

GPIO_14

GPIO_15

GPIO_16

GPIO_11

GPIO_10

GPIO_9

VSSA

DNC

GP_

INTERRUPT

DNC

VSSA

GPIO_18

SYSREF_IN+

SYNCIN1–

SYNCIN0–

SERDOUT3–

VSSA

RESET

TEST

VSSA

DNC

GPIO_2

GPIO_1

GPIO_0

VSSA

SYSREF_IN–

SYNCIN1+

SYNCIN0+

SERDOUT3+

SERDOUT1–

GPIO_5

GPIO_6

GPIO_4

GPIO_7

VSSD

CS

VSSA

GPIO_3

VSSD

WIDE TRACE TO

1.3V DIGITAL SUPPLY

HIGH CURRENT

VDDD1P3_

DIG

VDDA1P3_

SER

VDDA1P3_

SER

VDDD1P3_

DIG

VSSA

VSSD

GPIO_17

GPIO_8

TRACE THROUGH FB

VDDA1P1_

CLOCK_VCO

VDD_

INTERFACE

VDDA1P3_

SER

VDDA1P3_

SER

TO INTERFACE SUPPLY

VSSA

RX1_ENABLE

SERDOUT2–

SERDOUT1+

RX2_ENABLE

VSSA

TRACE THROUGH

FB TO 1.3V

JESD204B SUPPLY

VSSD

VDDA1P3_

CLOCK_

VCO_LDO

VDDA1P3_

SER

VDDA1P3_

SER

VDDA1P3_

SER

VDDA1P3_

SER

VDDA1P3_

SER

VDDA1P3_

SER

VSSA

SERDOUT2+

SERDOUT0–

VSSA

TRACE THROUGH

0Ω TO AP

AUX_SYNTH_

VTUNE

VDDA1P3_

SER

VDDA1P3_

SER

VDDA1P3_

SER

VDDA1P3_

SER

VDDA1P3_

SER

VDDA1P3_

SER

SERDOUT0+

VSSA

Figure 175. Power Supply Domains Interconnection Guidelines

Rev. 0 | Page 55 of 68

ADRV9008-1

Data Sheet

0Ω RESISTOR

PLACEHOLDERS

FOR FERRITE BEADS

RESERVOIR

CAPACITORS

DUT

1µ + 100nF bypass

CAPS ORIENTED SUCH

THAT CURRENTS FLOW

AWAY FROM OTHER

POWER PINS

0Ω RESISTOR

PLACEHOLDERS

FOR FERRITE BEADS

Figure 176. Placement Example of 0 Ω Resistor Placeholders for Ferrite Beads, Reservoir and Bypass Capacitors on the ADRV9008-1W/PCBZ (Layer 12 to Power and

Bottom)

Rev. 0 | Page 56 of 68

Data Sheet

ADRV9008-1

Signals with Lowest Routing Priority

RESET

pin (J4) high with a 10 kΩ resistor to

4. Pull the

VDD_INTERFACE for normal operation. To reset the

RESET

As a last step while designing the PCB layout, route the signals

shown in Figure 177. The following list outlines the

recommended order of signal routing:

device, drive the

pin low.

When routing analog signals such as GPIO_3p3_x or AUXADC_x,

it is recommended to route the signals away from the digital

section (Row H through Row P). Do not cross the analog section of

the ADRV9008-1, highlighted by a red dotted line in Figure 177, by

any digital signal routing.

1. Use ceramic 1 µF bypass capacitors at the VDDA1P1_

RF_VCO, VDDA1P1_AUX_VCO, and VDDA1P1_CLOCK_

VCO pins. Place these pins as close as possible to the

ADRV9008-1 device with the ground side of the bypass

capacitor placed so that ground currents flow away from

other power pins and the bypass capacitors, if possible.

2. Connect a 14.3 kΩ resistor to the RBIAS pin (C14). This

resistor must have a 1% tolerance.

3. Pull the TEST pin (J6) to ground for normal operation.

The device supports JTAG boundary scan, and this pin is

used to access that function. Refer to the JTAG Boundary

Scan section for JTAG boundary scan information.

When routing digital signals from Row H and below, it is

important to route the signals away from the analog section

(Row A through Row G). Do not cross the analog section of the

ADRV9008-1, highlighted by a red dotted line in Figure 177, by

any digital signal routing.

VSSA

RX2_IN+

RX2_IN–

VSSA

RX1_IN+

VSSA

RX1_IN–

VSSA

1µF CAPACITOR

VDDA1P3_

RX_RF

RF_EXT_

LO_I/O–

RF_EXT_

LO_I/O+

VSSA

VDDA1P3_

AUX_VCO_

LDO

VDDA1P3_

RF_VCO_LDO

VDDA1P3_RF_

VCO_LDO

VDDA1P1_

RF_VCO

VDDA1P3_

RF_LO

GPIO_3p3_0

GPIO_3p3_1

GPIO_3p3_2

VSSA

GPIO_3p3_3

GPIO_3p3_4

GPIO_3p3_5

VSSA

VDDA1P3_RX

VSSA

VDDA_3P3

GPIO_3p3_9

GPIO_3p3_8

GPIO_3p3_7

VSSA

RBIAS

14.3kΩ RESISTOR

VDDA1P1_

AUX_VCO

VSSA

GPIO_3p3_10

GPIO_3p3_11

VSSA

AUX_SYNTH_

OUT

GPIO_3p3_6

AUXADC_0

VSSA

VDDA1P8_BB VDDA1P3_BB

REF_CLK_IN+

AUXADC_3

AUXADC_2

VSSA

VDDA1P8_AN

REF_CLK_IN–

VSSA

AUXADC_1

VSSA

SDO

VSSA

VDDA1P3_

CLOCK_

SYNTH

VDDA1P3_

RF_SYNTH

RF_SYNTH_

VTUNE

VDDA1P3_

AUX_SYNTH

VSSA

ALL DIGITAL

GPIO SIGNALS

ROUTED BELOW

THE RED LINE

VSSA

DNC

VSSA

SDIO

SCLK

GPIO_12

GPIO_13

GPIO_14

GPIO_15

GPIO_16

GPIO_11

GPIO_10

GPIO_9

VSSA

DNC

GP_

INTERRUPT

DNC

VSSA

GPIO_18

SYSREF_IN+

SYNCIN1–

SYNCIN0–

SERDOUT3–

VSSA

RESET

TEST

VSSA

DNC

GPIO_2

GPIO_1

GPIO_0

VSSA

SYSREF_IN–

SYNCIN1+

SYNCIN0+

SERDOUT3+

SERDOUT1–

GPIO_5

GPIO_6

GPIO_4

GPIO_7

VSSD

CS

VSSA

GPIO_3

VSSD

VDDD1P3_

DIG

VDDA1P3_

SER

VDDA1P3_

SER

VDDD1P3_

DIG

VSSA

VSSD

GPIO_17

GPIO_8

VDDA1P1_

CLOCK_VCO

VDD_

INTERFACE

VDDA1P3_

SER

VDDA1P3_

SER

VSSA

RX1_ENABLE

SERDOUT2–

SERDOUT1+

RX2_ENABLE

VSSA

1µF CAPACITOR

VSSD

VDDA1P3_

CLOCK_

VCO_LDO

VDDA1P3_

SER

VDDA1P3_

SER

VDDA1P3_

SER

VDDA1P3_

SER

VDDA1P3_

SER

VDDA1P3_

SER

VSSA

SERDOUT2+

SERDOUT0–

VSSA

AUX_SYNTH_

VTUNE

VDDA1P3_

SER

VDDA1P3_

SER

VDDA1P3_

SER

VDDA1P3_

SER

VDDA1P3_

SER

VDDA1P3_

SER

SERDOUT0+

VSSA

Figure 177. AUXADC_x, Analog, and Digital GPIO Signals Routing Guidelines

Rev. 0 | Page 57 of 68

ADRV9008-1

Data Sheet

RF AND JESD204B TRANSMISSION LINE LAYOUT

RF Routing Guidelines

The ADRV9008-1W/PCBZ uses microstrip type lines for

receiver traces. In general, Analog Devices does not

recommend using vias to route RF traces unless a direct line

route is not possible. Differential lines from the balun to the

receiver pins must be as short as possible. Keep the length of the

single-ended transmission line short to minimize the effects of

parasitic coupling. It is important to note that these traces are

the most critical when optimizing performance and are, therefore,

routed before any other routing. These traces have the highest

priority if trade-offs are needed.

Figure 178 shows pi matching networks on the single-ended

side of the baluns. The receiver front end is dc biased internally.

Therefore, the differential side of the balun is ac-coupled. The

system designer can optimize the RF performance with a proper

selection of the balun, matching components, and ac coupling

capacitors. The external LO traces and the REF_CLK_IN

traces may also require matching components to ensure optimal

performance.

Figure 178. Pi Network Matching Components Available on Different RF Nets

All the RF signals mentioned previously must have a solid ground

reference under each trace. Do not run any of the critical traces

over a section of the reference plane that is discontinuous. The

ground flood on the reference layer must extend all the way to

the edge of the board. This flood length ensures signal integrity

for the SMA launch when an edge launch connector is used.

Refer to the RF Port Interface Information section for more

information on RF matching recommendations for the

ADRV9008-1.

Rev. 0 | Page 58 of 68

Data Sheet

ADRV9008-1

JESD204B Trace Routing Recommendations

Stripline Transmission Lines vs. Microstrip Transmission

Lines

The ADRV9008-1 receiver uses the JESD204B, high speed serial

interface. To ensure optimal performance of this interface, keep the

differential traces as short as possible by placing the ADRV9008-1

as close as possible to the FPGA or BBP, and route the traces

directly between the devices. Use a PCB material with a low

dielectric constant (< 4) to minimize loss. For distances greater

than 6 inches, use a premium PCB material, such as RO4350B

or RO4003C.

Stripline trasmission lines have less signal loss and emit less

electromagnetic interference than microstrip trasmission lines.

However, stripline trasmission lines require the use of vias that

add line inductance, increasing the difficulty of controlling the

impedance.

Microstrip trasmission lines are easier to implement if the

component placement and density allow routing on the top

layer. Microstrip trasmission lines make controlling the

impedance easier.

Routing Recommendations

Route the differential pairs on a single plane using a solid

ground plane as a reference on the layers above and/or below

these traces.

If the top layer of the PCB is used by other circuits or signals,

or if the advantages of stripline are more desirable over the

advantages of microstrip, follow these recommendations:

All JESD204B lane traces must be impedance controlled to

achieve 50 Ω to ground. It is recommended that the differential

pair be coplanar and loosely coupled. An example of a typical

configuration is 5 mil trace width and 15 mil edge to edge

spacing, with the trace width maximized as shown in Figure 179.

•

Minimize the number of vias.

Use blind vias where possible to eliminate via stub effects,

and use micro vias to minimize via inductance.

When using standard vias, use a maximum via length to

minimize the stub size. For example, on an 8-layer board,

use Layer 7 for the stripline pair.

•

Match trace widths with pin and ball widths as closely as

possible while maintaining impedance control. If possible, use

1 oz. copper trace widths of at least 8 mil (200 µm). The

coupling capacitor pad size must match JESD204B lane trace

widths as closely as possible. If trace width does not match pad

size, use a smooth transition between different widths.

Place a pair of ground vias near each via pair to minimize

the impedance discontinuity.

Route the JESD204B lines on the top side of the board as a

differential 100 Ω pair (microstrip). For the ADRV9008-

1W/PCBZ, the JESD204B differential signals are routed on

inner layers of the board (Layer 5 and Layer 10) as differential

100 Ω pairs (stripline). To minimize potential coupling, these

signals are placed on an inner layer using a via embedded in the

component footprint pad where the ball connects to the PCB.

The ac coupling capacitors (100 nF) on these signals are placed

near the connector and away from the chip to minimize

coupling. The JESD204B interface can operate at frequencies of

up to 12 GHz. Ensure that signal integrity from the chip to the

connector is maintained.

The pad area for all connector and passive component choices

must be minimized due to a capacitive plate effect that leads to

problems with signal integrity.

Reference planes for impedance controlled signals must not be

segmented or broken for the entire length of a trace.

The REF_CLK_IN signal trace and the SYSREF signal trace

are impedance controlled for character impedance (Z_O) = 50 Ω.

DIFF A

DIFF B

DIFF A

DIFF B

TIGHTLY COUPLED

DIFFERENTIAL LINES

LOOSELY COUPLED

DIFFERENTIAL LINES

Figure 179. Routing JESD204B, Diff A and Diff B Correspond to Differential Positive Signals or Negative Signals (One Differential Pair)

Rev. 0 | Page 59 of 68

ADRV9008-1

Data Sheet

Figure 180. Isolation Structures on the ADRV9008-1W-PCBZ

receivers. Spacing between square apertures must be no more

than 1/10 of a wavelength. Calculate the wavelength using

Equation 1:

ISOLATION TECHNIQUES USED ON THE

ADRV9008-1W/PCBZ

Isolation Goals

300

Significant isolation challenges were overcome in designing the

ADRV9008-1W/PCBZ. The following isolation requirement is

used to accurately evaluate the ADRV9008-1 receiver

performance: receiver to receiver, 65 dB out to 6 GHz.

(1)

Wavelength (m) =

Frequency (MHz) × E_R

where E_Ris the dielectric constant of the isolator material. For

RO4003C material, microstrip structure (+ air) E_R= 2.8. For FR4-

370HR material, stripline structure E_R= 4.1.

To meet these isolation goals with significant margin, isolation

structures are introduced.

For example, if the maximum RF signal frequency is 6 GHz,

and E_R= 2.8 for RO4003C material, microstrip structure (+ air),

the minimum wavelength is approximately 29.8 mm.

Figure 180 shows the isolation structures used on the ADRV9008-

1W/PCBZ. These structures consist of a combination of slots and

square apertures. These structures are present on every copper

layer of the PCB stack. The advantage of using square apertures is

that signals can be routed between the openings without affecting

the isolation benefits of the array of apertures. When using these

isolation structures, make sure to place ground vias around the

slots and apertures.

To follow the 1/10 wavelength spacing rule, square aperture

spacing must be 2.98 mm or less.

Isolation Between JESD204B Lines

The JESD204B interface uses eight line pairs that can operate at

speeds of up to 12 GHz. When configuring the PCB layout, ensure

that these lines are routed according to the rules outlined in the

JESD204B Trace Routing Recommendations section. In addition,

use isolation techniques to prevent crosstalk between different

JESD204B lane pairs.

Figure 181 outlines the methodology used on the ADRV9008-

1W/PCBZ. When using slots, ground vias must be placed at the

ends of the slots and along the sides of the slots. When using

square apertures, at least one single ground via must be placed

adjacent to each square. These vias must be through-hole vias

from the top to the bottom layer. The function of these vias is to

steer return current to the ground planes near the apertures.

Figure 182 shows a technique used on the ADRV9008-1W/PCBZ

that involves via fencing. Placing ground vias around each

JESD204B pair provides isolation and decreases crosstalk. The

spacing between vias is 1.2 mm.

For accurate slot spacing and square apertures layout, use

simulation software when designing a PCB for the ADRV9008-1

Rev. 0 | Page 60 of 68

Data Sheet

ADRV9008-1

Figure 181. Current Steering Vias Placed Next to Isolation Structures

1.24mm

Figure 182. Via Fencing Around JESD204B Lines, PCB Layer 10

Figure 182 shows the rule provided in Equation 1. JESD204B lines

are routed on Layer 5 and Layer 10 so that the lines use stripline

structures. The dielectric material used in the inner layers of the

ADRV9008-1W/PCBZ PCB is FR4-370HR.

The ADRV9008-1 is a highly integrated receiver device.

External impedance matching networks are required on the

receiver port to achieve performance levels indicated in the

Specifications section.

For accurate spacing of the JESD204B fencing vias, use layout

simulation software. Input the following data into Equation 1 to

calculate the wavelength and square aperture spacing:

Analog Devices recommends the use of simulation tools in the

design and optimization of impedance matching networks. To

achieve the closest match between computer simulated results and

measured results, accurate models of the board environment, SMD

components (including baluns and filters), and ADRV9008-1 port

impedances are required.

•

Maximum JESD204B signal frequency is approximately

12 GHz.

•

For FR4-370HR material, stripline structure, E_R= 4.1, the

minimum wavelength is approximately 12.4 mm.

RF Port Impedance Data

This section provides the port impedance data for the receivers

in the ADRV9008-1 integrated receiver. Note the following:

To follow the 1/10 wavelength spacing rule, spacing between vias

must be 1.24 mm or less. The minimum spacing recommendation

according to transmission line theory is 1/4 wavelength.

•

Z_Ois defined as 50 Ω.

The ADRV9008-1 ball pads are the reference plane for

this data.

RF PORT INTERFACE INFORMATION

This section details the RF receiver interfaces for optimal device

performance. This section also includes data for the anticipated

ADRV9008-1 RF port impedance values and examples of

impedance matching networks used in the evaluation platform.

This section also provides information on board layout techniques

and balun selection guidelines.

•

Single-ended mode port impedance data is not available.

However, a rough assessment is possible by taking the

differential mode port impedance data and dividing both

the real and imaginary components by 2.

Rev. 0 | Page 61 of 68

ADRV9008-1

Data Sheet

1.0

2.0

0.5

m15

FREQUENCY = 100MHz

S(1,1) = 0.390/–1.819

m20

IMPEDANCE = 113.933 – j3.331

FREQUENCY = 3GHz

S(1,1) = 0.267/–64.650

0.2

m16

5.0

FREQUENCY = 300MHz

S(1,1) = 0.390/–5.495

IMPEDANCE = 112.803 – j9.931

IMPEDANCE = 55.102 – j28.685

m21

M23

FREQUENCY = 4GHz

S(1,1) = 0.186/–104.336

IMPEDANCE = 42.821 – j16.026

m17

M15

M16

M17

M22

FREQUENCY = 500MHz

S(1,1) = 0.388/–9.198

IMPEDANCE = 110.398 – j16.107

0

m22

M21

M20

FREQUENCY = 5GHz

S(1,1) = 0.164/–173.106

IMPEDANCE = 35.977 – j1.455

m18

M19

M18

FREQUENCY = 1GHz

S(1,1) = 0.377–18.643

IMPEDANCE = 100.377 – j28.250

m23

FREQUENCY = 6GHz

S(1,1) = 0.266/130.063

IMPEDANCE = 32.890 + j14.399

–0.2

–5.0

m19

FREQUENCY = 2GHz

S(1,1) = 0.336/–39.123

IMPEDANCE = 74.966 – j35.800

–0.5

–2.0

–1.0

FREQUENCY (0Hz TO 6GHz)

Figure 183. Receiver 1 and Receiver 2 SEDZ and Parallel Equivalent Differential Impedance (PEDZ) Data

1.0

2.0

0.5

900

800

700

600

500

400

300

200

100

0

350

300

250

200

150

100

50

m1

FREQUENCY = 100MHz

S(1,1) = 0.018/–149.643

IMPEDANCE = 48.491 – j0.866

R_PEDZ

L_OR_C_PE

X_STATUS

M5

M6

0.2

m2

5.0

m7

FREQUENCY = 750MHz

S(1,1) = 0.074/–123.043

IMPEDANCE = 45.753 – j5.744

FREQUENCY = 5GHz

L_OR_C_PE = 1.336

m8

FREQUENCY = 5GHz

R_PEDZ = 31.172

m9

FREQUENCY = 5GHz

X_STATUS = 1

m3

M4

FREQUENCY = 1.5GHz

S(1,1) = 0.147/–138.745

IMPEDANCE = 39.362 – j7.804

M1

0

M2

M3

m4

FREQUENCY = 3GHz

S(1,1) = 0.292/–175.424

IMPEDANCE = 27.426 – j1.397

–0.2

–5.0

m5

FREQUENCY = 6GHz

S(1,1) = 0.538/123.271

IMPEDANCE = 18.885 – j23.935

m6

FREQUENCY = 12GHz

S(1,1) = 0.757/46.679

IMPEDANCE = 40.002 – j103.036

0

–0.5

–2.0

0

2

4

6

8

10

12

FREQUENCY (GHz)

–1.0

FREQUENCY (100MHz TO 12GHz)

Figure 184. RF_EXT_LO_I/O SEDZ and PEDZ Data

Rev. 0 | Page 62 of 68

Data Sheet

ADRV9008-1

1.0

2.0

0.5

1.0

13E+5

1.2E+5

1.1E+5

1.0E+5

9.0E+4

8.0E+4

7.0E+4

6.0E+4

5.0E+4

4.0E+4

m1

FREQUENCY = 100MHz

S(1,1) = 0.999/–1.396

IMPEDANCE = 159.977 – j4.099E3

R_PEDZ

L_OR_C_PE

X_STATUS

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

0.2

m2

5.0

m7

FREQUENCY = 250MHz

S(1,1) = 0.999/–3.480

IMPEDANCE = 30.567 – j1.645E3

FREQUENCY = 1GHz

L_OR_C_PE = 0.389

m8

FREQUENCY = 1GHz

R_PEDZ = 4.761E4

m9

FREQUENCY = 1GHz

X_STATUS = 0

m3

FREQUENCY = 500MHz

M1

0

S(1,1) = 0.999/–6.952

M2

M3

M4

M5

IMPEDANCE = 9.723 – j823.070

m4

FREQUENCY = 750MHz

S(1,1) = 0.998/–10.431

IMPEDANCE = 5.273 – j547.733

–0.2

–5.0

m5

FREQUENCY = 1GHz

S(1,1) = 0.999/–13.925

IMPEDANCE = 3.521 – j409.400

–0.5

–2.0

0

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1

FREQUENCY (GHz)

–1.0

FREQUENCY (0.000Hz TO 1.100GHz)

Figure 185. REF_CLK_IN SEDZ and PEDZ Data—On Average, the Real Part of Parallel Equivalent Differential Impedance (R_P) = ~70 kΩ

Rev. 0 | Page 63 of 68

ADRV9008-1

Data Sheet

Advanced Design System (ADS) Setup Using the

DataAccessComponent and SEDZ File

The mechanics of setting up a simulation for impedance

measurement and impedance matching is as follows:

Analog Devices supplies the port impedance as an .s1p file that

can be downloaded from the ADRV9008-1 product page. This

format allows simple interfacing to the ADS by using the data

access component. In Figure 186, Term1 is the single-ended

input or output, and Term2 is the differential input or output

RF port on the ADRV9008-1. The pi on the single-ended side

and the differential pi configuration on the differential side

allow maximum flexibility in designing matching circuits. The

pi configuration is suggested for all design layouts because the

pi configuration can step the impedance up or down as needed

with appropriate component population.

1. The data access component block reads the RF port .s1p

file. This file is the device RF port reflection coefficient.

2. The two equations convert the RF port reflection coefficient

to a complex impedance. The result is the RX_SEDZ

variable.

3. The RF port calculated complex impedance (RX_SEDZ) is

used to define the Term2 impedance.

4. Term2 is used in a differential mode, and Term1 is used in

a single-ended mode.

Setting up the simulation this way allows one to measure the

input reflection (S11), output reflection (S22), and through

reflection (S21) of the three port system without complex math

operations within the display page.

For the highest accuracy, the electromagnetic momentum (EM)

modeling result of the PCB artwork and S parameters (S11, S22,

and S21) of the matching components and balun must be used in

the simulations.

Figure 186 Simulation Setup in ADS with SEDZ .s1p Files and DataAccessComponent

Rev. 0 | Page 64 of 68

Data Sheet

ADRV9008-1

C

General Receiver Path Interface

RX1_IN–

RX1_IN+

RECEIVER

The ADRV9008-1 receivers can support up to a 200 MHz

bandwidth.

INPUT

STAGE

(MIXER OR LNA)

The ADRV9008-1 receivers support a wide range of operation

frequencies. In the case of the receiver channels, the differential

signals interface to an integrated mixer. The mixer input pins have

a dc bias of approximately 0.7 V and may need to be ac-coupled,

depending on the common-mode voltage level of the external

circuit.

Figure 188. Differential Receiver Interface Using a Transmission Line Balun

Impedance Matching Network Examples

Impedance matching networks are required to achieve the

ADRV9008-1 data sheet performance levels. This section provides

a description of the matching network topology and components

used on the ADRV9008-1W/PCBZ.

Important considerations for the receiver port interface are as

follows:

Device models, board models, and balun and SMD component

models are required to build an accurate system level simulation.

The board layout model can be obtained from an EM simulator.

The balun and SMD component models can be obtained from

the device vendors or built locally. Contact Analog Devices

applications engineering for ADRV9008-1 modeling details.

•

The device to be interfaced (filter, balun, transmit/receive

(T/R) switch, external low noise amplifier (LNA), external

PA, and so on).

The receiver maximum safe input power is 23 dBm (peak).

The receiver optimum dc bias voltage is 0.7 V bias to

ground.

•

The impedance matching network provided in this section is

not evaluated in terms of mean time to failure (MTTF) in high

volume production. Consult with component vendors for long-

term reliability concerns. Consult with balun vendors to determine

appropriate conditions for dc biasing.

•

The board design (reference planes, transmission lines,

impedance matching, and so on).

Figure 187 and Figure 188 show possible differential receiver

port interface circuits. The options in Figure 187 and Figure 188

are valid for all receiver inputs operating in differential mode,

though only the Receiver 1 signal names are indicated. Impedance

matching may be necessary to obtain data sheet performance levels.

Figure 190 shows three elements in parallel marked do not

install (DNI). However, only one set of SMD component pads

is placed on the board. For example, the R202, L202, and C202

components only have one set of SMD pads for one SMD

component. Figure 190 shows that, in a generic port impedance

matching network, the shunt or series elements may be a resistor,

inductor, or capacitor.

Given wide RF bandwidth applications, SMD balun devices

function well. Decent loss and differential balance are available

in a relatively small (0603, 0805) package.

RX1_IN–

RECEIVER

INPUT

STAGE

(MIXER OR LNA)

RX1_IN+

Figure 187. Differential Receiver Interface Using a Transformer

Rev. 0 | Page 65 of 68

ADRV9008-1

Data Sheet

Rx TOPOLOGY

3

4

BAL_OUT1

BAL_OUT2

Rx +

Rx –

1

UNBAL_IN

Rx IN

2

3 4 5

NC_6 GND GND_DC_FEED_RFGND

6

5

2

R328

0Ω

Figure 189. Impedance Matching Topology

RX1

T201

TCM1-83X+

J201

C248

18pF

RX1_UNBAL

RX1_BAL+

R205

R202

RX1_IN+

3

2

5

4

1

0Ω

2

3

4

5

C201

DNI

C203

DNI

C204

DNI

C207

DNI

NC

1

6

AGND

R206

RX1_IN-

AGND

RX1_BAL–

C240

10pF

DNI

C241

27pF

0Ω

AGND

RX2

T202

TCM1-83X+

J202

1

C249

RX2_UNBAL

R209

0Ω

R212

RX2_IN+

RX2_BAL+

3

2

5

4

0Ω

18pF

2

3

4

5

C208

DNI

C210

DNI

C214

DNI

C211

DNI

NC

AGND

6

1

AGND

R213

RX2_IN-

C243

27pF

RX2_BAL–

0Ω

C242

DNI

AGND

Figure 190. Receiver 1 (RX1) and Receiver 2 (RX2) Generic Matching Network Topology

Rev. 0 | Page 66 of 68

Data Sheet

ADRV9008-1

Table 9 and shows the selected balun and component values

used for three matching network sets. Refer to the ADRV9008-1

schematics for a wideband matching example that operates across

the entire device frequency range with somewhat reduced

performance.

The RF matching used in the ADRV9008-1W/PCBZ allows the

ADRV9008-1 to operate across the entire chip frequency range

with slightly reduced performance.

Table 9. Receiver 1 and Receiver 2 Evaluation Board Matching Components for Frequency Band 75 MHz to 6000 MHz

Component

Value

C201, C208

Do not install (DNI)

R202, R209

0 Ω

C203, C210

DNI

C248, C249

18 pF

C204, C211

DNI

R205/R206, R212/R213

C207, C214

0 Ω

DNI

T201, T202

Mini circuits TMC1-83X+

Rev. 0 | Page 67 of 68

ADRV9008-1

Data Sheet

OUTLINE DIMENSIONS

12.10

12.00 SQ

11.90

A1 BALL

PAD CORNER

A1 BALL

CORNER

14 13 12 11 10 9

8 7 6 5 4 3 2 1

A

B

C

D

E

F

PIN A1

INDICATOR

10.40 SQ

G

7.755 REF

H

J

K

L

0.80

M

N

P

TOP VIEW

BOTTOM VIEW

0.80 REF

8.090 REF

DETAIL A

1.27

1.18

1.09

0.91

0.84

0.77

DETAIL A

0.39

0.34

0.29

0.44 REF

0.50

0.45

0.40

SEATING

PLANE

COPLANARITY

0.12

BALL DIAMETER

COMPLIANT TO JEDEC STANDARDS MO-275-GGAB-1.

Figure 191. 196-Ball Chip Scale Package Ball Grid Array [CSP_BGA]

(BC-196-13)

Dimensions shown in millimeters

ORDERING GUIDE

Model¹

Temperature Range²

Package Description

Package Option

ADRV9008BBCZ-1

ADRV9008BBCZ-1REEL

ADRV9008-1W/PCBZ

−40°C to +85°C

196-Ball Chip Scale Package Ball Grid Array [CSP_BGA]

Pb-Free Evaluation Board, 75 MHz to 6000 MHz

BC-196-13

¹Z = RoHS Compliant Part.

²See the Thermal Management section.

registered trademarks are the property of their respective owners.

D16830-0-9/18(0)

Rev. 0 | Page 68 of 68


型号：	ADRV9008BBCZ-1REEL
厂家：	ADI
描述：	Integrated Dual RF Receivers
文件：	总68页 (文件大小：1833K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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