ADSP-BF539YBCZ-4F8_技术文档

Blackfin^®

Embedded Processor

a

Preliminary Technical Data

ADSP-BF539/ADSP-BF539F

External memory controller with glueless support

for SDRAM, SRAM, flash, and ROM

Flexible memory booting options from SPI^®, external

memory

FEATURES

1.0 V to 1.2 V core V_DDwith on-chip voltage regulation

3.3 V tolerant I/O with specific 5 V tolerant pins

316-ball Pb-free mini-BGA package

Up to 500 MHz high performance Blackfin processor

Two 16-bit MACs, two 40-bit ALUs, four 8-bit video ALUs,

40-bit shifter

RISC-like register and instruction model for ease of

programming and compiler friendly support

Advanced debug, trace, and performance monitoring

PERIPHERALS

Parallel peripheral interface (PPI),

supporting ITU-R 656 video data formats

Four dual-channel, full-duplex synchronous serial ports, sup-

porting 16 stereo I²S^®channels

Two DMA controllers supporting 26 channels

Controller area network (CAN) 2.0B controller

Media transceiver (MXVR) for connection

to a MOST^®network

MEMORY

148K bytes of on-chip memory:

16K bytes of instruction SRAM/cache

64K bytes of instruction SRAM

32K bytes of data SRAM

32K bytes of data SRAM/cache

4K bytes of scratchpad SRAM

512K x 16-bits or 256K x 16-bits of flash memory

(ADSP-BF539F only)

Four dual-channel memory DMA controllers

Memory management unit providing memory protection

Three SPI-compatible ports

Three timer/counters with PWM support

Three UARTs with support for IrDA^®

Two TWI controllers compatible with I²C^®industry standard

38 general purpose I/O pins (GPIO)

16 general purpose flag pins (GPF)

Real time clock

Watchdog timer

Debug/JTAG interface

On-chip PLL capable of 0.5x To 64x frequency multiplication

EVENT

JTAG TEST AND

WATCHDOG TIMER

MXVR

CONTROLLER/

EMULATION

CORE TIMER

REAL TIME CLOCK

PPI / GPF

VOLTAGE

B

REGULATOR

CAN 2.0B

L1

MMU

INSTRUCTION

MEMORY

DATA

MEMORY

TIMER0, 1, 2

UART0, 1, 2

CORE / SYSTEM BUS INTERFACE

GPIO

TWI0, 1

DMA

CONTROLLER

SPORT0, 1, 2,3

SPI PORT

BOOT ROM

EXTERNAL PORT

FLASH, SDRAM

CONTROL

256K X 16-BIT OR

512K X 16-BIT

FLASH MEMORY

Figure 1. Functional Block Diagram

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Rev. PrE

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www.analog.com

ADSP-BF539/ADSP-BF539F

Preliminary Technical Data

TABLE OF CONTENTS

General Description ................................................. 4

Low Power Architecture ......................................... 4

System Integration ................................................ 4

ADSP-BF539/ADSP-BF539F Processor Peripherals ....... 4

Blackfin Processor Core .......................................... 5

Memory Architecture ............................................ 5

DMA Controllers ................................................ 10

Real Time Clock ................................................. 10

Watchdog Timer ................................................ 11

Timers ............................................................. 11

Serial Ports (SPORTs) .......................................... 11

Serial Peripheral Interface (SPI) Ports ...................... 11

Two Wire Interface ............................................. 12

UART Port ........................................................ 12

Programmable I/O Pins ........................................ 12

Parallel Peripheral Interface ................................... 13

Controller Area Network (CAN) Interface ................ 14

Media Transceiver MAC layer (MXVR) ................... 14

Dynamic Power Management ................................ 15

Voltage Regulation .............................................. 16

Clock Signals ..................................................... 16

Booting Modes ................................................... 17

Instruction Set Description ................................... 18

Development Tools ............................................. 18

Designing an Emulator Compatible Processor Board ... 19

Example Connections and Layout Considerations ...... 19

Voltage Regulator Layout Guidelines ....................... 19

MXVR Board Layout Guidelines ............................ 19

Pin Descriptions .................................................... 22

Specifications ........................................................ 27

Recommended Operating Conditions ...................... 27

Electrical Characteristics ....................................... 27

Absolute Maximum Ratings ................................... 28

Package Information ............................................ 28

ESD Sensitivity ................................................... 28

Timing Specifications ........................................... 29

Clock and Reset Timing ..................................... 30

Asynchronous Memory Read Cycle Timing ............ 31

Asynchronous Memory Write Cycle Timing ........... 35

SDRAM Interface Timing .................................. 37

External Port Bus Request and Grant Cycle Timing .. 38

Parallel Peripheral Interface Timing ...................... 41

Serial Ports Timing ........................................... 44

Serial Peripheral Interface (SPI) Port

—Master Timing ........................................... 48

Serial Peripheral Interface (SPI) Port

—Slave Timing ............................................. 49

Universal Asynchronous Receiver-Transmitter

(UART) Port Timing ..................................... 50

Programmable Flags Cycle Timing ....................... 51

Timer Cycle Timing .......................................... 52

JTAG Test And Emulation Port Timing ................. 53

TWI Controller Timing ..................................... 54

MXVR Timing ................................................ 58

CAN Timing ................................................... 59

Output Drive Currents ......................................... 60

Power Dissipation ............................................... 62

Test Conditions .................................................. 62

Environmental Conditions .................................... 65

316-Ball Mini-BGA Pinout ....................................... 66

Outline Dimensions ................................................ 69

Ordering Guide ..................................................... 70

Recommended Operating Conditions

—Applies to 5V Tolerant pins ............................. 27

REVISION HISTORY

5/06—Revision PrE:

Changes Ordering Guide .......................................... 67

12/05—Revision PrD:

Added Maximum Duty Cycle for Input Transient Voltage 28

Added Package Information ..................................... 28

Added values in Power Dissipation ............................ 61

Added graphs in Output Drive Currents ...................... 59

Added graphs in Capacitive Loading .......................... 62

Changes number of GPIO and GPF pins Peripherals ........ 1

Changes wording in System Integration ........................ 4

Changes voltage regulator range in ADSP-BF539 processor

Peripherals ............................................................ 4

Rev. PrE

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Preliminary Technical Data

ADSP-BF539/ADSP-BF539F

Changes voltage regulator range in Voltage Regulation .... 15

Changes to Figure 8 and MXVR Board Layout Guidelines 19

Modified Example connections of ADSP-BF539 to MOST

Network ............................................................... 19

Changes to CAN, MXVR., and UART pullup in Pin

Descriptions .......................................................... 20

Adds footnotes to Recommended Operating Conditions .. 25

Adds footnotes to Absolute Maximum Ratings .............. 26

Adds die temperature specification Absolute Maximum Ratings

26

Adds table and figure to Asynchronous Memory Read Cycle

Timing ................................................................. 29

Adds table and figure to Asynchronous Memory Write Cycle

Timing ................................................................. 31

Deletes footnotes in External Port Bus Request and Grant Cycle

Timing ................................................................. 34

Adds t_WBRto External Port Bus Request and Grant Cycle Timing

34

Replaced Figure 17, Figure 18, Figure 19, and Figure 20 ... 38

Added footnotes in Serial Ports—External Clock and Serial

Ports—Internal Clock .............................................. 39

Changes to lower diagram in Serial Ports ...................... 40

Changes to External Late Frame Sync (Frame Sync Setup <

tSCLKE/2) ............................................................ 41

Replace section Power Dissipation .............................. 57

Added overbar to AOE in 316-Ball Sparse Mini-BGA Pin

Assignment (Alphabetically by Signal) .........................63

Adds section Surface Mount Design ............................ 65

Rev. PrE

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ADSP-BF539/ADSP-BF539F

Preliminary Technical Data

GENERAL DESCRIPTION

The ADSP-BF539/ADSP-BF539F processors are a members of

the Blackfin family of products, incorporating the Analog

Devices/Intel Micro Signal Architecture (MSA). Blackfin pro-

cessors combine a dual-MAC state-of-the-art signal processing

engine, the advantages of a clean, orthogonal RISC-like micro-

processor instruction set, and single-instruction, multiple-data

(SIMD) multimedia capabilities into a single instruction set

architecture.

substantial reduction in power consumption, compared with

just varying the frequency of operation. This translates into

longer battery life and lower heat dissipation.

SYSTEM INTEGRATION

The ADSP-BF539/ADSP-BF539F processor is a highly inte-

grated system-on-a-chip solution for the next generation of

industrial and automotive applications including audio and

video signal processing. By combining advanced memory con-

figurations, such as on-chip flash memory, with industry-

standard interfaces with a high performance signal processing

core, users can develop cost-effective solutions quickly without

the need for costly external components. The system peripherals

include a MOST^®Network Media Transceiver (MXVR), three

UART ports, three SPI ports, four serial ports (SPORT), one

CAN interface, two Two-Wire-Interfaces (TWI), four general

purpose timers (three with PWM capability), a real-time clock, a

watchdog timer, a Parallel Peripheral Interface, general purpose

I/O, and general purpose flag pins.

The ADSP-BF539/ADSP-BF539F processors are completely

code compatible with other Blackfin processors, differing only

with respect to performance, peripherals, and on-chip memory.

Specific performance, peripherals, and memory configurations

are shown in Table 1 on Page 4.

Table 1. Processor Features

ADSP-BF539 ADSP-BF539F4 ADSP-BF539F8

Maximum

500 MHz

1000 MMACs

Performance 1000 MMACs 1000 MMACs

Instruction

SRAM/Cache

16K bytes

64K bytes

32K bytes

16K bytes

64K bytes

32K bytes

16K bytes

64K bytes

32K bytes

ADSP-BF539/ADSP-BF539F PROCESSOR

PERIPHERALS

Instruction

SRAM

The ADSP-BF539/ADSP-BF539F processor contains a rich set

of peripherals connected to the core via several high bandwidth

buses, providing flexibility in system configuration as well as

excellent overall system performance (see the block diagram

on Page 1). The general purpose peripherals include functions

such as UART, Timers with PWM (Pulse Width Modulation)

and pulse measurement capability, general purpose flag I/O

pins, a Real Time Clock, and a Watchdog Timer. This set of

functions satisfies a wide variety of typical system support needs

and is augmented by the system expansion capabilities of the

device. In addition to these general purpose peripherals, the

ADSP-BF539/ADSP-BF539F processor contains high speed

serial and parallel ports for interfacing to a variety of audio,

video, and modem codec functions. An MXVR transceiver

transmits and receives audio and video data and control infor-

mation on a MOST^®automotive multimedia network. A CAN

2.0B controller is provided for automotive control networks. An

interrupt controller manages interrupts from the on-chip

peripherals or external sources. And power management con-

trol functions tailor the performance and power characteristics

of the processor and system to many application scenarios.

Data

SRAM/Cache

Data SRAM

Scratchpad

Flash

32K bytes

4K bytes

32K bytes

4K bytes

32K bytes

4K bytes

Not

applicable

256K x 16-bit

512K x 16-bit

SPORTs

SPI

4

3

2

3

1

4

3

TWI

2

UARTs

PPI

3

1

CAN

MXVR

1

Packageoption 316

316

By integrating a rich set of industry-leading system peripherals

and memory, Blackfin processors are the platform of choice for

next generation applications that require RISC-like program-

mability, multimedia support and leading edge signal

processing in one integrated package.

All of the peripherals, except for general purpose I/O, CAN,

TWI, Real Time Clock, and timers, are supported by a flexible

DMA structure. There are also four separate memory DMA

controllers dedicated to data transfers between the processor's

various memory spaces, including external SDRAM and asyn-

chronous memory. Multiple on-chip buses running at up to

133 MHz provide enough bandwidth to keep the processor core

running along with activity on all of the on-chip and external

peripherals.

LOW POWER ARCHITECTURE

Blackfin processors provide world class power management and

performance. Blackfin processors are designed in a low power

and low voltage design methodology and feature Dynamic

Power Management, the ability to vary both the voltage and fre-

quency of operation to significantly lower overall power

consumption. Varying the voltage and frequency can result in a

The ADSP-BF539/ADSP-BF539F processor includes an on-chip

voltage regulator in support of the ADSP-BF539/ADSP-BF539F

processor Dynamic Power Management capability. The voltage

Rev. PrE

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Preliminary Technical Data

ADSP-BF539/ADSP-BF539F

regulator provides a range of core voltage levels from a single

2.7 V to 3.6 V input. The voltage regulator can be bypassed at

the user's discretion.

memory holds instructions only. The two data memories hold

data, and a dedicated scratchpad data memory stores stack and

local variable information.

In addition, multiple L1 memory blocks are provided, offering a

configurable mix of SRAM and cache. The Memory Manage-

ment Unit (MMU) provides memory protection for individual

tasks that may be operating on the core and can protect system

registers from unintended access.

BLACKFIN PROCESSOR CORE

As shown in Figure 2 on Page 6, the Blackfin processor core

contains two 16-bit multipliers, two 40-bit accumulators, two

40-bit ALUs, four video ALUs, and a 40-bit shifter. The compu-

tation units process 8-bit, 16-bit, or 32-bit data from the register

file.

The architecture provides three modes of operation: User mode,

Supervisor mode, and Emulation mode. User mode has

restricted access to certain system resources, thus providing a

protected software environment, while Supervisor mode has

unrestricted access to the system and core resources.

The compute register file contains eight 32-bit registers. When

performing compute operations on 16-bit operand data, the

register file operates as 16 independent 16-bit registers. All

operands for compute operations come from the multiported

register file and instruction constant fields.

The Blackfin processor instruction set has been optimized so

that 16-bit opcodes represent the most frequently used instruc-

tions, resulting in excellent compiled code density. Complex

DSP instructions are encoded into 32-bit opcodes, representing

fully featured multifunction instructions. Blackfin processors

support a limited multi-issue capability, where a 32-bit instruc-

tion can be issued in parallel with two 16-bit instructions,

allowing the programmer to use many of the core resources in a

single instruction cycle.

Each MAC can perform a 16-bit by 16-bit multiply in each

cycle, accumulating the results into the 40-bit accumulators.

Signed and unsigned formats, rounding, and saturation are

supported.

The ALUs perform a traditional set of arithmetic and logical

operations on 16-bit or 32-bit data. In addition, many special

instructions are included to accelerate various signal processing

tasks. These include bit operations such as field extract and pop-

ulation count, modulo 2³²multiply, divide primitives, saturation

and rounding, and sign/exponent detection. The set of video

instructions include byte alignment and packing operations, 16-

bit and 8-bit adds with clipping, 8-bit average operations, and 8-

bit subtract/absolute value/accumulate (SAA) operations. Also

provided are the compare/select and vector search instructions.

The Blackfin processor assembly language uses an algebraic syn-

tax for ease of coding and readability. The architecture has been

optimized for use in conjunction with the C/C++ compiler,

resulting in fast and efficient software implementations.

MEMORY ARCHITECTURE

The ADSP-BF539/ADSP-BF539F processor views memory as a

single unified 4G byte address space, using 32-bit addresses. All

resources, including internal memory, external memory, and

I/O control registers, occupy separate sections of this common

address space. The memory portions of this address space are

arranged in a hierarchical structure to provide a good cost/per-

formance balance of some very fast, low latency on-chip

memory as cache or SRAM, and larger, lower cost and perfor-

mance off-chip memory systems. See Figure 3 on Page 7.

For certain instructions, two 16-bit ALU operations can be per-

formed simultaneously on register pairs (a 16-bit high half and

16-bit low half of a compute register). By also using the second

ALU, quad 16-bit operations are possible.

The 40-bit shifter can perform shifts and rotates and is used to

support normalization, field extract, and field deposit

instructions.

The program sequencer controls the flow of instruction execu-

tion, including instruction alignment and decoding. For

program flow control, the sequencer supports PC relative and

indirect conditional jumps (with static branch prediction), and

subroutine calls. Hardware is provided to support zero over-

head looping. The architecture is fully interlocked, meaning that

the programmer need not manage the pipeline when executing

instructions with data dependencies.

The L1 memory system is the primary highest performance

memory available to the Blackfin processor. The off-chip mem-

ory system, accessed through the External Bus Interface Unit

(EBIU), provides expansion with SDRAM, flash memory, and

SRAM, optionally accessing up to 132M bytes of physical

memory.

The memory DMA controller provides high bandwidth data

movement capability. It can perform block transfers of code or

data between the internal memory and the external memory

spaces.

The address arithmetic unit provides two addresses for simulta-

neous dual fetches from memory. It contains a multiported

register file consisting of four sets of 32-bit Index, Modify,

Length, and Base registers (for circular buffering), and eight

additional 32-bit pointer registers (for C style indexed stack

manipulation).

Internal (On-chip) Memory

The ADSP-BF539/ADSP-BF539F processor has three blocks of

on-chip memory providing high bandwidth access to the core.

Blackfin processors support a modified Harvard architecture in

combination with a hierarchical memory structure. Level 1 (L1)

memories are those that typically operate at the full processor

speed with little or no latency. At the L1 level, the instruction

The first is the L1 instruction memory, consisting of 80K bytes

SRAM, of which 16K bytes can be configured as a four way set-

associative cache. This memory is accessed at full processor

speed.

Rev. PrE

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ADSP-BF539/ADSP-BF539F

Preliminary Technical Data

ADDRESS ARITHMETIC UNIT

SP

FP

P5

P4

P3

P2

P1

P0

I3

I2

I1

I0

L3

L2

L1

L0

B3

B2

B1

B0

M3

M2

M1

M0

DAG1

DAG0

DA1

DA0

32

PREG

RAB

SD

LD1

LD0

32

ASTAT

32

SEQUENCER

R7.H

R7.L

R6.H

R5.H

R4.H

R3.H

R2.H

R1.H

R0.H

R6.L

R5.L

R4.L

R3.L

R2.L

R1.H

R0.L

ALIGN

16

8

DECODE

BARREL

SHIFTER

LOOP BUFFER

40

40 40

A0

A1

CONTROL

UNIT

32

DATA ARITHMETIC UNIT

Figure 2. Blackfin Processor Core

The second on-chip memory block is the L1 data memory, con-

sisting of two banks of up to 32K bytes each. Each memory bank

is configurable, offering both cache and SRAM functionality.

This memory block is accessed at full processor speed.

1M byte segment regardless of the size of the devices used, so

that these banks will only be contiguous if each is fully popu-

lated with 1M byte of memory.

Flash Memory (ADSP-BF539F only)

The third memory block is a 4K byte scratchpad SRAM which

runs at the same speed as the L1 memories, but is only accessible

as data SRAM and cannot be configured as cache memory.

The ADSP-BF539F4 and ADSP-BF539F8 processors contain a

separate flash die, connected to the EBIU bus, within the pack-

age of the ADSP-BF539F processors. Figure 4 on Page 7 shows

how the flash memory die and Blackfin processor die are

connected.

External (Off-Chip) Memory

External memory is accessed via the EBIU. This 16-bit interface

provides a glueless connection to a bank of synchronous DRAM

(SDRAM) as well as up to four banks of asynchronous memory

devices including flash, EPROM, ROM, SRAM, and memory

mapped I/O devices.

The ADSP-BF539F4 contains a 4 Mbit (256K x 16-bits) bottom

boot sector flash memory. The ADSP-BF539F8 contains an 8

Mbit (512K x 16-bits) bottom boot sector flash memory. Fea-

tures include the following.

The PC133-compliant SDRAM controller can be programmed

to interface to up to 128M bytes of SDRAM. The SDRAM con-

troller allows one row to be open for each internal SDRAM

bank, for up to four internal SDRAM banks, improving overall

system performance.

• access times as fast as 70 ns (EBIU registers be set

appropriately)

• sector protection

• one million write cycles per sector

• 20 year data retention

The asynchronous memory controller can be programmed to

control up to four banks of devices with very flexible timing

parameters for a wide variety of devices. Each bank occupies a

The Blackfin processor connects to the flash memory die with

address, data, chip enable, write enable, and output enable con-

trols as if it were an external memory device.

Rev. PrE

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Preliminary Technical Data

ADSP-BF539/ADSP-BF539F

Flash Memory Programming

0xFFFF FFFF

CORE MMR REGISTERS (2M BYTE)

0xFFE0 0000

SYSTEM MMR REGISTERS (2M BYTE)

0xFFC0 0000

The ADSP-BF539F4 and ADSP-BF539F8 flash memory may be

programmed before or after mounting on the printed circuit

board.

RESERVED

0xFFB0 1000

SCRATCHPAD SRAM (4K BYTE)

0xFFB0 0000

To program the flash prior to mounting on the printed circuit

board, use a hardware programming tool that can provide the

data, address, and control stimuli to the flash die through the

external pins on the package. During this programming, V_DDEXT

and GND must be provided to the package and the Blackfin

must be held in reset with bus request (BR) asserted and a

CLKIN provided.

RESERVED

0xFFA1 4000

INSTRUCTION SRAM / CACHE (16K BYTE)

0xFFA1 0000

INSTRUCTION SRAM (32K BYTE)

0xFFA0 8000

RESERVED

0xFF90 8000

DATA BANK B SRAM / CACHE (16K BYTE)

0xFF90 4000

RESERVED

The VDSP++ tools may be used to program the flash memory

after the device is mounted on a printed circuit board.

0xFF80 8000

DATA BANK A SRAM / CACHE (16K BYTE)

0xFF80 4000

RESERVED

0xEF00 0000

RESERVED

0x2040 0000

Flash Memory Sector Protection

To use the sector protection feature, a high voltage (+12 V nom-

inal) must be applied to the flash FRESET pin. Refer to the flash

datasheet for details.

ASYNC MEMORY BANK 3 (1M BYTE) OR

ON-CHIP FLASH

0x2030 0000

ASYNC MEMORY BANK 2 (1M BYTE) OR

ON-CHIP FLASH

0x2020 0000

I/O Memory Space

ASYNC MEMORY BANK 1 (1M BYTE) OR

ON-CHIP FLASH

0x2010 0000

Blackfin processors do not define a separate I/O space. All

resources are mapped through the flat 32-bit address space. On-

chip I/O devices have their control registers mapped into mem-

ory mapped registers (MMRs) at addresses near the top of the

4G byte address space. These are separated into two smaller

blocks, one which contains the control MMRs for all core func-

tions, and the other which contains the registers needed for

setup and control of the on-chip peripherals outside of the core.

The MMRs are accessible only in supervisor mode and appear

as reserved space to on-chip peripherals.

ASYNC MEMORY BANK 0 (1M BYTE) OR

ON-CHIP FLASH

0x2000 0000

RESERVED

0x0800 0000

SDRAM MEMORY (16M BYTE - 128M BYTE)

0x0000 0000

Figure 3. ADSP-BF539/ADSP-BF539F Internal/External Memory Map

Booting

The ADSP-BF539/ADSP-BF539F processor contains a small

boot kernel, which configures the appropriate peripheral for

booting. If the ADSP-BF539/ADSP-BF539F processor is config-

ured to boot from boot ROM memory space, the processor

starts executing from the on-chip boot ROM. For more infor-

mation, see Booting Modes on Page 17.

ADDR19-1

A18-0

OE

WE

RY/BY

DQ15-0

VSS

VCC

BYTE

CE

ARE

AWE

ARDY

DATA15-0

GND

DDEXT

V

AMS3-0

RESET

Event Handling

The event controller on the ADSP-BF539/ADSP-BF539F pro-

cessor handles all asynchronous and synchronous events to the

processor. The ADSP-BF539/ADSP-BF539F processor provides

event handling that supports both nesting and prioritization.

Nesting allows multiple event service routines to be active

simultaneously. Prioritization ensures that servicing of a higher

priority event takes precedence over servicing of a lower priority

event. The controller provides support for five different types of

events:

ADSP-BF539F

package

Figure 4. Internal Connection of Flash Memory

The flash chip enable pin FCE must be connected to AMS0 or

AMS3–1 through a printed circuit board trace. When connected

to AMS0 the Blackfin processor can boot from the flash die.

When connnected to AMS3–1 the flash memory will appear as

non-volatile memory in the processor memory map shown in

Figure 3 on Page 7.

• Emulation – An emulation event causes the processor to

enter emulation mode, allowing command and control of

the processor via the JTAG interface.

• Reset – This event resets the processor.

Rev. PrE

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ADSP-BF539/ADSP-BF539F

Preliminary Technical Data

• Non-Maskable Interrupt (NMI) – The NMI event can be

generated by the software watchdog timer or by the NMI

input signal to the processor. The NMI event is frequently

used as a power-down indicator to initiate an orderly shut-

down of the system.

cessor. Table 2 describes the inputs to the CEC, identifies their

names in the Event Vector Table (EVT), and lists their

priorities.

Table 2. Core Event Controller (CEC)

• Exceptions – Events that occur synchronously to program

flow (i.e., the exception will be taken before the instruction

is allowed to complete). Conditions such as data alignment

violations and undefined instructions cause exceptions.

Priority

(0 is Highest)

Event Class

EVT Entry

0

Emulation/Test Control

Reset

EMU

RST

1

• Interrupts – Events that occur asynchronously to program

flow. They are caused by input pins, timers, and other

peripherals, as well as by an explicit software instruction.

2

Non-Maskable Interrupt

Exception

NMI

3

EVX

Each event type has an associated register to hold the return

address and an associated return-from-event instruction. When

an event is triggered, the state of the processor is saved on the

supervisor stack.

4

Reserved

—

5

Hardware Error

IVHW

IVTMR

IVG7

IVG8

IVG9

IVG10

IVG11

IVG12

IVG13

IVG14

IVG15

6

Core Timer

7

General Interrupt 7

General Interrupt 8

General Interrupt 9

General Interrupt 10

General Interrupt 11

General Interrupt 12

General Interrupt 13

General Interrupt 14

General Interrupt 15

The ADSP-BF539/ADSP-BF539F processor Event Controller

consists of two stages, the Core Event Controller (CEC) and the

System Interrupt Controller (SIC). The Core Event Controller

works with the System Interrupt Controller to prioritize and

control all system events. Conceptually, interrupts from the

peripherals enter into the SIC, and are then routed directly into

the general purpose interrupts of the CEC.

8

9

10

11

12

13

14

15

Core Event Controller (CEC)

The CEC supports nine general purpose interrupts (IVG15–7),

in addition to the dedicated interrupt and exception events. Of

these general purpose interrupts, the two lowest priority inter-

rupts (IVG15–14) are recommended to be reserved for software

interrupt handlers, leaving seven prioritized interrupt inputs to

support the peripherals of the ADSP-BF539/ADSP-BF539F pro-

System Interrupt Controller (SIC)

The System Interrupt Controller provides the mapping and

routing of events from the many peripheral interrupt sources to

the prioritized general purpose interrupt inputs of the CEC.

Although the ADSP-BF539/ADSP-BF539F processor provides a

default mapping, the user can alter the mappings and priorities

of interrupt events by writing the appropriate values into the

Interrupt Assignment Registers (IAR). Table 3 describes the

inputs into the SIC and the default mappings into the CEC.

Table 3. System and Core Event Mapping

Event Source

Core

Event Name

PLL Wakeup Interrupt

DMA Controller 0 Error

DMA Controller 1 Error

PPI Error Interrupt

IVG7

SPORT0 Error Interrupt

SPORT1 Error Interrupt

SPORT2 Error Interrupt

SPORT3 Error Interrupt

MXVR Synchronous Data Interrupt

SPI0 Error Interrupt

SPI1 Error Interrupt

SPI2 Error Interrupt

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Preliminary Technical Data

ADSP-BF539/ADSP-BF539F

Table 3. System and Core Event Mapping (Continued)

Event Control

The ADSP-BF539/ADSP-BF539F processor provides the user

with a very flexible mechanism to control the processing of

events. In the CEC, three registers are used to coordinate and

control events. Each register is 16 bits wide:

Event Source

Core

Event Name

UART0 Error Interrupt

IVG7

UART1 Error Interrupt

IVG7

• CEC Interrupt Latch Register (ILAT) – The ILAT register

indicates when events have been latched. The appropriate

bit is set when the processor has latched the event and

cleared when the event has been accepted into the system.

This register is updated automatically by the controller, but

it may also be written to clear (cancel) latched events. This

register may be read while in supervisor mode and may

only be written while in supervisor mode when the corre-

sponding IMASK bit is cleared.

UART2 Error Interrupt

IVG7

CAN Error Interrupt

IVG7

Real Time Clock Interrupts

DMA0 Interrupt (PPI)

IVG8

DMA1 Interrupt (SPORT0 RX)

DMA2 Interrupt (SPORT0 TX)

DMA3 Interrupt (SPORT1 RX)

DMA4 Interrupt (SPORT1 TX)

DMA12 Interrupt (SPORT2 RX)

DMA13 Interrupt (SPORT2 TX)

DMA14 Interrupt (SPORT3 RX)

DMA15 Interrupt (SPORT3 TX)

DMA5 Interrupt (SPI0)

IVG9

• CEC Interrupt Mask Register (IMASK) – The IMASK reg-

ister controls the masking and unmasking of individual

events. When a bit is set in the IMASK register, that event is

unmasked and will be processed by the CEC when asserted.

A cleared bit in the IMASK register masks the event, pre-

venting the processor from servicing the event even though

the event may be latched in the ILAT register. This register

may be read or written while in supervisor mode. (Note

that general purpose interrupts can be globally enabled and

disabled with the STI and CLI instructions, respectively.)

IVG9

IVG10

IVG11

IVG12

IVG13

DMA18 Interrupt (SPI1)

DMA19 Interrupt (SPI2)

• CEC Interrupt Pending Register (IPEND) – The IPEND

register keeps track of all nested events. A set bit in the

IPEND register indicates the event is currently active or

nested at some level. This register is updated automatically

by the controller but may be read while in supervisor mode.

DMA6 Interrupt (UART0 RX)

DMA7 Interrupt (UART0 TX)

DMA20 Interrupt (UART1 RX)

DMA21 Interrupt (UART1 TX)

DMA22 Interrupt (UART2 RX)

DMA23 Interrupt (UART2 TX)

Timer0, Timer1, Timer2 Interrupts

TWI0 Interrupt

The SIC allows further control of event processing by providing

three 32-bit interrupt control and status registers. Each register

contains a bit corresponding to each of the peripheral interrupt

events shown in Table 3 on Page 8.

• SIC Interrupt Mask Registers (SIC_IMASKx)– These regis-

ters control the masking and unmasking of each peripheral

interrupt event. When a bit is set in these registers, that

peripheral event is unmasked and will be processed by the

system when asserted. A cleared bit in these registers masks

the peripheral event, preventing the processor from servic-

ing the event.

TWI1 Interrupt

CAN Receive Interrupt

CAN Transmit Interrupt

MXVR Status Interrupt

MXVR Control Message Interrupt

MXVR Asynchronous Packet Interrupt

Programmable Flags Interrupt

MDMA0 Stream 0 Interrupt

MDMA0 Stream 1 Interrupt

MDMA1 Stream 0 Interrupt

MDMA1 Stream 1 Interrupt

Software Watchdog Timer

• SIC Interrupt Status Registers (SIC_ISRx) – As multiple

peripherals can be mapped to a single event, these registers

allow the software to determine which peripheral event

source triggered the interrupt. A set bit indicates the

peripheral is asserting the interrupt, and a cleared bit indi-

cates the peripheral is not asserting the event.

• SIC Interrupt Wakeup Enable Registers (SIC_IWRx) – By

enabling the corresponding bit in these registers, a periph-

eral can be configured to wake up the processor, should the

core be idled when the event is generated. (For more infor-

mation, see Dynamic Power Management on Page 15.)

Because multiple interrupt sources can map to a single general

purpose interrupt, multiple pulse assertions can occur simulta-

neously, before or during interrupt processing for an interrupt

Rev. PrE

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ADSP-BF539/ADSP-BF539F

Preliminary Technical Data

event already detected on this interrupt input. The IPEND reg-

ister contents are monitored by the SIC as the interrupt

acknowledgement.

DMA transfers can be controlled by a very flexible descriptor

based methodology or by a standard register based autobuffer

mechanism.

The appropriate ILAT register bit is set when an interrupt rising

edge is detected (detection requires two core clock cycles). The

bit is cleared when the respective IPEND register bit is set. The

IPEND bit indicates that the event has entered into the proces-

sor pipeline. At this point the CEC will recognize and queue the

next rising edge event on the corresponding event input. The

minimum latency from the rising edge transition of the general

purpose interrupt to the IPEND output asserted is three core

clock cycles; however, the latency can be much higher, depend-

ing on the activity within and the state of the processor.

REAL TIME CLOCK

The ADSP-BF539/ADSP-BF539F processor Real Time Clock

(RTC) provides a robust set of digital watch features, including

current time, stopwatch, and alarm. The RTC is clocked by a

32.768 KHz crystal external to the ADSP-BF539/ADSP-BF539F

processor. The RTC peripheral has dedicated power supply pins

so that it can remain powered up and clocked even when the

rest of the processor is in a low power state. The RTC provides

several programmable interrupt options, including interrupt

per second, minute, hour, or day clock ticks, interrupt on pro-

grammable stopwatch countdown, or interrupt at a

DMA CONTROLLERS

programmed alarm time.

The ADSP-BF539/ADSP-BF539F processor has multiple, inde-

pendent DMA controllers that support automated data transfers

with minimal overhead for the processor core. DMA transfers

can occur between the ADSP-BF539/ADSP-BF539F processor

internal memories and any of its DMA capable peripherals.

Additionally, DMA transfers can be accomplished between any

of the DMA capable peripherals and external devices connected

to the external memory interfaces, including the SDRAM con-

troller and the asynchronous memory controller. DMA capable

peripherals include the SPORTs, SPI port, UART, and PPI. Each

individual DMA capable peripheral has at least one dedicated

DMA channel. The MXVR peripheral has its own dedicated

DMA controller, which supports its own unique set of operating

modes.

The 32.768 KHz input clock frequency is divided down to a

1 Hz signal by a prescaler. The counter function of the timer

consists of four counters: a 60 second counter, a 60 minute

counter, a 24 hour counter, and an 32,768 day counter.

When enabled, the alarm function generates an interrupt when

the output of the timer matches the programmed value in the

alarm control register. There are two alarms: The first alarm is

for a time of day. The second alarm is for a day and time of that

day.

The stopwatch function counts down from a programmed

value, with one second resolution. When the stopwatch is

enabled and the counter underflows, an interrupt is generated.

Like the other peripherals, the RTC can wake up the ADSP-

BF539/ADSP-BF539F processor from Sleep mode upon genera-

tion of any RTC wakeup event. Additionally, an RTC wakeup

event can wake up the ADSP-BF539/ADSP-BF539F processor

from Deep Sleep mode, and wake up the on-chip internal volt-

age regulator from a powered down state.

The ADSP-BF539/ADSP-BF539F processor DMA controllers

support both 1-dimensional (1D) and 2-dimensional (2D)

DMA transfers. DMA transfer initialization can be imple-

mented from registers or from sets of parameters called

descriptor blocks.

The 2D DMA capability supports arbitrary row and column

sizes up to 64K elements by 64K elements, and arbitrary row

and column step sizes up to 32K elements. Furthermore, the

column step size can be less than the row step size, allowing

implementation of interleaved data streams. This feature is

especially useful in video applications where data can be de-

interleaved on the fly.

Connect RTC pins RTXI and RTXO with external components

as shown in Figure 5.

RTXI

RTXO

R1

X1

Examples of DMA types supported by the ADSP-BF539/ADSP-

BF539F processor DMA controller include:

C1

C2

• A single, linear buffer that stops upon completion

• A circular, auto-refreshing buffer that interrupts on each

full or fractionally full buffer

• 1-D or 2-D DMA using a linked list of descriptors

SUGGESTED COMPONENTS:

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• 2-D DMA using an array of descriptors, specifying only the

base DMA address within a common page

EPSON MC405 12 pF LOAD (SURFACE-MOUNT PACKAGE)

C1 = 22 pF

C2 = 22 pF

R1 = 10 MΩ

In addition to the dedicated peripheral DMA channels, there are

four memory DMA channels provided for transfers between the

various memories of the ADSP-BF539/ADSP-BF539F processor

system. This enables transfers of blocks of data between any of

the memories—including external SDRAM, ROM, SRAM, and

flash memory—with minimal processor intervention. Memory

NOTE: C1 AND C2 ARE SPECIFIC TO CRYSTAL SPECIFIED FOR X1.

CONTACT CRYSTAL MANUFACTURER FOR DETAILS. C1 AND C2

SPECIFICATIONS ASSUME BOARD TRACE CAPACITANCE OF 3 pF.

Figure 5. External Components for RTC

Rev. PrE

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Page 10 of 70

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May 2006

Preliminary Technical Data

ADSP-BF539/ADSP-BF539F

• Clocking – Each transmit and receive port can either use an

external serial clock or generate its own, in frequencies

ranging from (f_SCLK/131,070) Hz to (f_SCLK/2) Hz.

WATCHDOG TIMER

The ADSP-BF539/ADSP-BF539F processor includes a 32-bit

timer that can be used to implement a software watchdog func-

tion. A software watchdog can improve system availability by

forcing the processor to a known state through generation of a

hardware reset, non-maskable interrupt (NMI), or general pur-

pose interrupt, if the timer expires before being reset by

software. The programmer initializes the count value of the

timer, enables the appropriate interrupt, then enables the timer.

Thereafter, the software must reload the counter before it

counts to zero from the programmed value. This protects the

system from remaining in an unknown state where software,

which would normally reset the timer, has stopped running due

to an external noise condition or software error.

• Word length – Each SPORT supports serial data words

from 3 to 32 bits in length, transferred most significant bit

first or least significant bit first.

• Framing – Each transmit and receive port can run with or

without frame sync signals for each data word. Frame sync

signals can be generated internally or externally, active high

or low, and with either of two pulsewidths and early or late

frame sync.

• Companding in hardware – Each SPORT can perform

A-law or µ-law companding according to ITU recommen-

dation G.711. Companding can be selected on the transmit

and/or receive channel of the SPORT without additional

latencies.

If configured to generate a hardware reset, the watchdog timer

resets both the core and the ADSP-BF539/ADSP-BF539F pro-

cessor peripherals. After a reset, software can determine if the

watchdog was the source of the hardware reset by interrogating

a status bit in the watchdog timer control register.

• DMA operations with single-cycle overhead – Each SPORT

can automatically receive and transmit multiple buffers of

memory data. The processor can link or chain sequences of

DMA transfers between a SPORT and memory.

The timer is clocked by the system clock (SCLK), at a maximum

frequency of f_SCLK

.

• Interrupts – Each transmit and receive port generates an

interrupt upon completing the transfer of a data word or

after transferring an entire data buffer or buffers through

DMA.

TIMERS

There are four general purpose programmable timer units in the

ADSP-BF539/ADSP-BF539F processor. Three timers have an

external pin that can be configured either as a Pulse Width

Modulator (PWM) or timer output, as an input to clock the

timer, or as a mechanism for measuring pulse widths and peri-

ods of external events. These timers can be synchronized to an

external clock input to the PF1 pin, an external clock input to

the PPI_CLK pin, or to the internal SCLK.

• Multichannel capability – Each SPORT supports 128 chan-

nels out of a 1024 channel window and is compatible with

the H.100, H.110, MVIP-90, and HMVIP standards.

SERIAL PERIPHERAL INTERFACE (SPI) PORTS

The ADSP-BF539/ADSP-BF539F processors incorporate three

SPI compatible ports that enable the processor to communicate

with multiple SPI compatible devices.

The timer units can be used in conjunction with the UART to

measure the width of the pulses in the data stream to provide an

auto-baud detect function for a serial channel.

The SPI interface uses three pins for transferring data: two data

pins (master output-slave input, MOSIx, and master input-slave

output, MISOx) and a clock pin (serial clock, SCKx). An SPI

chip select input pin (SPIxSS) lets other SPI devices select the

processor. For SPI0, seven SPI chip select output pins

(SPI0SEL7–1) let the processor select other SPI devices. The SPI

select pins are reconfigured GPIO pins. SPI1 and SPI2 have a

single SPI select for SPI point-to-point communication. Using

these pins, the SPI ports provide a full-duplex, synchronous

serial interface, which supports both master/slave modes and

multimaster environments.

The timers can generate interrupts to the processor core provid-

ing periodic events for synchronization, either to the system

clock or to a count of external signals.

In addition to the three general purpose programmable timers,

a fourth timer is also provided. This extra timer is clocked by the

internal processor clock and is typically used as a system tick

clock for generation of operating system periodic interrupts.

SERIAL PORTS (SPORTS)

The ADSP-BF539/ADSP-BF539F processor incorporates four

dual-channel synchronous serial ports for serial and multipro-

cessor communications. The SPORTs support the following

features:

The SPI ports’ baud rate and clock phase/polarities are pro-

grammable, and it has an integrated DMA controller,

configurable to support transmit or receive data streams. Each

SPI’s DMA controller can only service unidirectional accesses at

any given time.

• I²S capable operation.

• Bidirectional operation – Each SPORT has two sets of inde-

pendent transmit and receive pins, enabling eight channels

of I²S stereo audio.

The SPI port clock rate is calculated as:

f_SCLK

SPI Clock Rate = --------------------------------

2 × SPI_Baud

• Buffered (8-deep) transmit and receive ports – Each port

has a data register for transferring data words to and from

other processor components and shift registers for shifting

data in and out of the data registers.

Where the 16-bit SPI_Baud register contains a value of 2 to

65,535.

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ADSP-BF539/ADSP-BF539F

Preliminary Technical Data

During transfers, the SPI port simultaneously transmits and

receives by serially shifting data in and out on its two serial data

lines. The serial clock line synchronizes the shifting and sam-

pling of data on the two serial data lines.

The capabilities of the UARTs are further extended with sup-

port for the Infrared Data Association (IrDA^®) Serial Infrared

Physical Layer Link Specification (SIR) protocol.

PROGRAMMABLE I/O PINS

TWO WIRE INTERFACE

The ADSP-BF539/ADSP-BF539F processor has numerous

peripherals that may not all be required for every application.

Many of the pins thus have a secondary function, as general

purpose I/O pins. There are two types of programmable I/O

pins on the ADSP-BF539/ADSP-BF539F processor, with

slightly different functionality: programmable flags and general

purpose I/O.

The ADSP-BF539/ADSP-BF539F processor incorporates two

Two Wire Interface (TWI) modules that are compatible with

the Philips Inter-IC bus standard. The TWI modules offer the

capabilities of simultaneous master and slave operation, support

for 7-bit addressing and multimedia data arbitration. The TWI

also includes master clock synchronization and support for

clock low extension.

Programmable Flags (PFx)

The TWI interface uses two pins for transferring clock (SCL)

and data (SDA) and supports the protocol at speeds up to 400

kbits/sec.

The ADSP-BF539/ADSP-BF539F processor has 16 bi-direc-

tional, general purpose Programmable Flag (PF15–0) pins.

Each programmable flag can be individually controlled by

manipulation of the flag control, status and interrupt registers:

The TWI interface pins are compatible with 5V logic levels.

UART PORT

• Flag Direction Control Register – Specifies the direction of

each individual PFx pin as input or output.

The ADSP-BF539/ADSP-BF539F processor incorporates three

full-duplex Universal Asynchronous Receiver/Transmitter

(UART) ports, which are fully compatible with PC standard

UARTs. The UART ports provide a simplified UART interface

to other peripherals or hosts, supporting full-duplex, DMA sup-

ported, asynchronous transfers of serial data. The UART port

includes support for 5 to 8 data bits, 1 or 2 stop bits, and none,

even, or odd parity. The UART port supports two modes of

operation:

• Flag Control and Status Registers – The ADSP-

BF539/ADSP-BF539F processor employs a “write one to

modify” mechanism that allows any combination of indi-

vidual flags to be modified in a single instruction, without

affecting the level of any other flags. Four control registers

are provided. One register is written in order to set flag val-

ues, one register is written in order to clear flag values, one

register is written in order to toggle flag values, and one

register is written in order to specify a flag value. Reading

the flag status register allows software to interrogate the

sense of the flags.

• PIO (Programmed I/O) – The processor sends or receives

data by writing or reading I/O mapped UART registers.

The data is double buffered on both transmit and receive.

• Flag Interrupt Mask Registers – The two Flag Interrupt

Mask Registers allow each individual PFx pin to function as

an interrupt to the processor. Similar to the two Flag Con-

trol Registers that are used to set and clear individual flag

values, one Flag Interrupt Mask Register sets bits to enable

interrupt function, and the other Flag Interrupt Mask reg-

ister clears bits to disable interrupt function. PFx pins

defined as inputs can be configured to generate hardware

interrupts, while output PFx pins can be triggered by soft-

ware interrupts.

• DMA (Direct Memory Access) – The DMA controller

transfers both transmit and receive data. This reduces the

number and frequency of interrupts required to transfer

data to and from memory. The UART has two dedicated

DMA channels, one for transmit and one for receive. These

DMA channels have lower default priority than most DMA

channels because of their relatively low service rates.

The UART port's baud rate, serial data format, error code gen-

eration and status, and interrupts are programmable:

• Supporting bit rates ranging from (f_SCLK/ 1,048,576) to

(f_SCLK/16) bits per second.

• Flag Interrupt Sensitivity Registers – The two Flag Inter-

rupt Sensitivity Registers specify whether individual PFx

pins are level- or edge-sensitive and specify—if edge-sensi-

tive—whether just the rising edge or both the rising and

falling edges of the signal are significant. One register

selects the type of sensitivity, and one register selects which

edges are significant for edge-sensitivity.

• Supporting data formats from 7 to12 bits per frame.

• Both transmit and receive operations can be configured to

generate maskable interrupts to the processor.

The UART port’s clock rate is calculated as:

f_SCLK

UART Clock Rate = -----------------------------------------------

16 × UART_Divisor

General Purpose I/O

The ADSP-BF539/ADSP-BF539F has 38 General Purpose I/O

pins that are multiplexed with other peripherals. They are

arranged into Port C, D, E as shown in Table 4 on Page 13. The

GPIO differ from the Programmable Flags in that the GPIO

pins cannot generate interrupts to the processor.

Where the 16-bit UART_Divisor comes from the DLH register

(most significant 8 bits) and DLL register (least significant

8 bits).

In conjunction with the general purpose timer functions, auto-

baud detection is supported.

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Preliminary Technical Data

ADSP-BF539/ADSP-BF539F

The general purpose I/O pins may be individually controlled by

manipulation of the control and status registers. These pins will

not cause interrupts to be generated to the processor, but may

be polled to determine their status.

up to 16 data pins. The input clock supports parallel data rates

up to f_SCLK/2 MHz, and the synchronization signals can be con-

figured as either inputs or outputs.

The PPI supports a variety of general purpose and ITU-R 656

modes of operation. In general purpose mode, the PPI provides

half-duplex, bi-directional data transfer with up to 16 bits of

data. Up to 3 frame synchronization signals are also provided.

In ITU-R 656 mode, the PPI provides half-duplex, bi-direc-

tional transfer of 8- or 10-bit video data. Additionally, on-chip

decode of embedded start-of-line (SOL) and start-of-field (SOF)

preamble packets is supported.

• GPIO Direction Control Register – Specifies the direction

of each individual GPIOx pin as input or output.

• GPIO Control and Status Registers – The ADSP-

BF539/ADSP-BF539F processor employs a “write one to

modify” mechanism that allows any combination of indi-

vidual GPIO to be modified in a single instruction, without

affecting the level of any other GPIO. Four control registers

and a Data register are provided for each GPIO port. One

register is written in order to set GPIO values, one register

is written in order to clear GPIO values, one register is

written in order to toggle GPIO values, and one register is

written in order to specify a GPIO input or output. Reading

the GPIO Data allows software to determine the state of the

input GPIO pins.

General Purpose Mode Descriptions

The General Purpose modes of the PPI are intended to suit a

wide variety of data capture and transmission applications.

Three distinct submodes are supported:

• Input Mode – Frame Syncs and data are inputs into the

PPI.

Note that the GP pin is used to specify the status of the GPIO

ports C9–C4 at power up. If GP is tied high, then ports C9–C4

are configured as GPIO pins after reset. The ports cannot be

reconfigured through software and special care must be taken

with the MLF pin. If the GP pin is tied low, then the ports are

configured as MXVR pins after reset, but may be reconfigured

as GPIO pins through software.

• Frame Capture Mode – Frame Syncs are outputs from the

PPI, but data are inputs.

• Output Mode – Frame Syncs and data are outputs from the

PPI.

Input Mode

This mode is intended for ADC applications, as well as video

communication with hardware signaling. In its simplest form,

PPI_FS1 is an external frame sync input that controls when to

read data. The PPI_DELAY MMR allows for a delay (in

PPI_CLK cycles) between reception of this frame sync and the

initiation of data reads. The number of input data samples is

user programmable and defined by the contents of the

PPI_Count register. Data widths of 8, 10, 11, 12, 13, 14, 15 and

16-bits are supported, as programmed by the PPI_CONTROL

register.

Table 4. Programmable Flag / GPIO Ports

Peripheral

Alternate Programmable

Flag / GPIO Port Function

PPI

PF15–0

SPORT0

SPORT1

SPORT2

SPORT3

SPI0

GPIO Port E7–0

GPIO Port E15–8

Frame Capture Mode

This mode allows the video source(s) to act as a slave (e.g., for

frame capture). The ADSP-BF539/ADSP-BF539F processor

controls when to read from the video source(s). PPI_FS1 is an

HSYNC output and PPI_FS2 is a VSYNC output.

SPI1

GPIO Port D4–0

GPIO Port D9–5

SPI2

UART0

UART1

UART2

CAN

Output Mode

GPIO Port D11–10

GPIO Port D13–12

GPIO Port C1–0

GPIO Port C9–4

This mode is used for transmitting video or other data with up

to three output frame syncs. Typically, a single frame sync is

appropriate for data converter applications, whereas two or

three frame syncs could be used for sending video with hard-

ware signaling.

MXVR

TWI0

TWI1

ITU-R 656 Mode Descriptions

The ITU-R 656 modes of the PPI are intended to suit a wide

variety of video capture, processing, and transmission applica-

tions. Three distinct submodes are supported:

PARALLEL PERIPHERAL INTERFACE

The ADSP-BF539/ADSP-BF539F processor provides a Parallel

Peripheral Interface (PPI) that can connect directly to parallel

A/D and D/A converters, video encoders and decoders, and

other general purpose peripherals. The PPI consists of a dedi-

cated input clock pin, up to 3 frame synchronization pins, and

• Active Video Only Mode

• Vertical Blanking Only Mode

• Entire Field Mode

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ADSP-BF539/ADSP-BF539F

Preliminary Technical Data

The electrical characteristics of each network connection are

very stringent, therefore the CAN interface is typically divided

into 2 parts: a controller and a transceiver. This allows a single

controller to support different drivers and CAN networks. The

ADSP-BF539/ADSP-BF539F CAN module represents the con-

troller part of the interface. This module's network I/O is a

single transmit output and a single receive input, which connect

to a line transceiver.

Active Video Only Mode

This mode is used when only the active video portion of a field

is of interest and not any of the blanking intervals. The PPI will

not read in any data between the End of Active Video (EAV)

and Start of Active Video (SAV) preamble symbols, or any data

present during the vertical blanking intervals. In this mode, the

control byte sequences are not stored to memory; they are fil-

tered by the PPI. After synchronizing to the start of Field 1, the

PPI will ignore incoming samples until it sees an SAV code. The

user specifies the number of active video lines per frame (in

PPI_Count register).

The CAN clock is derived from the processor System Clock

(SCLK) through a programmable divider and therefore does not

require an additional crystal.

MEDIA TRANSCEIVER MAC LAYER (MXVR)

Vertical Blanking Interval Mode

In this mode, the PPI only transfers vertical blanking interval

(VBI) data.

The ADSP-BF539/ADSP-BF539F processor provides a Media

Transceiver (MXVR) MAC layer, allowing the processor to be

connected directly to a MOST^®network through just an FOT or

Electrical PHY.

Entire Field Mode

In this mode, the entire incoming bit stream is read in through

the PPI. This includes active video, control preamble sequences,

and ancillary data that may be embedded in horizontal and ver-

tical blanking intervals. Data transfer starts immediately after

synchronization to Field 1. The MXVR supports synchronous

data, asynchronous packets and control messages. Data is trans-

ferred to or from the synchronous channels through eight DMA

engines that work autonomously from the processor core.

The MXVR is fully compatible with the industry standard stan-

dalone MOST controller devices, supporting 22.579 Mbps or

24.576 Mbps data transfer. It offers faster lock times, greater jit-

ter immunity, a sophisticated DMA scheme for data transfers,

and the high-speed internal interface to the core and L1 mem-

ory allows the full bandwidth of the network to be utilized. The

MXVR can operate as either the network master or as a network

slave.

The MXVR supports synchronous data, asynchronous packets,

and control messages using dedicated DMA engines which

operate autonomously from the processor core moving data to

and from L1 memory. Synchronous data is transferred to or

from the synchronous data channels through eight programma-

ble DMA engines. The synchronous data DMA engines can

operate in various modes including modes which trigger DMA

operation when data patterns are detected in the receive data

stream. Furthermore two DMA engines support asynchronous

traffic and a further two support control message traffic.

CONTROLLER AREA NETWORK (CAN) INTERFACE

The ADSP-BF539/ADSP-BF539F processor provides a CAN

controller that is a communication controller implementing the

Controller Area Network (CAN) V2.0B protocol. This protocol

is an asynchronous communications protocol used in both

industrial and automotive control systems. CAN is well suited

for control applications due to its capability to communicate

reliably over a network since the protocol incorporates CRC

checking message error tracking, and fault node confinement.

The CAN controller is based on a 32 entry mailbox RAM and

supports both the standard and extended identifier (ID) mes-

sage formats specified in the CAN protocol specification,

revision 2.0, part B.

Interrupts are generated when a user defined amount of syn-

chronous data has been sent or received by the processor or

when asynchronous packets or control messages have been sent

or received.

Each mailbox consists of eight 16-bit data words. The data is

divided into fields, which includes a message identifier, a time

stamp, a byte count, up to 8 bytes of data, and several control

bits. Each node monitors the messages being passed on the net-

work. If the identifier in the transmitted message matches an

identifier in one of it's mailboxes, then the module knows that

the message was meant for it, passes the data into it's appropri-

ate mailbox, and signals the processor of message arrival with an

interrupt.

The MXVR peripheral can wake up the ADSP-BF539/ADSP-

BF539F processor from Sleep mode when a wakeup preamble is

received over the network or based on any other MXVR inter-

rupt event. Additionally, detection of network activity by the

MXVR can be used to wake up the ADSP-BF539/ADSP-BF539F

processor from Deep Sleep or Hibernate mode, and wake up the

on-chip internal voltage regulator from a powered-down state.

These features allow the ADSP-BF539/ADSP-BF539F to operate

in a low-power state when there is no network activity or when

data is not currently being received or transmitted by the

MXVR.

The CAN Controller can wake up the ADSP-BF539/ADSP-

BF539F processor from Sleep mode upon generation of a

wakeup event, such that the processor can be maintained in a

low power mode during idle conditions. Additionally, a CAN

wakeup event can wake up the ADSP-BF539/ADSP-BF539F

processor from Deep Sleep or Hibernate mode, and wake up the

on-chip internal voltage regulator from a powered-down state.

The MXVR clock is provided through a dedicated external crys-

tal or crystal oscillator. For 44.1 KHz frame syncs, a 45.1584

MHz crystal or oscillator should be used; or for 48 KHz frame

syncs, a 49.152 MHz crystal or oscillator should be used.

Rev. PrE

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Page 14 of 70

| May 2006

Preliminary Technical Data

ADSP-BF539/ADSP-BF539F

Deep Sleep Operating Mode—Maximum Dynamic Power

Savings

DYNAMIC POWER MANAGEMENT

The ADSP-BF539/ADSP-BF539F processor provides five oper-

ating modes, each with a different performance/power profile.

In addition, Dynamic Power Management provides the control

functions to dynamically alter the processor core supply voltage,

further reducing power dissipation. Control of clocking to each

of the ADSP-BF539/ADSP-BF539F processor peripherals also

reduces power consumption. See Table 5 for a summary of the

power settings for each mode.

The Deep Sleep mode maximizes dynamic power savings by

disabling the clocks to the processor core (CCLK) and to all syn-

chronous peripherals (SCLK). Asynchronous peripherals such

as the RTC may still be running, but will not be able to access

internal resources or external memory. This powered down

mode can only be exited by assertion of the reset interrupt

(RESET) or by an asynchronous interrupt generated by the

RTC. When in Deep Sleep mode, an RTC asynchronous inter-

rupt causes the processor to transition to the Active mode.

Assertion of RESET while in Deep Sleep mode causes the pro-

cessor to transition to the Full On mode.

Full-On Operating Mode—Maximum Performance

In the Full-On mode, the PLL is enabled and is not bypassed,

providing capability for maximum operational frequency. This

is the powerup default execution state in which maximum per-

formance can be achieved. The processor core and all enabled

peripherals run at full speed.

Hibernate Operating Mode—Maximum Static Power

Savings

The Hibernate mode maximizes static power savings by dis-

abling the voltage and clocks to the processor core (CCLK) and

to all the synchronous peripherals (SCLK). The internal voltage

regulator for the processor can be shut off by writing b#00 to the

FREQ bits of the VR_CTL register. This disables both CCLK

and SCLK. Furthermore, it sets the internal power supply volt-

age (V_DDINT) to 0 V to provide the lowest static power

dissipation. Any critical information stored internally (memory

contents, register contents, etc.) must be written to a non-vola-

tile storage device prior to removing power if the processor state

is to be preserved. Since V_DDEXTis still supplied in this mode, all

of the external pins three-state, unless otherwise specified. This

allows other devices that may be connected to the processor to

have power still applied without drawing unwanted current.

The internal supply regulator can be woken up either by a Real

Time Clock wakeup, by CAN bus traffic, by asserting the RESET

pin or by MOST bus traffic causing the MRXON pin to assert.

Active Operating Mode—Moderate Power Savings

In the Active mode, the PLL is enabled but bypassed. Because

the PLL is bypassed, the processor’s core clock (CCLK) and sys-

tem clock (SCLK) run at the input clock (CLKIN) frequency. In

this mode, the CLKIN to CCLK multiplier ratio can be changed,

although the changes are not realized until the Full-On mode is

entered. DMA access is available to appropriately configured L1

memories.

In the Active mode, it is possible to disable the PLL through the

PLL Control register (PLL_CTL). If disabled, the PLL must be

re-enabled before transitioning to the Full-On or Sleep modes.

Table 5. Power Settings

Power Savings

Full On

Active

Sleep

Enabled

No

Enabled Enabled On

Disabled Enabled On

Disabled Disabled On

Disabled Disabled Off

As shown in Table 6, the ADSP-BF539/ADSP-BF539F proces-

sor supports three different power domains. The use of multiple

power domains maximizes flexibility, while maintaining com-

pliance with industry standards and conventions. By isolating

the internal logic of the ADSP-BF539/ADSP-BF539F processor

into its own power domain, separate from the RTC and other

I/O, the processor can take advantage of Dynamic Power Man-

agement, without affecting the RTC or other I/O devices. There

are no sequencing requirements for the various power domains.

Enabled/ Disabled Yes

Enabled

Deep Sleep Disabled

Hibernate Disabled

Sleep Operating Mode—High Dynamic Power Savings

The Sleep mode reduces dynamic power dissipation by dis-

abling the clock to the processor core (CCLK). The PLL and

system clock (SCLK), however, continue to operate in this

mode. Typically an external event or RTC activity will wake up

the processor. When in the Sleep mode, assertion of wakeup will

cause the processor to sense the value of the BYPASS bit in the

PLL Control register (PLL_CTL). If BYPASS is disabled, the

processor will transition to the Full On mode. If BYPASS is

enabled, the processor will transition to the Active mode. When

in the Sleep mode, system DMA access to L1 memory is not

supported.

Table 6. Power Domains

Power Domain

VDD Range

VDDRTC

MXEVDD

MPIVDD

VDDINT

RTC crystal I/O and logic

MXVR crystal I/O

MXVR PLL analog and logic

All internal logic except RTC and MXVR PLL

All I/O except RTC and MXVR crystals

VDDEXT

The power dissipated by a processor is largely a function of the

clock frequency of the processor and the square of the operating

voltage. For example, reducing the clock frequency by 25%

Rev. PrE

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Page 15 of 70

| May 2006

ADSP-BF539/ADSP-BF539F

Preliminary Technical Data

results in a 25% reduction in power dissipation, while reducing

the voltage by 25% reduces power dissipation by more than

40%. Further, these power savings are additive, in that if the

clock frequency and supply voltage are both reduced, the power

savings can be dramatic.

I/O

POWER

PINS

100 µF

2.7 V - 3.6 V

INPUT VOLTAGE

RANGE

10 µH

0.1 µF

ZHCS1000

INTERNAL

POWER

PINS

The Dynamic Power Management feature of the ADSP-

BF539/ADSP-BF539F processor allows both the processor’s

input voltage (V_DDINT) and clock frequency (f_CCLK) to be dynam-

ically controlled.

FDS9431A

100 µF

1 µF

The savings in power dissipation can be modeled using the

Power Savings Factor and % Power Savings calculations.

VROUT1-0

EXTERNAL COMPONENTS

The Power Savings Factor is calculated as:

NOTE: VROUT1-0 SHOULD BE TIED TOGETHER EXTERNALLY

AND DESIGNER SHOULD MINIMIZE TRACE LENGTH TO FDS9431A.

Power Savings Factor

2

Figure 6. Voltage Regulator Circuit

f_CCLKRED

---------------------

f_CCLKNOM

V_DDINTRED

--------------------------

V_DDINTNOM

T_RED

------------

T_NOM

⎛

⎝

⎞

⎠

⎛

⎝

⎞

⎠

=

×

If an external clock is used, it should be a TTL compatible signal

and must not be halted, changed, or operated below the speci-

fied frequency during normal operation. This signal is

connected to the processor’s CLKIN pin. When an external

clock is used, the XTAL pin must be left unconnected.

where the variables in the equations are:

• f_CCLKNOMis the nominal core clock frequency

• f_CCLKREDis the reduced core clock frequency

• V_DDINTNOMis the nominal internal supply voltage

• V_DDINTREDis the reduced internal supply voltage

• T_NOMis the duration running at f_CCLKNOM

Alternatively, because the ADSP-BF539/ADSP-BF539F proces-

sor includes an on-chip oscillator circuit, an external crystal

may be used. The crystal should be connected across the CLKIN

and XTAL pins, with two capacitors connected as shown in

Figure 7. Capacitor values are dependent on crystal type and

should be specified by the crystal manufacturer. A parallel-reso-

nant, fundamental frequency, microprocessor-grade crystal

should be used.

• T_REDis the duration running at f_CCLKRED

The Power Savings Factor is calculated as:

% Power Savings = (1 – Power Savings Factor) × 100%

VOLTAGE REGULATION

The Blackfin processor provides an on-chip voltage regulator

that can generate processor core voltage levels

XTAL

CLKOUT

CLKIN

1.0 V(–5%/+10%) to 1.2V(–5% / +10%) from an external

2.7 V to 3.6 V supply. Figure 6 shows the typical external com-

ponents required to complete the power management system.^†

The regulator controls the internal logic voltage levels and is

programmable with the Voltage Regulator Control Register

(VR_CTL) in increments of 50 mV. To reduce standby power

consumption, the internal voltage regulator can be programmed

to remove power to the processor core while I/O power

(VDDRTC, MXEVDD, VDDEXT) is still supplied. While in

Hibernate mode, I/O power is still being applied, eliminating

the need for external buffers. The voltage regulator can be acti-

vated from this power-down state either through an RTC

wakeup, a CAN wakeup, an MXVR wakeup, or by asserting

RESET, which will then initiate a boot sequence. The regulator

can also be disabled and bypassed at the user’s discretion.

BLACKFIN

PROCESSOR

Figure 7. External Crystal Connections

As shown in Figure 8 on Page 17, the core clock (CCLK) and

system peripheral clock (SCLK) are derived from the input

clock (CLKIN) signal. An on-chip PLL is capable of multiplying

the CLKIN signal by a user programmable 0.5× to 64× multipli-

cation factor (bounded by specified minimum and maximum

VCO frequencies). The default multiplier is 10×, but it can be

modified by a software instruction sequence. On-the-fly fre-

quency changes can be effected by simply writing to the

PLL_DIV register.

CLOCK SIGNALS

All on-chip peripherals are clocked by the system clock (SCLK).

The system clock frequency is programmable by means of the

SSEL3–0 bits of the PLL_DIV register. The values programmed

The ADSP-BF539/ADSP-BF539F processor can be clocked by

an external crystal, a sine wave input, or a buffered, shaped

clock derived from an external clock oscillator.

^†See EE-228: Switching Regulator Design Considerations for ADSP-BF533

Blackfin Processors.

Rev. PrE

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Page 16 of 70

| May 2006

Preliminary Technical Data

ADSP-BF539/ADSP-BF539F

BOOTING MODES

“FINE” ADJUSTMENT

REQUIRES PLL SEQUENCING

“COARSE” ADJUSTMENT

ON-THE-FLY

The ADSP-BF539/ADSP-BF539F processor has three mecha-

nisms (listed in Table 9) for automatically loading internal L1

instruction memory after a reset. A fourth mode is provided to

execute from external memory, bypassing the boot sequence.

÷ 1, 2, 4, 8

CCLK

SCLK

PLL

0.5×-64×

CLKIN

VCO

Table 9. Booting Modes

÷ 1:15

BMODE1–0 Description

00

Execute from 16-bit external memory

(bypass boot ROM)

SCLK ≤ CCLK

SCLK ≤ 133MHz

01

Boot from 8-bit or 16-bit flash (ADSP-BF539 only) or

Boot from onboard flash (ADSP-BF539F only)

Figure 8. Frequency Modification Methods

10

11

Boot from SPI serial master

into the SSEL fields define a divide ratio between the PLL output

(VCO) and the system clock. SCLK divider values are 1 through

15. Table 7 illustrates typical system clock ratios:

Boot from SPI serial slave EEPROM /flash

(8-,16-, or 24-bit address range, or Atmel

AT45DB041, AT45DB081, or AT45DB161serial flash)

Table 7. Example System Clock Ratios

The BMODE pins of the Reset Configuration Register, sampled

during power-on resets and software initiated resets, implement

the following modes:

Signal Name Divider Ratio Example Frequency Ratios (MHz)

SSEL3–0

VCO/SCLK

VCO

100

300

500

SCLK

100

50

0001

0110

1010

1:1

• Execute from 16-bit external memory – Execution starts

from address 0x2000 0000 with 16-bit packing. The boot

ROM is bypassed in this mode. All configuration settings

are set for the slowest device possible (3-cycle hold time;

15-cycle R/W access times; 4-cycle setup).

6:1

10:1

50

The maximum frequency of the system clock is f_SCLK. Note that

the divisor ratio must be chosen to limit the system clock fre-

quency to its maximum of f_SCLK. The SSEL value can be changed

dynamically without any PLL lock latencies by writing the

appropriate values to the PLL divisor register (PLL_DIV).

• Boot from 8-bit external flash memory – The 8-bit flash

boot routine located in boot ROM memory space is set up

using asynchronous memory bank 0. If FCE is connected

to AMS0, then the on-chip flash is booted from the ADSP-

BF539F. All configuration settings are set for the slowest

device possible (3-cycle hold time; 15-cycle R/W access

times; 4-cycle setup).

Note that when the SSEL value is changed, it will affect all the

peripherals that derive their clock signals from the SCLK signal.

The core clock (CCLK) frequency can also be dynamically

changed by means of the CSEL1–0 bits of the PLL_DIV register.

Supported CCLK divider ratios are 1, 2, 4, and 8, as shown in

Table 8. This programmable core clock capability is useful for

fast core frequency modifications.

• Boot from SPI serial EEPROM/flash (8-, 16-, or 24-bit

addressable, or Atmel AT45DB041, AT45DB081, or

AT45DB161) – The SPI uses the PF2 output pin to select a

single SPI EEPROM/flash device, submits a read command

and successive address bytes (0x00) until a valid 8-, 16-, or

24-bit, or Atmel addressable device is detected, and begins

clocking data into the beginning of the L1 instruction

memory.

Table 8. Core Clock Ratios

Signal Name Divider Ratio Example Frequency Ratios

CSEL1–0

VCO/CCLK

• Boot from SPI host device – The Blackfin processor oper-

ates in SPI slave mode and is configured to receive the bytes

of the .LDR file from an SPI host (master) agent. To hold

off the host device from transmitting while the boot ROM

is busy, the Blackfin processor asserts a GPIO pin, called

host wait (HWAIT), to signal the host device not to send

any more bytes until the flag is deasserted. The flag is cho-

sen by the user and this information is transferred to the

Blackfin processor via bits 10:5 of the FLAG header.

VCO

300

500

200

CCLK

300

150

125

25

00

01

10

11

1:1

2:1

4:1

8:1

For each of the boot modes, a 10-byte header is first read from

an external memory device. The header specifies the number of

bytes to be transferred and the memory destination address.

Rev. PrE

|

Page 17 of 70

| May 2006

ADSP-BF539/ADSP-BF539F

Preliminary Technical Data

Multiple memory blocks may be loaded by any boot sequence.

Once all blocks are loaded, program execution commences from

the start of L1 instruction SRAM.

VisualDSP++^®^‡development environment. The same emulator

hardware that supports other Blackfin processors also fully

emulates the ADSP-BF539/ADSP-BF539F processor.

In addition, bit 4 of the Reset Configuration Register can be set

by application code to bypass the normal boot sequence during

a software reset. For this case, the processor jumps directly to

the beginning of L1 instruction memory.

The VisualDSP++ project management environment lets pro-

grammers develop and debug an application. This environment

includes an easy to use assembler (which is based on an alge-

braic syntax), an archiver (librarian/library builder), a linker, a

loader, a cycle-accurate instruction-level simulator, a C/C++

compiler, and a C/C++ runtime library that includes DSP and

mathematical functions. A key point for these tools is C/C++

code efficiency. The compiler has been developed for efficient

translation of C/C++ code to processor assembly. The processor

has architectural features that improve the efficiency of com-

piled C/C++ code.

To augment the boot modes, a secondary software loader is pro-

vided that adds additional booting mechanisms. This secondary

loader provides the capability to boot from 16-bit flash memory,

fast flash, variable baud rate, and other sources. In all Boot

modes except Bypass, program execution starts from on-chip L1

memory address 0xFFA0 0000.

INSTRUCTION SET DESCRIPTION

The VisualDSP++ debugger has a number of important fea-

tures. Data visualization is enhanced by a plotting package that

offers a significant level of flexibility. This graphical representa-

tion of user data enables the programmer to quickly determine

the performance of an algorithm. As algorithms grow in com-

plexity, this capability can have increasing significance on the

designer’s development schedule, increasing productivity. Sta-

tistical profiling enables the programmer to non intrusively poll

the processor as it is running the program. This feature, unique

to VisualDSP++, enables the software developer to passively

gather important code execution metrics without interrupting

the real time characteristics of the program. Essentially, the

developer can identify bottlenecks in software quickly and effi-

ciently. By using the profiler, the programmer can focus on

those areas in the program that impact performance and take

corrective action.

The Blackfin processor family assembly language instruction set

employs an algebraic syntax designed for ease of coding and

readability. The instructions have been specifically tuned to pro-

vide a flexible, densely encoded instruction set that compiles to

a very small final memory size. The instruction set also provides

fully featured multifunction instructions that allow the pro-

grammer to use many of the processor core resources in a single

instruction. Coupled with many features more often seen on

microcontrollers, this instruction set is very efficient when com-

piling C and C++ source code. In addition, the architecture

supports both user (algorithm/application code) and supervisor

(O/S kernel, device drivers, debuggers, ISRs) modes of opera-

tion, allowing multiple levels of access to core processor

resources.

The assembly language, which takes advantage of the proces-

sor’s unique architecture, offers the following advantages:

Debugging both C/C++ and assembly programs with the

VisualDSP++ debugger, programmers can:

• Seamlessly integrated DSP/CPU features are optimized for

both 8-bit and 16-bit operations.

• View mixed C/C++ and assembly code (interleaved source

and object information).

• A multi-issue load/store modified Harvard architecture,

which supports two 16-bit MAC or four 8-bit ALU plus

two load/store plus two pointer updates per cycle.

• Insert breakpoints.

• Set conditional breakpoints on registers, memory,

and stacks.

• All registers, I/O, and memory are mapped into a unified

4G byte memory space, providing a simplified program-

ming model.

• Trace instruction execution.

• Perform linear or statistical profiling of program execution.

• Fill, dump, and graphically plot the contents of memory.

• Perform source level debugging.

• Microcontroller features, such as arbitrary bit and bit-field

manipulation, insertion, and extraction; integer operations

on 8-, 16-, and 32-bit data types; and separate user and

supervisor stack pointers.

• Create custom debugger windows.

• Code density enhancements, which include intermixing of

16- and 32-bit instructions (no mode switching, no code

segregation). Frequently used instructions are encoded in

16 bits.

The VisualDSP++ IDDE lets programmers define and manage

software development. Its dialog boxes and property pages let

programmers configure and manage all of the Blackfin develop-

ment tools, including the color syntax highlighting in the

VisualDSP++ editor. This capability permits programmers to:

DEVELOPMENT TOOLS

• Control how the development tools process inputs and

generate outputs.

The ADSP-BF539/ADSP-BF539F processor is supported with a

complete set of CROSSCORE^®^†software and hardware develop-

ment tools, including Analog Devices emulators and

• Maintain a one-to-one correspondence with the tool’s

command line switches.

^†CROSSCORE is a registered trademark of Analog Devices, Inc.

^‡VisualDSP++ is a registered trademark of Analog Devices, Inc.

Rev. PrE

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Page 18 of 70

| May 2006

Preliminary Technical Data

ADSP-BF539/ADSP-BF539F

The VisualDSP++ Kernel (VDK) incorporates scheduling and

resource management tailored specifically to address the mem-

ory and timing constraints of DSP programming. These

capabilities enable engineers to develop code more effectively,

eliminating the need to start from the very beginning, when

developing new application code. The VDK features include

Threads, Critical and Unscheduled regions, Semaphores,

Events, and Device flags. The VDK also supports Priority-based,

Preemptive, Cooperative, and Time-Sliced scheduling

uses the TAP to access the internal features of the processor,

allowing the developer to load code, set breakpoints, observe

variables, observe memory, and examine registers. The proces-

sor must be halted to send data and commands, but once an

operation has been completed by the emulator, the processor

system is set running at full speed with no impact on system

timing.

To use these emulators, the target board must include a header

that connects the processor’s JTAG port to the emulator.

approaches. In addition, the VDK was designed to be scalable. If

the application does not use a specific feature, the support code

for that feature is excluded from the target system.

For details on target board design issues including mechanical

layout, single processor connections, multiprocessor scan

chains, signal buffering, signal termination, and emulator pod

logic, see EE-68: Analog Devices JTAG Emulation Technical Ref-

erence on the Analog Devices web site (www.analog.com)—use

site search on “EE-68.” This document is updated regularly to

keep pace with improvements to emulator support.

Because the VDK is a library, a developer can decide whether to

use it or not. The VDK is integrated into the VisualDSP++

development environment, but can also be used via standard

command line tools. When the VDK is used, the development

environment assists the developer with many error prone tasks

and assists in managing system resources, automating the gen-

eration of various VDK based objects, and visualizing the

system state, when debugging an application that uses the VDK.

EXAMPLE CONNECTIONS AND LAYOUT

CONSIDERATIONS

Figure 9 shows an example circuit connection of the ADSP-

BF539/ADSP-BF539F connecting to a MOST network. This

diagram is intended as an example and exact connections and

recommended circuit values should be obtained from Analog

Devices.

VCSE is Analog Devices technology for creating, using, and

reusing software components (independent modules of sub-

stantial functionality) to quickly and reliably assemble software

applications. Download components from the Web and drop

them into the application. Publish component archives from

within VisualDSP++. VCSE supports component implementa-

tion in C/C++ or assembly language.

VOLTAGE REGULATOR LAYOUT GUIDELINES

Regulator external component placement, board routing, and

bypass capacitors all have a significant effect on noise injected

into the other analog circuits on-chip. The VROUT1-0 traces

and voltage regulator external components should be consid-

ered as noise sources when doing board layout and should not

be routed or placed near sensitive circuits or components on the

board. All internal and I/O power supplies should be well

bypassed with bypass capacitors placed as close to the ADSP-

BF539/ADSP-BF539F as possible.

Use the Expert Linker to visually manipulate the placement of

code and data on the embedded system. View memory utiliza-

tion in a color coded graphical form, easily move code and data

to different areas of the processor or external memory with the

drag of the mouse, examine run time stack and heap usage. The

Expert Linker is fully compatible with existing Linker Definition

File (LDF), allowing the developer to move between the graphi-

cal and textual environments.

Analog Devices emulators use the IEEE 1149.1 JTAG Test

Access Port of the ADSP-BF539/ADSP-BF539F processor to

monitor and control the target board processor during emula-

tion. The emulator provides full speed emulation, allowing

inspection and modification of memory, registers, and proces-

sor stacks. Non intrusive in-circuit emulation is assured by the

use of the processor’s JTAG interface—the emulator does not

affect target system loading or timing.

For further details on the on-chip voltage regulator and related

board design guidelines, see the EE-228: Switching Regulator

Design Considerations for ADSP-BF533 Blackfin Processors

applications note on the Analog Devices web site (www.ana-

log.com)—use site search on “EE-228.”.

MXVR BOARD LAYOUT GUIDELINES

MLF pin

In addition to the software and hardware development tools

available from Analog Devices, third parties provide a wide

range of tools supporting the Blackfin processor family. Hard-

ware tools include Blackfin processor PC plug-in cards. Third

party software tools include DSP libraries, real time operating

systems, and block diagram design tools.

• Capacitors:

C1: 0.1µF (PPS type, 2% tolerance recommended)

C2: 0.01µF (PPS type, 2% tolerance recommended)

• Resistor:

R1: 220 ohm (1% tolerance)

DESIGNING AN EMULATOR COMPATIBLE

PROCESSOR BOARD

• The RC network connected to the MLF pin should be

located physically close to the MLF pin on the board.

The Analog Devices family of emulators are tools that every sys-

tem developer needs to test and debug hardware and software

systems. Analog Devices has supplied an IEEE 1149.1 JTAG

Test Access Port (TAP) on each JTAG processor. The emulator

• The RC network should be wired up and connected to the

MLF pin using wide traces.

• The capacitors in the RC network should be grounded to

MXEGND.

Rev. PrE

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Page 19 of 70

| May 2006

ADSP-BF539/ADSP-BF539F

Preliminary Technical Data

5 V

MOST FOT

VDDINT (1.2 V)

Rx_Vdd

ADSP-BF539F

FB

Tx_Vdd

MTXON

Power Gating Circuit

27 6

PIVDD

MOST

Network

TX_Data

RX_Data

Status

MTX

0.1 MF

0.01 MF

MRX

MXEGND

MRXON

49.152 MHz Oscillator

CLKO

MXI

MXO

MLF

RFS0

MFS

33 6

L/RCLK

MCLK

Audio

DAC

MMCLK

MBCLK

R1

220 6

Audio

C2

Channels

BCLK

0.01 MF

TSCLK0

RSCLK0

C1

0.1 MF

MXEGND

DT0PRI

SDATA

Figure 9. Example connections of ADSP-BF539/ADSP-BF539F to MOST Network

• The RC network should be shielded using MXEGND

traces.

MXEGND - MXVR Crystal Oscillator and MXVR PLL Ground

• Should be routed with wide traces or as ground plane.

• Avoid routing other switching signals near the RC network

to avoid crosstalk.

• Should be tied together to other board grounds at only one

point on the board.

MXI driven with external Clock Oscillator IC (recommended)

• Avoid routing other switching signals near to MXEGND to

avoid crosstalk.

• MXI should be driven with the clock output of a

49.152MHz or 45.1584MHz clock oscillator IC.

MXEVDD - MXVR Crystal Oscillator 3.3V Power

• Should be routed with wide traces or as power plane.

• MXO should be left unconnected.

• Avoid routing other switching signals near the oscillator

and clock output trace to avoid crosstalk. When not possi-

ble, shield traces with ground.

• Locally bypass MXEVDD with 0.1µF and 0.01µF decou-

pling capacitors to MXEGND.

• Avoid routing other switching signals near to MXEVDD to

avoid crosstalk.

MXI/MXO with external Crystal

• The crystal must be a 49.152MHz or 45.1584MHz funda-

mental mode crystal.

MPIVDD - MXVR PLL 1.2V Power

• Should be routed with wide traces or as power plane.

• The crystal and load capacitors should be placed physically

close to the MXI and MXO pins on the board.

• A ferrite bead should be placed between the 1.2V VDDINT

power plane and the MPIVDD pin for noise isolation.

• The load capacitors should be grounded to MXEGND.

• Locally bypass MPIVDD with 0.1µF and 0.01µF decou-

pling capacitors to MXEGND.

• The crystal and load capacitors should be wired up using

wide traces.

• Avoid routing other switching signals near to MPIVDD to

avoid crosstalk.

• Board trace capacitance on each lead should not be more

than 3pF.

Fiber Optic Transceiver (FOT) Connections

• Trace capacitance plus load capacitance should equal the

load capacitance specification for the crystal.

• The traces between ADSP-BF539/ADSP-BF539F and the

FOT should be kept as short as possible.

• Avoid routing other switching signals near the crystal and

components to avoid crosstalk. When not possible, shield

traces and components with ground.

• The receive data trace connecting the FOT Receive Data

output pin to the ADSP-BF539/ADSP-BF539F MRX input

pin should not have a series termination resistor. The edge

Rev. PrE

|

Page 20 of 70

| May 2006

Preliminary Technical Data

ADSP-BF539/ADSP-BF539F

rate of the FOT Receive Data signal driven by the FOT is

typically very slow and further degradation of the edge rate

is not desirable.

• The transmit data trace connecting the ADSP-

BF539/ADSP-BF539F MTX output pin to the FOT Trans-

mit Data input pin should have a 27 Ohm series

termination resistor placed close to the ADSP-

BF539/ADSP-BF539F MTX pin.

• The receive data trace and the transmit data trace between

the ADSP-BF539/ADSP-BF539F and the FOT should not

be routed close to each other in parallel over long distances

to avoid crosstalk.

Rev. PrE

|

Page 21 of 70

| May 2006

ADSP-BF539/ADSP-BF539F

Preliminary Technical Data

PIN DESCRIPTIONS

ADSP-BF539/ADSP-BF539F processor pin definitions are listed

in Table 10. In order to maintain maximum functionality and

reduce package size and pin count, some pins have dual, multi-

plexed functionality. In cases where pin functionality is

reconfigurable, the default state is shown in plain text, while

alternate functionality is shown in italics.

Table 10. Pin Descriptions

Driver

Pin Name

Type Function

Type¹Pull-Up/Down Requirement

Memory Interface

ADDR19–1

O

Address Bus for Async/Sync Access

A

DATA15–0

I/O

O

I

Data Bus for Async/Sync Access

A

Byte Enables/Data Masks for Async/Sync Access A

Bus Request

ABE1–0/SDQM1–0

BR

Pull High When Not Used

Pull LOW when not used.

BG

O

Bus Grant

A

BGH

Bus Grant Hang

Asynchronous Memory Control

AMS3–0

O

I

Bank Select

A

ARDY

Hardware Ready Control

Output Enable

Read Enable

AOE

O

A

ARE

AWE

Write Enable

Flash Control

FCE

I

Flash Enable (ADSP-BF539F only)

Flash Reset (ADSP-BF539F only)

Leave unconnected for ADSP-BF539

FRESET

Synchronous Memory Control

A

B

SRAS

O

Row Address Strobe

Column Address Strobe

Write Enable

SCAS

SWE

SCKE

Clock Enable

CLKOUT

Clock Output

A10 Pin

SA10

A

SMS

Bank Select

Timers

TMR0

I/O

Timer 0

C

TMR1/PPI_FS1

Timer 1/PPI Frame Sync1

Timer 2/PPI Frame Sync2

TMR2/PPI_FS2

Parallel Peripheral Interface Port/GPIO

PF0/SPI0SS

I/O

Programmable Flag 0/SPI Slave Select Input

C

PF1/SPI0SEL1/TMRCLK

Programmable Flag 1/SPI Slave Select Enable 1/

External Timer Reference

PF2/SPI0SEL2

I/O

Programmable Flag 2/SPI Slave Select Enable 2

C

PF3/SPI0SEL3/PPI_FS3

Programmable Flag 3/SPI Slave Select Enable 3/

PPI Frame Sync 3

Rev. PrE

|

Page 22 of 70

| May 2006

Preliminary Technical Data

ADSP-BF539/ADSP-BF539F

Table 10. Pin Descriptions (Continued)

Driver

Pin Name

Type Function

Type¹Pull-Up/Down Requirement

PF4/SPI0SEL4/PPI15

I/O

Programmable Flag 4/

SPI Slave Select Enable 4/PPI 15

C

PF5/SPI0SEL5/PPI14

PF6/SPI0SEL6/PPI13

PF7/SPI0SEL7/PPI12

Programmable Flag 5/

SPI Slave Select Enable 5/PPI 14

Programmable Flag 6/

SPI Slave Select Enable 6/PPI 13

Programmable Flag 7/

SPI Slave Select Enable 7/PPI 12

PF8/PPI11

PF9/PPI10

I/O

I

Programmable Flag 8/PPI 11

Programmable Flag 9/PPI 10

Programmable Flag 10/PPI 9

Programmable Flag 11/PPI 8

Programmable Flag 12/PPI 7

Programmable Flag 13/PPI 6

Programmable Flag 14/PPI 5

Programmable Flag 15/PPI 4

PPI3–0

C

PF10/PPI9

PF11/PPI8

PF12/PPI7

PF13/PPI6

PF14/PPI5

PF15/PPI4

PPI3–0

PPI_CLK

PPI Clock

Controller Area Network

CANTX/GPIOC0

CANRX/GPIOC1

I/O 5V CAN Transmit/GPIO_C_0

I/O 5V CAN Receive/GPIO_C_1

C

Media Transceiver ( MXVR)/

General Purpose I/O

MTX/GPIOC5

MTXON/GPIOC9

MRX/GPIOC4

MRXON

I/O

MXVR Transmit Data/GPIO_C_5

MXVR Transmit FOT On/GPIO_C_9

C

I/O 5V MXVR Receive Data/GPIO_C_4

C

Pull LOW when not used.

Pull High When Not Used

Pull LOW when not used.

Leave unconnected when not used.

Pull LOW when not used.

I 5V

I

MXVR FOT Receive On

MXVR Crystal Input

MXI

MXO

O

MXVR Crystal Output

MXVR Loop Filter

MLF

I

MMCLK/GPIOC6

MBCLK/GPIOC7

MFS/GPIOC8

GP

I/O

I

MXVR Master Clock/GPIO_C_6

MXVR Bit Clock/GPIO_C_7

MXVR Frame Sync/GPIO_C_8

GPIO_C_4–9 Enable

C

Pull LOW when not used.

Two Wire Interface Port

SDA0

I/O 5V TWI0 Serial Data

I/O 5V TWI0 Serial Clock

I/O 5V TWI1 Serial Data

I/O 5V TWI1 Serial Clock

E²

SCL0

SDA1

SCL1

Rev. PrE

|

Page 23 of 70

| May 2006

ADSP-BF539/ADSP-BF539F

Preliminary Technical Data

Table 10. Pin Descriptions (Continued)

Driver

Pin Name

Type Function

Type¹Pull-Up/Down Requirement

Serial Port0

RSCLK0

I/O

I

SPORT0 Receive Serial Clock

SPORT0 Receive Frame Sync

SPORT0 Receive Data Primary

SPORT0 Receive Data Secondary

SPORT0 Transmit Serial Clock

SPORT0 Transmit Frame Sync

SPORT0 Transmit Data Primary

SPORT0 Transmit Data Secondary

D

C

RFS0

DR0PRI

DR0SEC

I

TSCLK0

I/O

O

D

C

TFS0

DT0PRI

DT0SEC

O

Serial Port1

RSCLK1

I/O

I

SPORT1 Receive Serial Clock

SPORT1 Receive Frame Sync

SPORT1 Receive Data Primary

SPORT1 Receive Data Secondary

SPORT1 Transmit Serial Clock

SPORT1 Transmit Frame Sync

SPORT1 Transmit Data Primary

SPORT1 Transmit Data Secondary

D

C

RFS1

DR1PRI

DR1SEC

I

TSCLK1

I/O

O

D

C

TFS1

DT1PRI

DT1SEC

O

Serial Port2

RSCLK2 / GPIOE0

RFS2 / GPIOE1

DR2PRI /GPIOE2

DR2SEC / GPIOE3

TSCLK2 / GPIOE4

TFS2 / GPIOE5

DT2PRI / GPIOE6

DT2SEC / GPIOE7

Serial Port3

RSCLK3 / GPIOE8

RFS3 / GPIOE9

DR3PRI / GPIOE10

DR3SEC / GPIOE11

TSCLK3 / GPIOE12

TFS3 / GPIOE13

DT3PRI / GPIOE14

DT3SEC / GPIOE15

I/O

SPORT2 Receive Serial Clock/GPIO_E_0

SPORT2 Receive Frame Sync/GPIO_E_1

SPORT2 Receive Data Primary/GPIO_E_2

SPORT2 Receive Data Secondary/GPIO_E_3

SPORT2 Transmit Serial Clock/GPIO_E_4

SPORT2 Transmit Frame Sync/GPIO_E_5

SPORT2 Transmit Data Primary/GPIO_E_6

SPORT2 Transmit Data Secondary/GPIO_E_7

D

C

D

C

I/O

SPORT3 Receive Serial Clock/GPIO_E_8

SPORT3 Receive Frame Sync/GPIO_E_9

SPORT3 Receive Data Primary/GPIO_E_10

SPORT3 Receive Data Secondary/GPIO_E_11

SPORT3 Transmit Serial Clock/GPIO_E_12

SPORT3 Transmit Frame Sync/GPIO_E_13

SPORT3 Transmit Data Primary/GPIO_E_14

SPORT3 Transmit Data Secondary/GPIO_E_15

D

C

D

C

Rev. PrE

|

Page 24 of 70

| May 2006

Preliminary Technical Data

ADSP-BF539/ADSP-BF539F

Table 10. Pin Descriptions (Continued)

Driver

Pin Name

SPI0 Port

Type Function

Type¹Pull-Up/Down Requirement

MOSI0

I/O

SPI0 Master Out Slave In

SPI0 Master In Slave Out

SPI0 Clock

C

C³

MISO0

SCK0

D

SPI1 Port

MOSI1 / GPIOD0

MISO1 / GPIOD1

SCK1 / GPIOD2

SPI1SS / GPIOD3

SPI1SEL / GPIOD4

SPI2 Port

I/O

SPI1 Master Out Slave In/GPIO_D_0

SPI1 Master In Slave Out/GPIO_D_1

SPI1 Clock/GPIO_D_2

C

D

C

SPI1 Slave Select Input/GPIO_D_3

SPI1 Slave Select Enable/GPIO_D_4

MOSI2 / GPIOD5

MISO2 / GPIOD6

SCK2 / GPIOD7

SPI2SS / GPIOD8

SPI2SEL / GPIOD9

UART0 Port

RX0

I/O

SPI2 Master Out Slave In/GPIO_D_5

SPI2 Master In Slave Out/GPIO_D_6

SPI2 Clock/GPIO_D_7

C

D

C

SPI2 Slave Select Input/GPIO_D_8

SPI2 Slave Select Enable/GPIO_D_9

I

UART Receive

UART Transmit

TX0

O

C

UART1 Port

RX1 / GPIOD10

TX1 / GPIOD11

UART2 Port

RX2 / GPIOD12

TX2 / GPIOD13

Real Time Clock

RTXI

I/O

UART1 Receive/GPIO_D_10

UART1 Transmit/GPIO_D_11

C

I/O

UART2 Receive/GPIO_D_12

UART2 Transmit/GPIO_D_13

C

I

RTC Crystal Input

Pull LOW when not used.

RTXO

O

RTC Crystal Output

JTAG Port

TCK

I

JTAG Clock

TDO

O

I

JTAG Serial Data Out

JTAG Serial Data In

JTAG Mode Select

JTAG Reset

C

TDI

TMS

I

TRST

I

Pull LOW when JTAG port not used.

C

EMU

O

Emulation Output

Clock

CLKIN

I

Clock/Crystal Input

Crystal Output

XTAL

O

Rev. PrE

|

Page 25 of 70

| May 2006

ADSP-BF539/ADSP-BF539F

Preliminary Technical Data

Table 10. Pin Descriptions (Continued)

Driver

Pin Name

Mode Controls

RESET

Type Function

Type¹Pull-Up/Down Requirement

I

Reset

NMI

Non-maskable Interrupt

Boot Mode Strap

Pull High When Not Used

BMODE1–0

Voltage Regulator

VROUT0

VROUT1

Supplies

O

External FET Drive 0

External FET Drive 1

Leave unconnected when not used.

VDDEXT

VDDINT

P

G

I/O Power Supply

Internal Power Supply

Real Time Clock Power Supply

MXVR Internal Power Supply

MXVR External Power Supply

MXVR Ground

VDDRTC

MPIVDD

MXEVDD

MXEGND

GND

Ground

¹Refer to Figure 38 on Page 59 to Figure 49 on Page 60.

²Open drain output. See version 2.1 of I²C specification for proper resistor value.

³Pull HIGH through a 4.7 kW resistor if booting via the SPI port.

Rev. PrE

|

Page 26 of 70

| May 2006

Preliminary Technical Data

SPECIFICATIONS

ADSP-BF539/ADSP-BF539F

Component specifications are subject to change

without notice.

RECOMMENDED OPERATING CONDITIONS

Parameter

Min

0.95

2.7

Nominal

1.2

Max

1.32

3.6

0.6

85

Unit

V

V_DDINT

V_DDEXT

V_DDRTC

V_IH

Internal Supply Voltage¹

External Supply Voltage²

3.3

V

Real Time Clock Power Supply Voltage

High Level Input Voltage³, @ V_DDEXT=maximum

High Level Input Voltage⁴, @ V_DDEXT=maximum

Low Level Input Voltage^{3, 5}, @ V_DDEXT=minimum

Automotive Ambient Operating Temperature

2.25

2.0

V

V_IHCLKIN

V_IL

2.2

V

–0.3

–40

V

T_AMBIENT

ºC

¹Parameter value applies also to MPIVDD.

²Parameter value applies also to MXEVDD.

³The 3.3 V tolerant pins are capable of accepting up to 3.6 V maximum V_IHThe following bi-directional pins are 3.3 V tolerant: DATA15–0, MISO0, MOSI0, PF15–0, PPI3–0,

MTXON, MMCLK, MBCLK, MFS, MTX, SCK1, MISO1, MOSI1, SPI1SS, SPI1SEL, SCK2, MISO2, MOSI2, SPI2SS, SPI2SEL, RX1, TX1, RX2, TX2, DT2PRI, DT2SEC,

TSCLK2, DR2PRI, DT2SEC, RSCLK2, RFS2, TFS2, DT3PRI, DT3SEC, DR3PRI, DR3SEC, RSCLK3, RFS3, TFS3, RFS0, RFS1, RSCLK0, RSCLK1, TSCLK0, TSCLK1, SCK0,

TFS0, TFS1, and TMR2–0. The following input-only pins are 3.3 V tolerant: RESET, RX0, TCK, TDI, TMS, TRST, ARDY, BMODE1–0, BR, DR0PRI, DR0SEC, DR1PRI,

DR1SEC, NMI, PPI_CLK, RTXI, and GP.

⁴Parameter value applies to the CLKIN and MXI input pins.

⁵Parameter value applies to all input and bi-directional pins.

RECOMMENDED OPERATING CONDITIONS

—APPLIES TO 5V TOLERANT PINS

Parameter¹

Min

2.0

Nominal

Max

5.5

Unit

V

2

V_IH5V

High Level Input Voltage, @ V_DDEXT=maximum

Low Level Input Voltage, @ V_DDEXT=minimum

2

V_IL5V

–0.3

0.8

V

¹Specifications subject to change without notice.

²The 5.V tolerant pins are capable of accepting up to 5.5 V maximum V_IH. The following bi-directional pins are 5 V tolerant: SCL0, SCL1, SDA0, SDA1, MRX, CANRX, CANTX.

The following input-only pins are 5 V tolerant: MRXON.

ELECTRICAL CHARACTERISTICS

Parameter¹

V_OHHigh Level Output Voltage²

V_OLLow Level Output Voltage²

Test Conditions

Min

Max

Unit

V

@ V_DDEXT=3.0V, I_OH= –0.5 mA

@ V_DDEXT=3.0V, I_OL= 2.0 mA

2.4

0.4

V

I_IH

I_IL

High Level Input Current³

Low Level Input Current⁴

@ V_DDEXT=maximum, V_IN= V_DDmaximum

@ V_DDEXT=maximum, V_IN= 0 V

@ V_DDEXT= maximum, V_IN= V_DDmaximum

@ V_DDEXT= maximum, V_IN= 0 V

f_IN= 1 MHz, T_AMBIENT= 25°C, V_IN= 2.5 V

TBD

µA

pF

I_OZHThree-State Leakage Current⁴

I_OZLThree-State Leakage Current⁵

C_IN

Input Capacitance^{5, 6}

¹Specifications subject to change without notice.

²Applies to output and bidirectional pins.

³Applies to input pins.

⁴Applies to three-statable pins.

⁵Applies to all signal pins.

⁶Guaranteed, but not tested.

Rev. PrE

|

Page 27 of 70

| May 2006

ADSP-BF539/ADSP-BF539F

Preliminary Technical Data

ABSOLUTE MAXIMUM RATINGS

Stresses greater than those listed in the table may cause perma-

nent damage to the device. These are stress ratings only.

Functional operation of the device at these or any other condi-

tions greater than those indicated in the operational sections of

this specification is not implied. Exposure to absolute maximum

rating conditions for extended periods may affect device

reliability.

PACKAGE INFORMATION

The information presented in Figure 10 and Table 12 provides

information about how to read the package brand and relate it

to specific product features. For a complete listing of product

offerings, see the Ordering Guide on Page 69.

Parameter

Rating

a

ADSP-BF539

1

Internal (Core) Supply Voltage (V_DDINT

)

2

–0.3 V to +1.4 V

–0.3 V to +3.8 V

–0.5 V to 3.6 V

–0.5 V to 5.5 V

–0.5 V to V_DDEXT+0.5 V

200 pF

tppZccc

External (I/O) Supply Voltage (V_DDEXT

Input Voltage³

Input Voltage⁴

)

vvvvvv.x n.n

yyww country_of_origin

B

Output Voltage Swing

Load Capacitance⁵

Figure 10. Product Information on Package

Junction Temperature Under Bias

Storage Temperature Range

¹Parameter value applies also to MPIVDD.

+125ºC

Table 12. Package Brand Information

–65ºC to +150ºC

Brand Key

Field Description

Automotive Grade (Optional)

Temperature Range

Package Type

²Parameter value applies also to MXEVDD and VDDRTC.

³Applies to 100% transient duty cycle. For other duty cycles see Table 11.

⁴Applies to pins designated as 5V tolerant only.

W

t

⁵ForproperSDRAMcontrolleroperation, themaximumloadcapacitanceis50pF(at3.3V)

or 30 pF (at 2.5V) for ADDR19–1, DATA15–0, ABE1–0/SDQM1–0, CLKOUT, SCKE,

SA10, SRAS, SCAS, SWE, and SMS.

pp

Z

Lead Free Option (Optional)

See Ordering Guide

Assembly Lot Code

Silicon Revision

Table 11. Maximum Duty Cycle for Input Transient Voltage¹

ccc

vvvvvv.x

n.n

V_INMin (V)

–0.50

V_INMax (V)

+3.80

Maximum Duty Cycle

100%

40%

25%

15%

10%

yyww

Date Code

–0.70

+4.00

–0.80

+4.10

–0.90

+4.20

–1.00

+4.30

¹Applies to all signal pins with the exception of CLKIN, MXI, MXO, MLF,

VROUT1–0, XTAL.

ESD SENSITIVITY

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000V readily

accumulate on the human body and test equipment and can discharge without detection. Although

the ADSP-BF539/ADSP-BF539F processor feature proprietary ESD protection circuitry, permanent

damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper

ESD precautions are recommended to avoid performance degradation or loss of functionality.

Rev. PrE

|

Page 28 of 70

| May 2006

Preliminary Technical Data

ADSP-BF539/ADSP-BF539F

TIMING SPECIFICATIONS

Table 13 describes the timing requirements for the ADSP-

BF539/ADSP-BF539F processor clocks. Take care in selecting

MSEL, SSEL, and CSEL ratios so as not to exceed the maximum

core clock, system clock and Voltage Controlled Oscillator

(VCO) operating frequencies, as described in Absolute Maxi-

mum Ratings on Page 28. Table 14 describes Phase Locked

Loop operating conditions.

Table 13. Core Clock Requirements—ADSP-BF539/ADSP-BF539F—500 MHz

Parameter

Minimum

2.00

Maximum

Unit

ns

t_CCLK

Core Cycle Period (V_DDINT=1.20 V minimum)

Core Cycle Period (V_DDINT=1.045 V minimum)

Core Cycle Period (V_DDINT=0.95 V minimum)

Core Cycle Period (V_DDINT=0.85 V minimum)

Core Cycle Period (V_DDINT=0.80 V minimum)

2.25

ns

2.50

ns

3.00

ns

4.00

ns

Table 14. Phase Locked Loop Operating Conditions

Parameter

Minimum

Maximum

Unit

f_VCO

Voltage Controlled Oscillator (VCO) Frequency

50

Max CCLK

MHz

Table 15. Maximum SCLK Conditions

Parameter¹

V_DDEXT= 3.3 V

V_DDEXT= 2.5 V

Unit

f_SCLK

CLKOUT/SCLK Frequency (V_DDINT≥ 1.14 V)

133

100

133

100

MHz

f_SCLK

CLKOUT/SCLK Frequency (V_DDINT< 1.14 V)

¹t_SCLK(= 1/f_SCLK) must be greater than or equal to t_CCLK

.

Rev. PrE

|

Page 29 of 70

| May 2006

ADSP-BF539/ADSP-BF539F

Preliminary Technical Data

Clock and Reset Timing

Table 16 and Figure 11 describe clock and reset operations. Per

Absolute Maximum Ratings on Page 28, combinations of

CLKIN and clock multipliers must not select core/peripheral

clocks in excess of 500/133 MHz.

Table 16. Clock and Reset Timing

Parameter

Minimum

Maximum

Unit

Timing Requirements

t_CKIN

CLKIN Period

CLKIN Low Pulse¹

CLKIN High Pulse¹

RESET Asserted Pulsewidth Low²

20.0

8.0

100.0

ns

t_CKINL

t_CKINH

t_WRST

8.0

11 t_CKIN

¹Applies to bypass mode and non-bypass mode.

²Applies after power-up sequence is complete. At power-up, the processor’s internal phase locked loop requires no more than 2000 CLKIN cycles, while RESET is asserted,

assuming stable power supplies and CLKIN (not including startup time of external clock oscillator).

t_CKIN

CLKIN

t_CKINL

t_CKINH

t_WRST

RESET

Figure 11. Clock and Reset Timing

Rev. PrE

|

Page 30 of 70

| May 2006

Preliminary Technical Data

ADSP-BF539/ADSP-BF539F

Asynchronous Memory Read Cycle Timing

Table 17 and Table 18 on Page 31 and Figure 12 and Figure 13

on Page 33 describe asynchronous memory read cycle opera-

tions for synchronous and for asynchronous ARDY.

Table 17. Asynchronous Memory Read Cycle Timing with Synchronous ARDY

Parameter

Min

Max

Unit

Timing Requirements

t_SDAT

t_HDAT

t_SARDY

t_HARDY

t_DO

DATA15–0 Setup Before CLKOUT

DATA15–0 Hold After CLKOUT

2.1

0.8

tbd

ns

ARDY Setup Before the Falling Edge of CLKOUT

ARDY Hold After the Falling Edge of CLKOUT

Output Delay After CLKOUT¹

6.0

t_HO

Output Hold After CLKOUT¹

0.8

¹Output pins include AMS3–0, ABE1–0, ADDR19–1, AOE, ARE.

Table 18. Asynchronous Memory Read Cycle Timing with Asynchronous ARDY

Parameter

Min

Max

Unit

Timing Requirements

t_SDAT

t_HDAT

t_DANR

t_HAA

DATA15–0 Setup Before CLKOUT

DATA15–0 Hold After CLKOUT

ARDY Negated Delay from AMSx Asserted¹

ARDY Asserted Hold After ARE Negated

Output Delay After CLKOUT²

2.1

0.8

ns

(S+RA–2)*t_SCLKns

ns

0.0

0.8

t_DO

6.0

ns

t_HO

Output Hold After CLKOUT²

¹S = number of programmed setup cycles, RA = number of programmed read access cycles.

²Output pins include AMS3–0, ABE1–0, ADDR19–1, AOE, ARE.

Rev. PrE

|

Page 31 of 70

| May 2006

ADSP-BF539/ADSP-BF539F

Preliminary Technical Data

HOLD

1 CYCLE

SETUP

2 CYCLES

PROGRAMMED READ ACCESS

4 CYCLES

ACCESS EXTENDED

3 CYCLES

CLKOUT

t_DO

t_HO

AMSx

ABE1–0

BE, ADDRESS

ADDR19–1

AOE

t_DO

t_HO

ARE

t_HARDY

t_SARDY

t_HARDY

ARDY

t_SARDY

t_SDAT

t_HDAT

DATA15–0

READ

Figure 12. Asynchronous Memory Read Cycle Timing with Synchronous ARDY

Rev. PrE

|

Page 32 of 70

| May 2006

Preliminary Technical Data

ADSP-BF539/ADSP-BF539F

HOLD

1 CYCLE

SETUP

2 CYCLES

PROGRAMMED READ ACCESS

4 CYCLES

ACCESS EXTENDED

CLKOUT

t_DO

t_HO

AMSx

ABE1–0

BE, ADDRESS

ADDR19–1

AOE

ARE

t_DO

t_HO

t_HAA

t_DANR

ARDY

t_SDAT

t_HDAT

DATA15–0

READ

Figure 13. Asynchronous Memory Read Cycle Timing with Asynchronous ARDY

Rev. PrE

|

Page 33 of 70

| May 2006

ADSP-BF539/ADSP-BF539F

Preliminary Technical Data

Asynchronous Memory Write Cycle Timing

Table 19 and Table 20 on Page 34 and Figure 14 and Figure 15

on Page 35 describe asynchronous memory write cycle opera-

tions for synchronous and for asynchronous ARDY.

Table 19. Asynchronous Memory Write Cycle Timing with Synchronous ARDY

Parameter

Min

Max

Unit

Timing Requirements

t_SARDY

t_HARDY

Switching Characteristics

ARDY Setup Before the Falling Edge of CLKOUT

tbd

ns

ARDY Hold After the Falling Edge of CLKOUT

t_DDAT

t_ENDAT

t_DO

DATA15–0 Disable After CLKOUT

6.0

ns

DATA15–0 Enable After CLKOUT

Output Delay After CLKOUT¹

Output Hold After CLKOUT¹

1.0

0.8

t_HO

¹Output pins include AMS3–0, ABE1–0, ADDR19–1, DATA15–0, AOE, AWE.

Table 20. Asynchronous Memory Write Cycle Timing with Asynchronous ARDY

Parameter

Min

Max

Unit

Timing Requirements

t_DANR

t_HAA

Switching Characteristics

ARDY Negated Delay from AMSx Asserted¹

ARDY Asserted Hold After ARE Negated

(S+WA–2)*t_SCLKns

ns

0.0

t_DDAT

t_ENDAT

t_DO

DATA15–0 Disable After CLKOUT

6.0

ns

DATA15–0 Enable After CLKOUT

Output Delay After CLKOUT²

Output Hold After CLKOUT²

1.0

0.8

t_HO

¹S = number of programmed setup cycles, WA = number of programmed write access cycles.

²Output pins include AMS3–0, ABE1–0, ADDR19–1, DATA15–0, AOE, AWE.

Rev. PrE

|

Page 34 of 70

| May 2006

Preliminary Technical Data

ADSP-BF539/ADSP-BF539F

ACCESS

EXTENDED

1 CYCLE

SETUP

2 CYCLES

HOLD

1 CYCLE

PROGRAMMED WRITE

ACCESS 2 CYCLES

CLKOUT

AMSx

t_DO

t_HO

ABE1–0

BE, ADDRESS

ADDR19–1

t_DO

t_HO

AWE

t_SARDY

ARDY

t_SARDY

t_HARDY

t_DDAT

t_ENDAT

DATA15–0

WRITE DATA

Figure 14. Asynchronous Memory Write Cycle Timing with Synchronous ARDY

ACCESS

EXTENDED

SETUP

2 CYCLES

HOLD

1 CYCLE

PROGRAMMED WRITE

ACCESS 2 CYCLES

CLKOUT

AMSx

t_DO

t_HO

ABE1–0

BE, ADDRESS

ADDR19–1

t_DO

t_HO

AWE

t_DANW

t_HAA

ARDY

t_ENDAT

DATA15–0

WRITE DATA

Figure 15. Asynchronous Memory Write Cycle Timing with Asynchronous ARDY

Rev. PrE

|

Page 35 of 70

| May 2006

ADSP-BF539/ADSP-BF539F

Preliminary Technical Data

SDRAM Interface Timing

Table 21. SDRAM Interface Timing

Parameter

Minimum

Maximum

Unit

Timing Requirements

t_SSDAT

t_HSDAT

DATA Setup Before CLKOUT

DATA Hold After CLKOUT

2.1

0.8

ns

Switching Characteristics

t_SCLK

CLKOUT Period

7.5

2.5

ns

t_SCLKH

t_SCLKL

t_DCAD

t_HCAD

t_DSDAT

t_ENSDAT

CLKOUT Width High

CLKOUT Width Low

Command, ADDR, Data Delay After CLKOUT¹

Command, ADDR, Data Hold After CLKOUT¹

Data Disable After CLKOUT

Data Enable After CLKOUT

6.0

0.8

1.0

¹Command pins include: SRAS, SCAS, SWE, SDQM, SMS, SA10, SCKE.

t_SCLK

t_SCLKH

CLKOUT

t_SSDAT

t_SCLKL

t_HSDAT

DATA (IN)

t_DCAD

t_DSDAT

t_ENSDAT

t_HCAD

DATA(OUT)

t_DCAD

CMND ADDR

(OUT)

t_HCAD

NOTE: COMMAND = SRAS, SCAS, SWE, SDQM, SMS, SA10, SCKE.

Figure 16. SDRAM Interface Timing

Rev. PrE

|

Page 36 of 70

| May 2006

Preliminary Technical Data

ADSP-BF539/ADSP-BF539F

External Port Bus Request and Grant Cycle Timing

Table 22 and Table 23 on Page 37 and Figure 17 and Figure 18

on Page 39 describe external port bus request and grant cycle

operations for synchronous and for asynchronous BR.

Table 22. External Port Bus Request and Grant Cycle Timing with Synchronous BR

Parameter

Min

Max

Unit

Timing Requirements

t_BS

BR Setup to Falling Edge of CLKOUT

tbd

ns

t_BH

Falling Edge of CLKOUT to BR Deasserted Hold Time

Switching Characteristics

t_SD

CLKOUT Low to xMS, Address, and RD/WR disable

4.5

3.6

ns

t_SE

CLKOUT Low to xMS, Address, and RD/WR enable

CLKOUT High to BG High Setup

t_DBG

t_EBG

t_DBH

t_EBH

CLKOUT High to BG Deasserted Hold Time

CLKOUT High to BGH High Setup

CLKOUT High to BGH Deasserted Hold Time

Table 23. External Port Bus Request and Grant Cycle Timing with Asynchronous BR

Parameter

Min

Max

Unit

Timing Requirements

t_WBR

BR Pulsewidth

2 x t_SCLK

ns

Switching Characteristics

t_SD

CLKOUT Low to xMS, Address, and RD/WR disable

4.5

3.6

ns

t_SE

CLKOUT Low to xMS, Address, and RD/WR enable

CLKOUT High to BG High Setup

t_DBG

t_EBG

t_DBH

t_EBH

CLKOUT High to BG Deasserted Hold Time

CLKOUT High to BGH High Setup

CLKOUT High to BGH Deasserted Hold Time

Rev. PrE

|

Page 37 of 70

| May 2006

ADSP-BF539/ADSP-BF539F

Preliminary Technical Data

CLKOUT

t_BH

t_BS

BR

t_SD

t_SE

AMSx

t_SD

t_SE

ADDR19-1

ABE1-0

t_SD

t_SE

AWE

ARE

t_DBG

t_EBG

BG

t_DBH

t_EBH

BGH

Figure 17. External Port Bus Request and Grant Cycle Timing with Synchronous BR

Rev. PrE

|

Page 38 of 70

| May 2006

Preliminary Technical Data

ADSP-BF539/ADSP-BF539F

CLKOUT

t_WBR

BR

t_SD

t_SE

AMSx

t_SD

t_SE

ADDR19-1

ABE1-0

t_SD

t_SE

AWE

ARE

t_DBG

t_EBG

BG

t_DBH

t_EBH

BGH

Figure 18. External Port Bus Request and Grant Cycle Timing with Asynchronous BR

Rev. PrE

|

Page 39 of 70

| May 2006

ADSP-BF539/ADSP-BF539F

Preliminary Technical Data

Parallel Peripheral Interface Timing

Table 24 and Figure 19, Figure 20, Figure 21, and Figure 22

describe Parallel Peripheral Interface operations.

Table 24. Parallel Peripheral Interface Timing

Parameter

Min

Max

Unit

Timing Requirements

t_PCLKW

t_PCLK

PPI_CLK Width

PPI_CLK Period¹

6.0

15.0

3.0

2.0

4.0

ns

t_SFSPE

t_HFSPE

t_SDRPE

t_HDRPE

External Frame Sync Setup Before PPI_CLK

External Frame Sync Hold After PPI_CLK

Receive Data Setup Before PPI_CLK

Receive Data Hold After PPI_CLK

Switching Characteristics — GP Output and Frame Capture Modes

t_DFSPE

t_HOFSPE

t_DDTPE

t_HDTPE

Internal Frame Sync Delay After PPI_CLK

Internal Frame Sync Hold After PPI_CLK

Transmit Data Delay After PPI_CLK

Transmit Data Hold After PPI_CLK

10.0

ns

0.0

¹PPI_CLK frequency cannot exceed f_SCLK/2

FRAME

SYNC IS

DRIVEN

OUT

DATA0

IS

SAMPLED

POLC = 0

PPI_CLK

POLC = 1

t

DFSPE

t

HOFSPE

POLS = 1

PPI_FS1

POLS = 0

POLS = 1

PPI_FS2

POLS = 0

t

SDRPE

HDRPE

PPI_DATA

Figure 19. PPI GP Rx Mode with Internal Frame Sync Timing

Rev. PrE

|

Page 40 of 70

| May 2006

Preliminary Technical Data

ADSP-BF539/ADSP-BF539F

FRAME

SYNC IS

SAMPLED

FOR

DATA0 IS

DATA1 IS

SAMPLED

DATA0

SAMPLED

PPI_CLK

POLC = 0

PPI_CLK

POLC = 1

t

HFSPE

t

SFSPE

POLS = 1

POLS = 0

PPI_FS1

POLS = 1

POLS = 0

PPI_FS2

t

SDRPE

HDRPE

PPI_DATA

Figure 20. PPI GP Rx Mode with External Frame Sync Timing

FRAME

SYNC IS

SAMPLED

DATA0 IS

DRIVEN

OUT

PPI_CLK

POLC = 0

PPI_CLK

POLC = 1

t

HFSPE

t

SFSPE

POLS = 1

POLS = 0

PPI_FS1

POLS = 1

POLS = 0

PPI_FS2

t

HDTPE

PPI_DATA

DATA0

Figure 21. PPI GP Tx Mode with External Frame Sync Timing

Rev. PrE

|

Page 41 of 70

| May 2006

ADSP-BF539/ADSP-BF539F

Preliminary Technical Data

FRAME

SYNC IS

DRIVEN

OUT

DATA0 IS

DRIVEN

OUT

PPI_CLK

POLC = 0

PPI_CLK

POLC = 1

t

DFSPE

t

HOFSPE

POLS = 1

PPI_FS1

POLS = 0

POLS = 1

PPI_FS2

POLS = 0

t

DDTPE

t

HDTPE

PPI_DATA

DATA0

Figure 22. PPI GP Tx Mode with Internal Frame Sync Timing

Rev. PrE

|

Page 42 of 70

| May 2006

Preliminary Technical Data

ADSP-BF539/ADSP-BF539F

Serial Ports Timing

Table 25 through Table 28 on Page 44 and Figure 23 on Page 44

through Figure 25 on Page 46 describe Serial Port operations.

Table 25. Serial Ports—External Clock

Parameter

Min

Max

Unit

Timing Requirements

t_SFSE

TFS/RFS Setup Before TSCLK/RSCLK (externally generated TFS/RFS)¹

3.0

4.5

15.0

ns

t_HFSE

TFS/RFS Hold After TSCLK/RSCLK (externally generated TFS/RFS)¹

Receive Data Setup Before RSCLK¹

Receive Data Hold After RSCLK¹

TSCLK/RSCLK Width

t_SDRE

t_HDRE

t_SCLKEW

t_SCLKE

TSCLK/RSCLK Period

Switching Characteristics

t_DFSE

t_HOFSE

t_DDTE

t_HDTE

TFS/RFS Delay After TSCLK/RSCLK (Internally Generated TFS/RFS)²

TFS/RFS Hold After TSCLK/RSCLK (Internally Generated TFS/RFS)²

Transmit Data Delay After TSCLK²

10.0

ns

0.0

Transmit Data Hold After TSCLK²

¹Referenced to sample edge.

²Referenced to drive edge.

Table 26. Serial Ports—Internal Clock

Parameter

Min

Max

Unit

Timing Requirements

t_SFSI

TFS/RFS Setup Before TSCLK/RSCLK (externally generated TFS/RFS)¹

8.0

ns

t_HFSI

TFS/RFS Hold After TSCLK/RSCLK (externally generated TFS/RFS)¹

Receive Data Setup Before RSCLK¹

Receive Data Hold After RSCLK¹

TSCLK/RSCLK Width

–2.0

6.0

t_SDRI

t_HDRI

t_SCLKEW

t_SCLKE

0.0

4.5

TSCLK/RSCLK Period

15.0

Switching Characteristics

t_DFS

TFS/RFS Delay After TSCLK/RSCLK (Internally Generated TFS/RFS)²

3.0

ns

I

t_HOFS

TFS/RFS Hold After TSCLK/RSCLK (Internally Generated TFS/RFS)²

Transmit Data Delay After TSCLK²

–1.0

I

t_DDT

I

t_HDT

Transmit Data Hold After TSCLK²

–2.0

4.5

I

t_SCLKIW

TSCLK/RSCLK Width

¹Referenced to sample edge.

²Referenced to drive edge.

Table 27. Serial Ports—Enable and Three-State

Parameter

Min

0

Max

Unit

Switching Characteristics

t_DTENE

t_DDTTE

t_DTENI

t_DDTTI

Data Enable Delay from External TSCLK¹

Data Disable Delay from External TSCLK¹

Data Enable Delay from Internal TSCLK¹

Data Disable Delay from Internal TSCLK¹

ns

10.0

3.0

–2.0

¹Referenced to drive edge.

Rev. PrE

|

Page 43 of 70

| May 2006

ADSP-BF539/ADSP-BF539F

Preliminary Technical Data

Table 28. External Late Frame Sync

Parameter

Min

Max

Unit

Switching Characteristics

t_DDTLFSE

t_DTENLFS

Data Delay from Late External TFS or External RFS with MCE = 1, MFD = 0^{1, 2}

Data Enable from late FS or MCE = 1, MFD = 0^{1, 2}

10.0

ns

0

¹MCE = 1, TFS enable and TFS valid follow t_DTENLFSand t_DDTLFSE

²If external RFS/TFS setup to RSCLK/TSCLK > t_SCLKE/2, then t_DDTE/Iand t_DTENE/Iapply; otherwise t_DDTLFSEand t_DTENLFSapply.

.

DATA RECEIVE- INTERNAL CLOCK

DATA RECEIVE- EXTERNAL CLOCK

DRIVE

EDGE

SAMPLE

EDGE

DRIVE

EDGE

SAMPLE

EDGE

t_SCLKIW

t_SCLKEW

RSCLK

t_DFSE

t_HOFSE

RFS

t_SFSI

t_HFSI

t_HOFSE

t_SFSE

t_HFSE

RFS

t_SDRI

t_HDRI

t_SDRE

t_HDRE

DR

NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK OR TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE.

DATA TRANSMIT- INTERNAL CLOCK

DATA TRANSMIT- EXTERNAL CLOCK

DRIVE

EDGE

SAMPLE

EDGE

DRIVE

EDGE

SAMPLE

EDGE

t_SCLKIW

t_SCLKEW

TSCLK

t_DFSI

t_DFSE

t_HOFSI

t_SFSI

t_HFSI

t_HOFSE

t_SFSE

t_HFSE

TFS

DT

TFS

t_DDTI

t_DDTE

t_HDTI

t_HDTE

DT

NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK OR TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE.

DRIVE

EDGE

DRIVE

EDGE

TSCLK (EXT)

TFS ("LATE", EXT.)

TSCLK / RSCLK

t_DDTTE

t_DTENE

DT

DRIVE

EDGE

DRIVE

EDGE

TSCLK (INT)

TFS ("LATE", INT.)

TSCLK / RSCLK

t_DTENI

t_DDTTI

DT

Figure 23. Serial Ports

Rev. PrE

|

Page 44 of 70

| May 2006

Preliminary Technical Data

ADSP-BF539/ADSP-BF539F

EXTERNAL RFS WITH MCE = 1, MFD = 0 (INTERNAL OR EXTERNAL CLOCK)

DRIVE SAMPLE DRIVE

RSCLK

RFS

t_HOFSE/I

t_SFSE/I

t_DDTE/I

t_DTENLFS

t_HDTE/I

1ST BIT

2ND BIT

DT

t_DDTLFSE

LATE EXTERNAL TFS (INTERNAL OR EXTERNAL CLOCK)

DRIVE SAMPLE

DRIVE

TSCLK

t_SFSE/I

t_HOFSE/I

TFS

t_DDTE/I

T_DTENLFS

t_HDTE/I

DT

1ST BIT

2ND BIT

t_DDTLFSE

Figure 24. External Late Frame Sync (Frame Sync Setup < t_SCLKE/2)

Rev. PrE

|

Page 45 of 70

| May 2006

ADSP-BF539/ADSP-BF539F

Preliminary Technical Data

EXTERNAL RFS WITH MCE = 1, MFD = 0

DRIVE

SAMPLE

DRIVE

RSCLK

RFS

t_SFSE/I

t_HOFSE/I

t_DDTE/I

t_HDTE/I

t_DTENLSCK

1ST BIT

DT

2ND BIT

t_DDTLSCK

LATE EXTERNAL TFS

DRIVE

SAMPLE

DRIVE

TSCLK

TFS

t_SFSE/I

t_HOFSE/I

t_DDTE/I

t_HDTE/I

t_DTENLSCK

DT

1ST BIT

2ND BIT

t_DDTLSCK

Figure 25. External Late Frame Sync (Frame Sync Setup > t_SCLKE/2)

Rev. PrE

|

Page 46 of 70

| May 2006

Preliminary Technical Data

ADSP-BF539/ADSP-BF539F

Serial Peripheral Interface (SPI) Port

—Master Timing

Table 29 and Figure 26 describe SPI port master operations.

Table 29. Serial Peripheral Interface (SPI) Port—Master Timing

Parameter

Min

Max

Unit

Timing Requirements

t_SSPIDM

t_HSPIDM

Switching Characteristics

Data Input Valid to SCK Edge (Data Input Setup)

7.5

ns

SCK Sampling Edge to Data Input Invalid

–1.5

t_SDSCIM

t_SPICHM

t_SPICLM

t_SPICLK

SPI0SELx Low to First SCK edge (x=0 or 1)

2t_SCLK–1.5

4t_SCLK–1.5

2t_SCLK–1.5

0

ns

Serial Clock High period

Serial Clock Low period

Serial Clock Period

t_HDSM

Last SCK Edge to SPI0SELx High (x=0 or 1)

Sequential Transfer Delay

t_SPITDM

t_DDSPIDM

t_HDSPIDM

SCK Edge to Data Out Valid (Data Out Delay)

SCK Edge to Data Out Invalid (Data Out Hold)

6

–1.0

4.0

SPISELx

(OUTPUT)

t_SPICLK

t_HDSM

t_SPITDM

t_SDSCIM

t_SPICHM

t_SPICLM

SCK

(CPOL = 0)

(OUTPUT)

t_SPICLM

t_SPICHM

SCK

(CPOL = 1)

(OUTPUT)

t_DDSPIDM

t_HDSPIDM

MOSI

(OUTPUT)

MSB

LSB

CPHA=1

t_SSPIDM

t_HSPIDM

t_SSPIDM

t_HSPIDM

MISO

(INPUT)

MSB VALID

LSB VALID

t_DDSPIDM

t_HDSPIDM

MOSI

(OUTPUT)

MSB

LSB

CPHA=0

t_SSPIDM

t_HSPIDM

MISO

(INPUT)

MSB VALID

LSB VALID

Figure 26. Serial Peripheral Interface (SPI) Port—Master Timing

Rev. PrE

|

Page 47 of 70

| May 2006

ADSP-BF539/ADSP-BF539F

Preliminary Technical Data

Serial Peripheral Interface (SPI) Port

—Slave Timing

Table 30 and Figure 27 describe SPI port slave operations.

Table 30. Serial Peripheral Interface (SPI) Port—Slave Timing

Parameter

Min

Max

Unit

Timing Requirements

t_SPICHS

t_SPICLS

t_SPICLK

t_HDS

Serial Clock High Period

2t_SCLK–1.5

4t_SCLK–1.5

2t_SCLK–1.5

1.6

ns

Serial Clock low Period

Serial Clock Period

Last SCK Edge to SPI0SS Not Asserted

Sequential Transfer Delay

t_SPITDS

t_SDSCI

t_SSPID

t_HSPID

SPI0SS Assertion to First SCK Edge

Data Input Valid to SCK Edge (Data Input Setup)

SCK Sampling Edge to Data Input Invalid

1.6

Switching Characteristics

t_DSOE

SPI0SS Assertion to Data Out Active

0

8

ns

t_DSDHI

t_DDSPID

t_HDSPID

SPI0SS Deassertion to Data High impedance

SCK Edge to Data Out Valid (Data Out Delay)

SCK Edge to Data Out Invalid (Data Out Hold)

8

10

SPISS

(INPUT)

t_SPICHS

t_SPICLS

t_SPICLK

t_HDS

t_SPITDS

SCK

(CPOL = 0)

(INPUT)

t_SDSCI

t_SPICLS

t_SPICHS

SCK

(CPOL = 1)

(INPUT)

t_DSOE

t_DDSPID

t_HDSPID

MSB

t_DDSPID

t_DSDHI

LSB

MISO

(OUTPUT)

t_HSPID

t_SSPID

CPHA=1

t_SSPID

t_HSPID

MOSI

(INPUT)

MSB VALID

LSB VALID

t_DSOE

t_DDSPID

t_DSDHI

MISO

(OUTPUT)

MSB

LSB

t_HSPID

CPHA=0

t_SSPID

MOSI

(INPUT)

MSB VALID

LSB VALID

Figure 27. Serial Peripheral Interface (SPI) Port—Slave Timing

Rev. PrE

|

Page 48 of 70

| May 2006

Preliminary Technical Data

ADSP-BF539/ADSP-BF539F

Universal Asynchronous Receiver-Transmitter

(UART) Port Timing

Figure 28 describes UART port receive and transmit operations.

The maximum baud rate is SCLK/16. As shown in Figure 28

there is some latency between the generation internal UART

interrupts and the external data operations. These latencies are

negligible at the data transmission rates for the UART.

CLKOUT

(SAMPLE CLOCK)

RXD

DATA(5–8)

STOP

RECEIVE

INTERNAL

UART RECEIVE

INTERRUPT

UART RECEIVE BIT SET BY DATA STOP;

CLEARED BY FIFO READ

START

TXD

DATA(5–8)

STOP (1–2)

TRANSMIT

INTERNAL

UART TRANSMIT

INTERRUPT

UART TRANSMIT BIT SET BY PROGRAM;

CLEARED BY WRITE TO TRANSMIT

Figure 28. UART Port—Receive and Transmit Timing

Rev. PrE

|

Page 49 of 70

| May 2006

ADSP-BF539/ADSP-BF539F

Preliminary Technical Data

Programmable Flags Cycle Timing

Table 31 and Figure 29 describe programmable flag operations.

Table 31. Programmable Flags Cycle Timing

Parameter

Minimum

Maximum

Unit

ns

Timing Requirement

t_WFI

Switching Characteristic

t_DFOFlag output delay from CLKOUT low

Flag input pulsewidth

t_SCLK+ 1

6

ns

CLKOUT

t_DFO

PF (OUTPUT)

FLAG OUTPUT

FLAG INPUT

t_WFI

PF (INPUT)

Figure 29. Programmable Flags Cycle Timing

Rev. PrE

|

Page 50 of 70

| May 2006

Preliminary Technical Data

ADSP-BF539/ADSP-BF539F

Timer Cycle Timing

Table 32 and Figure 30 describe timer expired operations. The

input signal is asynchronous in “width capture mode” and

“external clock mode” and has an absolute maximum input fre-

quency of f_SCLK/2 MHz.

Table 32. Timer Cycle Timing

Parameter

Minimum

Maximum

Unit

Timing Characteristics

t_WL

t_WH

Timer Pulsewidth Input Low¹(measured in SCLK cycles)

Timer Pulsewidth Input High¹(measured in SCLK cycles)

1

SCLK

Switching Characteristic

t_HTO

Timer Pulsewidth Output²(measured in SCLK cycles)

1

(2³²–1)

SCLK

¹The minimum pulsewidths apply for TMRx input pins in width capture and external clock modes. They also apply to the PF1 or PPI_CLK input pins in PWM output mode.

²The minimum time for t_HTOis one cycle, and the maximum time for t_HTOequals (2³²–1) cycles.

CLKOUT

t_HTO

TMRx

(PWM OUTPUT MODE)

TMRx

t_WL

t_WH

(WIDTH CAPTURE AND

EXTERNAL CLOCK MODES)

Figure 30. Timer PWM_OUT Cycle Timing

Rev. PrE

|

Page 51 of 70

| May 2006

ADSP-BF539/ADSP-BF539F

Preliminary Technical Data

JTAG Test And Emulation Port Timing

Table 33 and Figure 31 describe JTAG port operations.

Table 33. JTAG Port Timing

Parameter

Minimum

Maximum

Unit

Timing Requirements

t_TCK

TCK Period

20

4

ns

t_STAP

t_HTAP

t_SSYS

t_HSYS

t_TRSTW

TDI, TMS Setup Before TCK High

TDI, TMS Hold After TCK High

System Inputs Setup Before TCK High¹

System Inputs Hold After TCK High¹

TRST Pulsewidth²(measured in TCK cycles)

ns

4

ns

4

ns

5

ns

4

TCK

Switching Characteristics

t_DTDOTDO Delay from TCK Low

t_DSYS

System Outputs Delay After TCK Low³

10

12

ns

0

¹System Inputs=ARDY, BMODE1–0, BR, DATA15–0.DR0PRI, DR0SEC, DR1PRI, DR1SEC, MISO0, MOSI0, NMI, PF15–0, PPI_CLK, PPI3–0.SCL0, SCL1, SDA0, SDA1,

SCK, MTXON, MRXON, MMCLK, MBCLK, MFS, MTX, MRX, SCK1, MISO1, MOSI1, SPI1SS, SPI1SEL, SCK2, MISO2, MOSI2, SPI2SS, SPI2SEL, RX1, TX1, RX2, TX2,

DT2PRI, DT2SEC, TSCLK2, DR2PRI, DT2SEC, RSCLK2, RFS2, TFS2, DT3PRI, DT3SEC, DR3PRI, DR3SEC, RSCLK3, RFS3, TFS3, CANTX, CANRX, RESET, RFS0, RFS1,

RSCLK0, RSCLK1, TSCLK0, TSCLK1, RX0,.SCK0, TFS0, TFS1, and TMR2–0,

²50 MHz Maximum

³System Outputs = AMS, AOE, ARE, AWE, ABE, BG, DATA15–0, DT0PRI, DT0SEC, DT1PRI, DT1SEC, MISO0, MOSI0, PF15–0, PPI3–0, MTXON, MRXON, MMCLK,

MBCLK, MFS, MTX, MRX, SCK1, MISO1, MOSI1, SPI1SS, SPI1SEL, SCK2, MISO2, MOSI2, SPI2SS, SPI2SEL, RX1, TX1, RX2, TX2, DT2PRI, DT2SEC, TSCLK2, DR2PRI,

DR2SEC, RSCLK2, RFS2, TFS2, DT3PRI, DT3SEC, TSCLK3, DR3PRI, DR3SEC, RSCLK3, RFS3, TFS3, CANTX, CANRX, RFS0, RFS1, RSCLK0, RSCLK1, TSCLK0, TSCLK1,

CLKOUT, TX0, SA10, SCAS, SCK0, SCKE, SMS, SRAS, SWE, and TMR2–0.

t_TCK

TCK

t_STAP

t_HTAP

TMS

TDI

t_DTDO

TDO

t_SSYS

t_HSYS

SYSTEM

INPUTS

t_DSYS

SYSTEM

OUTPUTS

Figure 31. JTAG Port Timing

Rev. PrE

|

Page 52 of 70

| May 2006

Preliminary Technical Data

ADSP-BF539/ADSP-BF539F

TWI Controller Timing

Table 34 through Table 41 and Figure 32 through Figure 35

describe the TWI Controller operations.

Table 34. TWI Controller Timing: Bus Start/Stop Bits, Slave Mode, 100 kHz

Parameter

Min

4.7

4.0

4.7

Max

Unit

µs

t_SU:STA

t_HD:STA

t_SU:STO

t_BUF

Start condition setup time

Start condition hold time

µs

Stop condition setup time

µs

Bus free time between STOP and START condition

µs

Table 35. TWI Controller Timing: Bus Data Requirements, Slave Mode, 100 kHz

Parameter

Min

4.0

Max

Unit

µs

t_HIGH

t_LOW

t_R

Clock high time

Clock low time

4.7

µs

SDA and SCL rise time

SDA and SCL fall time

Data input hold time

Data input setup time¹

Bus capacitive loading

1000

300

ns

t_F

ns

t_HD:DAT

t_SU:DAT

C_B

0

ns

250

ns

400

pF

¹As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. TBD ns) of the falling edge of SCL to avoid unintended

generation of START or STOP conditions.

Table 36. TWI Controller Timing: Bus Start/Stop Bits, Slave Mode, 400 kHz

Parameter

t_SU:STA

Min

0.6

1.3

Max

Unit

µs

Start condition setup time

t_HD:STA

Start condition hold time

µs

t_SU:STO

Stop condition setup time

µs

t_BUF

Bus free time between STOP and START condition

µs

Table 37. TWI Controller Timing: Bus Data Requirements, Slave Mode, 400 kHz

Parameter

Min

0.6

Max

Unit

µs

t_HIGH

t_LOW

t_R

Clock high time

Clock low time

1.3

µs

SDA and SCL rise time

SDA and SCL fall time

Data input hold time

Data input setup time¹

Bus capacitive loading

TBD

0

300

0.9

ns

t_F

ns

t_HD:DAT

t_SU:DAT

C_B

µs

100

ns

400

pF

¹As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. TBD ns) of the falling edge of SCL to avoid unintended

generation of START or STOP conditions.

Rev. PrE

|

Page 53 of 70

| May 2006

ADSP-BF539/ADSP-BF539F

Preliminary Technical Data

Table 38. TWI Controller Timing: Bus Start/Stop Bits, Master Mode, 100 kHz

Parameter

Min

4.7

4.0

4.7

Max

Unit

µs

t_SU:STA

t_HD:STA

t_SU:STO

t_BUF

Start condition setup time

Start condition hold time

µs

Stop condition setup time

µs

Bus free time between STOP and START condition

µs

Table 39. TWI Controller Timing: Bus Data Requirements, Master Mode, 100 kHz

Parameter

Min

4.0

Max

Unit

µs

t_HIGH

t_LOW

t_R

Clock high time

Clock low time

4.7

µs

SDA and SCL rise time

SDA and SCL fall time

Data input hold time

Data input setup time¹

Bus capacitive loading

1000

300

ns

t_F

ns

t_HD:DAT

t_SU:DAT

C_B

0

ns

250

ns

400

pF

¹A Fast mode I²C bus device can be used in a Standard mode I²C bus system, but the requirement T_SU:DAT>= 250 ns must then be met. This will automatically be the case if the

device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line.

Before the SCL line is released, T_Rmax. + T_SU:DAT= 1000 + 250 = 1250 ns (according to the Standard mode I²C bus specification).

Table 40. TWI Controller Timing: Bus Start/Stop Bits, Master Mode, 400 kHz

Parameter

t_SU:STA

Min

0.6

1.3

Max

Unit

µs

Start condition setup time

t_HD:STA

Start condition hold time

µs

t_SU:STO

Stop condition setup time

µs

t_BUF

Bus free time between STOP and START condition

µs

Table 41. TWI Controller Timing: Bus Data Requirements, Master Mode, 400 kHz

Parameter

Min

0.6

Max

Unit

µs

t_HIGH

t_LOW

t_R

Clock high time

Clock low time

1.3

µs

SDA and SCL rise time

SDA and SCL fall time

Data input hold time

Data input setup time¹

Bus capacitive loading

TBD

0

300

0.9

ns

t_F

ns

t_HD:DAT

t_SU:DAT

C_B

µs

100

ns

400

pF

¹A Fast mode I²C bus device can be used in a Standard mode I²C bus system, but the requirement T_SU:DAT>= 250 ns must then be met. This will automatically be the case if the

device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line.

Before the SCL line is released, T_Rmax. + T_SU:DAT= 1000 + 250 = 1250 ns (according to the Standard mode I²C bus specification).

Rev. PrE

|

Page 54 of 70

| May 2006

Preliminary Technical Data

ADSP-BF539/ADSP-BF539F

SCL

t_HD:STA

t_HD:STO

t_SU:STA

t_SU:STO

SDA

STOP

START

Figure 32. TWI Controller Timing: Bus Start/Stop Bits, Slave Mode

t_F

t_R

t_HIGH

t_{LO W}

SCL

t_{SU:S TA}

t_HD:STA

t_HD:DAT

t_SU:DAT

t_{S U:STO}

SDA

(I N)

t_AA

t_BUF

t_AA

SDA

(OUT)

Figure 33. TWI Controller Timing: Bus Data, Slave Mode

SCL

t_HD:STA

t_HD:STO

t_SU:STO

t_SU:STA

SDA

STOP

START

Figure 34. TWI Controller Timing: Bus Start/Stop Bits, Master Mode

Rev. PrE

|

Page 55 of 70

| May 2006

ADSP-BF539/ADSP-BF539F

Preliminary Technical Data

t_F

t_R

t_HIGH

t_{LO W}

SCL

t_SU:STA

t_HD:STA

t_HD:DAT

t_{S U:DAT}

t_SU:STO

SDA

(I N)

t_AA

t_BUF

t_AA

SDA

(OUT)

Figure 35. TWI Controller Timing: Bus Data, Master Mode

Rev. PrE

|

Page 56 of 70

| May 2006

Preliminary Technical Data

ADSP-BF539/ADSP-BF539F

MXVR Timing

Table 42 through Table 43 and Figure 36 describe the MXVR

operations.

Table 42. MXVR Timing—Input Clock Requirements

Parameter

Min

Max

Unit

Timing Requirements

t_CKIN

MXI Period¹

20

8

ns

t_CKINL

t_CKINH

MXI Low Pulse

MXI High Pulse

8

¹For F_S=48 KHz, f_MXIshould be 49.152 MHz. For Fs=44.1 KHz, f_MXIshould be 45.1584 MHz. For F_S=38 KHz, f_MXIshould be 38.912 MHz.

Table 43. MXVR Timing—Rise and Fall Time

Parameter

Min

Max

TBD

Unit

ns

t_R

t_F

MTX/MMCLK/MBCLK/MFS/MTXON Rise Time

MTX/MMCLK/MBCLK/MFS/MTXON Fall Time

-

ns

TBD

Figure 36. MXVR Timing

Rev. PrE

|

Page 57 of 70

| May 2006

ADSP-BF539/ADSP-BF539F

Preliminary Technical Data

CAN Timing

Table 44 and Figure 37 describe the CAN operations.

Table 44. CAN Timing—Rise and Fall Time

Parameter

Minimum

Maximum

TBD

Unit

ns

t_R

t_F

CANTX rise time

CANTX fall time

-

TBD

ns

TBD

Figure 37. CAN Timing

Rev. PrE

|

Page 58 of 70

| May 2006

Preliminary Technical Data

ADSP-BF539/ADSP-BF539F

OUTPUT DRIVE CURRENTS

200

150

V_{DD E XT}= 3.0V @ 95°C

V_{DD E XT}= 3.3V @ 25°C

Figure 38 shows typical current-voltage characteristics for the

output drivers of the ADSP-BF539/ADSP-BF539F processor.

The curves represent the current drive capability of the output

drivers as a function of output voltage.

V_DDEXT= 3.6V @

-40°C

100

50

0

V_{O H}

120

V_DDEXT= 2.25V @ 95°C

V_DDEXT= 2.50V @ 25°C

V_DDEXT= 2.75V @ 40°C

100

80

-50

-

100

150

200

60

40

20

V_OL

V_OH

0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

0

SOURCE VOLTAGE (V)

-

20

40

Figure 41. Drive Current B (High V_DDEXT

)

-

V_OL

-

60

80

60

-

V_DDEXT= 2.25V @ 95°C

V_DDEXT= 2.50V @ 25°C

-100

3.0

0

0.5

1.0

1.5

2.0

2.5

V_{DDEX T}= 2.75V @ -40°C

SOURCE VOLTAGE (V)

40

20

0

V_OH

Figure 38. Drive Current A (Low V_DDEXT

)

150

100

50

V_DDEXT= 3.0V @ 95°C

V_DDEXT= 3.3V @ 25°C

-

20

V_DDEXT= 3.6V @ -40°C

V_OL

-

40

60

V_{O H}

-

0

0.5

1.0

1.5

2.0

2.5

3.0

SOURCE VOLTAGE (V)

-50

Figure 42. Drive Current C (Low V_DDEXT

)

V_OL

-

100

80

V_{DDEX T}= 3.0V @ 95°C

_{DDEX T}= 3.3V @ 25°C

V_{DDE XT}= 3.6V @ 40°C

-150

V

0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

-

60

SOURCE VOLTAGE (V)

40

Figure 39. Drive Current A (High V_DDEXT

)

V_OH

20

0

150

100

50

V_{DDEX T}= 2.25V @ 95°C

_{DDE XT}= 2.50V @ 25°C

-20

-40

-60

-80

V

V_{DDE XT}= 2.75V @

-40°C

V_{O L}

V_OH

0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

SOURCE VOLTAGE (V)

-50

Figure 43. Drive Current C (High V_DDEXT

)

V_OL

-100

-150

0

0.5

1.0

1.5

2.0

2.5

3.0

SOURCE VOLTAGE (V)

Figure 40. Drive Current B (Low V_DDEXT

)

Rev. PrE

|

Page 59 of 70

| May 2006

ADSP-BF539/ADSP-BF539F

Preliminary Technical Data

100

80

60

40

V_DDEXT= 2.25V @ 95°C

V_DDEXT= 2.50V @ 25°C

V_{DDEX T}= 3.0V @ 95°C

V_{DDEX T}= 3.3V @ 25°C

V_{DDE XT}= 2.75V @ -40°C

60

V_{DD E XT}= 3.6V @

-40°C

40

20

0

V_OH

V_{O H}

20

0

-20

-40

-60

-80

-20

-40

-60

-80

V_OL

4.0

0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

0

0.5

1.0

1.5

2.0

2.5

3.0

SOURCE VOLTAGE (V)

Figure 47. Drive Current E (High V_DDEXT

)

Figure 44. Drive Current D (Low V_DDEXT

)

0

150

100

V_DDEXT= 3.0V @ 95°C

V_DDEXT= 3.3V @ 25°C

V_{DDE XT}= 2.25V @ 95°C

V_{DDE XT}= 2.50V @ 25°C

-10

-20

-30

-40

-50

-60

V

_{DD E XT}= 3.6V @ -40°C

V_{DDEX T}= 2.75V @ -40°C

50

0

V_OH

V_OL

-50

V_OL

-

100

150

-

0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

0.5

1.0

1.5

2.0

2.5

3.0

SOURCE VOLTAGE (V)

Figure 45. Drive Current D (High V_DDEXT

)

Figure 48. Drive Current F (Low V_DDEXT

)

50

40

30

20

10

0

-10

-20

V_{DDEX T}= 2.25V @ 95°C

_{DDEX T}= 2.50V @ 25°C

V_{DDEX T}= 2.75V @ 40°C

V_{DDEX T}= 3.0V @ 95°C

V_{DDEX T}= 3.3V @ 25°C

V

-

V_DDEXT= 3.6V @ -40°C

V_OH

-30

-40

V_OL

-10

-20

-30

-40

-50

-60

-70

-80

V_OL

4.0

3. 0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

0

0.5

1.0

1.5

2.0

2.5

SOURCE VOLTAGE (V)

Figure 49. Drive Current F (High V_DDEXT

)

Figure 46. Drive Current E (Low V_DDEXT

)

Rev. PrE

|

Page 60 of 70

| May 2006

Preliminary Technical Data

ADSP-BF539/ADSP-BF539F

POWER DISSIPATION

TEST CONDITIONS

Total power dissipation has two components: one due to inter-

nal circuitry (P_INT) and one due to the switching of external

output drivers (P_EXT). Table 45 through Table 47 show the power

dissipation for internal circuitry (V_DDINT).

All timing parameters appearing in this data sheet were mea-

sured under the conditions described in this section. Figure 50

shows the measurement point for AC measurements (except

output enable/disable). The measurement point V_MEASis 1.5 V

for V_DDEXT(nominal) = 2.5/3.3 V.

See the ADSP-BF53x Blackfin Processor Hardware Reference

Manual for definitions of the various operating -modes and for

instructions on how to minimize system power.

INPUT

OR

OUTPUT

V_MEAS

Many operating conditions can affect power dissipation. System

designers should refer to EE-229: Estimating Power for

ADSP-BF531/ADSP-BF532 Blackfin Processors on the Analog

Devices website (www.analog.com)—use site search on

“EE-229.” This document provides detailed information for

optimizing your design for lowest power.

Figure 50. Voltage Reference Levels for AC

Measurements (Except Output Enable/Disable)

Output Enable Time Measurement

Table 45. Internal Power Dissipation (Hibernate mode)

Output pins are considered to be enabled when they have made

a transition from a high impedance state to the point when they

start driving.

I_DD(nominal¹)

Unit

µA

2

I_DDHIBERNATE

50

20

The output enable time t_ENAis the interval from the point when

a reference signal reaches a high or low voltage level to the point

when the output starts driving as shown on the right side of Fig-

ure 51, “Output Enable/Disable,” on page 62.

3

I_DDRTC

µA

¹Nominal assumes an operating temperature of 25°C.

²Measured at V_DDEXT= 3.65 V with voltage regulator off (V_DDINT= 0 V).

³Measured at V_DDRTC= 3.3 V at 25°C.

The time t_{ENA_MEASURED}is the interval, from when the reference

signal switches, to when the output voltage reaches V_TRIP(high)

or V_TRIP(low). V_TRIP(high) is 2.0 V and V_TRIP(low) is 1.0 V for

_DDEXT(nominal) = 2.5/3.3 V. Time t_TRIPis the interval from

when the output starts driving to when the output reaches the

V_TRIP(high) or V_TRIP(low) trip voltage.

Table 46. Internal Power Dissipation (Deep Sleep mode)

1

I_DD(nominal²)

28.00

Unit

mA

V

V_DDINT

0.95

1.00

1.10

1.26

32.00

Time t_ENAis calculated as shown in the equation:

40.00

t_ENA= t_{ENA_MEASURED}– t_TRIP

54.00

If multiple pins (such as the data bus) are enabled, the measure-

ment value is that of the first pin to start driving.

¹Assumes V_DDINTis regulated externally.

²Nominal assumes an operating temperature of 25°C.

Output Disable Time Measurement

Table 47. Internal Power Dissipation (Full On¹mode)

Output pins are considered to be disabled when they stop driv-

ing, go into a high impedance state, and start to decay from their

output high or low voltage. The output disable time t_DISis the

difference between t_{DIS_MEASURED}and t_DECAYas shown on the left

V_DDINT²@ f_CCLK(MHz)

0.95 @ 50 MHz

I_DD(nominal³)

46.00

Unit

mA

side of Figure 51.

0.95 @ 250 MHz

0.95 @ 300 MHz

1.00 @ 350 MHz

1.10 @ 444 MHz

1.26 @ 500 MHz

98.00

t_DIS= t_{DIS_MEASURED}– t_DECAY

110.00

The time for the voltage on the bus to decay by ∆V is dependent

on the capacitive load C_Land the load current I_L. This decay time

can be approximated by the equation:

132.00

180.00

235.00

t_DECAY= (C_L∆V) ⁄ I_L

¹Processor executing 75% dual MAC, 25% ADD with moderate data bus activity.

²Assumes V_DDINTis regulated externally.

The time t_DECAYis calculated with test loads C_Land I_L, and with

∆V equal to 0.5 V for V_DDEXT(nominal) = 2.5/3.3 V.

³Nominal assumes an operating temperature of 25°C.

The time t_{DIS+_MEASURED}is the interval from when the reference

signal switches, to when the output voltage decays ∆V from the

measured output high or output low voltage.

Rev. PrE

|

Page 61 of 70

| May 2006

ADSP-BF539/ADSP-BF539F

Preliminary Technical Data

The delay and hold specifications given should be derated by a

factor derived from these figures. The graphs in these figures

may not be linear outside the ranges shown.

Example System Hold Time Calculation

To determine the data output hold time in a particular system,

first calculate t_DECAYusing the equation given above. Choose ∆V

to be the difference between the ADSP-BF539/ADSP-BF539F

processor’s output voltage and the input threshold for the

device requiring the hold time. C_Lis the total bus capacitance

(per data line), and I_Lis the total leakage or three-state current

(per data line). The hold time will be t_DECAYplus the various out-

put disable times as specified in the Timing Specifications on

Page 29 (for example t_DSDATfor an SDRAM write cycle as shown

in Table 21 on Page 36).

ABE_B[0] (133 MHz DRIVER), V

(MIN) = 2.25V,TEMPERATURE = 85°C

DDEXT

14

12

RISE TIME

10

FALL TIME

8

6

4

REFERENCE

SIGNAL

2

0

t_{DIS_MEASURED}

t_{ENA_MEASURED}

t_DIS

t_ENA

0

50

100

150

200

250

V_OH

V_OH(MEASURED)

LOAD CAPACITANCE (pF)

(MEASURED)

V_OH(MEASURED) ؊⌬V

V_OL(MEASURED) + ⌬V

V_TRIP(HIGH)

Figure 53. Typical Rise and Fall Times (10%–90%) versus Load Capacitance

for Driver A at V_DDEXT(min)

V_TRIP(LOW)

V_OL

V_OL(MEASURED)

(MEASURED)

t_DECAY

t_TRIP

ABE0 (133 MHz DRIVER), V

(MAX) = 3.65V,TEMPERATURE = 85°C

DDEXT

12

OUTPUT STOPS DRIVING

OUTPUT STARTS DRIVING

10

8

HIGH IMPEDANCE STATE

RISE TIME

Figure 51. Output Enable/Disable

FALL TIME

50⍀

TO

OUTPUT

6

V

LOAD

4

30pF

2

Figure 52. Equivalent Device Loading for AC Measurements

(Includes All Fixtures)

0

50

100

150

200

250

LOAD CAPACITANCE (pF)

Capacitive Loading

Figure 54. Typical Rise and Fall Times (10%–90%) versus Load Capacitance

for Driver A at V_DDEXT(max)

Output delays and holds are based on standard capacitive loads:

30 pF on all pins (see Figure 52). V_LOADis 1.5 V for V_DDEXT

(nominal) = 2.5/3.3 V. Figure 53 on Page 62 through Figure 60

on Page 63 show how output rise time varies with capacitance.

Rev. PrE

|

Page 62 of 70

| May 2006

Preliminary Technical Data

ADSP-BF539/ADSP-BF539F

CLKOUT (CLKOUT DRIVER), V

(MIN) = 2.25V,TEMPERATURE = 85

°C

PF9 (33 MHz DRIVER), V

(MAX) = 3.65V,TEMPERATURE = 85°C

DDEXT

12

20

18

16

14

10

RISE TIME

8

6

4

2

0

12

10

FALL TIME

8

6

4

2

0

50

100

150

200

250

0

50

100

150

200

250

LOAD CAPACITANCE (pF)

Figure 58. Typical Rise and Fall Times (10%–90%) versus Load Capacitance

for Driver C at V_DDEXT(max)

Figure 55. Typical Rise and Fall Times (10%–90%) versus Load Capacitance

for Driver B at V_DDEXT(min)

SCK (66 MHz DRIVER), V

(MIN) = 2.25V,TEMPERATURE = 85°C

CLKOUT (CLKOUT DRIVER), V

(MAX) = 3.65V,TEMPERATURE = 85°C

DDEXT

18

16

14

12

10

8

10

9

8

7

RISE TIME

6

5

FALL TIME

4

3

2

1

0

6

4

2

0

50

100

150

200

250

0

50

100

150

200

250

LOAD CAPACITANCE (pF)

Figure 59. Typical Rise and Fall Times (10%–90%) versus Load Capacitance

for Driver D at V_DDEXT(min)

Figure 56. Typical Rise and Fall Times (10%–90%) versus Load Capacitance

for Driver B at V_DDEXT(max)

SCK (66 MHz DRIVER), V (MAX) = 3.65V,TEMPERATURE = 85°C

DDEXT

PF9 (33 MHz DRIVER), V

(MIN) = 2.25V,TEMPERATURE = 85°C

DDEXT

14

30

25

20

15

10

5

12

10

8

RISE TIME

FALL TIME

6

4

2

0

50

100

150

200

250

0

50

100

150

200

250

LOAD CAPACITANCE (pF)

Figure 60. Typical Rise and Fall Times (10%–90%) versus Load Capacitance

for Driver D at V_DDEXT(max)

Figure 57. Typical Rise and Fall Times (10%–90%) versus Load Capacitance

for Driver C at V_DDEXT(min)

Rev. PrE

|

Page 63 of 70

| May 2006

ADSP-BF539/ADSP-BF539F

Preliminary Technical Data

ENVIRONMENTAL CONDITIONS

To determine the junction temperature on the application

printed circuit board use:

T_J= T_CASE+ (Ψ_JT× P_D)

where:

T_J= Junction temperature (؇C)

T_CASE= Case temperature (؇C) measured by customer at top

center of package.

Ψ_JT= From Table 48 or Table 49

P_D= Power dissipation (see Power Dissipation on Page 61 for

the method to calculate P_D)

Values of θ_JAare provided for package comparison and printed

circuit board design considerations. θ_JAcan be used for a first

order approximation of T_Jby the equation:

T_J= T_A+ (θ_JA× P_D)

where:

T_A= Ambient temperature (؇C)

Values of θ_JCare provided for package comparison and printed

circuit board design considerations when an external heatsink is

required.

Values of θ_JBare provided for package comparison and printed

circuit board design considerations.

In Table 48 and Table 49, airflow measurements comply with

JEDEC standards JESD51-2 and JESD51-6, and the junction-to-

board measurement complies with JESD51-8. The junction-to-

case measurement complies with MIL-STD-883 (Method

1012.1). All measurements use a 2S2P JEDEC test board.

Table 48. Thermal Characteristics BC-316 Without Flash

Parameter

θ_JA

Condition

Typical

21.6

Unit

؇C/W

0 linear m/s air flow

1 linear m/s air flow

2 linear m/s air flow

θ_JMA

θ_JC

18.8

18.1

5.36

0.13

0.25

Ψ_JT

0 linear m/s air flow

1 linear m/s air flow

2 linear m/s air flow

Ψ_JT

Table 49. Thermal Characteristics BC-316 With Flash

Parameter

θ_JA

Condition

Typical

20.9

Unit

؇C/W

0 linear m/s air flow

1 linear m/s air flow

2 linear m/s air flow

θ_JMA

θ_JC

18.1

17.4

5.01

0.12

0.24

Ψ_JT

0 linear m/s air flow

1 linear m/s air flow

2 linear m/s air flow

Ψ_JT

Rev. PrE

|

Page 64 of 70

| May 2006

Preliminary Technical Data

316-BALL MINI-BGA PINOUT

Figure 61 lists the top view of the mini-BGA pin configuration.

Figure 62 lists the bottom view of the mini-BGA pin

configuration.

ADSP-BF539/ADSP-BF539F

Table 50 on Page 66 lists the mini-BGA pinout by pin number.

Table 51 on Page 67 lists the mini-BGA pinout by signal.

A1 BALL

A

B

C

D

E

F

A

B

C

D

E

F

G

H

J

G

H

J

K

L

K

L

M

N

P

R

T

M

N

P

R

T

U

V

W

Y

U

V

W

Y

1

2

3

4

5

6

7

8 9 10 11 12 13 14 15 16 17 18 19 20

20 19 18 17 16 15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

GND

I/O

GND

VDDRTC

VROUTx

NC

VDDINT

VDDEXT

VDDINT

NC

I/O

VROUTx

VDDEXT

Note: H18 andY14 are NC for ADSP-BF539

and I/O (FCE and FRESET) for ADSP-BF539F

Note: H18 andY14 are NC for ADSP-BF539

and I/O (FCE and FRESET) for ADSP-BF539F

Figure 61. 316-Ball Mini-BGA Pin Configuration (Top View)

Figure 62. 316-Ball Mini-BGA Pin Configuration (Bottom View)

Rev. PrE

|

Page 65 of 70

|

May 2006

ADSP-BF539/ADSP-BF539F

Preliminary Technical Data

Table 50. 316-Ball Mini-BGA Pin Assignment (Numerically by Pin Number)

Ball No. Signal

Ball No. Signal Ball No. Signal Ball No. Signal Ball No. Signal Ball No. Signal

Ball No. Signal

A1

GND

PF10

PF11

C7

C8

C9

SPI2SEL F8

SPI2SS F9

MOSI2 F10

MISO2 F11

GND

J12

J13

J14

J18

J19

J20

K1

GND

AMS0

AMS2

SA10

RFS1

TMR2

GP

M19

M20

N1

ABE0

ABE1

TFS0

T3

T7

T8

GND

W1

TCK

A2

VDDEXT W2

VDDEXT W3

VDDEXT W4

VDDEXT W5

VDDEXT W6

VDDINT W7

VDDINT W8

VDDINT W9

GND

A3

DATA15

DATA13

DATA11

DATA9

DATA7

DATA5

DATA3

DATA1

RSCK2

DR2PRI

DT2PRI

RX2

A4

PPI_CLK C10

N2

DR0PRI T9

A5

PPI0

PPI2

PF15

PF13

C11

C12

C13

C14

SCK2

F12

N3

GND

T10

A6

MPIVDD F13

SPI1SEL F14

MISO1 F18

SPI1SS F19

MOSI1 F20

N7

VDDEXT T11

A7

N8

GND

T12

T13

T14

T18

T19

T20

A8

DT3PRI K2

N9

A9

VDDRTC C15

MRX

MFS

SCK0

K3

K7

K8

N10

N11

N12

N13

N14

N18

N19

N20

P1

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

B1

RTXO

RTXI

GND

CLKIN

XTAL

MLF

C16

C17

C18

C19

C20

D1

GND

AMS3

AMS1

AOE

RFS3

W10

SCK1

GND

G1

G2

ADDR7 W11

ADDR8 W12

MOSI0 K9

DT0SEC K10

MMCLK G3

VDDINT U1

DT3SEC U2

ADDR1 U3

ADDR2 U7

TRST

TMS

GND

W13

W14

W15

SCKE

PF4

G7

G8

G9

GND

BR

K11

K12

K13

K14

K18

K19

K20

L1

TX2

MXO

MXI

D2

PF5

VDDEXT W16

VDDEXT W17

VDDEXT W18

VDDEXT W19

VDDEXT W20

VDDINT Y1

VDDINT Y2

VDDINT Y3

ADDR18

ADDR15

ADDR13

GND

D3

DT1SEC G10

TSCK0

RFS0

GND

U8

MRXON D7

VROUT1 D8

GND

G11

G12

G13

G14

G18

G19

G20

H1

P2

U9

P3

U10

GND

PF8

D9

P7

VDDEXT U11

ADDR14

GND

D10

D11

D12

D13

D14

D18

D19

D20

E1

RSCK1

TMR1

GND

TSCK3

ARE

P8

GND

U12

U13

U14

U18

U19

U20

B2

GND

PF9

L2

P9

TDO

B3

CLKOUT L3

SRAS L7

DT1PRI L8

TSCK1 L9

DR1SEC L10

P10

P11

P12

P13

P14

P18

P19

P20

R1

DATA14

DATA12

DATA10

DATA8

DATA6

DATA4

DATA2

DATA0

RFS2

B4

PF3

RSCK3

Y4

B5

PPI1

ADDR9 Y5

ADDR10 Y6

B6

PPI3

H2

B7

PF14

PF12

SCL0

SDA0

CANRX

CANTX

NMI

MBCLK H3

VDDINT V1

DR3SEC V2

ADDR3 V3

ADDR4 V4

TDI

Y7

Y8

Y9

B8

SMS

PF1

H7

GND

FCE

L11

L12

L13

L14

L18

L19

L20

M1

M2

M3

M7

M8

GND

B9

H8

B10

B11

B12

B13

B14

B15

B16

B17

B18

B19

B20

C1

E2

PF2

H9

BMODE1 Y10

BMODE0 Y11

E3

GND

MTX

ARDY

PF0

H10

H11

H12

H13

H14

H18

H19

H20

J1

TX0

V5

V6

V7

E7

R2

RSCK0

GND

Y12

TSCK2

TFS2

E8

R3

VDDEXT Y13

VDDEXT Y14

VDDEXT Y15

VDDEXT Y16

VDDEXT Y17

VDDINT Y18

DR2SEC Y19

RESET

E9

AWE

R7

VDDEXT V8

FRESET

SCL1

MXEVDD E10

MXEGND E11

MTXON E12

DT0PRI R8

GND

V9

TMR0

GND

R9

V10

V11

V12

V13

V14

SDA1

SCAS

SWE

TFS1

R10

ADDR19

ADDR17

ADDR16

GND

E13

E14

VDDEXT R11

GND

R12

R13

R14

R18

R19

R20

VROUT0 E18

J2

DR1PRI M9

DR0SEC M10

BG

Y20

PF6

E19

E20

F1

J3

VDDINT V15

DR3PRI V16

ADDR5 V17

ADDR6 V18

BGH

C2

PF7

J7

GND

M11

M12

M13

M14

M18

DT2SEC

GND

C3

GND

RX1

TX1

J8

C4

F2

MISO0 J9

GND

C5

F3

GND

J10

J11

VDDINT T1

RX0

V19

V20

ADDR11

ADDR12

C6

F7

TFS3

T2

EMU

Rev. PrE

|

Page 66 of 70

|

May 2006

Preliminary Technical Data

ADSP-BF539/ADSP-BF539F

Table 51. 316-Ball Mini-BGA Pin Assignment (Alphabetically by Signal)

Signal

ABE0

Ball No. Signal Ball No. Signal Ball No. Signal Ball No. Signal

Ball No. Signal Ball No. Signal Ball No.

M19

M20

N19

N20

P19

P20

R19

R20

T19

T20

U19

U20

V19

V20

W18

W20

W17

Y19

Y18

W16

Y17

J18

DATA8 Y6

DATA9 W6

DATA10 Y5

DATA11 W5

DATA12 Y4

DATA13 W4

DATA14 Y3

DATA15 W3

DR0PRI N2

DR0SEC J3

DR1PRI J2

DR1SEC H3

DR2PRI W12

DR2SEC V13

DR3PRI R18

DR3SEC P18

DT0PRI M1

DT0SEC G3

DT1PRI H1

DT1SEC D3

DT2PRI W13

DT2SEC V16

DT3PRI F18

DT3SEC N18

GND

E7

GND

K11

K12

K13

K14

L3

GND

GP

V17

V18

W2

W19

Y1

PPI2

PPI3

A6

B6

TSCK1

TSCK2

TSCK3

TX0

H2

ABE1

E8

Y12

L18

R1

ADDR1

ADDR2

ADDR3

ADDR4

ADDR5

ADDR6

ADDR7

ADDR8

ADDR9

ADDR10

ADDR11

ADDR12

ADDR13

ADDR14

ADDR15

ADDR16

ADDR17

ADDR18

ADDR19

AMS0

E9

RESET B14

E10

E11

E12

E13

E14

E18

F3

RFS0

RFS1

RFS2

RFS3

P2

K1

TX1

C6

L7

Y20

K3

Y11

T18

TX2

W15

L8

VDDEXT M7

VDDEXT N7

VDDEXT P7

VDDEXT R7

VDDEXT T7

VDDEXT T8

VDDEXT T9

VDDEXT T10

VDDEXT T11

VDDEXT U7

VDDEXT U8

VDDEXT U9

VDDEXT U10

VDDEXT U11

VDDEXT V7

VDDEXT V8

VDDEXT V9

VDDEXT V10

VDDEXT V11

VDDINT M14

VDDINT N14

VDDINT P14

VDDINT R14

VDDINT T12

VDDINT T13

VDDINT T14

VDDINT U12

VDDINT U13

VDDINT U14

VDDINT V12

VDDRTC A9

VROUT0 B20

VROUT1 A19

L9

MBCLK

MFS

D19

F20

RSCK0 R2

RSCK1 L1

RSCK2 W11

RSCK3 U18

L10

L11

L12

L13

L14

M3

M8

M9

M10

M11

M12

M13

N3

MMCLK C19

F7

MLF

A15

F2

F8

MISO0

MISO1

MISO2

MOSI0

MOSI1

MOSI2

RTXI

RTXO

RX0

A11

A10

T1

F9

C14

C10

G2

F10

F11

F12

F13

F14

G7

RX1

C5

C16

C9

RX2

W14

J20

H19

G1

SA10

SCAS

SCK0

SCK1

SCK2

SCKE

SCL0

SCL1

SDA0

SDA1

SMS

MPIVDD C12

MRXON A18

G8

MRX

MTX

F19

E19

C17

C11

C20

B9

G9

G10

G11

G12

G13

G14

H7

N8

MTXON B17

MXEGND B16

MXEVDD B15

AMS1

K19

J19

N9

AMS2

N10

N11

N12

N13

P3

Y15

B10

Y16

D20

AMS3

K18

K20

E20

L19

L20

V14

V15

V5

EMU

FCE

T2

MXI

MXO

NMI

PF0

A17

A16

B13

F1

AOE

H18

ARDY

FRESET Y14

ARE

GND

A1

H8

SPI1SEL C13

SPI1SS C15

SPI2SEL C7

SPI2SS C8

AWE

A12

A20

B2

H9

P8

PF1

E1

BG

H10

H11

H12

H13

H14

J7

P9

PF2

E2

BGH

P10

P11

P12

P13

R3

PF3

B4

BMODE0

BMODE1

BR

B18

B19

C3

PF4

D1

D2

C1

C2

B1

SRAS

SWE

TCK

G20

H20

W1

V1

V4

PF5

G18

B11

B12

A13

G19

Y10

W10

Y9

PF6

CANRX

CANTX

CLKIN

C4

PF7

TDI

C18

D7

J8

R8

PF8

TDO

TFS0

TFS1

TFS2

TFS3

TMR0

TMR1

TMR2

TMS

Y2

J9

R9

PF9

B3

N1

J1

CLKOUT

DATA0

DATA1

DATA2

DATA3

DATA4

DATA5

DATA6

DATA7

D8

J10

J11

J12

J13

J14

K7

R10

R11

R12

R13

T3

PF10

PF11

PF12

PF13

PF14

PF15

A2

A3

B8

D9

Y13

M18

M2

L2

D10

D11

D12

D13

D14

D18

E3

XTAL

A14

A8

B7

W9

Y8

U3

A7

K2

W8

K8

V2

PPI_CLK A4

U2

Y7

K9

V3

PPI0

PPI1

A5

B5

TRST

U1

W7

K10

V6

TSCK0 P1

Rev. PrE

|

Page 67 of 70

|

May 2006

ADSP-BF539/ADSP-BF539F

Preliminary Technical Data

OUTLINE DIMENSIONS

Dimensions in Figure 63—316-Ball Mini Ball Grid Array

(BC-316) are shown in millimeters.

15.20 BSC SQ

17.00 BSC SQ

A1 BALL

0.80 BSC BALL PITCH

A1 BALL INDICATOR

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

U

V

W

Y

20 19 18 17 16 1514 13 12 11 10

9 8 7 6 5 4 3 2 1

BOTTOM VIEW

TOP VIEW

0.30 MIN

0.12 MAX

COPLANARITY

1.70

1.61

SIDE VIEW

0.50

SEATING PLANE

1.46

BALL DIAMETER 0.45

0.40

DETAIL A

NOTES:

1. ALL DIMENSIONS ARE IN MILLIMETERS.

2. COMPLIANT TO JEDEC REGISTERED OUTLINE MO-205, VARIATION AM,

WITH THE EXCEPTION OF BALL DIAMETER.

3. CENTER DIMENSIONS ARE NOMINAL.

Figure 63. 316-Ball Mini Ball Grid Array (BC-316)

Rev. PrE

|

Page 68 of 70

| May 2006

Preliminary Technical Data

ADSP-BF539/ADSP-BF539F

SURFACE MOUNT DESIGN

Table 52 is provided as an aid to PCB design. For industry-

standard design recommendations, refer to IPC-7351,

Generic Requirements for Surface Mount Design and Land Pat-

tern Standard.

Table 52. BGA Data for Use with Surface Mount Design

Package

Ball Attach Type

Solder Mask Opening

Ball Pad Size

316-Ball Mini Ball Grid Array (BC-316)

Solder Mask Defined

0.40 mm diameter

0.50 mm diameter

ORDERING GUIDE

Model^{1, 2}

Temperature

Range³

Package Instruction Operating Voltage

Option Rate (Max) (Nominal)

Package Description

ADSP-BF539BBCZ-5A

ADSP-BF539WBBCZ-5A

ADSP-BF539YBCZ-4A

ADSP-BF539WYBCZ-4A

ADSP-BF539BBCZ-5F4⁴

ADSP-BF539WBBCZ5F4⁴

ADSP-BF539BBCZ-5F8⁵

ADSP-BF539WBBCZ5F8⁵

ADSP-BF539YBCZ-4F4⁴

ADSP-BF539WYBCZ4F4⁴

ADSP-BF539YBCZ-4F8⁵

ADSP-BF539WYBCZ4F8⁵

–40ºC to +85ºC

316-Ball Mini Ball Grid Array

BC-316

500 MHz

400 MHz

500 MHz

400 MHz

1.2 V internal, 2.5 V or 3.3 V I/O

1.0 V internal, 2.5 V or 3.3 V I/O

1.2 V internal, 2.5 V or 3.3 V I/O

1.0 V internal, 2.5 V or 3.3 V I/O

–40ºC to +105ºC 316-Ball Mini Ball Grid Array

–40ºC to +85ºC

316-Ball Mini Ball Grid Array

–40ºC to +105ºC 316-Ball Mini Ball Grid Array

¹W indicates this product is available for use in specific automotive applications. Contact your local ADI sales office for specific ordering information.

²Z indicates Pb-free part.

³Referenced temperature is ambient temperature.

⁴F4 indicates 256K x 16-bit flash memory.

⁵F8 indicates 512K x 16-bit flash memory.

Rev. PrE

|

Page 69 of 70

| May 2006

ADSP-BF539/ADSP-BF539F

Preliminary Technical Data

registered trademarks are the property of their respective owners.

PR06167-0-5/06(PrE)

Rev. PrE

|

Page 70 of 70

| May 2006


型号：	ADSP-BF539YBCZ-4F8
厂家：	ADI
描述：	16-BIT, 50MHz, OTHER DSP, PBGA316, LEAD FREE, MO-205AM, MBGA-316 时钟外围集成电路
文件：	总70页 (文件大小：2678K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADSP-BF539YBCZ-4F8 [ADI]

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