ADV7175 [ADI]
Integrated Digital CCIR-601 YCrCb to PAL/NTSC Video Encoder; 集成数字CCIR -601的YCrCb到PAL / NTSC视频编码器
| 型号： | ADV7175 |
| 厂家： | 
ADI |
| 描述： | Integrated Digital CCIR-601 YCrCb to PAL/NTSC Video Encoder |
| 文件： | 总36页 (文件大小：448K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Integrated Digital CCIR-601
YCrCb to PAL/NTSC Video Encoder
a
ADV7175/ADV7176
Close Captioning Support
FEATURES
Teletext Support (Passthrough Mode)
On-Board Color Bar Generation
CCIR-601 YCrCb to PAL/ NTSC Video Encoder
Single 27 MHz Clock Required (
؋
2 Oversam pling) Pixel Port Supports:
CCIR-656 4:2:2 8-Bit Parallel Input Form at
4:2:2 16-Bit Parallel Input Form at
SMPTE 170M NTSC Com patible Com posite Video Output
CCIR624/ CCIR601 PAL Com patible Com posite Video Output
SCART/ PeriTV Support
YUV Output Mode
Sim ultaneous Com posite and S-VHS Y/ C or RGB YUV
Video Outputs
Program m able Lum a Filters (Low -Pass/ Notch)
Square Pixel Support (Slave Mode)
Allow s Subcarrier Phase Locking w ith External Video
Source
On-Board Voltage Reference
2-Wire Serial MPU Interface (I2C Com patible)
+5 V CMOS Monolithic Construction
44-Pin PQFP Therm ally Enhanced Package
APPLICATIONS
MPEG-1 and MPEG-2 Video
DVD
Digital Satellite/ Cable System s (Set Top Boxes/ IRDs)
Video Gam es
CD Video/ Karaoke
Professional Studio Quality
PC Video/ Multim edia
10-Bit DAC Resolution for Encoded Video Channels
8-Bit DAC Resolution for RGB Output
YUV Interpolation for Accurate Subcarrier Construction
Program m able Subcarrier Frequency and Phase
Program m able LUMA Delay
Color Signal Control/ Burst Signal Control
Interlaced/ Noninterlaced Operation
Com plete On-Chip Video Tim ing Generator
Master/ Slave Operation Supported
Master Mode Tim ing Program m ability
Macrovision Antitaping Facility Rev 6.1/ 7.x (ADV7175 Only)*
GENERAL D ESCRIP TIO N
The ADV7175/ADV7176 is an integrated digital video encoder
that converts Digital CCIR-601 4:2:2 component video data into a
standard analog baseband television signal compatible with world
wide standards NTSC, PAL B/D/G/H/I, PAL M or PAL N. In
addition to the composite output signal, there is the facility to out-
put S-VHS Y/C video, YUV or RGB video. The Y/C, YUV or
RGB format is simultaneously available at the analog outputs with
the composite video signal. Each analog output generates a
standard video-level signal into a doubly terminated 75 Ω load.
(Continued on page 6)
FUNCTIO NAL BLO CK D IAGRAM
M
U
L
T
I
P
L
E
X
E
R
8
8
10
10
10
GREEN/
LUMA/
Y
V
AA
10-BIT
DAC
YUV TO
RBG
MATRIX
RED/
CHROMA/
V
10-BIT
DAC
RESET
8
BLUE/
COMPOSITE/
U
10-BIT
DAC
Y
8
8
8
8
10
10
8
8
8
8
INTER-
POLATOR
ADD
SYNC
LOW-PASS
FILTER
COLOR
DATA
YCrCb
TO
YUV
P7–P0
4:2:2 TO
4:4:4
INTER-
U
8
8
INTER-
POLATOR
ADD
BURST
LOW-PASS
FILTER
10
MATRIX
P15–P8
10-BIT
DAC
POLATOR
COMPOSITE
10
10
V
8
8
INTER-
POLATOR
ADD
BURST
LOW-PASS
FILTER
ADV7175/ADV7176
10
HSYNC
V
REAL-TIME
CONTROL
CIRCUIT
REF
VOLTAGE
REFERENCE
CIRCUIT
VIDEO TIMING
GENERATOR
2
I C MPU PORT
FIELD/VSYNC
SIN/COS
DDS BLOCK
R
SET
BLANK
COMP
CLOCK
SCRESET/RTC
SCLOCK SDATA ALSB
GND
*T his device is protected by U.S. Patent Numbers 4631603, 4577216, 4819098 a nd other intellectual property rights. T he Macrovision anticopy process is
licensed for noncommercial home use only, which is its sole intended use in the devic e. Please contact sales office for latest Macrovision version available.
REV. A
Inform ation furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assum ed by Analog Devices for its
use, nor for any infringem ents of patents or other rights of third parties
which m ay result from its use. No license is granted by im plication or
otherwise under any patent or patent rights of Analog Devices.
© Analog Devices, Inc., 1996
One Technology Way, P.O. Box 9106, Norw ood, MA 02062-9106, U.S.A.
Tel: 617/ 329-4700 Fax: 617/ 326-8703
1
(V = +5 V , V = 1.235 V RSET = 150 ⍀. All specifications
AA
REF
2
ADV7175/ADV7176–SPECIFICATIONS T to TMAX unless otherwise noted)
MIN
Model
P aram eter
AD V7175/AD V7176
Conditions1
Min
Typ
Max
Units
ST AT IC PERFORMANCE
Resolution (Each DAC)
Accuracy (Each DAC)
Integral Nonlinearity
10
Bits
±1
±1
LSB
LSB
Differential Nonlinearity
Guaranteed Monotonic
VIN = 0.4 V or 2.4 V
DIGIT AL INPUT S
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IIN
2
V
V
µA
0.8
±1
Input Capacitance, CIN
10
10
pF
DIGIT AL OUT PUT S
Output High Voltage, VOH
Output Low Voltage, VOL
Floating-State Leakage Current
Floating-State Output Capacitance
ISOURCE = 400 µA
ISINK = 3.2 mA
2.4
33
V
V
µA
pF
0.4
10
ANALOG OUT PUT S
Output Current3
34.7
8
182.5
33.9
2
37
mA
mA
IRE
µA
%
V
kΩ
pF
Output Current4
Full-Scale DAC Output
LSB Size
DAC-to-DAC Matching
Output Compliance, VOC
Output Impedance, ROUT
Output Capacitance, COUT
5
0
+1.4
15
IOUT = 0 mA
30
VOLT AGE REFERENCE
Voltage Reference Range, VREF
IVREFOUT = 20 µA
1.112
1.235
1.359
V
POWER REQUIREMENT S5
VAA
5
V
6
IDAC
ICCT
140
110
0.02
155
150
0.5
mA
mA
%/%
7
Power Supply Rejection Ratio
COMP = 0.1 µF
DYNAMIC PERFORMANCE8
Luma Bandwidth9 (Low-Pass Filter)
Stopband Cutoff
Pass Band Cutoff
Chroma Bandwidth
Stopband Cutoff
Pass Band Cutoff
Luma Bandwidth9 (Low-Pass Filter)
Stopband Cutoff
Pass Band Cutoff
Chroma Bandwidth
Stopband Cutoff
NT SC Mode
>50 dB Attenuation
<0.06 dB Attenuation
NT SC Mode
<40 dB Attenuation
>0.1 dB Attenuation
PAL MODE
>50 dB Attenuation
<0.06 dB Attenuation
PAL MODE
<40 dB Attenuation
>0.1 dB Attenuation
7.5
2.3
MHz
MHz
3.6
1.0
MHz
MHz
8.0
3.4
MHz
MHz
4.0
1.3
MHz
MHz
%
Degree
%
Degree
dB rms
dB p-p
Degree
%
Pass Band Cutoff
Differential Gain
Differential Phase
Differential Gain
Differential Phase
SNR
SNR
0.8
0.8
7
Lower Power Mode
Lower Power Mode
RMS
2
60
56
1.0
1.0
Peak Periodic
Hue Accuracy
Color Saturation Accuracy
NOT ES
1±5% for all versions.
2T emperature range T MIN to T MAX: 0°C to 70°C.
3Full drive into 37.5 Ω load.
4Minimum drive with buffered/scaled output load.
5Power measurements are taken with Clock Frequency = 27 MHz. Max TJ = 100°C.
6IDAC is the total current to drive all four DACs. T urning off one DAC reduces IDAC correspondingly.
7ICCT (Circuit Currrent) is the continuous currrent required to drive the device.
8Guaranteed by characterization.
9T hese specifications are for the low-pass filter only. For the other internal filters please see Figure 3.
Specifications subject to change without notice.
–2–
REV. A
ADV7175/ADV7176
AC CH ARACTERISTICS1
P aram eter
Min
Typ
Max
Units Condition
Chroma Nonlinear Gain
Chroma Nonlinear Phase
Chroma Nonlinear Phase
Chroma/Luma Intermod
Chroma/Luma Intermod
Chroma/Luma Gain Ineq
Chroma/Luma Delay Ineq
Luminance Nonlinearity
Chroma AM Noise
0.6
1
±%
±°
±°
±%
±%
±%
ns
±%
dB
dB
Referenced to 40 IRE
NT SC
PAL
Referenced to 714 mV (NT SC)
Referenced to 700 mV (PAL)
1.7
0.2
0.4
0.6
1
0.8
60
59
Chroma PM Noise
2
3
4
TIMING–SPECIFICATIONS (V = +5 V , V = 1.235 V RSET = 150 ⍀. All specifications T to TMAX unless otherwise noted)
AA
REF
MIN
P aram eter
Min
Typ
Max
Units Condition
MPU PORT1
SCLOCK Frequency
0
100
kHz
µs
µs
µs
µs
ns
µs
ns
µs
SCLOCK High Pulse Width, t1
SCLOCK Low Pulse Width, t2
Hold T ime (Start Condition), t3
Setup T ime (Start Condition), t4
Data Setup T ime, t5
SDAT A, SCLOCK Rise T ime, t6
SDAT A, SCLOCK Fall T ime, t7
Setup T ime (Stop Condition), t8
4.0
4.7
4.0
4.7
250
After this period the first clock pulse is generated
Relevant for repeated start condition.
1
300
4.7
ANALOG OUT PUT S1, 5
Analog Output Delay
DAC Analog Output Skew
5
0
ns
ns
CLOCK CONT ROL
AND PIXEL PORT6
FCLOCK
24.52 27
8
29.5
MHz
ns
Clock High T ime t9
Clock Low T ime t10
8
ns
Data Setup T ime t11
Data Hold T ime t12
3.5
1
ns
ns
Control Setup T ime t11
Control Hold T ime t12
Digital Output Access T ime t13
Digital Output Hold T ime t14
Pipeline Delay t15
4
2
ns
ns
ns
ns
24
6
37
Clock Cycles
NOT ES
1Guaranteed by characterization.
2T T L input values are 0 to 3 volts, with input rise/fall times ≤ 3 ns, measured between the 10% and 90% points. T iming reference points at 50% for inputs and
outputs. Analog Output Load ≤ 3 pF.
3±5% for all versions.
4T emperature range (T MIN to T MAX); 0°C to +70°C.
5Output delay measured from the 50% point of the rising edge of CLOCK to the 50% point of full-scale transition.
6Pixel Port consists of the following inputs:
Pixel Inputs:
Pixel Controls:
Clock Input:
P15–P0
HSYNC, FIELD/VSYNC, BLANK
CLOCK
Specifications subject to change without notice.
–3–
REV. A
ADV7175/ADV7176
t5
t3
t3
SDATA
t6
t2
SCLOCK
t1
t7
t4
t8
Figure 1. MPU Port Tim ing Diagram
CLOCK
t12
t9
t10
HSYNC,
CONTROL
I/PS
FIELD/VSYNC,
BLANK
PIXEL INPUT
DATA
Cb
Y
Cr
Y
Cb
t13
Y
t11
HSYNC,
FIELD/VSYNC,
BLANK
CONTROL
O/PS
t14
Figure 2. Pixel and Control Data Tim ing Diagram
ABSO LUTE MAXIMUM RATINGS 1
O RD ERING GUID E
VAA to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Voltage on Any Digital Input Pin . GND – 0.5 V to VAA + 0.5 V
Storage T emperature (TS) . . . . . . . . . . . . . –65°C to +150°C
Junction T emperature (TJ) . . . . . . . . . . . . . . . . . . . . +150°C
Lead T emperature (Soldering, 10 secs) . . . . . . . . . . . +260°C
Analog Outputs to GND2 . . . . . . . . . . . . . GND –0.5 to VAA
Tem perature
Range
P ackage
O ption
Model
ADV7175KS
ADV7176KS
0°C to +70°C
0°C to +70°C
S-44
S-44
NOT ES
1Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. T his is a stress rating only and functional
operation of the device at these or any other conditions above those listed in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
2Analog Output Short Circuit to any Power Supply or Common can be of an
indefinite duration.
CAUTIO N
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADV7175/ADV7176 feature proprietary ESD protection circuitry, permanent
damage may occur on devices subjected to high energy electrostatic discharges. T herefore,
proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
–4–
REV. A
ADV7175/ADV7176
P IN D ESCRIP TIO N
Input/O utput Function
Mnem onic
P15-P0
I
I
8-Bit 4:2:2 Multiplexed YCrCb Pixel Port (P7–P0) or
16-Bit YCrCb Pixel Port (P15–P0). P0 represents the LSB.
CLOCK
T T L Clock Input. Requires a stable 27 MHz reference Clock for proper operation.
Alternatively a 24.52 MHz (NT SC) or 29.5 MHz (PAL) can be used for square pixel
operation.
HSYNC
I/O
I/O
I/O
I
HSYNC (Modes 1 & 2) Control Signal. T his pin may be configured to output (Mas-
ter Mode) or accept (Slave Mode) Sync signals.
FIELD/VSYNC
BLANK
Dual Function FIELD (Mode 1) and VSYNC (Mode 2) Control Signal. T his pin may
be configured to output (Master Mode) or accept (Slave Mode) these control signals.
Video Blanking Control Signal. T he pixel inputs are ignored when this is logic level
“0.” T his signal is optional.
SCRESET /RT C
T his pin can be configured as an input by setting MR22 and MR21 of Mode
Register 2. It can be configured as a subcarrier reset pin, in which case a high to low
transition on this pin will reset the subcarrier to field 0. Alternatively it may be con-
figured as a Real T ime Control (RT C) input.
VREF
RSET
I/O
I
Voltage Reference Input for DACs or Voltage Reference Output (1.2 V).
A 150 Ω resistor connected from this pin to GND is used to control full-scale ampli-
tudes of the video signals.
COMP
O
O
Compensation Pin. Connect a 0.1 µF capacitor from COMP to VAA.
COMPOSIT E
PAL/NT SC Composite Video Output. Full-Scale Output is 180IRE (1286 mV) for
NT SC and 1300 mV for PAL.
RED/CHROMA/V
GREEN/LUMA/Y
BLUE/COMPOSIT E/U
SCLOCK
O
O
O
I
RED/S-VHS C/V Analog Output.
GREEN/S-VHS Y/Y Analog Output.
BLUE/Composite/U Analog Output.
MPU Port Serial Interface Clock Input.
MPU Port Serial Data Input/Output.
SDAT A
I/O
I
ALSB
T T L Address Input. T his signal set up the LSB of the MPU address.
RESET
I
T he input resets the on chip timing generator and sets the ADV7175/ADV7176 into
default mode. T his is NT SC operation, T iming Slave Mode 0, 8-bit operation, 2 ×
composite & S VHS out.
VAA
P
+5 V Supply.
Ground Pin.
GND
G
P IN CO NFIGURATIO N
42
44 43
PIN 1
41 40 39 38 37 36 35 34
1
2
V
33
32
V
AA
REF
IDENTIFIER
COMPOSITE
P5
P6
3
31 BLUE/COMPOSITE/U
30
4
V
P7
AA
5
29 GND
P8
ADV7175/ADV7176
PQFP
6
28
27
26
25
P9
V
AA
TOP VIEW
(Not to Scale)
7
GREEN/LUMA/Y
RED/CHROMA/V
COMP
P10
P11
P12
GND
8
9
10
11
24 SDATA
23
V
SCLOCK
AA
12 13 14 15 16 17 18 19
21 22
20
–5–
REV. A
ADV7175/ADV7176
(Continued from page 1)
T he ADV7175/ADV7176 is protected by U.S. Patent Numbers
5,343,196 and 5,442,355 and other intellectual property rights.
T he ADV7175/ADV7176 also supports both a PAL and NT SC
square pixel mode in slave mode.
D ATA P ATH D ESCRIP TIO N
T he video encoder accepts an 8-bit parallel pixel data stream in
CCIR-656 format or a 16-bit parallel data stream. T his 4:2:2
data stream is interpolated into 4:4:4 component video (YUV).
T he YUV video is interpolated to two times the pixel rate. T he
color-difference components (UV) are quadrature modulated
using a subcarrier frequency generated by an on-chip synthesizer
(also running at two times the pixel rate). T he two times pixel
rate sampling allows more accurate generation of the subcarrier
because frequency and phase errors are reduced by the higher
sampling rate. T he ADV7175/ADV7176 also offers the option to
output the YUV information directly.
For PAL B, D, G, H, I, M, N and NT SC M, N modes, YCrCb
4:2:2 data is input via the CCIR-656 compatible pixel port at a
13.5 MHz data rate. T he pixel data is de-multiplexed to form
three data paths. Y has a range of 16 to 235, Cr and Cb have a
range of 128 ± 112. T he ADV7175/ADV7176 supports PAL
(B, D, G, H, I, N, M) and NT SC (with and without Pedestal)
standards. The appropriate SYNC, BLANK and burst levels are
added to the YCrCb data. Macrovision antitaping (ADV7175
only) and close-captioning levels are also added to Y and the
resultant data is interpolated to a rate of 27 MHz. T he interpo-
lated data is filtered and scaled by three digital FIR filters.
T he luminance and chrominance components are digitally com-
bined and the resulting composite signal is output via a 10-bit
DAC. T hree additional 10-/8-bit DACs are provided to output
S-VHS Y/C Video (10 bits), YUV or RGB Video (8 bits).
T he U and V signals are modulated by the appropriate subcarrier
sine/cosine phases and added together to make up the chromi-
nance signal. T he luma (Y) signal can be delayed 1-3 luma
cycles (each cycle is 74 ns) with respect to the chroma signal.
T he luma and chroma signals are then added together to make
up the composite video signal. All edges are slew rate limited.
T he output video frames are synchronized with the incoming
data timing reference codes. Optionally the encoder accepts (and
can generate) HSYNC, VSYNC & FIELD timing signals. T hese
timing signals can be adjusted to change pulse width and posi-
tion while the part is in the master mode. T he encoder requires a
single two times pixel rate (27 MHz) clock for standard operation.
Alternatively the encoder requires 24.54 MHz clock for NT SC
or 29.5 MHz clock for PAL square pixel mode operation. All in-
ternal clocks are generated on-chip. T he ADV7175/ADV7176
modes are set up over a two wire serial bidirectional port (I2C
Compatible) with two slave addresses.
T he YCrCb data is also used to generate RGB data with appro-
priate SYNC and BLANK levels. T he RGB data is in sychro-
nization with the composite video output. Alternatively analog
YUV data can be generated instead of RGB.
T he four 10-bit DACs can be used to output:
1. 10-bit composite video + 8-bit RGB video.
2. 10-bit composite video + 8-bit YUV video.
3. T wo 10-bit composite video signals
+ 10-bit LUMA & CHROMA (Y/C) signals.
Additionally, the ADV7175/ADV7176 allows a subcarrier phase
lock with an external video source and has a color bar generator
on-board.
Alternatively, each DAC can be individually powered off if not
required.
Functionally the ADV7175 and ADV7176 are the same with
the exception that the ADV7175 can output the Macrovision
(Revision 6.1/7.x) anticopy algorithm.
All possible video outputs are illustrated in Appendix 3, 4 and 5.
INTERNAL FILTER RESP O NSE
T he Y filter supports several different frequency responses in-
cluding two 4.5/5.0 MHz low-pass and PAL/NT SC subcarrier
notch responses. T he U and V filters have a 0.6/1 0.3 MHz
low-pass response.
T he ADV7175/ADV7176 is fabricated in a +5 V CMOS pro-
cess. Its monolithic CMOS construction ensures greater func-
tionality with low power dissipation.
T he ADV7175/ADV7176 is packaged in a 44-pin thermally en-
hanced PQFP package (patent pending).
T hese filter characteristics are illustrated in Figures 3 to 11.
PASSBAND
STOPBAND
PASSBAND
STOPBAND
FILTER SELECTION
CUT OFF (MHz)
RIPPLE (dB)
ATTENUATION (dB)
CUT OFF (MHz)
F
3dB
MR04
MR03
NTSC
PAL
NTSC
PAL
NTSC/PAL
NTSC
PAL
0
0
0
0
1
1
1
0
0
1
1
0
1
1
2.3
3.4
1.0
1.4
4.0
2.3
3.4
0.026
0.098
0.085
0.107
0.150
0.054
0.106
7.5
8.0
3.57
4.43
8.0
>
>
>
>
>
>
>
50
4.2
5.0
2.1
2.7
5.65
4.2
5.0
51.3
27.6
29.3
40
54
50.3
7.5
8.0
Figure 3. Y Filter Specifications
PASSBAND
STOPBAND
STOPBAND
ATTENUATION (dB)
ATTENUATION @
1.3MHz (dB)
PASSBAND
CUT OFF (MHz)
F
3dB
FILTER SELECTION
RIPPLE (dB)
CUT OFF (MHz)
NTSC
PAL
1.0
1.3
0.085
0.04
3.6
4.0
>
40
40
0.3
0.02
2.05
2.45
>
Figure 4. UV Filter Specifications
–6–
REV. A
ADV7175/ADV7176
0
–20
0
–20
TYPE A
TYPE A
TYPE B
–40
–40
TYPE B
–60
–60
–80
–80
–100
–120
–100
–120
0
2
4
6
8
10
12
0
2
4
6
8
10
12
FREQUENCY – MHz
FREQUENCY – MHz
Figure 5. NTSC Low-Pass Filter
Figure 7. PAL Low-Pass Filter
0
–20
0
–20
–40
–40
–60
–60
–80
–80
–100
–120
–100
–120
0
2
4
6
8
10
12
0
2
4
6
8
10
12
FREQUENCY – MHz
FREQUENCY – MHz
Figure 6. NTSC Notch Filter
Figure 8. PAL Notch Filter
0
–20
–40
–60
–80
–100
–120
0
2
4
6
8
10
12
FREQUENCY – MHz
Figure 9. NTSC/PAL Extended Mode Filter
–7–
REV. A
ADV7175/ADV7176
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
0
2
4
6
8
10
12
0
2
4
6
8
10
12
FREQUENCY – MHz
FREQUENCY – MHz
Figure 11. PAL UV Filter
Figure 10. NTSC UV Filter
CO LO R BAR GENERATIO N
CLOCK
T he ADV7175/ADV7176 can be configured to generate 75%
amplitude, 75% saturation (75/7.5/75/7.5) for NT SC or 75%
amplitude, 100% saturation (100/0/75/0) for PAL color bars.
T hese are enabled by setting MR17 of Mode Register 1 to
Logic “1.”
COMPOSITE
SCRESET/RTC
VIDEO
DECODER
(e.g.SAA7110)
VIDEO
e.g. VCR
OR CABLE
GREEN/LUMA/Y
RED/CHROMA/V
M
U
X
P7–P0
BLUE/COMPOSITE/U
COMPOSITE
MPEG
DECODER
SQ UARE P IXEL MO D E
HSYNC
T he ADV7175/ADV7176 can be used to operate in square
pixel mode. For NT SC operation an input clock of 24.54 MHz
is required. Alternatively, for PAL operation, an input clock of
29.5 MHz is required. T he internal filters scale accordingly for
square pixel mode operation.
FIELD/VSYNC
ADV7175/ADV7176
Figure 12. RTC Connections
CO LO R SIGNAL CO NTRO L
T he color information can be switched on and off the video
output using Bit MR24 of Mode Register 2.
P IXEL TIMING D ESCRIP TIO N
T he ADV7175/ADV7176 can operate in either 8-bit or 16-bit
YCrCb Mode.
BURST SIGNAL CO NTRO L
T he burst information can be switched on and off the video
output using Bit MR25 of Mode Register 2.
8-Bit YCr Cb Mode
T his default mode accepts multiplexed YCrCb inputs through
the P7–P0 pixel inputs. T he inputs follow the sequence Cb0,
Y0 Cr0, Y1 Cb1, Y2, etc. T he Y, Cb and Cr data are input on
a rising clock edge.
NTSC P ED ESTAL CO NTRO L
T he pedestal information on both odd and even fields can be
controlled on a line by line basis using the NT SC Pedestal
Control Registers. T his allows the pedestals to be controlled
during the vertical blanking interval (Lines 10 to 25).
16-Bit YCr Cb Mode
T his mode accepts Y inputs through the P7-P0 pixel inputs and
multiplexed CrCb inputs through the P15-P8 pixel inputs. T he
data is loaded on every second rising clock edge of CLOCK.
T he inputs follow the sequence Cb0, Y0 Cr0, Y1 Cb1, Y2, etc.
SUBCARRIER RESET
T ogether with the SCRESET /RT C PIN and Bits MR22 and
MR21 of Mode Register 2, the ADV7175/ADV7176 can be
used in subcarrier reset mode. T he subcarrier will reset to field
0 at the start of the following field when a high to low transition
occurs on this input pin.
VID EO TIMING D ESCRIP TIO N
T he ADV7175/ADV7176 is intended to interface to off the shelf
MPEG1 and MPEG2 Decoders. As a consequence the
ADV7175/ADV7176 accepts 4:2:2 YCrCb pixel data via a
CCIR-656 pixel port and has several video timing modes of
operation that allow it to be configured as either system master
video timing generator or a slave to the system video timing gen-
erator. The ADV7175/ADV7176 generates all of the required
horizontal and vertical timing periods and levels for the analog
video outputs.
REAL TIME CO NTRO L
T ogether with the SCRESET /RT C PIN and Bits MR22 and
MR21 of Mode Register 2, the ADV7175/ADV7176 can be
used to lock an external video source. T he real time control
mode allows the ADV7175/ADV7176 to automatically alter the
subcarrier frequency to compensate for line length variation.
When the part is connected to a device that outputs out a digi-
tal datastream in the RT C format (such as a Phillips SAA7110
video decoder), the part will automatically change to the com-
pensated subcarrier frequency on a line by line basis. T his
digital datastream is 67 bits wide and the subcarrier is con-
tained in bits 0 to 21. Each bit is 2 clock cycles long.
T he ADV7175/ADV7176 calculates the width and placement
of analog sync pulses, blanking levels and color burst envelopes.
Color bursts are disabled on appropriate lines and serration and
equalization pulses are inserted where required.
(Continued on page 15)
–8–
REV. A
ADV7175/ADV7176
Mode 0 (CCIR-656): Slave O ption.
(T iming Register 0 T R0 = X X X X X 0 0 0)
T he ADV7175/ADV7176 is controlled by the SAV (Start Active Video) and EAV (End Active Video) time codes in the pixel data.
All timing information is transmitted using a 4-byte synchronization pattern. A synchronization pattern is sent immediately before
and after each line during active picture and retrace. Mode 0 is illustrated in Figure 13. T he HSYNC, FIELD/VSYNC and BLANK
(if not used) pins should be tied high in this mode.
ANALOG
VIDEO
EAV CODE
SAV CODE
8
0
0
0
F
F
F
F
A
B
A
B
A
B
8
0
0
0
C
r
C
b
F
F
0
0
0
0
X
Y
1
0
8
0
1
0
8
0
1
0
1
0
F
F
0
0
X
Y
C
b
C
r
C
r
C
b
C
r
C
b
Y
Y
Y
INPUT PIXELS
Y
ANCILLARY DATA
(HANC)
4 PIXELS
4 PIXELS
4 PIXELS
4 PIXELS
268 PIXELS
1440 PIXELS
1440 PIXELS
NTSC SYSTEM
PAL SYSTEM
280 PIXELS
END OF ACTIVE
VIDEO LINE
START OF ACTIVE
VIDEO LINE
Figure 13. Tim ing Mode 0 (Slave Mode)
Mode 0 (CCIR-656): Master O ption.
(T iming Register 0 T R0 = X X X X X 0 0 1)
T he ADV7175/ADV7176 generates H, V and F signals required for the SAV (start active video) and EAV (end active video) time
codes in the CCIR656 standard. T he H bit is output on the HSYNC pin, the V bit is output on the BLANK pin and the F bit is
output on the FIELD/VSYNC pin. Mode 0 is illustrated in Figure 14 (NT SC) and Figure 15 (PAL). T he H, V and F transitions
relative to the video waveform are illustrated in Figure 16.
DISPLAY
DISPLAY
VERTICAL BLANK
522
523
524
525
1
2
3
4
6
7
10
11
20
21
22
5
9
8
H
V
EVEN FIELD
ODD FIELD
F
DISPLAY
DISPLAY
VERTICAL BLANK
283
285
284
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
H
V
F
ODD FIELD
EVEN FIELD
Figure 14. Tim ing Mode 0 (NTSC Master Mode)
–9–
REV. A
ADV7175/ADV7176
DISPLAY
DISPLAY
VERTICAL BLANK
622
623
624
625
1
2
3
4
6
7
22
23
5
21
H
V
EVEN FIELD
ODD FIELD
F
DISPLAY
DISPLAY
VERTICAL BLANK
318
335
336
309
310
311
312
313
314
315
316
317
319
320
334
H
V
F
ODD FIELD EVEN FIELD
Figure 15. Tim ing Mode 0 (PAL Master Mode)
ANALOG
VIDEO
H
F
V
Figure 16. Tim ing Mode 0 Data Transitions (Master Mode)
–10–
REV. A
ADV7175/ADV7176
Mode 1: Slave O ption. HSYNC, BLANK, FIELD.
(T iming Register 0 T R0 = X X X X X 0 1 0)
In this mode the ADV7175/ADV7176 accepts horizontal SYNC and Odd/Even FIELD signals. A transition of the FIELD input
when HSYNC is low indicates a new frame, i.e., vertical retrace. T he BLANK signal is optional. When the BLANK input is disabled
the ADV7175/ADV7176 automatically blanks all normally blank lines as per CCIR-624. Mode 1 is illustrated in Figure 17 (NT SC)
and Figure 18 (PAL).
DISPLAY
DISPLAY
VERTICAL BLANK
522
523
524
525
20
21
22
1
2
3
4
6
7
8
10
11
5
9
HSYNC
BLANK
FIELD
EVEN FIELD
ODD FIELD
DISPLAY
DISPLAY
VERTICAL BLANK
283
285
284
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
HSYNC
BLANK
FIELD
ODD FIELD
EVEN FIELD
Figure 17. Tim ing Mode 1 (NTSC)
DISPLAY
DISPLAY
VERTICAL BLANK
622
623
624
625
1
2
3
4
6
7
5
21
22
23
HSYNC
BLANK
FIELD
EVEN FIELD
ODD FIELD
DISPLAY
DISPLAY
VERTICAL BLANK
309
310
311
312
313
314
315
316
318
319
320
317
334
335
336
HSYNC
BLANK
FIELD
ODD FIELD
EVEN FIELD
Figure 18. Tim ing Mode 1 (PAL)
–11–
REV. A
ADV7175/ADV7176
Mode 1: Master O ption. HSYNC, BLANK, FIELD.
(T iming Register 0 T R0 = X X X X X 0 1 1)
In this mode the ADV7175/ADV7176 can generate horizontal SYNC and Odd/Even FIELD signals. A transition of the FIELD
input when HSYNC is low indicates a new frame i.e., vertical retrace. T he BLANK signal is optional. When the BLANK input is
disabled the ADV7175/ADV7176 automatically blanks all normally blank lines as per CCIR-624. Pixel data is latched on the rising
clock edge following the timing signal transitions. Mode 1 is illustrated in Figure 17 (NT SC) and Figure 18 (PAL). Figure 19 illus-
trates the HSYNC, BLANK and FIELD for an odd or even field transition relative to the pixel data.
HSYNC
FIELD
PAL = 12 * CLOCK/2
NTSC = 16 * CLOCK/2
BLANK
PIXEL
DATA
Cr
Y
Cb
Y
PAL = 132 * CLOCK/2
NTSC = 118 * CLOCK/2
Figure 19. Tim ing Mode 1 Odd/Even Field Transitions
Mode 2: Slave O ption. HSYNC, VSYNC, BLANK.
(T iming Register 0 T R0 = X X X X X 1 0 0)
In this mode the ADV7175/ADV7176 accepts horizontal and vertical SYNC signals. A coincident low transition of both HSYNC
and VSYNC inputs indicates the start of an odd field. A VSYNC low transition when HSYNC is high indicates the start of an even
field. T he BLANK signal is optional. When the BLANK input is disabled, the ADV7175/ADV7176 automatically blanks all nor-
mally blank lines as per CCIR-624. Mode 2 is illustrated in Figure 20 (NT SC) and Figure 21 (PAL).
DISPLAY
DISPLAY
VERTICAL BLANK
522
523
524
525
20
21
22
1
2
3
4
6
7
8
10
11
5
9
HSYNC
BLANK
VSYNC
EVEN FIELD
ODD FIELD
DISPLAY
DISPLAY
VERTICAL BLANK
283
285
284
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
HSYNC
BLANK
VSYNC
ODD FIELD
EVEN FIELD
Figure 20. Tim ing Mode 2 (NTSC)
–12–
REV. A
ADV7175/ADV7176
DISPLAY
DISPLAY
VERTICAL BLANK
622
623
624
625
1
2
3
4
6
7
5
21
22
23
HSYNC
BLANK
VSYNC
EVEN FIELD
ODD FIELD
DISPLAY
DISPLAY
VERTICAL BLANK
309
310
311
312
313
314
315
316
318
319
320
317
334
335
336
HSYNC
BLANK
VSYNC
ODD FIELD
EVEN FIELD
Figure 21. Tim ing Mode 2 (PAL)
Mode 2: Master O ption. HSYNC, VSYNC, BLANK.
(T iming Register 0 T R0 = X X X X X 1 0 1 )
In this mode the ADV7175/ADV7176 can generate horizontal and vertical SYNC signals. A coincident low transition of both
HSYNC and VSYNC inputs indicates the start of an odd field. A VSYNC low transition when HSYNC is high indicates the start of
an even field. T he BLANK signal is optional. When the BLANK input is disabled the ADV7175/ADV7176 automatically blanks all
normally blank lines as per CCIR-624. Mode 2 is illustrated in Figure 20 (NT SC) and Figure 21 (PAL). Figure 22 illustrates the
HSYNC, BLANK and VSYNC for an even to odd field transition relative to the pixel data. Figure 23 illustrates the HSYNC,
BLANK and VSYNC for an odd to even field transition relative to the pixel data.
HSYNC
VSYNC
PAL = 12* CLOCK/2
NTSC = 16 * CLOCK/2
BLANK
PIXEL
DATA
Cb
Y
Cr
Y
PAL = 132* CLOCK/2
NTSC = 118 * CLOCK/2
LINE 3
LINE 4
Figure 22. Tim ing Mode 2 Even-to-Odd Field Transition
–13–
REV. A
ADV7175/ADV7176
HSYNC
VSYNC
PAL = 864 * CLOCK/2
NTSC = 858 * CLOCK/2
PAL = 12 * CLOCK/2
NTSC = 16 * CLOCK/2
BLANK
PIXEL
DATA
Cb
Y
Cr
Y
Cb
PAL = 132 * CLOCK/2
NTSC = 118 * CLOCK/2
LINE 266
LINE 265
Figure 23. Tim ing Mode 2 Odd-to-Even Field Transition
Mode 3: Master /Slave O ption. HSYNC, BLANK, FIELD.
(T iming Register 0 T R0 = X X X X X 1 1 0 or X X X X X 1 1 1)
In this mode the ADV7175/ADV7176 accepts or generates Horizontal SYNC and odd/even FIELD signals. A transition of the
FIELD input when HSYNC is high indicates a new frame i.e., vertical retrace. T he BLANK signal is optional. When the BLANK
input is disabled the ADV7175/ADV7176 automatically blanks all normally blank lines as per CCIR-624. Mode 3 is illustrated in
Figure 24 (NT SC) and Figure 25 (PAL).
DISPLAY
DISPLAY
VERTICAL BLANK
522
523
524
525
20
21
22
1
2
3
4
6
7
8
10
11
5
9
HSYNC
BLANK
FIELD
EVEN FIELD
ODD FIELD
DISPLAY
DISPLAY
VERTICAL BLANK
283
285
284
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
HSYNC
BLANK
FIELD
ODD FIELD
EVEN FIELD
Figure 24. Tim ing Mode 3 (NTSC)
–14–
REV. A
ADV7175/ADV7176
DISPLAY
DISPLAY
VERTICAL BLANK
622
623
624
625
1
2
3
4
6
7
5
21
22
23
HSYNC
BLANK
FIELD
EVEN FIELD
ODD FIELD
DISPLAY
DISPLAY
VERTICAL BLANK
309
310
311
312
313
314
315
316
318
319
320
317
334
335
336
HSYNC
BLANK
FIELD
EVEN FIELD
ODD FIELD
Figure 25. Tim ing Mode 3 (PAL)
(Continued from page 8)
P AL–Inter laced: Scan lines 1–6, 311–318 and 624–625 are al-
ways blanked and vertical sync pulses are included in Fields 1,
2, 5 and 6. Scan lines 1–5, 311–319 and 624–625 are always
blanked and vertical sync pulses are included in Fields 3, 4, 7
and 8. T he remaining scan lines in the vertical interval are also
blanked and can be used for close captioning data. Burst is dis-
abled on lines 1–6, 311–318 and 623–625 in Fields 1, 2, 5 and
6. Burst is disabled on lines 1–5, 311–319 and 623–625 in
Fields 3, 4, 7 and 8.
In addition the ADV7175/ADV7176 supports a PAL or NT SC
square pixel operation in slave mode. T he part requires an in-
put pixel clock of 24.54 MHz for NT SC and an input pixel
clock of 29.5 MHz for PAL. T he internal horizontal line
counters place the various video waveform sections in the cor-
rect location for the new clock frequencies.
T he ADV7175/ADV7176 has 8 distinct master or slave timing
configurations. T hese are divided into 4 timing modes which
operate at one discrete clock frequency (27 MHz). T iming con-
trol is established with the bidirectional SYNC, BLANK and
FIELD/VSYNC pins. T iming Mode Register 1 can also be
used to vary the timing pulse widths and the where they occur in
relation to each other.
P AL–Noninter laced: Scan lines 1–6 and 311–312 are always
blanked and vertical sync pulses are included. T he remaining
scan lines in the vertical interval are also blanked and can be
used for close captioning data. Burst is disabled on lines 1–5,
310–312.
O UTP UT VID EO TIMING
P O WER-O N RESET
T he video timing generator generates the appropriate SYNC,
BLANK and BURST sequence that controls the output analog
waveforms. T hese sequences are summarized below. In slave
modes the following sequences are synchronized with the input
timing control signals. In master modes the timing generator
free runs and generates the following sequences in addition to
the output timing control signals.
After power-up, it is necessary to execute a reset operation. A
reset occurs on the falling edge of a high to low transition on the
RESET pin. T his initializes the pixel port such that the pixel
inputs P7–P0 are selected. After reset, the ADV7175/ADV7176
is automatically set up to operate in NT SC mode. Subcarrier
frequency code 21F07C16 HEX is loaded into the subcarrier
frequency registers. All other registers, with the exception of
Mode Register 0, are set to 00H. All bits in Mode Register 0
are set to Logic Level “0” except Bit MR02. Bit MR02 of
Mode Register 0 is set to Logic “1.” T his enables the 7.5 IRE
pedestal.
NTSC–Inter laced: Scan lines 1–9 and 264–272 are always
blanked and vertical sync pulses are included. Scan lines 525,
10–21 and 262, 263, 273–284 are also blanked and can be used
for close captioning data. Burst is disabled on lines 1–6, 261–
269 and 523–525.
NTSC–Noninter laced: Scan lines 1–9 are always blanked
and vertical sync pulses are included. Scan lines 10–21 are also
blanked and can be used for close captioning data. Burst is dis-
abled on lines 1–6, 261–262.
–15–
REV. A
ADV7175/ADV7176
MP U P O RT D ESCRIP TIO N
will write information to the peripheral. A Logic “1” on the
LSB of the first byte means that the master will read informa-
tion from the peripheral.
T he ADV7175 and ADV7176 support a two wire serial (I2C
compatible) microprocessor bus driving multiple peripherals.
T wo inputs serial data (SDAT A) and serial clock (SCLOCK)
carry information between any device connected to the bus.
Each slave device is recognized by a unique address. T he
ADV7175 and ADV7176 each have four possible slave ad-
dresses for both read and write operations. T hese are unique
addresses for each device and are illustrated in Figure 26 and
Figure 27. T he LSB sets either a read or write operation.
Logic Level “1” corresponds to a read operation while Logic
Level “0” corresponds to a write operation. A1 is set by setting
the ALSB pin of the ADV7175/ADV7176 to Logic Level “0” or
Logic Level “1.”
T he ADV7175/ADV7176 acts as a standard slave device on the
bus. T he data on the SDAT A pin is 8 bits long supporting the
7-bit addresses plus the R/W bit. T he ADV7175 has 33 sub-
addresses and the ADV7176 has 19 subaddresses to enable ac-
cess to the internal registers. It, therefore, interprets the first
byte as the device address and the second byte as the starting
subaddress. T he subaddresses auto increment allowing data to
be written to or from the starting subaddress. A data transfer is
always terminated by a stop condition. T he user can also access
any unique subaddress register on a one by one basis without
having to update all the registers. T here is one exception. T he
Subcarrier Frequency Registers should be updated in sequence,
starting with Subcarrier Frequency Register 0. T he auto incre-
ment function should be then used to increment and access
subcarrier frequency registers 1, 2 and 3. T he subcarrier fre-
quency registers should not be accessed independently.
1
1
0
1
0
1
A1
X
ADDRESS
CONTROL
SET UP BY
ALSB
READ/WRITE
CONTROL
Stop and start conditions can be detected at any stage during
the data transfer. If these conditions are asserted out of se-
quence with normal read and write operations, then these cause
an immediate jump to the idle condition. During a given
SCLOCK high period the user should only issue one start con-
dition, one stop condition or a single stop condition followed by
a single start condition. If an invalid subaddress is issued by the
user, the ADV7175/ADV7176 will not issue an acknowledge
and will return to the idle condition. If in auto-increment
mode, the user exceeds the highest subaddress then the follow-
ing action will be taken:
0
1
WRITE
READ
Fig 26. ADV7175 Slave Address
0
1
0
1
0
1
A1
X
ADDRESS
CONTROL
SET UP BY
ALSB
READ/WRITE
CONTROL
1. In Read Mode the highest subaddress register contents will
continue to be output until the master device issues a no-ac-
knowledge. This indicates the end of a read. A no-acknowledge
condition is where the SDAT A line is not pulled low on the
ninth pulse.
0
1
WRITE
READ
Fig 27. ADV7176 Slave Address
T o control the various devices on the bus the following protocol
must be followed. First the master initiates a data transfer by es-
tablishing a start condition, defined by a high to low transition
on SDAT A while SCLOCK remains high. T his indicates that
an address/data stream will follow. All peripherals respond to
the start condition and shift the next eight bits (7-bit address +
R/W bit). T he bits transferred from MSB down to LSB. T he
peripheral that recognizes the transmitted address responds by
pulling the data line low during the ninth clock pulse. T his is
known as an acknowledge bit. All other devices withdraw from
the bus at this point and maintain an idle condition. T he idle
condition is where the device monitors the SDATA and SCLOCK
lines waiting for the Start condition and the correct transmitted
address. T he R/W bit determines the direction of the data. A
Logic “0” on the LSB of the first byte means that the master
2. In Write Mode, the data for the invalid byte will be not be
loaded into any subaddress register, a no-acknowledge will
be issued by the ADV7175/ADV7176 and the part will re-
turn to the idle condition.
Figure 28 illustrates an example of data transfer for a read se-
quence and the start and stop conditions.
SDATA
SCLOCK
8
9
S
1-7
8
1-7
9
1-7
DATA
8
9
P
START ADDR R/W ACK
ACK
STOP
SUBADDRESS
ACK
Figure 28. Bus Data Transfer
Figure 29 shows bus write and read sequences.
WRITE
SEQUENCE
S
S
A(S)
LSB = 0
A(S)
SLAVE ADDR
SUB ADDR
DATA
A(S)
A(S)
DATA
A(S)
P
LSB = 1
READ
SEQUENCE
S
A(S)
SLAVE ADDR
SUB ADDR A(S)
SLAVE ADDR
DATA
A(M)
DATA
A(M ) P
A(S) = NO-ACKNOWLEDGE BY SLAVE
A(M) = NO-ACKNOWLEDGE BY MASTER
A(S) = ACKNOWLEDGE BY SLAVE
A(M) = ACKNOWLEDGE BY MASTER
S = START BIT
P = STOP BIT
Figure 29. Write and Read Sequences
–16–
REV. A
ADV7175/ADV7176
SR1
SR7
SR6
SR5
SR4
SR3
SR2
SR0
SUBADDRESS REGISTER
SR7–SR5
(000)
SR4 SR3 SR2 SR1 SR0
ZERO SHOULD
BE WRITTEN TO
THESE BITS
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
•
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
•
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
•
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
•
MODE REGISTER 0
MODE REGISTER 1
SUB CARRIER FREQ REGISTER 0
SUB CARRIER FREQ REGISTER 1
SUB CARRIER FREQ REGISTER 2
SUB CARRIER FREQ REGISTER 3
SUB CARRIER PHASE REGISTER
TIMING MODE REGISTER 0
CLOSED CAPTIONING EXTENDED DATA – BYTE 0
CLOSED CAPTIONING EXTENDED DATA – BYTE 1
CLOSED CAPTIONING DATA – BYTE 0
CLOSED CAPTIONING DATA – BYTE 1
TIMING MODE REGISTER 1
MODE REGISTER 2
NTSC PEDESTAL CONTROL REG 0 (FIELD 1/3)
NTSC PEDESTAL CONTROL REG 1 (FIELD 1/3)
NTSC PEDESTAL CONTROL REG 2 (FIELD 2/4)
NTSC PEDESTAL CONTROL REG 3 (FIELD 2/4)
MODE REGISTER 3
MACROVISION REGISTERS (ADV7175 ONLY)
•
•
"
"
"
"
"
"
•
•
•
•
1
1
1
1
1
MACROVISION REGISTERS (ADV7175 ONLY)
Figure 30. Subaddress Register
REGISTER ACCESSES
Subaddr ess Register (SR7–SR0)
T he MPU can write to or read from all of the registers of the
ADV7175/ADV7176 except the subaddress register which is a
write only register. T he subaddress register determines which
register the next read or write operation accesses. All communi-
cations with the part through the bus start with an access to the
subaddress register. T hen a read/write operation is performed
from/to the target address which then increments to the next
address until a stop command on the bus is performed.
T he communications register is an eight bit write-only register.
After the part has been accessed over the bus and a read/write
operation is selected, the subaddress set up. T he subaddress
register determines to/from which register the operation takes
place.
Figure 30 shows the various operations under the control of the
subaddress register. Zero should always be written to SR7–
SR5.
REGISTER P RO GRAMMING
Register Select (SR4–SR0):
T hese bits are setup to point to the required starting address.
T he following section describes each register, including
subaddress register, mode registers, subcarrier frequency regis-
ters, subcarrier phase register, timing registers, closed captioning
extended data registers, closed captioning data registers and
NT SC pedestal control registers in terms of its configuration.
MO D E REGISTER 0 MR0 (MR07–MR00)
(Addr ess (SR4–SR0) = 00H )
Mode Register 0 is a 8-bit wide register.
Figure 31 shows the various operations under the control of
Mode Register 0. This register can be read from as well written to.
MR06
MR05
MR04
MR03
MR02
MR01
MR00
MR07
OUTPUT SELECT
MR06
FILTER SELECT
MR04 MR03
OUTPUT VIDEO
STANDARD SELECTION
MR01
MR00
0
1
YC OUTPUT
RGB/YUV OUTPUT
0
0
1
1
0
1
0
1
LOW PASS FILTER (A)
NOTCH FILTER
EXTENDED MODE
LOW PASS FILTER (B)
0
0
1
1
0
1
0
1
NTSC
PAL (B, D, G, H, I)
PAL (M)
RESERVED
RGB SYNC
MR07
(0)
PEDESTAL CONTROL
MR02
MR05
ZERO SHOULD
BE WRITTEN TO
THIS BIT
0
1
DISABLE
ENABLE
0
1
PEDESTAL OFF
PEDESTAL ON
Figure 31. Mode Register 0
–17–
REV. A
ADV7175/ADV7176
MO D E REGISTER 0 (MR07–MR00) BIT D ESCRIP TIO N
Encode Mode Contr ol (MR01–MR00):
MO D E REGISTER 1 MR1 (MR17–MR10)
(Addr ess (SR4–SR0) = 01H )
T hese bits are used to set up the encode mode. T he ADV7175/
ADV7176 can be set up to output NT SC, PAL (B, D, G, H, I),
PAL (M) and PAL (N) standard video.
Mode Register 1 is a 8-bit wide register.
Figure 32 shows the various operations under the control of Mode
Register 1. T his register can be read from as well written to.
P edestal Contr ol (MR02)
MO D E REGISTER 1 (MR17–MR10) BIT D ESCRIP TIO N
Inter laced Mode Contr ol (MR10):
T his bit is used to setup the output to interlaced or non-inter-
laced mode. T his mode is only relevant when the part is in
composite video mode.
T his bit specifies whether a pedestal is to be generated on the
NT SC composite video signal. T his bit is invalid if the
ADV7175/ADV7176 is configured in PAL mode.
Lum inance Filter Contr ol (MR04–MR03)
T hese bits are used for selecting between a filter for the lumi-
nance signal. T hese filters automatically are set to the cutoff fre-
quency for the low-pass filters and the subcarrier frequency for
the notch filter. T he extended mode filter is a 5.5 MHz low-pass
filter. T he filters are illustrated in Figures 3 to 11.
Closed Captioning Field Contr ol (MR12–MR11)
T hese bits control the field that close captioning data is displayed
on close captioning information can be displayed on an odd field,
even field or both fields.
D AC Contr ol (MR16–MR13)
RGB Sync (MR05)
T his bit is used to set up the RGB outputs with the sync infor-
mation encoded.
T hese bits can be used to power down the DACs. T his can be
used to reduce the power consumption of the ADV7175/ADV7176
if any of the DACs are not required in the application.
O utput Contr ol (MR06)
Color Bar Contr ol (MR17)
T his bit specifies if the part is in composite video or RGB/YUV
mode. Please note that in RGB/YUV mode the main composite
signal is still available.
T his bit can be used to generate and output an internal color
bar. T he color bar configuration is 75/75/75/7.5 for NT SC and
100/0/75/0 for PAL.
MR17
MR16
MR15
MR14
MR13
MR12
MR11
MR10
COMPOSITE DAC
CONTROL
GREEN/LUMA
DAC CONTROL
CLOSED CAPTIONING
FIELD SELECTION
MR16
MR14
MR12
MR11
0
1
NORMAL
POWER DOWN
0
1
NORMAL
POWER DOWN
0
0
1
1
0
1
0
1
NO DATA OUT
ODD FIELD ONLY
EVEN FIELD ONLY
DATA OUT
(BOTH FIELDS)
COLOR BAR
CONTROL
BLUE/COMPOSITE
DAC CONTROL
RED/CHROMA
DAC CONTROL
INTERLACE
CONTROL
MR15
MR13
MR10
MR17
0
1
DISABLE
ENABLE
0
1
INTERLACED
NON-INTERLACED
0
1
NORMAL
POWER DOWN
0
1
NORMAL
POWER DOWN
Figure 32. Mode Register 1
–18–
REV. A
ADV7175/ADV7176
SUBCARRIER FREQUENCY REGISTERS 3–0 (FSC3–FSC0)
(Addr ess (SR4–SR0) = 05H –02H )
TIMING REGISTER 0 (TR07–TR00)
(Addr ess (SR4-SR0) = 07H )
T hese 8-bit wide registers are used to set up the subcarrier fre-
quency. T he value of these registers are calculated by using the
following equation:
T iming Register 0 is a 8-bit wide register.
Figure 34 shows the various operations under the control of
T iming Register 0. T his register can be read from as well
written to.
232 –1
FCLK
*FSCF
Subcarrier Frequency Register =
TIMING REGISTER 0 (TR07–TR00)
BIT D ESCRIP TIO N
Master /Slave Contr ol (TR00)
T his bit controls whether the ADV7175/ADV7176 is in master
or slave mode.
i.e.: NTSC Mode, FCLK = 27 MHz, FSCF = 3.5796 MHz
232 –1
27 ×106
Subcarrier Frequency Register =
* 3.579545 ×106
Subcarrier Frequency Register = 21F07C16 HEX
Figure 33 shows how the frequency is set up by the 4 registers.
Tim ing Mode Contr ol (TR02–TR01)
T hese bits control the timing mode of the ADV7175/ADV7176
T hese modes are described in the T iming and Control section
of the data sheet.
SUBCARRIER
FSC31 FSC30 FSC29 FSC28 FSC27 FSC26 FSC25 FSC24
FREQUENCY
REG 0
BLANK Contr ol (TR03)
T his bit controls whether the BLANK input is used when the
part is in slave mode.
SUBCARRIER
FREQUENCY
REG 1
FSC23 FSC22 FSC21 FSC20 FSC19 FSC18 FSC17 FSC16
FSC15 FSC14 FSC13 FSC12 FSC11 FSC10 FSC9 FSC8
SUBCARRIER
FREQUENCY
REG 2
Lum a D elay Contr ol (TR05–TR04)
T hese bits control the addition of a luminance delay. Each bit
represents a delay of 74 ns.
SUBCARRIER
FREQUENCY
REG 3
FSC7 FSC6 FSC5 FSC4 FSC3 FSC2 FSC1 FSC0
P ixel P or t Select (TR06)
T his bit is used to set the pixel port to accept 8-bit or 16-bit
data. If an 8-bit input is selected the data will be set up on
Pins P7–P0.
Figure 33. Subcarrier Frequency Register
SUBCARRIER P H ASE REGISTER (FP 7–FP 0):
(Addr ess (SR4–SR0) = 06H )
Tim ing Register Reset (TR07)
T his 8-bit wide register is used to set up the subcarrier phase.
Each bit represents 1.41°.
T oggling T R07 from low to high and low again resets the inter-
nal timing counters. T his bit should be toggled after setting up a
new timing mode.
TR01
TR07
TR06
TR05
TR04
TR03
TR02
TR00
BLACK INPUT
CONTROL
TIMING
REGISTER RESET
MASTER/SLAVE
CONTROL
TR03
TR00
TR07
0
1
ENABLE
DISABLE
0
1
SLAVE TIMING
MASTER TIMING
PIXEL PORT
CONTROL
TIMING MODE
SELECTION
LUMA DELAY
TR05 TR04
TR06
TR02 TR01
0
0
1
1
0
1
0
1
0ns DELAY
0
8-BIT
0
0
1
1
0
1
0
1
MODE 0
74ns DELAY
148ns DELAY
222ns DELAY
1
16-BIT
MODE 1
MODE 2
MODE 3
Figure 34. Tim ing Register 0
–19–
REV. A
ADV7175/ADV7176
HSYNC to VSYNC/FIELD D elay Contr ol (TR13–TR12)
T hese bits adjust the position of the HSYNC output relative to
the FIELD/VSYNC output.
CLO SED CAP TIO NING EXTEND ED D ATA REGISTERS
1–0 (CED 15–CED 00)
(Addr ess (SR4–SR0) = 09–08H )
T hese 8-bit wide registers are used to set up the closed
captioning extended data bytes. Figure 35 shows how the high
and low bytes are set up in the registers.
HSYNC to FIELD D elay Contr ol (TR15–TR14)
When the ADV7175/ADV7176 is in T iming Mode 1, these bits
adjust the position of the HSYNC output relative to the FIELD
output rising edge.
CED15 CED14 CED13 CED12 CED11 CED10 CED9 CED8
CED7 CED6 CED5 CED4 CED3 CED2 CED1 CED0
BYTE 1
VSYNC Width (TR15–TR14)
When the ADV7175/ADV7176 is in T iming Mode 2, these bits
adjust the VSYNC pulse width.
BYTE 0
HSYNC to P ixel D ata Adjust (TR17–TR16)
T his enables the HSYNC to be adjusted with respect to the
pixel data. T his allows the Cr and Cb components to be
swapped. T his adjustment is available in both master and slave
timing modes.
Figure 35. Closed Captioning Extended Data Register
CLO SED CAP TIO NING D ATA REGISTERS 1–0
(CCD 15–CCD 00)
(Subaddr ess (SR4–SR0) = 0B–0AH )
T hese 8-bit wide registers are used to set up the closed
captioning data bytes. Figure 36 shows how the high and low
bytes are set up in the registers.
MO D E REGISTER 2 MR2 (MR27–MR20)
(Addr ess (SR4-SR0) = 0D H )
Mode Register 2 is an 8-bit wide register.
CCD15 CCD14 CCD13 CCD12 CCD11 CCD10 CCD9 CCD8
CCD7 CCD6 CCD5 CCD4 CCD3 CCD2 CCD1 CCD0
BYTE 1
Figure 38 shows the various operations under the control of
Mode Register 2. This register can be read from as well written to.
BYTE 0
MO D E REGISTER 2 (MR27–MR20) BIT D ESCRIP TIO N
Squar e P ixel Mode Contr ol (MR20)
Figure 36. Closed Captioning Data Register
T his bit is used to setup square pixel mode. T his is available in
slave mode only. For NT SC, a 24.54 MHz clock must be sup-
plied. For PAL, a 29.5 MHz clock must be supplied.
TIMING REGISTER 1 (TR17–TR10)
(Addr ess (SR4–SR0) = 0CH )
T iming Register 1 is an 8-bit wide register.
Genlock Contr ol (MR22–MR21)
T hese bits control the genlock feature of the ADV7175/
ADV7176 Setting MR21 to a Logic “1” configures the
SCRESET /RT C pin as an input. Setting MR22 to logic level
“0” configures the SCRESET /RT C pin as a subcarrier reset in-
put. T herefore, the subcarrier will reset to Field 0 following a
low to high transition on the SCRESET /RT C pin. Setting
MR22 to Logic Level “1” configures the SCRESET /RT C pin as
a real time control input.
Figure 37 shows the various operations under the control of
T iming Register 1. T his register can be read from as well
written to. T his register can be used to adjust the width and
position of the master mode timing signals.
TIMING REGISTER 1 (TR17–TR10) BIT D ESCRIP TIO N
HSYNC Width (TR11–TR10)
T hese bits adjust the HSYNC pulse width.
TR11
TR17
TR16
TR15
TR14
TR13
TR12
TR10
HSYNC WIDTH
HSYNC TO PIXEL
DATA ADJUSTMENT
HSYNC TO FIELD
RISING EDGE DELAY
(MODE 1 ONLY)
HSYNC TO
FIELD/VSYNC DELAY
T
TR11 TR10
a
TR17 TR16
TR13 TR12
0
0
1
1
0
1
0
1
1 x T
4 x T
PCLK
PCLK
T
TR15 TR14
c
0
0
1
1
0
1
0
1
0 x T
1 x T
2 x T
3 x T
0
0
1
1
0
1
0
1
1 x T
3 x T
PCLK
PCLK
PCLK
PCLK
PCLK
PCLK
x
x
0
1
T
T
16 x T
PCLK
b
b
+ 32µs
128 x T
PCLK
16 x T
64 x T
PCLK
PCLK
VSYNC WIDTH
(MODE 2 ONLY)
TR15 TR14
0
0
1
1
0
1
0
1
1 x T
4 x T
PCLK
PCLK
16 x T
64 x T
PCLK
PCLK
TIMING MODE 1 (MASTER/PAL)
LINE 1
LINE 313
LINE 314
T
a
HSYNC
T
c
T
b
FIELD/VSYNC
Figure 37. Tim ing Register 1
–20–
REV. A
ADV7175/ADV7176
MR27
MR26
MR25
MR24
MR23
MR22
MR21
MR20
CHROMINANCE
CONTROL
RGB/YUV
CONTROL
GENLOCK SELECTION
MR22 MR21
MR24
MR26
x
0
0
1
DISABLE GENLOCK
ENABLE SUBCARRIER
RESET PIN
0
1
ENABLE COLOR
DISABLE COLOR
0
1
RGB OUTPUT
YUV OUTPUT
1
1
ENABLE RTC PIN
LOWER POWER
MODE
BURST
CONTROL
CCIR624/CCIR601
CONTROL
SQUARE PIXEL
CONTROL
MR27
MR25
MR23
MR20
0
1
DISABLE
ENABLE
0
1
ENABLE BURST
DISABLE BURST
0
1
DISABLE
ENABLE
0
1
CCIR624 OUTPUT
CCIR601 OUTPUT
Figure 38. Mode Register 2
LINE 17 LINE 16 LINE 15 LINE 14 LINE 13 LINE 12 LINE 11 LINE 10
PCO7 PCO6 PCO5 PCO4 PCO3 PCO2 PCO1 PCO0
CCIR624/CCIR601 Contr ol (MR23)
T his bit switches the video output between CCIR624 and
CCIR601 video standard.
FIELD 1/3
LINE 25 LINE 24 LINE 23 LINE 22 LINE 21 LINE 20 LINE 19 LINE 18
PCO15 PCO14 PCO13 PCO12 PCO11 PCO10 PCO9 PCO8
FIELD 1/3
Chr om inance Contr ol (MR24)
T his bit enables the color information to be switched on and off
the video output.
LINE 17 LINE 16 LINE 15 LINE 14 LINE 13 LINE 12 LINE 11 LINE 10
PCE7 PCE6 PCE5 PCE4 PCE3 PCE2 PCE1 PCE0
LINE 25 LINE 24 LINE 23 LINE 22 LINE 21 LINE 20 LINE 19 LINE 18
FIELD 2/4
FIELD 2/4
Bur st Contr ol (MR25)
T his bit enables the burst information to be switched on and off
the video output.
PCE15 PCE14 PCE13 PCE12 PCE11 PCE10 PCE9
PCE8
RGB/YUV Contr ol (MR26)
T his bit enables the output from the RGB DACs to be set to
YUV output video standard. Bit MR06 of Mode Register 0
must be set to Logic Level “1” before MR26 is set.
Figure 39. Pedestal Control Registers
MO D E REGISTER 3 MR3 (MR37–30)
(Addr ess (SR4–SR0) = 12H )
Mode Register 3 is an 8-bit wide register.
Lower P ower Contr ol (MR27)
T his bit enables the lower power mode of the ADV7175/
ADV7176.
Figure 34 shows the various operations under the control of
Mode Register 3. Bits MR36–MR30 are reserved and Logic “0”
should be written to them.
NTSC P ED ESTAL CO NTRO L REGISTERS 3–0
(P CE15–0, P CO 15–0)
(Subaddr ess (SR4–SR0) = 11-0EH )
MO D E REGISTER 3 (MR37–MR30) D ESCRIP TIO N
D AC Switching Contr ol (MR37)
T his bit is used to switch the luminance signal onto the compos-
ite DAC. Figure 40 illustrates the DAC outputs and how they
switch when MR 37 is set to Logic “1”.
T hese 8-bit wide registers are used to set up the NT SC pedestal
on a line by line basis in the vertical blanking interval for both
odd and even fields. Figure 39 shows the four control registers.
A Logic “1” in any of the bits of these registers has the effect of
turning the pedestal off on the equivalent line.
MR37
MR36
MR35
MR34
MR33
MR32
MR31
MR30
MR36-MR30
(RESERVED)
ZERO SHOULD BE
WRITTEN TO THESE BITS
DAC OUTPUT
SWITCHING
DAC A
DAC B
DAC C
DAC D
MR37
0
1
COMPOSITE
BLUE/COMP/U RED/CHROMA/V GREEN/LUMA/Y
GREEN/LUMA/Y BLUE/COMP/U RED/CHROMA/V COMPOSITE
Figure 40. Mode Register 3
–21–
REV. A
ADV7175/ADV7176
AP P END IX 1
BO ARD D ESIGN AND LAYO UT CO NSID ERATIO NS
operation, to reduce the lead inductance. Best performance is
obtained with 0.1 µF ceramic capacitor decoupling. Each group
of VAA pins on the ADV7175/ADV7176 must have at least one
0.1 µF decoupling capacitor to GND. T hese capacitors should
be placed as close as possible to the device.
T he ADV7175/ADV7176 is a highly integrated circuit contain-
ing both precision analog and high speed digital circuitry. It has
been designed to minimize interference effects on the integrity
of the analog circuitry by the high speed digital circuitry. It is
imperative that these same design and layout techniques be ap-
plied to the system level design such that high speed, accurate
performance is achieved. T he “Recommended Analog Circuit
Layout” shows the analog interface between the device and
monitor.
It is important to note that while the ADV7175/ADV7176
contains circuitry to reject power supply noise, this rejection
decreases with frequency. If a high frequency switching power
supply is used, the designer should pay close attention to reduc-
ing power supply noise and consider using a three terminal volt-
age regulator for supplying power to the analog power plane.
T he layout should be optimized for lowest noise on the
ADV7175/ADV7176 power and ground lines by shielding the
digital inputs and providing good decoupling. T he lead length
between groups of VAA and GND pins should by minimized so
as to minimize inductive ringing.
D igital Signal Inter connect
T he digital inputs to the ADV7175/ADV7176 should be iso-
lated as much as possible from the analog outputs and other
analog circuitry. Also, these input signals should not overlay
the analog power plane.
Gr ound P lanes
T he ground plane should encompass all ADV7175/ADV7176
ground pins, voltage reference circuitry, power supply bypass
circuitry for the ADV7175/ADV7176, the analog output traces,
and all the digital signal traces leading up to the ADV7175/
ADV7176. T he ground plane is the board’s common ground
plane.
Due to the high clock rates involved, long clock lines to the
ADV7175/ADV7176 should be avoided to reduce noise pickup.
Any active termination resistors for the digital inputs should be
connected to the regular PCB power plane (VCC), and not the
analog power plane.
P ower P lanes
Analog Signal Inter connect
T he ADV7175/ADV7176 and any associated analog circuitry
should have its own power plane, referred to as the analog
power plane (VAA). T his power plane should be connected to
the regular PCB power plane (VCC) at a single point through a
ferrite bead. T his bead should be located within three inches of
the ADV7175/ADV7176.
T he ADV7175/ADV7176 should be located as close as possible
to the output connectors to minimize noise pickup and reflec-
tions due to impedance mismatch.
T he video output signals should overlay the ground plane, and
not the analog power plane, to maximize the high frequency
power supply rejection.
T he PCB power plane should provide power to all digital logic
on the PC board, and the analog power plane should provide
power to all ADV7175/ADV7176 power pins and voltage refer-
ence circuitry.
Digital inputs, especially pixel data inputs and clocking signals
should never overlay any of the analog signal circuitry and
should be kept as far away as possible.
For best performance, the outputs should each have a 75 Ω
load resistor connected to GND. T hese resistors should be
placed as close as possible to the ADV7175/ADV7176 so as to
minimize reflections.
Plane-to-plane noise coupling can be reduced by ensuring that
portions of the regular PCB power and ground planes do not
overlay portions of the analog power plane, unless they can be
arranged such that the plane-to-plane noise is common mode.
T he ADV7175/ADV7176 should have no inputs left floating.
Any inputs that are not required should be tied to ground.
Supply D ecoupling
For optimum performance, bypass capacitors should be in-
stalled using the shortest leads possible, consistent with reliable
–22–
REV. A
ADV7175/ADV7176
POWER SUPPLY DECOUPLING
FOR EACH POWER SUPPLY GROUP
0.1µF
0.01µF
L1
(FERRITE BEAD)
+5V (V
)
AA
+5V (V
GND
)
+5V (V
AA
)
+5V (V
AA
)
CC
1, 11, 20, 28, 30, 37
33µF
10µF
0.1µF
0.1µF
V
AA
COMP
25
33
GREEN/
LUMA/ 27
Y
V
REF
75Ω
75Ω
75Ω
75Ω
ADV7175
ADV7176
38–42,
2–9, 12–14
RED/
CHROMA/
26
31
P15–P0
S VIDEO
V
BLUE/
COMPOSITE/
U
“UNUSED
INPUTS
35
15
16
17
SCRESET/RTC
HSYNC
SHOULD BE
GROUNDED”
FIELD/VSYNC
BLANK
32
23
COMPOSITE
SCLOCK
+5V (V
CC
)
+5V (V )
CC
5kΩ
5kΩ
22
44
RESET
MPU BUS
SDATA 24
34
27MHz CLOCK
(SAME CLOCK AS USED BY
MPEG2 DECODER)
CLOCK
R
SET
+5V (V
AA
)
ALSB
18
GND
150Ω
10kΩ
10, 19, 21
29, 36, 43
Figure 41. Recom m ended Analog Circuit Layout
T he circuit below can be used to generate a 13.5 MHz waveform using the 27 MHz clock and the HSYNC pulse. T his waveform is
guaranteed to produce the 13.5 MHz clock in synchronization with the 27 MHz clock. T his 13.5 MHz clock can be used if
13.5 MHz clock is required by the MPEG decoder. T his will guarantee that the Cr and Cb pixel information is input to the
ADV7175/ADV7176 in the correct sequence.
D
Q
13.5MHz
D
Q
CLOCK
CK
CK
HSYNC
Figure 42. Circuit to Generate 13.5 MHz
–23–
REV. A
ADV7175/ADV7176
AP P END IX 2
CLO SED CAP TIO NING
T he ADV7175/ADV7176 supports closed captioning conforming to the standard television synchronizing waveform for color trans-
mission. Closed captioning is transmitted during the blanked active line time of line 21 of the odd fields.
Closed captioning consists of a 7-cycle sinusoidal burst that is frequency and phase locked to the caption data. After the clock run in
signal, the blanking level is held for two data bits and is followed by a Logic Level “1” start bit. Sixteen bits of data follow the start
bit. T hese consist of two 8-bit bytes. T he data for these bytes is stored in closed captioning data registers 0 and 1.
T he ADV7175/ADV7176 also supports the extended closed captioning operation which is active during even fields and is encoded
on scan line 284. T he data for this operation is stored in closed captioning extended data registers 0 and 1.
All clock run-in signals and timing to support closed captioning on lines 21 and 282 are generated automatically by the ADV7175/
ADV7176. All pixels inputs are ignored during lines 21 and 282.
FCC Code of Federal Regulations (CFR) 47 section 15.119 and EIA208 describe the closed captioning information for lines
21 and 284.
13.407µs
P
A
R
I
T
Y
S
T
A
R
T
P
A
R
I
T
Y
D6–D0
D6–D0
50 IRE
40 IRE
REFERENCE COLOR BURST
(9 CYCLES)
FREQUENCY = F = 3.579545MHz
SC
AMPLITUDE = 40 IRE
10.003µs
17.379µs
33.764µs
Figure 43. Closed Captioning Waveform (NTSC)
–24–
REV. A
ADV7175/ADV7176
AP P END IX 3
NTSC WAVEFO RMS (With P edestal)
1268.1mV
130.8 IRE
100 IRE
PEAK COMPOSITE
1048.4mV
REF WHITE
714.2mV
387.6mV
334.2mV
7.5 IRE
0 IRE
BLACK LEVEL
BLANK LEVEL
48.3mV
SYNC LEVEL
–40 IRE
Figure 44. NTSC Com posite Video Levels
1048.4mV
100 IRE
REF WHITE
714.2mV
387.6mV
334.2mV
7.5 IRE
0 IRE
BLACK LEVEL
BLANK LEVEL
48.3mV
SYNC LEVEL
–40 IRE
Figure 45. NTSC Lum a Video Levels
PEAK CHROMA
1067.7mV
835mV (pk-pk)
286mV (pk-pk)
BLANK/BLACK LEVEL
PEAK CHROMA
650mV
232.2mV
0mV
Figure 46. NTSC Chrom a Video Levels
100 IRE
1052.2mV
REF WHITE
720.8mV
387.5mV
331.4mV
7.5 IRE
0 IRE
BLACK LEVEL
BLANK LEVEL
45.9mV
SYNC LEVEL
–40 IRE
Figure 47. NTSC RGB Video Levels
–25–
REV. A
ADV7175/ADV7176
NTSC WAVEFO RMS (Without P edestal)
1289.8mV
1052.2mV
130.8 IRE
100 IRE
PEAK COMPOSITE
REF WHITE
714.2mV
BLANK/BLACK LEVEL 338mV
0 IRE
52.1mV
SYNC LEVEL
–40 IRE
Figure 48. NTSC Com posite Video Levels
1052.2mV
100 IRE
REF WHITE
714.2mV
338mV
52.1mV
BLANK /BLACK LEVEL
SYNC LEVEL
0 IRE
–40 IRE
Figure 49. NTSC Lum a Video Levels
PEAK CHROMA
1101.6mV
650mV
903.2mV (pk-pk)
307mV (pk-pk)
BLANK/BLACK LEVEL
PEAK CHROMA
198.4mV
0mV
Figure 50. NTSC Chrom a Video Levels
100 IRE
1052.2mV
REF WHITE
715.7mV
BLANK/BLACK LEVEL
SYNC LEVEL
336.5mV
51mV
0 IRE
–40 IRE
Figure 51. NTSC RGB Video Levels
–26–
REV. A
ADV7175/ADV7176
P AL WAVEFO RMS
PEAK COMPOSITE
1284.2mV
1047.1mV
REF WHITE
696.4mV
BLANK/BLACK LEVEL
SYNC LEVEL
350.7mV
50.8mV
Figure 52. PAL Com posite Video Levels
1047mV
REF WHITE
696.4mV
350.7mV
50.8mV
BLANK/BLACK LEVEL
SYNC LEVEL
Figure 53. PAL Lum a Video Levels
PEAK CHROMA
1092.5mV
885mV (pk-pk)
300mV (pk-pk)
BLANK/BLACK LEVEL
650mV
PEAK CHROMA
207.5mV
0mV
Figure 54. PAL Chrom a Video Levels
1050.2mV
REF WHITE
698.4mV
351.8mV
51mV
BLANK /BLACK LEVEL
SYNC LEVEL
Figure 55. PAL RGB Video Levels
–27–
REV. A
ADV7175/ADV7176
AP P END IX 4
REGISTER VALUES
T he ADV7175/ADV7176 registers can be set depending on the
user standard required.
P AL (M)
Mode Register 0
Mode Register 1
06 Hex
00 Hex
A3 Hex
EF Hex
E6 Hex
21 Hex
00 Hex
08 Hex
00 Hex
00 Hex
00 Hex
00 Hex
00 Hex
00 Hex
00 Hex
00 Hex
00 Hex
00 Hex
00 Hex
T he following examples give the various register formats for
several video standards.
Subcarrier Frequency Register 0
Subcarrier Frequency Register 1
Subcarrier Frequency Register 2
Subcarrier Frequency Register 3
Subcarrier Phase Register
T iming Register 0
Closed Captioning Ext Register 0
Closed Captioning Ext Register 1
Closed Captioning Register 0
Closed Captioning Register 1
T iming Register 1
In each case the output is set to composite o/p with all DACs
powered up and with the BLANK input control disabled. Ad-
ditionally, the burst and color information are enabled on the
output and the internal color bar generator is switched off. In
the examples shown the timing mode is set to Mode 0 in slave
format. T R02–T R00 of the timing register 0 control the timing
modes. For a detailed explanation of each bit in the command
registers, please turn to the register programming section of the
data sheet. T R07 should be toggled after setting up a new tim-
ing mode. T iming Register 1 provides additional control over
the position and duration of the timing signals. In the examples
this register is programmed in default mode.
Mode Register 2
Pedestal Control Register 0
Pedestal Control Register 1
Pedestal Control Register 2
Pedestal Control Register 3
Mode Register 3
NTSC
Mode Register 0
Mode Register 1
04 Hex
00 Hex
16 Hex
7C Hex
F0 Hex
21 Hex
00 Hex
08 Hex
00 Hex
00 Hex
00 Hex
00 Hex
00 Hex
00 Hex
00 Hex
00 Hex
00 Hex
00 Hex
00 Hex
Subcarrier Frequency Register 0
Subcarrier Frequency Register 1
Subcarrier Frequency Register 2
Subcarrier Frequency Register 3
Subcarrier Phase Register
T iming Register 0
Closed Captioning Ext Register 0
Closed Captioning Ext Register 1
Closed Captioning Register 0
Closed Captioning Register 1
T iming Register 1
P AL (N)
Mode Register 0
Mode Register 1
05 Hex
00 Hex
CB Hex
8A Hex
09 Hex
2A Hex
00 Hex
08 Hex
00 Hex
00 Hex
00 Hex
00 Hex
00 Hex
00 Hex
00 Hex
00 Hex
00 Hex
00 Hex
00 Hex
Subcarrier Frequency Register 0
Subcarrier Frequency Register 1
Subcarrier Frequency Register 2
Subcarrier Frequency Register 3
Subcarrier Phase Register
T iming Register 0
Closed Captioning Ext Register 0
Closed Captioning Ext Register 1
Closed Captioning Register 0
Closed Captioning Register 1
T iming Register 1
Mode Register 2
Pedestal Control Register 0
Pedestal Control Register 1
Pedestal Control Register 2
Pedestal Control Register 3
Mode Register 3
Mode Register 2
Pedestal Control Register 0
Pedestal Control Register 1
Pedestal Control Register 2
Pedestal Control Register 3
Mode Register 3
P AL (B, D , G, H , I)
Mode Register 0
Mode Register 1
01 Hex
00 Hex
CB Hex
8A Hex
09 Hex
2A Hex
00 Hex
08 Hex
00 Hex
00 Hex
00 Hex
00 Hex
00 Hex
00 Hex
00 Hex
00 Hex
00 Hex
00 Hex
00 Hex
Subcarrier Frequency Register 0
Subcarrier Frequency Register 1
Subcarrier Frequency Register 2
Subcarrier Frequency Register 3
Subcarrier Phase Register
T iming Register 0
Closed Captioning Ext Register 0
Closed Captioning Ext Register 1
Closed Captioning Register 0
Closed Captioning Register 1
T iming Register 1
Mode Register 2
Pedestal Control Register 0
Pedestal Control Register 1
Pedestal Control Register 2
Pedestal Control Register 3
Mode Register 3
–28–
REV. A
ADV7175/ADV7176
AP P END IX 5
O UTP UT FILTER
If an output filter is required for the composite output of the ADV7175/ADV7176. T he following filter can be used.
Plots of the filter characteristics can be produced on request.
L
L
L
1µH
2.7µH
0.7µH
IN
OUT
C
C
C
56pF
470pF
330pF
Figure 56. Output Filter
–29–
REV. A
ADV7175/ADV7176
AP P END IX 6
O UTP UT WAVEFO RMS
Figure 57. 100/75% Color Bars NTSC
Figure 58. 100/75% Color Bars NTSC (Chrom inance Only)
–30–
REV. A
ADV7175/ADV7176
Figure 59. 100/75% Color Bars NTSC (Lum inance Only)
Figure 60. 100/75% Color Bars PAL
–31–
REV. A
ADV7175/ADV7176
Figure 61. Differential Phase and Gain Measurem ents (PAL)
Figure 62. Vectorscope Measurem ents (PAL)
–32–
REV. A
ADV7175/ADV7176
Figure 63. Modulated Ram p Measurem ents (PAL)
–33–
REV. A
ADV7175/ADV7176
IND EX
Contents
P age No.
Contents
P age No.
REGIST ER ACCESSES . . . . . . . . . . . . . . . . . . . . . . . . . . 17
REGIST ER PROGRAMMING . . . . . . . . . . . . . . . . . . . . 17
Subaddress Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Mode Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Mode Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Subcarrier Frequency Registers . . . . . . . . . . . . . . . . . . . 19
Subcarrier Phase Register . . . . . . . . . . . . . . . . . . . . . . . . 19
T iming Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Closed Captioning Extended Data Registers 1-0 . . . . . . 20
Closed Captioning Data Registers 1-0 . . . . . . . . . . . . . . 20
T iming Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Mode Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
NT SC Pedestal Control Registers 3-0 . . . . . . . . . . . . . . 21
APPENDIX 1. BOARD DESIGN AND LAYOUT
CONSIDERAT IONS . . . . . . . . . . . . . . . . . . . . . . . . . . 22
APPENDIX 2. CLOSED CAPT IONING . . . . . . . . . . . . 24
APPENDIX 3. VIDEO WAVEFORMS . . . . . . . . . . . . . . 25
APPENDIX 4. REGIST ER VALUES . . . . . . . . . . . . . . . 28
APPENDIX 5. OUT PUT FILT ER . . . . . . . . . . . . . . . . . 29
APPENDIX 6. OUT PUT WAVEFORMS . . . . . . . . . . . . 30
OUT LINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . 35
GENERAL DESCRIPT ION . . . . . . . . . . . . . . . . . . . . . . . .
ADV7175/ADV7176 SPECIFICAT IONS . . . . . . . . . . . . . .
T IMING SPECIFICAT IONS . . . . . . . . . . . . . . . . . . . . . .
1
2
3
ABSOLUT E MAXIMUM RAT INGS . . . . . . . . . . . . . . . . . 4
ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PIN DESCRIPT ION/PIN CONFIGURAT ION . . . . . . . . .
DAT A PAT H DESCRIPT ION . . . . . . . . . . . . . . . . . . . . . .
INT ERNAL FILT ER RESPONSE . . . . . . . . . . . . . . . . . . .
COLOR BAR GENERAT ION . . . . . . . . . . . . . . . . . . . . . .
SQUARE PIXEL MODE . . . . . . . . . . . . . . . . . . . . . . . . . .
COLOR SIGNAL CONT ROL . . . . . . . . . . . . . . . . . . . . . .
BURST SIGNAL CONT ROL . . . . . . . . . . . . . . . . . . . . . .
NT SC PEDEST AL CONT ROL . . . . . . . . . . . . . . . . . . . . .
SUBCARRIER RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . .
REAL T IME CONT ROL . . . . . . . . . . . . . . . . . . . . . . . . . .
PIXEL T IMING DESCRIPT ION . . . . . . . . . . . . . . . . . . .
VIDEO T IMING DESCRIPT ION . . . . . . . . . . . . . . . . . . .
T iming Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
T iming Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
T iming Mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
T iming Mode 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
OUT PUT VIDEO T IMING . . . . . . . . . . . . . . . . . . . . . . . 15
POWER-ON RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
MPU PORT DESCRIPT ION . . . . . . . . . . . . . . . . . . . . . . 16
4
5
6
6
8
8
8
8
8
8
8
8
8
9
–34–
REV. A
ADV7175/ADV7176
O UTLINE D IMENSIO NS
D imensions shown in inches and (mm).
P lastic Quad Flatpack
(S-44)
0.548 (13.925)
0.546 (13.875)
0.096 (2.44)
0.398 (10.11)
MAX
0.390 (9.91)
0.037 (0.94)
0.025 (0.64)
8°
0.8°
33
23
34
22
SEATING
PLANE
TOP VIEW
(PINS DOWN)
4
4
12
1
11
0.040 (1.02)
0.032 (0.81)
0.040 (1.02)
0.032 (0.81)
0.033 (0.84)
0.029 (0.74)
0.016 (0.41)
0.012 (0.30)
0.083 (2.11)
0.077 (1.96)
–35–
REV. A
–36–
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