ADV7181CWBSTZ-REEL [ADI]
10-Bit, Integrated, Multiformat SDTV/HDTV Video Decoder and RGB Graphics Digitizer;
| 型号： | ADV7181CWBSTZ-REEL |
| 厂家： | 
ADI |
| 描述： | 10-Bit, Integrated, Multiformat SDTV/HDTV Video Decoder and RGB Graphics Digitizer 解码器 电视 |
| 文件： | 总96页 (文件大小：872K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Multiformat SDTV Video Decoder
ADV7181B
FEATURES
Differential phase: 0.6° typ
Programmable video controls:
Multiformat video decoder supports NTSC-(M, J, 4.43),
PAL-(B/D/G/H/I/M/N), SECAM
Peak white/hue/brightness/saturation/contrast
Integrated on-chip video timing generator
Free-run mode (generates stable video ouput with no I/P)
Integrates three 54 MHz, 9-bit ADCs
Clocked from a single 27 MHz crystal
Line-locked clock-compatible (LLC)
VBI decode support for close captioning, WSS, CGMS, EDTV,
Gemstar® 1×/2×
Power-down mode
Adaptive Digital Line Length Tracking (ADLLT™), signal
processing, and enhanced FIFO management give mini
TBC functionality
2-wire serial MPU interface (I2C®-compatible)
3.3 V analog, 1.8 V digital core; 3.3 V IO supply
Temperature grade:–40°C to +85°C
5-line adaptive comb filters
Proprietary architecture for locking to weak, noisy, and
unstable video sources such as VCRs and tuners
Subcarrier frequency lock and status information output
80-lead LQFP Pb-free package
Integrated AGC with adaptive peak white mode
Macrovision® copy protection detection
CTI (chroma transient improvement)
DNR (digital noise reduction)
Multiple programmable analog input formats:
CVBS (composite video)
APPLICATIONS
DVD recorders
PC Video
HDD-based PVRs/DVDRs
LCD TVs
Set-top boxes
Security systems
Digital televisions
Portable video devices
Automotive entertainment
AVR receiver
S-Video (Y/C)
YPrPb component (VESA, MII, SMPTE, and BetaCam)
6 analog video input channels
Automatic NTSC/PAL/SECAM identification
Digital output formats (8-bit or16-bit):
ITU-R BT.656 YCrCb 4:2:2 output + HS, VS, and FIELD
0.5 V to 1.6 V analog signal input range
Differential gain: 0.6% typ
GENERAL DESCRIPTION
video signal peak-to-peak range of 0.5 V to 1.6 V. Alternatively,
these can be bypassed for manual settings.
The ADV7181B integrated video decoder automatically detects
and converts a standard analog baseband television signal-
compatible with worldwide standards NTSC, PAL, and SECAM
into 4:2:2 component video data-compatible with 16-/8-bit
CCIR601/CCIR656.
The fixed 54 MHz clocking of the ADCs and datapath for all
modes allows very precise, accurate sampling and digital
filtering. The line-locked clock output allows the output data
rate, timing signals, and output clock signals to be synchronous,
asynchronous, or line locked even with 5ꢀ line length
variation. The output control signals allow glueless interface
connections in almost any application. The ADV7181B modes
are set up over a 2-wire, serial, bidirectional port (I2C-
compatible).
The advanced and highly flexible digital output interface
enables performance video decoding and conversion in line-
locked clock-based systems. This makes the device ideally
suited for a broad range of applications with diverse analog
video characteristics, including tape based sources, broadcast
sources, security/surveillance cameras, and professional
systems.
The ADV7181B is fabricated in a 3.3 V CMOS process. Its
monolithic CMOS construction ensures greater functionality
with lower power dissipation.
The 6 analog input channels accept standard Composite,
S-Video, YPrPb video signals in an extensive number of
combinations. AGC and clamp restore circuitry allow an input
The ADV7181B is packaged in a small 80-lead LQFP Pb-free
package.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.326.8703
www.analog.com
© 2004 Analog Devices, Inc. All rights reserved.
ADV7181B
TABLE OF CONTENTS
Introduction ...................................................................................... 3
Analog Front End......................................................................... 3
Standard Definition Processor ................................................... 3
Functional Block Diagram .............................................................. 4
Specifications..................................................................................... 5
Electrical Characteristics............................................................. 5
Video Specifications..................................................................... 6
Timing Specifications .................................................................. 7
Analog Specifications................................................................... 7
Thermal Specifications ................................................................ 8
Timing Diagrams.......................................................................... 8
Absolute Maximum Ratings............................................................ 9
ESD Caution.................................................................................. 9
Pin Configuration and Function Descriptions........................... 10
Analog Front End ........................................................................... 12
Analog Input Muxing ................................................................ 12
Global Control Registers ............................................................... 14
Power-Save Modes...................................................................... 14
Reset Control .............................................................................. 14
Global Pin Control..................................................................... 15
Global Status Registers................................................................... 17
Identification............................................................................... 17
Status 1 ......................................................................................... 17
Autodetection Result.................................................................. 17
Status 2 ......................................................................................... 17
Status 3 ......................................................................................... 18
Standard Definition Processor (SDP).......................................... 19
SD Luma Path ............................................................................. 19
SD Chroma Path......................................................................... 19
Sync Processing........................................................................... 20
VBI Data Recovery..................................................................... 20
General Setup.............................................................................. 20
Color Controls ............................................................................ 22
Clamp Operation........................................................................ 24
REVISION HISTORY
Luma Filter.................................................................................. 25
Chroma Filter.............................................................................. 28
Gain Operation........................................................................... 29
Chroma Transient Improvement (CTI) .................................. 32
Digital Noise Reduction (DNR)............................................... 33
Comb Filters................................................................................ 34
AV Code Insertion and Controls ............................................. 36
Synchronization Output Signals............................................... 38
Sync Processing .......................................................................... 45
VBI Data Decode ....................................................................... 46
Pixel Port Configuration ............................................................... 58
MPU Port Description................................................................... 59
Register Accesses ........................................................................ 60
Register Programming............................................................... 60
I2C Sequencer.............................................................................. 60
I2C Register Maps ........................................................................... 61
I2C Register Map Details ........................................................... 66
I2C Programming Examples.......................................................... 88
Mode 1 CVBS Input (Composite Video on AIN6)................ 88
Mode 2 S-Video Input (Y on AIN1 and C on AIN4) ............ 88
Mode 3 525i/625i YPrPb Input (Y on AIN1, Pr on AIN3, and
Pb on AIN5)................................................................................ 89
Mode 4 CVBS Tuner Input CVBS PAL on AIN6................... 89
PCB Layout Recommendations.................................................... 90
Analog Interface Inputs............................................................. 90
Power Supply Decoupling ......................................................... 90
PLL ............................................................................................... 90
Digital Outputs (Both Data and Clocks)................................. 90
Digital Inputs .............................................................................. 91
Antialiasing Filters ..................................................................... 91
Typical Circuit Connection........................................................... 92
Outline Dimensions....................................................................... 94
Ordering Guide .......................................................................... 95
7/04—Revision 0: Initial Version
Rev. 0 | Page 2 of 96
ADV7181B
INTRODUCTION
The ADV7181B is a high quality, single chip, multiformat video
decoder that automatically detects and converts PAL, NTSC,
and SECAM standards in the form of composite, S-Video, and
component video into a digital ITU-R BT.656 format.
STANDARD DEFINITION PROCESSOR
The ADV7181B is capable of decoding a large selection of
baseband video signals in composite, S-Video, and component
formats. The video standards supported by the ADV7181B
include PAL B/D/I/G/H, PAL60, PAL M, PAL N, PAL Nc, NTSC
M/J, NTSC 4.43, and SECAM B/D/G/K/L. The ADV7181B can
automatically detect the video standard and process it
accordingly.
The advanced and highly flexible digital output interface enables
performance video decoding and conversion in line-locked
clock based systems. This makes the device ideally suited for a
broad range of applications with diverse analog video charac-
teristics, including tape based sources, broadcast sources,
security/surveillance cameras, and professional systems.
The ADV7181B has a 5-line, superadaptive, 2D comb filter that
gives superior chrominance and luminance separation when
decoding a composite video signal. This highly adaptive filter
automatically adjusts its processing mode according to video
standard and signal quality with no user intervention required.
Video user controls such as brightness, contrast, saturation, and
hue are also available within the ADV7181B.
ANALOG FRONT END
The ADV7181B analog front end comprises three 9-bit ADCs
that digitize the analog video signal before applying it to the
standard definition processor. The analog front end employs
differential channels to each ADC to ensure high performance
in mixed-signal applications.
The ADV7181B implements a patented adaptive digital line-
length tracking (ADLLT) algorithm to track varying video line
lengths from sources such as a VCR. ADLLT enables the
ADV7181B to track and decode poor quality video sources such
as VCRs, noisy sources from tuner outputs, VCD players, and
camcorders. The ADV7181B contains a chroma transient
improvement (CTI) processor that sharpens the edge rate of
chroma transitions, resulting in sharper vertical transitions.
The front end also includes a 6-channel input mux that enables
multiple video signals to be applied to the ADV7181B. Current
and voltage clamps are positioned in front of each ADC to
ensure that the video signal remains within the range of the
converter. Fine clamping of the video signals is performed
downstream by digital fine clamping within the ADV7181B.
The ADCs are configured to run in 4× oversampling mode.
The ADV7181B can process a variety of VBI data services such
as closed captioning (CC), wide screen signaling (WSS), copy
generation management system (CGMS), EDTV, Gemstar
1×/2×, and extended data service (XDS). The ADV7181B is
fully Macrovision certified; detection circuitry enables Type I,
II, and III protection levels to be identified and reported to the
user. The decoder is also fully robust to all Macrovision signal
inputs.
Rev. 0 | Page 3 of 96
ADV7181B
FUNCTIONAL BLOCK DIAGRAM
OUTPUT FORMATTER
Figure 1.
Rev. 0 | Page 4 of 96
ADV7181B
SPECIFICATIONS
Temperature range: TMIN to TMAX, –40°C to +85°C. The min/max specifications are guaranteed over this range.
ELECTRICAL CHARACTERISTICS
At AVDD = 3.15 V to 3.45 V, DVDD = 1.65 V to 2.0 V, DVDDIO = 3.0 V to 3.6 V, PVDD = 1.65 V to 2.0 V (operating temperature range, unless
otherwise noted).
Table 1.
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
STATIC PERFORMANCE
Resolution (Each ADC)
Integral Nonlinearity
Differential Nonlinearity
DIGITAL INPUTS
N
INL
DNL
9
Bits
LSB
LSB
BSL at 54 MHz
BSL at 54 MHz
–0.475/+0.6
–0.25/+0.5
−1.5/+2
–0.7/+2
Input High Voltage
Input Low Voltage
Input Current
VIH
VIL
IIN
2
V
V
µA
µA
pF
0.8
Pin 29
All other pins
–50
–10
+50
+10
10
Input Capacitance
CIN
DIGITAL OUTPUTS
Output High Voltage
Output Low Voltage
High Impedance Leakage Current
Output Capacitance
VOH
VOL
ILEAK
COUT
ISOURCE = 0.4 mA
ISINK = 3.2 mA
2.4
V
V
µA
pF
0.4
10
20
POWER REQUIREMENTS1
Digital Core Power Supply
Digital I/O Power Supply
PLL Power Supply
Analog Power Supply
Digital Core Supply Current
Digital I/O Supply Current
PLL Supply Current
DVDD
DVDDIO
PVDD
AVDD
IDVDD
IDVDDIO
IPVDD
1.65
3.0
1.65
3.15
1.8
3.3
1.8
3.3
80
2
10.5
85
2
V
V
V
V
mA
mA
mA
mA
mA
mA
ms
3.6
2.0
3.45
Analog Supply Current
IAVDD
CVBS input2
YPrPb input3
180
1.5
20
Power-Down Current
Power-Up Time
IPWRDN
tPWRUP
1 Guaranteed by characterization.
2 ADC1 and ADC2 powered down.
3 All three ADCs powered on.
Rev. 0 | Page 5 of 96
ADV7181B
VIDEO SPECIFICATIONS
Guaranteed by characterization. At AVDD = 3.15 V to 3.45 V, DVDD = 1.65 V to 2.0 V, DVDDIO = 3.0 V to 3.6 V, PVDD = 1.65 V to 2.0 V
(operating temperature range, unless otherwise noted).
Table 2.
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
NONLINEAR SPECIFICATIONS
Differential Phase
Differential Gain
Luma Nonlinearity
NOISE SPECIFICATIONS
SNR Unweighted
DP
DG
LNL
CVBS I/P, modulate 5-step
CVBS I/P, modulate 5-step
CVBS I/P, 5-step
0.6
0.6
0.6
0.7
0.7
0.7
°
%
%
Luma ramp
54
58
60
dB
dB
dB
Luma flat field
Analog Front End Crosstalk
LOCK TIME SPECIFICATIONS
Horizontal Lock Range
Vertical Lock Range
–5
40
+5
70
%
Hz
Fsc Subcarrier Lock Range
Color Lock In Time
Sync Depth Range
1.3
60
kHz
Lines
%
20
5
200
200
Color Burst Range
%
Vertical Lock Time
2
100
Fields
Lines
Autodetection Switch Speed
CHROMA SPECIFICATIONS
Hue Accuracy
Color Saturation Accuracy
Color AGC Range
Chroma Amplitude Error
Chroma Phase Error
Chroma Luma Intermodulation
LUMA SPECIFICATIONS
Luma Brightness Accuracy
Luma Contrast Accuracy
HUE
CL_AC
1
1
°
%
%
%
°
5
400
0.5
0.5
0.2
%
CVBS, 1 V I/P
CVBS, 1 V I/P
1
1
%
%
Rev. 0 | Page 6 of 96
ADV7181B
TIMING SPECIFICATIONS
Guaranteed by characterization. At AVDD = 3.15 V to 3.45 V, DVDD = 1.65 V to 2.0 V, DVDDIO = 3.0 V to 3.6 V, PVDD = 1.65 V to 2.0 V
(operating temperature range, unless otherwise noted).
Table 3.
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
SYSTEM CLOCK AND CRYSTAL
Nominal Frequency
Frequency Stability
27.00
MHz
ppm
50
I2C PORT
SCLK Frequency
400
kHz
µs
µs
µs
µs
ns
ns
ns
µs
SCLK Min Pulse Width High
SCLK Min Pulse Width Low
Hold Time (Start Condition)
Setup Time (Start Condition)
SDA Setup Time
SCLK and SDA Rise Time
SCLK and SDA Fall Time
Setup Time for Stop Condition
RESET FEATURE
t1
t2
t3
t4
t5
t6
t7
t8
0.6
1.3
0.6
0.6
100
300
300
0.6
Reset Pulse Width
5
ms
CLOCK OUTPUTS
LLC1 Mark Space Ratio
DATA AND CONTROL OUTPUTS
Data Output Transitional Time
t9:t10
45:55
55:45 % Duty Cycle
t11
t12
Negative Clock Edge to start of valid
data. (tACCESS = t10 – t11)
End of valid data to negative clock
edge. (tHOLD = t9 + t12)
3.4
2.4
ns
ns
Data Output Transitional Time
ANALOG SPECIFICATIONS
Guaranteed by characterization. At AVDD = 3.15 V to 3.45 V, DVDD = 1.65 V to 2.0 V, DVDDIO = 3.0 V to 3.6 V, PVDD = 1.65 V to 2.0 V
(operating temperature range, unless otherwise noted).
Table 4.
Parameter
Symbol Test Conditions
Min Typ
Max
Unit
CLAMP CIRCUITRY
External Clamp Capacitor
Input Impedance
Large Clamp Source Current
Large Clamp Sink Current
Fine Clamp Source Current
Fine Clamp Sink Current
0.1
10
0.75
0.75
60
µF
Clamps switched off
MΩ
mA
mA
µA
60
µA
Rev. 0 | Page 7 of 96
ADV7181B
THERMAL SPECIFICATIONS
Table 5.
Parameter
Symbol Test Conditions
Min Typ Max Unit
THERMAL CHARACTERISTICS
Junction-to-Ambient Thermal
Resistance (Still Air)
θJA
4-layer PCB with solid ground plane, 64-lead LFCSP
45.5
°C/W
Junction-to-Case Thermal Resistance
Junction-to-Ambient Thermal
Resistance (Still Air)
θJC
θJA
4-layer PCB with solid ground plane, 64-lead LFCSP
4-layer PCB with solid ground plane, 64-lead LQFP
9.2
47
°C/W
°C/W
Junction-to-Case Thermal Resistance
θJC
4-layer PCB with solid ground plane, 64-lead LQFP
11.1
°C/W
TIMING DIAGRAMS
t5
t3
t3
SDA
t1
t6
SCLK
t4
t7
t8
t2
Figure 2. I2C Timing
t9
t10
OUTPUT LLC
t11
t12
OUTPUTS P0–P15, VS,
HS, FIELD,
SFL
Figure 3. Pixel Port and Control Output Timing
Rev. 0 | Page 8 of 96
ADV7181B
ABSOLUTE MAXIMUM RATINGS
Table 6.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may
affect device reliability.
Parameter
Rating
AVDD to GND
4 V
AVDD to AGND
4 V
DVDD to DGND
2.2 V
PVDD to AGND
2.2 V
DVDDIO to DGND
DVDDIO to AVDD
PVDD to DVDD
DVDDIO – PVDD
DVDDIO – DVDD
4 V
–0.3 V to +0.3 V
–0.3 V to +0.3 V
–0.3V to +2 V
–0.3V to +2 V
–0.3V to +2 V
–0.3V to +2 V
–0.3V to DVDDIO + 0.3 V
–0.3V to DVDDIO + 0.3 V
AGND – 0.3 V to AVDD + 0.3 V
150°C
AVDD – PVDD
AVDD – DVDD
Digital Inputs Voltage to DGND
Digital Output Voltage to DGND
Analog Inputs to AGND
Maximum Junction Temperature
(TJ max)
Storage Temperature Range
Infrared Reflow Soldering (20 s)
–65°C to +150°C
260°C
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. 0 | Page 9 of 96
ADV7181B
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
INTRQ
1
2
3
4
5
6
7
8
9
48 AIN5
PIN 1
INDICATOR
HS
DGND
DVDDIO
P11
47 AIN4
46 AIN3
45 AGND
44 CAPC2
43 AGND
42 CML
P10
P9
ADV7181B
TOP VIEW
(Not to Scale)
P8
41 REFOUT
40 AVDD
39 CAPY2
38 CAPY1
37 AGND
36 AIN2
SFL
DGND 10
DVDDIO 11
NC 12
NC 13
P7 14
35 AIN1
P6 15
34 DGND
33 NC
P5 16
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
NC = NO CONNECT
Figure 4. 64-Lead LFCSP/LQFP Pin Configuration
Table 7. Pin Function Descriptions
Pin No.
3, 10, 24, 34, 57
32, 37, 43, 45
4, 11
23, 58
40
Mnemonic
Type Function
DGND
AGND
DVDDIO
DVDD
AVDD
PVDD
AIN1–AIN6
NC
G
G
P
P
P
P
I
Digital Ground.
Analog Ground.
Digital I/O Supply Voltage (3.3 V).
Digital Core Supply Voltage (1.8 V).
Analog Supply Voltage (3.3 V).
PLL Supply Voltage (1.8 V).
Analog Video Input Channels.
No Connect Pins.
31
35, 36, 46–49
12, 13, 27, 28, 33,
50, 55, 56
26, 25, 19, 18, 17,
16, 15, 14, 8, 7, 6, 5,
62, 61, 60, 59
P0–P15
O
Video Pixel Output Port.
2
HS
VS
FIELD
INTRQ
O
O
O
O
Horizontal Synchronization Output Signal.
Vertical Synchronization Output Signal.
Field Synchronization Output Signal.
Interrupt Request Output. Interrupt occurs when certain signals are detected on the input
video. See the interrupt register map in Table 82.
I2C Port Serial Data Input/Output Pin.
I2C Port Serial Clock Input (Maximum Clock Rate of 400 kHz).
This pin selects the I2C address for the ADV7181B. ALSB set to a Logic 0 sets the address for
a write as 0x40; for ALSB set to a logic high, the address selected is 0x42.
64
63
1
53
54
52
SDA
SCLK
ALSB
I/O
I
I
51
20
22
RESET
LLC
I
System Reset Input, Active Low. A minimum low reset pulse width of 5 ms is required to
reset the ADV7181B circuitry.
This is a line-locked output clock for the pixel data output by the ADV7181B. Nominally
27 MHz, but varies up or down according to video line length.
This is the input pin for the 27 MHz crystal, or can be overdriven by an external 3.3 V,
27 MHz clock oscillator source. In crystal mode, the crystal must be a fundamental crystal.
O
I
XTAL
Rev. 0 | Page 10 of 96
ADV7181B
Pin No.
Mnemonic
Type Function
21
XTAL1
O
This pin should be connected to the 27 MHz crystal or left as a no connect if an external
3.3 V, 27 MHz clock oscillator source is used to clock the ADV7181B. In crystal mode, the
crystal must be a fundamental crystal.
29
30
9
PWRDN
ELPF
I
A logic low on this pin places the ADV7181B in a power-down mode. Refer to the I2C
Register Maps section for more options on power-down modes for the ADV7181B.
The recommended external loop filter must be connected to this ELPF pin, as shown in
Figure 44.
Subcarrier Frequency Lock. This pin contains a serial output stream that can be used to lock
the subcarrier frequency when this decoder is connected to any Analog Devices digital
video encoder.
I
SFL
O
41
REFOUT
CML
O
O
I
Internal Voltage Reference Output. Refer to Figure 44 for a recommended capacitor
network for this pin.
The CML pin is a common-mode level for the internal ADCs. Refer to Figure 44 for a
recommended capacitor network for this pin.
ADC’s Capacitor Network. Refer to Figure 44 for a recommended capacitor network for
this pin.
ADC’s Capacitor Network. Refer to Figure 44 for a recommended capacitor network for
this pin.
42
38, 39
44
CAPY1, CAPY2
CAPC2
I
Rev. 0 | Page 11 of 96
ADV7181B
ANALOG FRONT END
ADC_SW_MAN_EN
AIN2
AIN1
AIN4
AIN3
AIN6
AIN5
ADC0_SW[3:0]
ADC0
AIN4
AIN3
AIN6
AIN5
ADC1_SW[3:0]
ADC1
AIN6
AIN5
ADC0_SW[3:0]
ADC2
Figure 5. Internal Pin Connections
There are two key steps to configure the ADV7181B to correctly
decode the input video.
SETADC_sw_man_en, Manual Input Muxing Enable,
Address C4 [7]
1. The analog input muxing section must be configured to
correctly route the video from the analog input pins to the
correct set of ADCs.
ADC0_sw[3:0], ADC0 mux configuration, Address C3 [3:0]
ADC1_sw[3:0], ADC1 mux configuration, Address C3 [7:4]
ADC2_sw[3:0], ADC2 mux configuration, Address C4 [3:0]
2. The standard definition processor block, which decodes
the digital data, should be configured to process either
CVBS, YC, or YPrPb.
To configure the ADV7181B analog muxing section, the user
must select the analog input (AIN1–AIN6) that is to be
processed by each ADC. SETADC_sw_man_en must be set to 1
to enable the muxing blocks to be configured. The three mux
sections are controlled by the signal buses ADC0/1/2_sw[3:0].
Table 8 explains the control words used.
ANALOG INPUT MUXING
The ADV7181B has an integrated analog muxing section that
allows more than one source of video signal to be connected to
the decoder. Figure 5 outlines the overall structure of the input
muxing provided in the ADV7181B.
The input signal that contains the timing information (H/V
syncs) must be processed by ADC0. For example, in YC input
configuration, ADC0 should be connected to the Y channel and
ADC1 to the C channel. When one or more ADCs are not used
to process video, for example, CVBS input, the idle ADCs should
be powered down, (see the ADC Power-Down Control section).
A maximum of 6 CVBS inputs can be connected and decoded
by the ADV7181B. As can be seen from the Pin Configuration
and Function Description section, these analog input pins lie in
close proximity to one another. This calls for a careful design of
the PCB layout, for example, ground shielding between all
signals routed through tracks that are physically close together.
It is strongly recommended to connect any unused analog input
pins to AGND to act as a shield.
Restrictions on the channel routing are imposed by the analog
signal routing inside the IC; every input pin cannot be routed to
each ADC. Refer to Table 8 for an overview on the routing
capabilities inside the chip.
Rev. 0 | Page 12 of 96
ADV7181B
Table 8. Manual Mux Settings for All ADCs (SETADC_sw_man_en = 1)
ADC0_sw[3:0]
ADC0 Connected To:
No Connection
AIN2
No Connection
No Connection
AIN4
ADC1_sw[3:0]
ADC1 Connected To:
No Connection
No Connection
No Connection
No Connection
AIN4
ADC2_sw[3:0]
0000
0001
0010
0011
ADC2 Connected To:
No Connection
No Connection
No Connection
No Connection
No Connection
AIN6
0000
0001
0010
0011
0100
0101
0000
0001
0010
0011
0100
0101
0100
0101
AIN6
AIN6
0110
0111
1000
1001
1010
1011
1100
1101
No Connection
No Connection
No Connection
AIN1
No Connection
No Connection
AIN3
0110
0111
1000
1001
1010
1011
1100
1101
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
AIN3
0110
0111
1000
1001
1010
1011
1100
1101
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
No Connection
AIN5
AIN5
AIN5
1110
1111
No Connection
No Connection
1110
1111
No Connection
No Connection
1110
1111
No Connection
No Connection
CONNECTING
ANALOG SIGNALS
TO ADV7181B
INSEL[3:0] Input Selection, Address 0x00 [3:0]
The INSEL bits allow the user to select the input format. It
configures the standard definition processor core to process
CVBS (Comp), S-Video (Y/C), or Component (YPbPr) format.
SET INSEL[3:0] TO
CONFIGURE ADV7181B TO
DECODE VIDEO FORMAT:
CVBS: 0000
YC: 0110
Table 9. Standard Definition Processor Format Selection,
INSEL[3:0]
YPrPb: 1001
INSEL[3:0]
Video Format
Composite
YC
CONFIGURE ADC INPUTS USING
MUXING CONTROL BITS
(ADC_sw_man_en,
0000
0110
ADC0_sw,adc1_sw, ADC2_sw)
1001
YPrPb
Figure 6. Input Muxing Overview
Rev. 0 | Page 13 of 96
ADV7181B
GLOBAL CONTROL REGISTERS
Register control bits listed in this section affect the whole chip.
PWRDN_ADC_0, Address 0x3A [3]
POWER-SAVE MODES
Power-Down
When PWRDN_ADC_0 is 0 (default), the ADC is in normal
operation.
PDBP, Address 0x0F [2]
When PWRDN_ADC_0 is 1, ADC 0 is powered down.
The digital core of the ADV7181B can be shut down by using a
PWRDN_ADC_1, Address 0x3A [2]
pin (
) and a bit (PWRDN see below). The PDBP
PWRDN
controls which of the two has the higher priority. The default is
to give the pin ( ) priority. This allows the user to have
When PWRDN_ADC_1 is 0 (default), the ADC is in normal
operation.
PWRDN
the ADV7181B powered down by default.
When PWRDN_ADC_1 is 1, ADC 1 is powered down.
When PDBD is 0 (default), the digital core power is controlled
by the
pin (the bit is disregarded).
PWRDN
PWRDN_ADC_2, Address 0x3A [1]
When PDBD is 1, the bit has priority (the pin is disregarded).
When PWRDN_ADC_2 is 0 (default), the ADC is in normal
operation (default).
PWRDN, Address 0x0F [5]
When PWRDN_ADC_2 is 1, ADC 2 is powered down.
RESET CONTROL
Setting the PWRDN bit switches the ADV7181B into a chip-
wide power-down mode. The power-down stops the clock from
entering the digital section of the chip, thereby freezing its
operation. No I2C bits are lost during power-down. The
PWRDN bit also affects the analog blocks and switches them
into low current modes. The I2C interface itself is unaffected,
and remains operational in power-down mode.
Chip Reset (RES), Address 0x0F [7]
RESET
Setting this bit, equivalent to controlling the
pin on the
ADV7181B, issues a full chip reset. All I2C registers are reset to
their default values. Note that some register bits do not have a
reset value specified. They keep their last written value. Those
bits are marked as having a reset value of x in the register table.
After the reset sequence, the part immediately starts to acquire
the incoming video signal.
The ADV7181B leaves the power-down state if the PWRDN bit
is set to 0 (via I2C), or if the overall part is reset using the
RESET
pin.
PDBP must be set to 1 for the PWRDN bit to power down the
ADV7181B.
After setting the RES bit (or initiating a reset via the pin), the
part returns to the default mode of operation with respect to its
primary mode of operation. All I2C bits are loaded with their
default values, making this bit self-clearing.
When PWRDN is 0 (default), the chip is operational.
When PWRDN is 1, the ADV7181B is in chip-wide power-down.
Executing a software reset takes approximately 2 ms. However, it
is recommended to wait 5 ms before any further I2C writes are
performed.
ADC Power-Down Control
The ADV7181B contains three 9-bit ADCs (ADC 0, ADC 1, and
ADC 2). If required, it is possible to power down each ADC
individually.
The I2C master controller receives a no acknowledge condition
on the ninth clock cycle when chip reset is implemented. See the
MPU Port Description section.
When should the ADCs be powered down?
•
CVBS mode. ADC 1 and ADC 2 should be powered down
to save on power consumption.
When RES is 0 (default), operation is normal.
When RES is 1, the reset sequence starts.
•
S-Video mode. ADC 2 should be powered down to save on
power consumption.
Rev. 0 | Page 14 of 96
ADV7181B
When TIM_OE is 0 (default), HS, VS, and FIELD are three-
stated according to the TOD bit.
GLOBAL PIN CONTROL
Three-State Output Drivers
When TIM_OE is 1, HS, VS, and FIELD are forced active all the
time.
TOD, Address 0x03 [6]
This bit allows the user to three-state the output drivers of the
ADV7181B.
Drive Strength Selection (Data)
DR_STR[1:0] Address 0xF4 [5:4]
Upon setting the TOD bit, the P15–P0, HS, VS, FIELD, and SFL
pins are three-stated.
For EMC and crosstalk reasons, it may be desirable to
strengthen or weaken the drive strength of the output drivers.
The DR_STR[1:0] bits affect the P[15:0] output drivers.
The timing pins (HS/VS/FIELD) can be forced active via the
TIM_OE bit. For more information on three-state control, refer
to the Three-State LLC Driver and the Timing Signals Output
Enable sections.
For more information on three-state control, refer to the Drive
Strength Selection (Clock) and the Drive Strength Selection
(Sync) sections.
Individual drive strength controls are provided via the
DR_STR_XX bits.
Table 10. DR_STR Function
DR_STR[1:0]
Description
When TOD is 0 (default), the output drivers are enabled.
00
Low drive strength (1×).
Medium low drive strength (2×).
Medium high drive strength (3×).
High drive strength (4×).
01 (default)
10
11
When TOD is 1, the output drivers are three-stated.
Three-State LLC Driver
TRI_LLC, Address 0x1D [7]
Drive Strength Selection (Clock)
This bit allows the output drivers for the LLC pin of the
ADV7181B to be three-stated. For more information on three-
state control, refer to the Three-State Output Drivers and the
Timing Signals Output Enable sections.
DR_STR_C[1:0] Address 0xF4 [3:2]
The DR_STR_C[1:0] bits can be used to select the strength of
the clock signal output driver (LLC pin). For more information,
refer to the Drive Strength Selection (Sync) and the Drive
Strength Selection (Data) sections.
Individual drive strength controls are provided via the
DR_STR_XX bits.
Table 11. DR_STR Function
When TRI_LLC is 0 (default), the LLC pin drivers work
according to the DR_STR_C[1:0] setting (pin enabled).
DR_STR[1:0]
Description
00
Low drive strength (1×).
Medium low drive strength (2×).
Medium high drive strength (3×).
High drive strength (4×).
01 (default)
10
11
When TRI_LLC is 1, the LLC pin drivers are three-stated.
Timing Signals Output Enable
TIM_OE, Address 0x04 [3]
Drive Strength Selection (Sync)
The TIM_OE bit should be regarded as an addition to the TOD
bit. Setting it high forces the output drivers for HS, VS, and
FIELD into the active (i.e., driving) state even if the TOD bit is
set. If set to low, the HS, VS, and FIELD pins are three-stated
dependent on the TOD bit. This functionality is useful if the
decoder is to be used as a timing generator only. This may be
the case if only the timing signals are to be extracted from an
incoming signal, or if the part is in free-run mode where a
separate chip can output, for instance, a company logo.
DR_STR_S[1:0] Address 0xF4 [1:0]
The DR_STR_S[1:0] bits allow the user to select the strength of
the synchronization signals with which HS, VS, and F are driven.
For more information, refer to the Drive Strength Selection
(Data) section.
Table 12. DR_STR Function
DR_STR[1:0]
Description
00
Low drive strength (1×).
Medium low drive strength (2×).
Medium high drive strength (3×).
High drive strength (4×).
For more information on three-state control, refer to the Three-
State Output Drivers and the Three-State LLC Driver sections.
01 (default)
10
11
Individual drive strength controls are provided via the
DR_STR_XX bits.
Rev. 0 | Page 15 of 96
ADV7181B
Enable Subcarrier Frequency Lock Pin
Polarity LLC Pin
EN_SFL_PIN Address 0x04 [1]
PCLK Address 0x37 [0]
The EN_SFL_PIN bit enables the output of subcarrier lock
information (also known as GenLock) from the ADV7181B
core to an encoder in a decoder-encoder back-to-back
arrangement.
The polarity of the clock that leaves the ADV7181B via the LLC
pin can be inverted using the PCLK bit.
Changing the polarity of the LLC clock output may be
necessary to meet the setup-and-hold time expectations of
follow-on chips.
When EN_SFL_PIN is 0 (default), the subcarrier frequency lock
output is disabled.
When PCLK is 0, the LLC output polarity is inverted.
When EN_SFL_PIN is 1, the subcarrier frequency lock
information is presented on the SFL pin.
When PCLK is 1 (default), the LLC output polarity is normal
(as per the timing diagrams).
Rev. 0 | Page 16 of 96
ADV7181B
GLOBAL STATUS REGISTERS
Four registers provide summary information about the video
decoder. The IDENT register allows the user to identify the
revision code of the ADV7181B. The other three registers
contain status bits from the ADV7181B.
Depending on the setting of the FSCLE bit, the Status 0 and
Status 1 are based solely on horizontal timing info or on the
horizontal timing and lock status of the color subcarrier. See the
FSCLE Fsc Lock Enable, Address 0x51 [7] section.
IDENTIFICATION
AUTODETECTION RESULT
IDENT[7:0] Address 0x11 [7:0]
AD_RESULT[2:0] Address 0x10 [6:4]
The register identification of the revision of the ADV7181B.
The AD_RESULT[2:0] bits report back on the findings from the
ADV7181B autodetection block. Consult the General Setup
section for more information on enabling the autodetection
block, and the Autodetection of SD Modes section to find out
how to configure it.
An identification value of 0x11 indicates the ADV7181, released
silicon.
An identification value of 0x13 indicates the ADV7181B.
STATUS 1
Table 13. AD_RESULT Function
AD_RESULT[2:0]
Description
000
001
010
011
100
101
110
111
NTSM-MJ
NTSC-443
PAL-M
PAL-60
PAL-BGHID
SECAM
STATUS_1[7:0] Address 0x10 [7:0]
This read-only register provides information about the internal
status of the ADV7181B.
See CIL[2:0] Count Into Lock, Address 0x51 [2:0] and COL[2:0
Count Out of Lock, Address 0x51 [5:3] for information on the
timing.
PAL-Combination N
SECAM 525
Table 14. STATUS 1 Function
STATUS 1 [7:0]
Bit Name
Description
0
1
2
3
4
5
6
7
IN_LOCK
LOST_LOCK
FSC_LOCK
FOLLOW_PW
AD_RESULT.0
AD_RESULT.1
AD_RESULT.2
COL_KILL
In lock (right now).
Lost lock (since last read of this register).
Fsc locked (right now).
AGC follows peak white algorithm.
Result of autodetection.
Result of autodetection.
Result of autodetection.
Color kill active.
STATUS 2
STATUS_2[7:0], Address 0x12 [7:0]
Table 15. STATUS 2 Function
STATUS 2 [7:0]
Bit Name
MVCS DET
MVCS T3
MV_PS DET
MV_AGC DET
LL_NSTD
Description
Detected Macrovision color striping.
Macrovision color striping protection. Conforms to Type 3 (if high), and Type 2 (if low).
Detected Macrovision pseudo Sync pulses.
Detected Macrovision AGC pulses.
0
1
2
3
4
5
6
7
Line length is nonstandard.
Fsc frequency is nonstandard.
FSC_NSTD
Reserved
Reserved
Rev. 0 | Page 17 of 96
ADV7181B
STATUS 3
STATUS_3[7:0], Address 0x13 [7:0]
Table 16. STATUS 3 Function
STATUS 3 [7:0]
Bit Name
INST_HLOCK
GEMD
Description
0
1
2
3
4
Horizontal lock indicator (instantaneous).
Gemstar Detect.
Flags whether 50 Hz or 60 Hz is present at output.
Reserved for future use.
ADV7181B outputs a blue screen (see the DEF_VAL_EN Default Value Enable,
Address 0x0C [0] section).
SD_OP_50HZ
FREE_RUN_ACT
5
6
7
STD_FLD_LEN
INTERLACED
PAL_SW_LOCK
Field length is correct for currently selected video standard.
Interlaced video detected (field sequence found).
Reliable sequence of swinging bursts detected.
Rev. 0 | Page 18 of 96
ADV7181B
STANDARD DEFINITION PROCESSOR (SDP)
STANDARD DEFINITION PROCESSOR
MACROVISION
DETECTION
STANDARD
AUTODETECTION
SLLC
CONTROL
VBI DATA
RECOVERY
LUMA
DIGITAL
FINE
DIGITIZED CVBS
DIGITIZED Y (YC)
LUMA
2D COMB
LUMA
FILTER
GAIN
CONTROL
LUMA
RESAMPLE
CLAMP
LINE
AV
SYNC
EXTRACT
RESAMPLE
CONTROL
VIDEO DATA
OUTPUT
LENGTH
CODE
PREDICTOR
INSERTION
CHROMA
DIGITAL
FINE
MEASUREMENT
BLOCK (= >1 C)
DIGITIZED CVBS
DIGITIZED C (YC)
CHROMA
DEMOD
CHROMA
FILTER
GAIN
CONTROL
CHROMA
RESAMPLE
CHROMA
2D COMB
2
CLAMP
VIDEO DATA
PROCESSING
BLOCK
F
SC
RECOVERY
Figure 7. Block Diagram of the Standard Definition Processor
A block diagram of the ADV7181B’s standard definition
processor (SDP) is shown in Figure 7.
SD CHROMA PATH
The input signal is processed by the following blocks:
The ADV7181B can handle standard definition video in CVBS,
YC, and YPrPb formats. It can be divided into a luminance and
chrominance path. If the input video is of a composite type
(CVBS), both processing paths are fed with the CVBS input.
•
Digital Fine Clamp. This block uses a high precision
algorithm to clamp the video signal.
•
Chroma Demodulation. This block employs a color
subcarrier (Fsc) recovery unit to regenerate the color
subcarrier for any modulated chroma scheme. The
demodulation block then performs an AM demodulation
for PAL and NTSC, and an FM demodulation for SECAM.
SD LUMA PATH
The input signal is processed by the following blocks:
•
Digital Fine Clamp. This block uses a high precision
algorithm to clamp the video signal.
•
•
Chroma Filter Block. This block contains a chroma
decimation filter (CAA) with a fixed response, and some
shaping filters (CSH) that have selectable responses.
•
Luma Filter Block. This block contains a luma decimation
filter (YAA) with a fixed response, and some shaping filters
(YSH) that have selectable responses.
Gain Control. Automatic gain control (AGC) can operate
on several different modes, including gain based on the
color subcarrier’s amplitude, gain based on the depth of the
horizontal sync pulse on the luma channel, or fixed manual
gain.
•
•
Luma Gain Control. The automatic gain control (AGC) can
operate on a variety of different modes, including gain
based on the depth of the horizontal sync pulse, peak white
mode, and fixed manual gain.
•
Chroma Resample. The chroma data is digitally resampled
to keep it perfectly aligned with the luma data. The
resampling is done to correct for static and dynamic line-
length errors of the incoming video signal.
Luma Resample. To correct for line-length errors as well as
dynamic line-length changes, the data is digitally
resampled.
•
•
Luma 2D Comb. The two-dimensional comb filter provides
YC separation.
•
•
Chroma 2D Comb. The two-dimensional, 5-line,
superadaptive comb filter provides high quality YC
separation in case the input signal is CVBS.
AV Code Insertion. At this point, the decoded luma (Y)
signal is merged with the retrieved chroma values. AV
codes (as per ITU-R. BT-656) can be inserted.
AV Code Insertion. At this point, the demodulated chroma
(Cr and Cb) signal is merged with the retrieved luma
values. AV codes (as per ITU-R. BT-656) can be inserted.
Rev. 0 | Page 19 of 96
ADV7181B
SYNC PROCESSING
GENERAL SETUP
Video Standard Selection
The ADV7181B extracts syncs embedded in the video data
stream. There is currently no support for external HS/VS inputs.
The sync extraction has been optimized to support imperfect
video sources such as videocassette recorders with head
switches. The actual algorithm used employs a coarse detection
based on a threshold crossing followed by a more detailed
detection using an adaptive interpolation algorithm. The raw
sync information is sent to a line-length measurement and
prediction block. The output of this is then used to drive the
digital resampling section to ensure that the ADV7181B outputs
720 active pixels per line.
The VID_SEL[3:0] register allows the user to force the digital
core into a specific video standard. Under normal circumstances,
this should not be necessary. The VID_SEL[3:0] bits default to
an autodetection mode that supports PAL, NTSC, SECAM, and
variants thereof. The following section provides more informa-
tion on the autodetection system.
Autodetection of SD Modes
In order to guide the autodetect system of the ADV7181B,
individual enable bits are provided for each of the supported
video standards. Setting the relevant bit to 0 inhibits the
standard from being detected automatically. Instead, the system
picks the closest of the remaining enabled standards. The results
of the autodetection block can be read back via the status
registers. See the Global Status Registers section for more
information.
The sync processing on the ADV7181B also includes the
following specialized postprocessing blocks that filter and
condition the raw sync information retrieved from the digitized
analog video.
•
VSYNC Processor. This block provides extra filtering of the
detected VSYNCs to give improved vertical lock.
VID_SEL[3:0]Address 0x00 [7:4]
Table 17. VID_SEL Function
•
HSYNC Processor. The HSYNC processor is designed to
filter incoming HSYNCs that have been corrupted by
noise, providing much improved performance for video
signals with stable time base but poor SNR.
VID_SEL[3:0]
Description
0000 (default)
Autodetect (PAL BGHID) <–> NTSC J (no
pedestal), SECAM.
0001
0010
0011
Autodetect (PAL BGHID) <–> NTSC M
(pedestal), SECAM.
Autodetect (PAL N) (pedestal) <–> NTSC J (no
pedestal), SECAM.
Autodetect (PAL N) (pedestal)<–> NTSC M
(pedestal), SECAM.
VBI DATA RECOVERY
The ADV7181B can retrieve the following information from the
input video:
•
•
•
•
•
•
Wide-screen signaling (WSS)
Copy generation management system (CGMS)
Closed caption (CC)
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
NTSC J (1).
NTSC M (1).
PAL 60.
NTSC 4.43 (1).
PAL BGHID.
Macrovision protection presence
EDTV data
PAL N (= PAL BGHID (with pedestal)).
PAL M (without pedestal).
PAL M.
PAL combination N.
PAL combination N (with pedestal).
SECAM.
Gemstar-compatible data slicing
The ADV7181B is also capable of automatically detecting the
incoming video standard with respect to
SECAM (with pedestal).
•
•
•
Color subcarrier frequency
Field rate
AD_SEC525_EN Enable Autodetection of SECAM 525
Line Video, Address 0x07 [7]
Line rate
Setting AD_SEC525_EN to 0 (default) disables the
autodetection of a 525-line system with a SECAM style, FM-
modulated color component.
The ADV7181B can configure itself to support PAL-BGHID,
PAL-M/N, PAL-combination N, NTSC-M, NTSC-J, SECAM
50 Hz/60 Hz, NTSC4.43, and PAL60.
Setting AD_SEC525_EN to 1 enables the detection.
Rev. 0 | Page 20 of 96
ADV7181B
AD_SECAM_EN Enable Autodetection of SECAM,
Address 0x07 [6]
AD_PAL_EN Enable Autodetection of PAL,
Address 0x07 [0]
Setting AD_SECAM_EN to 0 (default) disables the
autodetection of SECAM.
Setting AD_PAL_EN to 0 (default) disables the detection of
standard PAL.
Setting AD_SECAM_EN to 1 enables the detection.
Setting AD_PAL_EN to 1 enables the detection.
SFL_INV Subcarrier Frequency Lock Inversion
AD_N443_EN Enable Autodetection of NTSC 443,
Address 0x07 [5]
This bit controls the behavior of the PAL switch bit in the SFL
(GenLock Telegram) data stream. It was implemented to solve
some compatibility issues with video encoders. It solves two
problems.
Setting AD_N443_EN to 0 disables the autodetection of NTSC
style systems with a 4.43 MHz color subcarrier.
Setting AD_N443_EN to 1 (default) enables the detection.
First, the PAL switch bit is only meaningful in PAL. Some
encoders (including Analog Devices encoders) also look at the
state of this bit in NTSC.
AD_P60_EN Enable Autodetection of PAL60,
Address 0x07 [4]
Second, there was a design change in Analog Devices encoders
from ADV717x to ADV719x. The older versions used the SFL
(GenLock Telegram) bit directly, while the later ones invert the
bit prior to using it. The reason for this is that the inversion
compensated for the 1-line delay of an SFL (GenLock Telegram)
transmission.
Setting AD_P60_EN to 0 disables the autodetection of PAL
systems with a 60 Hz field rate.
Setting AD_P60_EN to 1 (default) enables the detection.
AD_PALN_EN Enable Autodetection of PAL N,
Address 0x07 [3]
As a result, ADV717x encoders need the PAL switch bit in the
SFL (GenLock Telegram) to be 1 for NTSC to work. Also,
ADV7190/ADV7191/ADV7194 encoders need the PAL switch
bit in the SFL to be 0 to work in NTSC. If the state of the PAL
switch bit is wrong, a 180° phase shift occurs.
Setting AD_PALN_EN to 0 (default) disables the detection of
the PAL N standard.
Setting AD_PALN_EN to 1 enables the detection.
AD_PALM_EN Enable Autodetection of PAL M,
Address 0x07 [2]
In a decoder/encoder back-to-back system in which SFL is used,
this bit must be set up properly for the specific encoder used.
Setting AD_PALM_EN to 0 (default) disables the autodetection
of PAL M.
SFL_INV Function Address 0x41 [6]
Setting AD_PALM_EN to 1 enables the detection.
Setting SFL_INV to 0 makes the part SFL-compatible with
ADV7190/ADV7191/ADV7194 encoders.
AD_NTSC_EN Enable Autodetection of NTSC,
Address 0x07 [1]
Setting SFL_INV to 1 (default) makes the part SFL-compatible
with ADV717x/ADV7173x encoders.
Setting AD_NTSC_EN to 0 (default) disables the detection of
standard NTSC.
Lock Related Controls
Lock information is presented to the user through Bits [1:0] of
the Status 1 register. See the STATUS_1[7:0] Address 0x10 [7:0]
section. Figure 8 outlines the signal flow and the controls
available to influence the way the lock status information is
generated.
Setting AD_NTSC_EN to 1 enables the detection.
SELECT THE RAW LOCK SIGNAL
SRLS
FILTER THE RAW LOCK SIGNAL
CIL[2:0], COL[2:0]
TIME_WIN
1
0
0
1
FREE_RUN
COUNTER INTO LOCK
COUNTER OUT OF LOCK
STATUS 1 [0]
STATUS 1 [1]
F
LOCK
SC
MEMORY
TAKE F LOCK INTO ACCOUNT
SC
FSCLE
Figure 8. Lock Related Signal Path
Rev. 0 | Page 21 of 96
ADV7181B
SRLS Select Raw Lock Signal, Address 0x51 [6]
COL[2:0] Count Out of Lock, Address 0x51 [5:3]
Using the SRLS bit, the user can choose between two sources for
determining the lock status (per Bits [1:0] in the Status 1 register).
COL[2:0] determines the number of consecutive lines for which
the out of lock condition must be true before the system
switches into unlocked state, and reports this via Status 0 [1:0].
It counts the value in lines of video.
•
The time_win signal is based on a line-to-line evaluation of
the horizontal synchronization pulse of the incoming
video. It reacts quite quickly.
Table 19. COL Function
COL[2:0]
Description
000
001
010
1
2
5
•
The free_run signal evaluates the properties of the
incoming video over several fields, and takes vertical
synchronization information into account.
011
100 (default)
101
110
111
10
Setting SRLS to 0 (default) selects the free_run signal.
Setting SRLS to 1 selects the time_win signal.
100
500
1000
100000
FSCLE Fsc Lock Enable, Address 0x51 [7]
The FSCLE bit allows the user to choose whether the status of
the color subcarrier loop is taken into account when the overall
lock status is determined and presented via Bits [1:0] in Status
Register 1. This bit must be set to 0 when operating the
ADV7181B in YPrPb component mode in order to generate a
reliable HLOCK status bit.
COLOR CONTROLS
These registers allow the user to control picture appearance,
including control of the active data in the event of video being
lost. These controls are independent of any other controls. For
instance, brightness control is independent from picture
clamping, although both controls affect the signal’s dc level.
When FSCLE is set to 0 (default), the overall lock status only is
dependent on horizontal sync lock.
CON[7:0] Contrast Adjust, Address 0x08 [7:0]
When FSCLE is set to 1, the overall lock status is dependent on
horizontal sync lock and Fsc Lock.
This register allows the user to control contrast adjustment of
the picture.
Table 20. CON Function
CIL[2:0] Count Into Lock, Address 0x51 [2:0]
CON[7:0]
0x80 (default)
0x00
Description
Gain on luma channel = 1.
Gain on luma channel = 0.
Gain on luma channel = 2.
CIL[2:0] determines the number of consecutive lines for which
the into lock condition must be true before the system switches
into the locked state, and reports this via Status 0 [1:0]. It counts
the value in lines of video.
0xFF
Table 18. CIL Function
SD_SAT_Cb[7:0] SD Saturation Cb Channel,
Address 0xE3 [7:0]
CIL[2:0]
Description
000
1
This register allows the user to control the gain of the Cb
channel only, which in turn adjusts the saturation of the picture.
001
2
010
5
011
10
Table 21. SD_SAT_Cb Function
100 (default)
101
110
100
500
1000
100000
SD_SAT_Cb[7:0] Description
0x80 (default)
0x00
Gain on Cb channel = 0 dB.
Gain on Cb channel = −42 dB.
Gain on Cb channel = +6 dB.
111
0xFF
Rev. 0 | Page 22 of 96
ADV7181B
SD_SAT_Cr[7:0] SD Saturation Cr Channel, Address 0xE4 [7:0]
HUE[7:0] Hue Adjust, Address 0x0B [7:0]
This register contains the value for the color hue adjustment. It
allows the user to adjust the hue of the picture.
This register allows the user to control the gain of the Cr
channel only, which in turn adjusts the saturation of the picture.
Table 22. SD_SAT_Cr Function
SD_SAT_Cr[7:0] Description
HUE[7:0] has a range of 90°, with 0x00 equivalent to an
adjustment of 0°. The resolution of HUE[7:0] is 1 bit = 0.7°.
0x80 (default)
0x00
0xFF
Gain on Cr channel = 0 dB.
Gain on Cb channel = −42 dB.
Gain on Cb channel = +6 dB.
The hue adjustment value is fed into the AM color demodula-
tion block. Therefore, it only applies to video signals that contain
chroma information in the form of an AM-modulated carrier
(CVBS or Y/C in PAL or NTSC). It does not affect SECAM and
does not work on component video inputs (YPrPb).
SD_OFF_Cb[7:0] SD Offset Cb Channel, Address 0xE1 [7:0]
Table 26. HUE Function
This register allows the user to select an offset for the Cb
channel only and adjust the hue of the picture. There is a
functional overlap with the Hue [7:0] register.
HUE[7:0]
0x00 (default)
0x7F
Description (Adjust Hue of the Picture)
Phase of the chroma signal = 0°.
Phase of the chroma signal = –90°.
Phase of the chroma signal = +90°.
0x80
Table 23. SD_OFF_Cb Function
SD_OFF_Cb[7:0] Description
0x80 (default)
0x00
0xFF
0 offset applied to the Cb channel.
−312 mV offset applied to the Cb channel.
+312 mV offset applied to the Cb channel.
DEF_Y[5:0] Default Value Y, Address 0x0C [7:2]
When the ADV7181B loses lock on the incoming video signal
or when there is no input signal, the DEF_Y[5:0] register allows
the user to specify a default luma value to be output. This value
is used under the following conditions:
SD_OFF_Cr [7:0] SD Offset Cr Channel, Address 0xE2 [7:0]
This register allows the user to select an offset for the Cr channel
only and adjust the hue of the picture. There is a functional
overlap with the Hue [7:0] register.
•
If DEF_VAL_AUTO_EN bit is set to high and the
ADV7181B lost lock to the input video signal. This is the
intended mode of operation (automatic mode).
Table 24. SD_OFF_Cr Function
•
The DEF_VAL_EN bit is set, regardless of the lock status of
SD_OFF_Cr[7:0]
0x80 (default)
0x00
Description
the video decoder. This is a forced mode that may be useful
during configuration.
0 offset applied to the Cr channel
−312 mV offset applied to the Cr channel
+312 mV offset applied to the Cr channel
The DEF_Y[5:0] values define the 6 MSBs of the output video.
The remaining LSBs are padded with 0s. For example, in 8-bit
mode, the output is Y[7:0] = {DEF_Y[5:0], 0, 0}.
0xFF
BRI[7:0] Brightness Adjust, Address 0x0A [7:0]
DEF_Y[5:0] is 0x0D (Blue) is the default value for Y.
Register 0x0C has a default value of 0x36.
This register controls the brightness of the video signal. It allows
the user to adjust the brightness of the picture.
Table 25. BRI Function
DEF_C[7:0] Default Value C, Address 0x0D [7:0]
BRI[7:0]
0x00 (default)
0x7F
Description
The DEF_C[7:0] register complements the DEF_Y[5:0] value. It
defines the 4 MSBs of Cr and Cb values to be output if
Offset of the luma channel = 0IRE.
Offset of the luma channel = 100IRE.
Offset of the luma channel = –100IRE.
0x80
•
The DEF_VAL_AUTO_EN bit is set to high and the
ADV7181B can’t lock to the input video (automatic mode).
•
DEF_VAL_EN bit is set to high (forced output).
The data that is finally output from the ADV7181B for the
chroma side is Cr[7:0] = {DEF_C[7:4], 0, 0, 0, 0}, Cb[7:0] =
{DEF_C[3:0], 0, 0, 0, 0}.
DEF_C[7:0] is 0x7C (blue) is the default value for Cr and Cb.
Rev. 0 | Page 23 of 96
ADV7181B
DEF_VAL_EN Default Value Enable, Address 0x0C [0]
The clamping can be divided into two sections:
•
Clamping before the ADC (analog domain): current
sources.
This bit forces the use of the default values for Y, Cr, and Cb.
Refer to the descriptions for DEF_Y and DEF_C for additional
information. In this mode, the decoder also outputs a stable
27 MHz clock, HS, and VS.
•
Clamping after the ADC (digital domain): digital
processing block.
Setting DEF_VAL_EN to 0 (default) outputs a colored screen
determined by user programmable Y, Cr, and Cb values when
the decoder free-runs. Free-run mode is turned on and off by
the DEF_VAL_AUTO_EN bit.
The ADCs can digitize an input signal only if it resides within
the ADC’s 1.6 V input voltage range. An input signal with a dc
level that is too large or too small is clipped at the top or bottom
of the ADC range.
Setting DEF_VAL_EN to 1 forces a colored screen output
determined by user programmable Y, Cr, and Cb values. This
overrides picture data even if the decoder is locked.
The primary task of the analog clamping circuits is to ensure
that the video signal stays within the valid ADC input window
so that the analog-to-digital conversion can take place. It is not
necessary to clamp the input signal with a very high accuracy in
the analog domain as long as the video signal fits the ADC range.
DEF_VAL_AUTO_EN Default Value Automatic Enable,
Address 0x0C [1]
After digitization, the digital fine clamp block corrects for any
remaining variations in dc level. Since the dc level of an input
video signal refers directly to the brightness of the picture
transmitted, it is important to perform a fine clamp with high
accuracy; otherwise, brightness variations may occur. Further-
more, dynamic changes in the dc level almost certainly lead to
visually objectionable artifacts, and must therefore be prohibited.
This bit enables the automatic use of the default values for Y, Cr,
and Cb when the ADV7181B cannot lock to the video signal.
Setting DEF_VAL_AUTO_EN to 0 disables free-run mode. If
the decoder is unlocked, it outputs noise.
Setting DEF_VAL_EN to 1 (default) enables free-run mode, and
a colored screen set by user programmable Y, Cr and Cb values
is displayed when the decoder loses lock.
The clamping scheme has to complete two tasks. It must be able
to acquire a newly connected video signal with a completely
unknown dc level, and it must maintain the dc level during
normal operation.
CLAMP OPERATION
The input video is ac-coupled into the ADV7181B. Therefore,
its dc value needs to be restored. This process is referred to as
clamping the video. This section explains the general process of
clamping on the ADV7181B, and shows the different ways in
which a user can configure its behavior.
For quickly acquiring an unknown video signal, the large current
clamps may be activated. Note that it is assumed that the ampli-
tude of the video signal at this point is of a nominal value.
Control of the coarse and fine current clamp parameters is
performed automatically by the decoder.
The ADV7181B uses a combination of current sources and a
digital processing block for clamping, as shown in Figure 9. The
analog processing channel shown is replicated three times
inside the IC. While only one single channel (and only one
ADC) would be needed for a CVBS signal, two independent
channels are needed for YC (S-VHS) type signals, and three
independent channels are needed to allow component signals
(YPrPb) to be processed.
Standard definition video signals may have excessive noise on
them. In particular, CVBS signals transmitted by terrestrial
broadcast and demodulated using a tuner usually show very
large levels of noise (>100 mV). A voltage clamp would be
unsuitable for this type of video signal. Instead, the ADV7181B
employs a set of four current sources that can cause coarse
(>0.5 mA) and fine (<0.1 mA) currents to flow into and away
from the high impedance node that carries the video signal (see
Figure 9).
FINE
CURRENT
SOURCES
COARSE
CURRENT
SOURCES
DATA
SDP
WITH DIGITAL
PROCESSOR
FINE CLAMP
(DPP)
ANALOG
VIDEO
INPUT
PRE-
ADC
CLAMP CONTROL
Figure 9. Clamping Overview
Rev. 0 | Page 24 of 96
ADV7181B
The following sections describe the I2C signals that can be used
to influence the behavior of the clamping block.
LUMA FILTER
Data from the digital fine clamp block is processed by three sets
of filters. Note that the data format at this point is CVBS for
CVBS input or luma only for Y/C and YPrPb input formats.
Previous revisions of the ADV7181B had controls (FACL/FICL,
fast and fine clamp length) to allow configuration of the length
for which the coarse (fast) and fine current sources are switched
on. These controls were removed on the ADV7181-FT and
replaced by an adaptive scheme.
•
Luma antialias filter (YAA). The ADV7181B receives video
at a rate of 27 MHz. (In the case of 4× oversampled video,
the ADCs sample at 54 MHz, and the first decimation is
performed inside the DPP filters. Therefore, the data rate
into the ADV7181B is always 27 MHz.) The ITU-R BT.601
recommends a sampling frequency of 13.5 MHz. The luma
antialias filter decimates the oversampled video using a
high quality, linear phase, low-pass filter that preserves the
luma signal while at the same time attenuating out-of-band
components. The luma antialias filter (YAA) has a fixed
response.
CCLEN Current Clamp Enable, Address 0x14 [4]
The current clamp enable bit allows the user to switch off the
current sources in the analog front end altogether. This may be
useful if the incoming analog video signal is clamped externally.
When CCLEN is 0, the current sources are switched off.
When CCLEN is 1 (default), the current sources are enabled.
•
Luma shaping filters (YSH). The shaping filter block is a
programmable low-pass filter with a wide variety of
responses. It can be used to selectively reduce the luma
video signal bandwidth (needed prior to scaling, for
example). For some video sources that contain high
frequency noise, reducing the bandwidth of the luma signal
improves visual picture quality. A follow-on video
compression stage may work more efficiently if the video is
low-pass filtered.
DCT[1:0] Digital Clamp Timing, Address 0x15 [6:5]
The Clamp Timing register determines the time constant of the
digital fine clamp circuitry. It is important to realize that the
digital fine clamp reacts very quickly since it is supposed to
immediately correct any residual dc level error for the active
line. The time constant of the digital fine clamp must be much
quicker than the one from the analog blocks.
By default, the time constant of the digital fine clamp is adjusted
dynamically to suit the currently connected input signal.
The ADV7181B has two responses for the shaping filter:
one that is used for good quality CVBS, component, and S-
VHS type sources, and a second for nonstandard CVBS
signals.
Table 27. DCT Function
DCT[1:0]
Description
00
01
Slow (TC = 1 sec).
Medium (TC = 0.5 sec).
Fast (TC = 0.1 sec).
Determined by ADV7181B, depending on the
input video parameters.
The YSH filter responses also include a set of notches for
PAL and NTSC. However, it is recommended to use the
comb filters for YC separation.
10 (default)
11
•
Digital resampling filter. This block is used to allow dynamic
resampling of the video signal to alter parameters such as
the time base of a line of video. Fundamentally, the resam-
pler is a set of low-pass filters. The actual response is chosen
by the system with no requirement for user intervention.
DCFE Digital Clamp Freeze Enable, Address 0x15 [4]
This register bit allows the user to freeze the digital clamp loop
at any time. It is intended for users who would like to do their
own clamping. Users should disable the current sources for
analog clamping via the appropriate register bits, wait until the
digital clamp loop settles, and then freeze it via the DCFE bit.
Figure 11 through Figure 14 show the overall response of all
filters together. Unless otherwise noted, the filters are set into a
typical wideband mode.
When DCFE to 0 (default), the digital clamp is operational .
When DCFE is 1, the digital clamp loop is frozen.
Rev. 0 | Page 25 of 96
ADV7181B
Y Shaping Filter
In automatic mode, the system preserves the maximum possible
bandwidth for good CVBS sources (since they can successfully
be combed) as well as for luma components of YPrPb and YC
sources, since they need not be combed. For poor quality
signals, the system selects from a set of proprietary shaping
filter responses that complements comb filter operation in order
to reduce visual artifacts.
For input signals in CVBS format, the luma shaping filters play
an essential role in removing the chroma component from a
composite signal. YC separation must aim for best possible
crosstalk reduction while still retaining as much bandwidth
(especially on the luma component) as possible. High quality
YC separation can be achieved by using the internal comb filters
of the ADV7181B. Comb filtering, however, relies on the
frequency relationship of the luma component (multiples of the
video line rate) and the color subcarrier (Fsc). For good quality
CVBS signals, this relationship is known; the comb filter
algorithms can be used to separate out luma and chroma with
high accuracy.
The decisions of the control logic are shown in Figure 10.
YSFM[4:0] Y Shaping Filter Mode, Address 0x17 [4:0]
The Y shaping filter mode bits allow the user to select from a
wide range of low-pass and notch filters. When switched in
automatic mode, the filter is selected based on other register
selections, for example, detected video standard, as well as
properties extracted from the incoming video itself, for
example, quality, time base stability. The automatic selection
always picks the widest possible bandwidth for the video input
encountered.
In the case of nonstandard video signals, the frequency
relationship may be disturbed and the comb filters may not be
able to remove all crosstalk artifacts in an optimum fashion
without the assistance of the shaping filter block.
An automatic mode is provided. Here, the ADV7181B evaluates
the quality of the incoming video signal and selects the filter
responses in accordance with the signal quality and video
standard. YFSM, WYSFMOVR, and WYSFM allow the user to
manually override the automatic decisions in part or in full.
•
If the YSFM settings specify a filter (i.e., YSFM is set to
values other than 00000 or 00001), the chosen filter is
applied to all video, regardless of its quality.
The luma shaping filter has three control registers:
•
In automatic selection mode, the notch filters are only used
for bad quality video signals. For all other video signals,
wideband filters are used.
•
YSFM[4:0] allows the user to manually select a shaping
filter mode (applied to all video signals) or to enable an
automatic selection (dependent on video quality and video
standard).
WYSFMOVR Wideband Y Shaping Filter Override,
Address 0x18,[7]
•
•
WYSFMOVR allows the user to manually override the
WYSFM decision.
Setting the WYSFMOVR bit enables the use of the WYSFM[4:0]
settings for good quality video signals. For more information,
refer to the general discussion of the luma shaping filters in the
Y Shaping Filter section and the flowchart shown in Figure 10.
WYSFM[4:0] allows the user to select a different shaping
filter mode for good quality CVBS, component (YPrPb),
and S-VHS (YC) input signals.
When WYSFMOVR is 0, the shaping filter for good quality
video signals is selected automatically.
Setting WYSFMOVR to 1 (default) enables manual override via
WYSFM[4:0].
Rev. 0 | Page 26 of 96
ADV7181B
SET YSFM
YSFM IN AUTO MODE?
00000 OR 00001
YES
NO
VIDEO
QUALITY
BAD
GOOD
USE YSFM SELECTED
FILTER REGARDLESS FOR
GOOD AND BAD VIDEO
AUTO SELECT LUMA
SHAPING FILTER TO
COMPLEMENT COMB
WYSFMOVR
1
0
SELECT WIDEBAND
FILTER AS PER
WYSFM[4:0]
SELECT AUTOMATIC
WIDEBAND FILTER
Figure 10. YSFM and WYSFM Control Flowchart
Table 28. YSFM Function
YSFM[4:0] Description
WYSFM[4:0] Wide Band Y Shaping Filter Mode,
Address 0x18 [4:0]
0'0000
Automatic selection including a wide notch
response (PAL/NTSC/SECAM)
Automatic selection including a narrow notch
response (PAL/NTSC/SECAM)
SVHS 1
SVHS 2
SVHS 3
SVHS 4
SVHS 5
SVHS 6
SVHS 7
SVHS 8
SVHS 9
SVHS 10
SVHS 11
SVHS 12
SVHS 13
SVHS 14
SVHS 15
SVHS 16
SVHS 17
SVHS 18 (CCIR 601)
PAL NN 1
PAL NN 2
PAL NN 3
PAL WN 1
PAL WN 2
NTSC NN 1
NTSC NN 2
NTSC NN 3
NTSC WN 1
NTSC WN 2
NTSC WN 3
Reserved
The WYSFM[4:0] bits allow the user to manually select a
shaping filter for good quality video signals, for example, CVBS
with stable time base, luma component of YPrPb, luma
component of YC. The WYSFM bits are only active if the
WYSFMOVR bit is set to 1. See the general discussion of the
shaping filter settings in the Y Shaping Filter section.
0'0001
(default)
0'0010
0'0011
0'0100
0'0101
0'0110
0'0111
0'1000
0'1001
0'1010
0'1011
0'1100
0'1101
0'1110
0'1111
1'0000
1'0001
1'0010
1'0011
1'0100
1'0101
1'0110
1'0111
1'1000
1'1001
1'1010
1'1011
1'1100
1'1101
1'1110
1'1111
Table 29. WYSFM Function
WYSFM[4:0]
Description
Do not use
Do not use
SVHS 1
0'0000
0'0001
0'0010
0'0011
SVHS 2
0'0100
SVHS 3
0'0101
SVHS 4
0'0110
SVHS 5
0'0111
SVHS 6
0'1000
SVHS 7
0'1001
SVHS 8
0'1010
SVHS 9
0'1011
0'1100
0'1101
0'1110
0'1111
1'0000
1'0001
1'0010
SVHS 10
SVHS 11
SVHS 12
SVHS 13
SVHS 14
SVHS 15
SVHS 16
SVHS 17
SVHS 18 (CCIR 601)
Do not use
1'0011 (default)
1'0100–1’1111
Rev. 0 | Page 27 of 96
ADV7181B
v740a COMBINED Y ANTIALIAS, S-VHS LOW-PASS FILTERS,
Y RESAMPLE
v740a COMBINED Y ANTIALIAS, NTSC NOTCH FILTERS,
Y RESAMPLE
0
–10
–20
–30
–40
–50
–60
–70
0
–10
–20
–30
–40
–50
–60
–70
0
2
4
6
8
10
12
FREQUENCY (MHz)
0
2
4
6
8
10
12
FREQUENCY (MHz)
Figure 11. Y S-VHS Combined Responses
Figure 14. Y S-VHS 18 Extra Wideband Filter (601)
The filter plots in Figure 11 show the S-VHS 1 (narrowest) to
S-VHS 18 (widest) shaping filter settings. Figure 13 shows the
PAL notch filter responses. The NTSC-compatible notches are
shown in Figure 14.
CHROMA FILTER
Data from the digital fine clamp block is processed by three sets
of filters. Note that the data format at this point is CVBS for
CVBS inputs, chroma only for Y/C, or U/V interleaved for
YPrPb input formats.
v740a COMBINED Y ANTIALIAS, CCIR MODE SHAPING FILTER,
Y RESAMPLE
0
–20
•
Chroma Antialias Filter (CAA). The ADV7181B over-
samples the CVBS by a factor of 2 and the Chroma/PrPb
by a factor of 4. A decimating filter (CAA) is used to
preserve the active video band and to remove any out-of-
band components. The CAA filter has a fixed response.
–40
–60
•
•
Chroma Shaping Filters (CSH). The shaping filter block
(CSH) can be programmed to perform a variety of low-
pass responses. It can be used to selectively reduce the
bandwidth of the chroma signal for scaling or compression.
–80
–100
–120
0
2
4
6
8
10
12
Digital Resampling Filter. This block is used to allow
dynamic resampling of the video signal to alter parameters
such as the time base of a line of video. Fundamentally, the
resampler is a set of low-pass filters. The actual response is
chosen by the system without user intervention.
FREQUENCY (MHz)
Figure 12.Y S-VHS 18 Extra Wideband Filter (CCIR 601 Compliant)
v740a COMBINED Y ANTIALIAS, PAL NOTCH FILTERS,
Y RESAMPLE
The plots in Figure 15 show the overall response of all filters
together.
0
–10
–20
–30
–40
–50
–60
–70
0
2
4
6
8
10
12
FREQUENCY (MHz)
Figure 13.Y S-VHS 18 Extra Wideband Filter (CCIR 601 Compliant)
Rev. 0 | Page 28 of 96
ADV7181B
CSFM[2:0] C Shaping Filter Mode, Address 0x17 [7]
GAIN OPERATION
The gain control within the ADV7181B is done on a purely
digital basis. The input ADCs support a 9-bit range, mapped
into a 1.6 V analog voltage range. Gain correction takes place
after the digitization in the form of a digital multiplier.
The C shaping filter mode bits allow the user to select from a
range of low-pass filters for the chrominance signal. When
switched in automatic mode, the widest filter is selected based
on the video standard/format and user choice (see settings 000
and 001 in Table 30).
Advantages of this architecture over the commonly used PGA
(programmable gain amplifier) before the ADC include the fact
that the gain is now completely independent of supply,
temperature, and process variations.
Table 30. CSFM Function
CSFM[2:0]
000 (default)
001
Description
Autoselect 1.5 MHz bandwidth
Autoselect 2.17 MHz bandwidth
As shown in Figure 16, the ADV7181B can decode a video
signal as long as it fits into the ADC window. The components
to this are the amplitude of the input signal and the dc level it
resides on. The dc level is set by the clamping circuitry (see the
Clamp Operation section).
010
SH1
011
SH2
100
SH3
101
SH4
110
SH5
111
Wideband mode
If the amplitude of the analog video signal is too high, clipping
may occur, resulting in visual artifacts. The analog input range
of the ADC, together with the clamp level, determines the
maximum supported amplitude of the video signal.
v740a COMBINED C ANTIALIAS, C SHAPING FILTER,
C RESAMPLER
0
–10
–20
–30
–40
–50
The minimum supported amplitude of the input video is
determined by the ADV7181B’s ability to retrieve horizontal
and vertical timing and to lock to the color burst, if present.
There are separate gain control units for luma and chroma data.
Both can operate independently of each other. The chroma unit,
however, can also take its gain value from the luma path.
The possible AGC modes are summarized in Table 31.
It is possible to freeze the automatic gain control loops. This
causes the loops to stop updating and the AGC determined gain
at the time of the freeze to stay active until the loop is either
unfrozen or the gain mode of operation is changed.
–60
0
1
2
3
4
5
6
FREQUENCY (MHz)
Figure 15. Chroma Shaping Filter Responses
The currently active gain from any of the modes can be read
back. Refer to the description of the dual-function manual gain
registers, LG[11:0] Luma Gain and CG[11:0] Chroma Gain, in
the Luma Gain and the Chroma Gain sections.
Figure 15 shows the responses of SH1 (narrowest) to SH5
(widest) in addition to the wideband mode (in red).
ANALOG VOLTAGE
RANGE SUPPORTED BY ADC (1.6V RANGE FOR ADV7181B)
MAXIMUM
VOLTAGE
SDP
(GAIN SELECTION ONLY)
DATA
PRE-
ADC
PROCESSOR
(DPP)
GAIN
CONTROL
MINIMUM
VOLTAGE
CLAMP
LEVEL
Figure 16. Gain Control Overview
Rev. 0 | Page 29 of 96
ADV7181B
Table 31. AGC Modes
Input Video Type
Luma Gain
Chroma Gain
Any
Manual gain luma.
Manual gain chroma.
CVBS
Dependent on horizontal sync depth.
Dependent on color burst amplitude.
Taken from luma path.
Peak White.
Dependent on color burst amplitude.
Taken from luma path.
Y/C
Dependent on horizontal sync depth.
Peak White.
Dependent on color burst amplitude.
Taken from luma path.
Dependent on color burst amplitude.
Taken from luma path.
YPrPb
Dependent on horizontal sync depth.
Taken from luma path.
Luma Gain
Table 33. LAGT Function
LAGT[1:0]
Description
LAGC[2:0] Luma Automatic Gain Control, Address 0x30 [7:0]
00
01
10
Slow (TC = 2 sec)
Medium (TC = 1 sec)
Fast (TC = 0.2 sec)
Adaptive
The luma automatic gain control mode bits select the mode of
operation for the gain control in the luma path.
11 (default)
There are ADI internal parameters to customize the peak white
gain control. Contact ADI for more information.
LG[11:0] Luma Gain, Address 0x2F [3:0];
Address 0x30 [7:0]; LMG[11:0] Luma Manual Gain,
Address 0x2F [3:0]; Address 0x30 [7:0]
Table 32. LAGC Function
LAGC[2:0]
Description
000
Manual fixed gain (use LMG[11:0]).
001
AGC (blank level to sync tip). No override through
peak white.
Luma gain [11:0] is a dual-function register. If written to, a
desired manual luma gain can be programmed. This gain
becomes active if the LAGC[2:0] mode is switched to manual
fixed gain. Equation 1 shows how to calculate a desired gain.
010(default) AGC (blank level to sync tip). Automatic override
through peak white.
011
100
101
110
111
Reserved.
Reserved.
Reserved.
Reserved.
Freeze gain.
If read back, this register returns the current gain value.
Depending on the setting in the LAGC[2:0] bits, this is one of
the following values:
•
Luma manual gain value (LAGC[2:0] set to luma manual
gain mode)
LAGT[1:0] Luma Automatic Gain Timing, Address 0x2F [7:6]
•
Luma automatic gain value (LAGC[2:0] set to any of the
automatic modes)
The luma automatic gain timing register allows the user to
influence the tracking speed of the luminance automatic gain
control. Note that this register only has an effect if the
LAGC[2:0] register is set to 001, 010, 011, or 100 (automatic
gain control modes).
Table 34. LG/LMG Function
LG[11:0]/LMG[11:0] Read/Write Description
LMG[11:0] = X
Write
Manual gain for luma
path.
LG[11:0]
Read
Actually used gain.
If peak white AGC is enabled and active (see the
STATUS_1[7:0] Address 0x10 [7:0] section), the actual gain
update speed is dictated by the peak white AGC loop and, as a
result, the LAGT settings have no effect. As soon as the part
leaves peak white AGC, LAGT becomes relevant again.
(
0 < LG ≤ 4095
)
Luma _ Gain =
= 0...2
(1)
2048
The update speed for the peak white algorithm can be
customized by the use of internal parameters. Contact ADI for
more information.
Rev. 0 | Page 30 of 96
ADV7181B
For example, program the ADV7181B into manual fixed gain
mode with a desired gain of 0.89.
PW_UPD Peak White Update, Address 0x2B [0]
The peak white and average video algorithms determine the
gain based on measurements taken from the active video. The
PW_UPD bit determines the rate of gain change. LAGC[2:0]
must be set to the appropriate mode to enable the peak white or
average video mode in the first place. For more information,
refer to the LAGC[2:0] Luma Automatic Gain Control, Address
0x30 [7:0] section.
1. Use Equation 1 to convert the gain:
0.89 × 2048 = 1822.72
2. Truncate to integer value:
1822.72 = 1822
3. Convert to hexadecimal:
1822d = 0x71E
Setting PW_UPD to 0 updates the gain once per video line.
4. Split into two registers and program:
Luma Gain Control 1 [3:0] = 0x7
Luma Gain Control 2 [7:0] = 0x1E
Setting PW_UPD to 1 (default) updates the gain once per field.
Chroma Gain
5. Enable Manual Fixed Gain Mode:
Set LAGC[2:0] to 000
CAGC[1:0] Chroma Automatic Gain Control,
Address 0x2C [1:0]
BETACAM Enable Betacam Levels, Address 0x01 [5]
The two bits of Color Automatic Gain Control mode select the
basic mode of operation for automatic gain control in the
chroma path.
If YPrPb data is routed through the ADV7181B, the automatic
gain control modes can target different video input levels, as
outlined in Table 41. Note that the BETACAM bit is valid only if
the input mode is YPrPb (component). The BETACAM bit
basically sets the target value for AGC operation.
Table 36. CAGC Function
CAGC[1:0]
Description
00
01
Manual fixed gain (use CMG[11:0]).
Use luma gain for chroma.
Automatic gain (based on color burst).
Freeze chroma gain.
A review of the following sections is useful:
10 (default)
11
•
•
SETADC_sw_man_en, Manual Input Muxing Enable,
Address C4 [7] to find how component video (YPrPb) can
be routed through the ADV7181B.
CAGT[1:0] Chroma Automatic Gain Timing,
Address 0x2D [7:6]
Video Standard Selection to select the various standards,
for example, with and without pedestal.
The Chroma Automatic Gain Timing register allows the user to
influence the tracking speed of the chroma automatic gain
control. This register has an effect only if the CAGC[1:0]
register is set to 10 (automatic gain).
The automatic gain control (AGC) algorithms adjust the levels
based on the setting of the BETACAM bit (see Table 35.).
Table 35. BETACAM Function
BETACAM Description
Table 37. CAGT Function
0 (default) Assuming YPrPb is selected as input format.
Selecting PAL with pedestal selects MII.
Selecting PAL without pedestal selects SMPTE.
Selecting NTSC with pedestal selects MII.
Selecting NTSC without pedestal selects SMPTE.
CAGT[1:0]
Description
00
01
10
Slow (TC = 2 sec)
Medium (TC = 1 sec)
Fast (TC = 0.2 sec)
Adaptive
11 (default)
1
Assuming YPrPb is selected as input format.
Selecting PAL with pedestal selects BETACAM.
Selecting PAL without pedestal selects BETACAM
variant.
Selecting NTSC with pedestal selects BETACAM.
Selecting NTSC without pedestal selects BETACAM
variant.
Table 38. Betacam Levels
Name
Betacam (mV)
Betacam Variant (mV)
SMPTE (mV)
0 to 700
–350 to +350
300
MII (mV)
Y Range
Pb and Pr Range
Sync Depth
0 to 714 (incl. 7.5% pedestal)
–467 to +467
286
0 to 714
–505 to +505
286
0 to 700 (incl. 7.5% pedestal)
–324 to +324
300
Rev. 0 | Page 31 of 96
ADV7181B
CG[11:0] Chroma Gain, Address 0x2D [3:0]; Address 0x2E [7:0]
CMG[11:0] Chroma Manual Gain, Address 0x2D [3:0];
Address 0x2E [7:0]
CKILLTHR[2:0] Color Kill Threshold,
Address 0x3D [6:4]
The CKILLTHR[2:0] bits allow the user to select a threshold for
the color kill function. The threshold applies to only QAM-
based (NTSC and PAL) or FM-modulated (SECAM) video
standards.
Chroma gain [11:0] is a dual-function register. If written to, a
desired manual chroma gain can be programmed. This gain
becomes active if the CAGC[1:0] mode is switched to manual
fixed gain. Refer to Equation 2 for calculating a desired gain.
To enable the color kill function, the CKE bit must be set. For
settings 000, 001, 010, and 011, chroma demodulation inside the
ADV7181B may not work satisfactorily for poor input video
signals.
If read back, this register returns the current gain value.
Depending on the setting in the CAGC[1:0] bits, this is either:
•
•
Chroma manual gain value (CAGC[1:0] set to chroma
manual gain mode).
Table 40. CKILLTHR Function
Description
Chroma automatic gain value (CAGC[1:0] set to any of the
automatic modes).
CKILLTHR[2:0] SECAM
NTSC, PAL
000
No color kill
Kill at < 0.5%
Kill at < 1.5%
Kill at < 2.5%
Kill at < 4.0%
Kill at < 8.5%
Kill at < 16.0%
Kill at < 32.0%
001
010
011
100 (default)
101
Kill at < 5%
Kill at < 7%
Kill at < 8%
Kill at < 9.5%
Kill at < 15%
Kill at < 32%
Table 39. CG/CMG Function
CG[11:0]/CMG[11:0] Read/Write Description
CMG[11:0]
Write
Manual gain for chroma
path.
CG[11:0]
Read
Currently active gain.
110
111
Reserved for ADI internal use only. Do not
select.
(
0 < CG ≤ 4095
)
Chroma _ Gain =
= 0...4
(2)
1024
CHROMA TRANSIENT IMPROVEMENT (CTI)
For example, freezing the automatic gain loop and reading back
the CG[11:0] register results in a value of 0x47A.
The signal bandwidth allocated for chroma is typically much
smaller than that of luminance. In the past, this was a valid way
to fit a color video signal into a given overall bandwidth because
the human eye is less sensitive to chrominance than to
luminance.
1. Convert the readback value to decimal:
0x47A = 1146d
2. Apply Equation 2 to convert the readback value:
1146/1024 = 1.12
The uneven bandwidth, however, may lead to visual artifacts in
sharp color transitions. At the border of two bars of color, both
components (luma and chroma) change at the same time (see
Figure 17). Due to the higher bandwidth, the signal transition of
the luma component is usually a lot sharper than that of the
chroma component. The color edge is not sharp but blurred, in
the worst case, over several pixels.
CKE Color Kill Enable, Address 0x2B [6]
The Color Kill Enable bit allows the optional color kill function
to be switched on or off.
For QAM-based video standards (PAL and NTSC) as well as
FM based systems (SECAM), the threshold for the color kill
decision is selectable via the CKILLTHR[2:0] bits.
LUMA SIGNAL WITH A
If color kill is enabled, and if the color carrier of the incoming
video signal is less than the threshold for 128 consecutive video
lines, color processing is switched off (black and white output).
To switch the color processing back on, another 128 consecutive
lines with a color burst greater than the threshold are required.
TRANSITION, ACCOMPANIED
LUMA
BY A CHROMA TRANSITION
SIGNAL
ORIGINAL, "SLOW" CHROMA
TRANSITION PRIOR TO CTI
DEMODULATED
CHROMA
SHARPENED CHROMA
TRANSITION AT THE
OUTPUT OF CTI
SIGNAL
The color kill option only works for input signals with a
modulated chroma part. For component input (YPrPb), there is
no color kill.
Figure 17. CTI Luma/Chroma Transition
Setting CKE to 0 disables color kill.
Setting CKE to 1 (default) enables color kill.
Rev. 0 | Page 32 of 96
ADV7181B
The chroma transient improvement block examines the input
video data. It detects transitions of chroma, and can be
programmed to “steepen” the chroma edges in an attempt to
artificially restore lost color bandwidth. The CTI block,
however, operates only on edges above a certain threshold to
ensure that noise is not emphasized. Care has also been taken to
ensure that edge ringing and undesirable saturation or hue
distortion are avoided.
Table 41. CTI_AB Function
CTI_AB[1:0] Description
00
Sharpest mixing between sharpened and original
chroma signal.
01
Sharp mixing.
10
Smooth mixing.
11 (default)
Smoothest alpha blend function.
Chroma transient improvements are needed primarily for
signals that experienced severe chroma bandwidth limitations.
For those types of signals, it is strongly recommended to enable
the CTI block via CTI_EN.
CTI_C_TH[7:0] CTI Chroma Threshold,
Address 0x4E [7:0]
The CTI_C_TH[7:0] value is an unsigned, 8-bit number speci-
fying how big the amplitude step in a chroma transition has to
be in order to be steepened by the CTI block. Programming a
small value into this register causes even smaller edges to be
steepened by the CTI block. Making CTI_C_TH[7:0] a large
value causes the block to improve large transitions only.
CTI_EN Chroma Transient Improvement Enable,
Address 0x4D [0]
Setting CTI_EN to 0 disables the CTI block.
Setting CTI_EN to 1 (default) enables the CTI block.
The default value for CTI_C_TH[7:0] is 0x08, indicating the
threshold for the chroma edges prior to CTI.
CTI_AB_EN Chroma Transient Improvement
lpha Blend Enable, Address 0x4D [1]
DIGITAL NOISE REDUCTION (DNR)
Digital noise reduction is based on the assumption that high
frequency signals with low amplitude are probably noise and
that their removal, therefore, improves picture quality.
The CTI_AB_EN bit enables an alpha-blend function within
the CTI block. If set to 1, the alpha blender mixes the transient
improved chroma with the original signal. The sharpness of the
alpha blending can be configured via the CTI_AB[1:0] bits.
DNR_EN Digital Noise Reduction Enable,
Address 0x4D [5]
For the alpha blender to be active, the CTI block must be
enabled via the CTI_EN bit.
The DNR_EN bit enables the DNR block or bypasses it.
Setting DNR_EN to 0 bypasses DNR (disables it).
Setting CTI_AB_EN to 0 disables the CTI alpha blender.
Setting CTI_AB_EN to 1 (default) enables the CTI alpha-blend
mixing function.
Setting DNR_EN to 1 (default) enables digital noise reduction
on the luma data.
CTI_AB[1:0] Chroma Transient Improvement Alpha Blend,
Address 0x4D [3:2]
DNR_TH[7:0] DNR Noise Threshold, Address 0x50 [7:0]
The DNR_TH[7:0] value is an unsigned 8-bit number used to
determine the maximum edge that is interpreted as noise and
therefore blanked from the luma data. Programming a large
value into DNR_TH[7:0] causes the DNR block to interpret
even large transients as noise and remove them. The effect on
the video data is, therefore, more visible.
The CTI_AB[1:0] controls the behavior of alpha blend circuitry
that mixes the sharpened chroma signal with the original one. It
thereby controls the visual impact of CTI on the output data.
For CTI_AB[1:0] to become active, the CTI block must be
enabled via the CTI_EN bit, and the alpha blender must be
switched on via CTI_AB_EN.
Programming a small value causes only small transients to be
seen as noise and to be removed.
Sharp blending maximizes the effect of CTI on the picture, but
may also increase the visual impact of small amplitude, high
frequency chroma noise.
The recommended DNR_TH[7:0] setting for A/V inputs is
0x04, and the recommended DNR_TH[7:0] setting for tuner
inputs is 0x0A.
The default value for DNR_TH[7:0] is 0x08, indicating the
threshold for maximum luma edges to be interpreted as noise.
Rev. 0 | Page 33 of 96
ADV7181B
Table 42. NSFSEL Function
NSFSEL[1:0]
COMB FILTERS
Description
Narrow
Medium
Medium
Wide
The comb filters of the ADV7181B have been greatly improved
to automatically handle video of all types, standards, and levels
of quality. The NTSC and PAL configuration registers allow the
user to customize comb filter operation, depending on which
video standard is detected (by autodetection) or selected (by
manual programming). In addition to the bits listed in this
section, there are some further ADI internal controls; contact
ADI for more information.
00 (default)
01
10
11
CTAPSN[1:0] Chroma Comb Taps NTSC,
Address 0x38 [7:6]
NTSC Comb Filter Settings
Table 43. CTAPSN Function
Used for NTSC-M/J CVBS inputs.
CTAPSN[1:0]
Description
00
01
Do not use.
NSFSEL[1:0] Split Filter Selection NTSC, Address 0x19 [3:2]
NTSC chroma comb adapts 3 lines (3 taps) to 2
lines (2 taps).
NTSC chroma comb adapts 5 lines (5 taps) to 3
lines (3 taps).
NTSC chroma comb adapts 5 lines (5 taps) to 4
lines (4 taps).
The NSFSEL[1:0] control selects how much of the overall signal
bandwidth is fed to the combs. A narrow split filter selection
gives better performance on diagonal lines, but leaves more dot
crawl in the final output image. The opposite is true for selecting
a wide bandwidth split filter.
10 (default)
11
CCMN[2:0] Chroma Comb Mode NTSC, Address 0x38 [5:3]
Table 44. CCMN Function
CCMN[2:0]
Description
Configuration
0xx (default)
Adaptive comb mode.
Adaptive 3-line chroma comb for CTAPSN = 01.
Adaptive 4-line chroma comb for CTAPSN = 10.
Adaptive 5-line chroma comb for CTAPSN = 11.
100
101
Disable chroma comb.
Fixed chroma comb (top lines of line memory).
Fixed 2-line chroma comb for CTAPSN = 01.
Fixed 3-line chroma comb for CTAPSN = 10.
Fixed 4-line chroma comb for CTAPSN = 11.
Fixed 3-line chroma comb for CTAPSN = 01.
Fixed 4-line chroma comb for CTAPSN = 10.
Fixed 5-line chroma comb for CTAPSN = 11.
Fixed 2-line chroma comb for CTAPSN = 01.
Fixed 3-line chroma comb for CTAPSN = 10.
Fixed 4-line chroma comb for CTAPSN = 11.
110
111
Fixed chroma comb (all lines of line memory).
Fixed chroma comb (bottom lines of line memory).
YCMN[2:0] Luma Comb Mode NTSC, Address 0x38 [2:0]
Table 45. YCMN Function
YCMN[2:0]
0xx (default)
100
101
110
Description
Configuration
Adaptive comb mode.
Disable luma comb.
Fixed luma comb (top lines of line memory).
Fixed luma comb (all lines of line memory).
Fixed luma comb (bottom lines of line memory).
Adaptive 3-line (3 taps) luma comb.
Use low-pass/notch filter; see the Y Shaping Filter section.
Fixed 2-line (2 taps) luma comb.
Fixed 3-line (3 taps) luma comb.
Fixed 2-line (2 taps) luma comb.
111
Rev. 0 | Page 34 of 96
ADV7181B
PAL Comb Filter Settings
Table 46. PSFSEL Function
PSFSEL[1:0]
Description
Narrow
Medium
Wide
Used for PAL-B/G/H/I/D, PAL-M, PAL-Combinational N,
PAL-60, and NTSC443 CVBS inputs.
00
01 (default)
10
11
PSFSEL[1:0] Split Filter Selection PAL, Address 0x19 [1:0]
Widest
The NSFSEL[1:0] control selects how much of the overall signal
bandwidth is fed to the combs. A wide split filter selection
eliminates dot crawl, but shows imperfections on diagonal lines.
The opposite is true for selecting a narrow bandwidth split filter.
CTAPSP[1:0] Chroma Comb Taps PAL, Address 0x39 [7:6]
Table 47. CTAPSP Function
CTAPSP[1:0]
Description
00
01
Do not use.
PAL chroma comb adapts 5 lines (3 taps) to
3 lines (2 taps); cancels cross luma only.
10
PAL chroma comb adapts 5 lines (5 taps) to
3 lines (3 taps); cancels cross luma and hue error less well.
11 (default)
PAL chroma comb adapts 5 lines (5 taps) to
4 lines (4 taps); cancels cross luma and hue error well.
CCMP[2:0] Chroma Comb Mode PAL, Address 0x39 [5:3]
Table 48. CCMP Function
CCMP[2:0]
Description
Configuration
0xx (default)
Adaptive comb mode.
Adaptive 3-line chroma comb for CTAPSP = 01.
Adaptive 4-line chroma comb for CTAPSP = 10.
Adaptive 5-line chroma comb for CTAPSP = 11.
100
101
Disable chroma comb.
Fixed chroma comb (top lines of line memory).
Fixed 2-line chroma comb for CTAPSP = 01.
Fixed 3-line chroma comb for CTAPSP = 10.
Fixed 4-line chroma comb for CTAPSP = 11.
Fixed 3-line chroma comb for CTAPSP = 01.
Fixed 4-line chroma comb for CTAPSP = 10.
Fixed 5-line chroma comb for CTAPSP = 11.
Fixed 2-line chroma comb for CTAPSP = 01.
Fixed 3-line chroma comb for CTAPSP = 10.
Fixed 4-line chroma comb for CTAPSP = 11.
110
111
Fixed chroma comb (all lines of line memory).
Fixed chroma comb (bottom lines of line memory).
YCMP[2:0] Luma Comb Mode PAL, Address 0x39 [2:0]
Table 49. YCMP Function
YCMP[2:0]
0xx (default)
100
101
110
Description
Configuration
Adaptive comb mode.
Disable luma comb.
Fixed luma comb (top lines of line memory).
Fixed luma comb (all lines of line memory).
Fixed luma comb (bottom lines of line memory).
Adaptive 5 lines (3 taps) luma comb.
Use low-pass/notch filter; see the Y Shaping Filter section.
Fixed 3 lines (2 taps) luma comb.
Fixed 5 lines (3 taps) luma comb.
Fixed 3 lines (2 taps) luma comb.
111
Rev. 0 | Page 35 of 96
ADV7181B
AV CODE INSERTION AND CONTROLS
This section describes the I2C based controls that affect
In an 8-bit-wide output interface (Cb/Y/Cr/Y interleaved data),
the AV codes are defined as FF/00/00/AV, with AV being the
transmitted word that contains information about H/V/F.
•
•
•
Insertion of AV codes into the data stream.
Data blanking during the vertical blank interval (VBI).
In this output interface mode, the following assignment takes
place: Cb = FF, Y = 00, Cr = 00, and Y = AV.
The range of data values permitted in the output data
stream.
In a 16-bit output interface where Y and Cr/Cb are delivered via
separate data buses, the AV code is over the whole 16 bits. The
SD_DUP_AV bit allows the user to replicate the AV codes on
both busses, so the full AV sequence can be found on the Y bus
as well as on the Cr/Cb bus. See Figure 18.
•
The relative delay of luma versus chroma signals.
Note that some of the decoded VBI data is being inserted
during the horizontal blanking interval. See the Gemstar Data
Recovery section for more information.
When SD_DUP_AV is 0 (default), the AV codes are in single
fashion (to suit 8-bit interleaved data output).
BT656-4 ITU Standard BT-R.656-4 Enable, Address 0x04 [7]
When SD_DUP_AV is 1, the AV codes are duplicated (for
16-bit interfaces).
The ITU has changed the position for toggling of the V bit
within the SAV EAV codes for NTSC between revisions 3 and 4.
The BT656-4 standard bit allows the user to select an output
mode that is compliant with either the previous or the new
standard. For further information, review the standard at
http://www.itu.int.
VBI_EN Vertical Blanking Interval Data Enable,
Address 0x03 [7]
The VBI enable bit allows data such as intercast and closed
caption data to be passed through the luma channel of the
decoder with a minimal amount of filtering. All data for Lines 1
to 21 is passed through and available at the output port. The
ADV7181B does not blank the luma data, and automatically
switches all filters along the luma data path into their widest
bandwidth. For active video, the filter settings for YSH and YPK
are restored.
Note that the standard change affects NTSC only and has no
bearing on PAL.
When BT656-4 is 0 (default), the BT656-3 specification is used.
The V bit goes low at EAV of Lines 10 and 273.
When BT656-4 is 1, the BT656-4 specification is used. The V bit
goes low at EAV of Lines 20 and 283.
Refer to the BL_C_VBI Blank Chroma during VBI section for
information on the chroma path.
SD_DUP_AV Duplicate AV codes, Address 0x03 [0]
When VBI_EN is 0 (default), all video lines are filtered/scaled.
Depending on the output interface width, it may be necessary to
duplicate the AV codes from the luma path into the chroma path.
When VBI_EN is 1, only the active video region is
filtered/scaled.
SD_DUP_AV = 1
SD_DUP_AV = 0
16-BIT INTERFACE
16-BIT INTERFACE
AV
8-BIT INTERFACE
Y DATA BUS
FF
FF
00
00
AV
AV
Y
00
Y
Cb/Y/Cr/Y
INTERLEAVED
FF
00
00
AV
Cb
Cr/Cb DATA BUS
00
00
Cb
FF
00
Cb
AV CODE SECTION
AV CODE SECTION
AV CODE SECTION
Figure 18. AV Code Duplication Control
Rev. 0 | Page 36 of 96
ADV7181B
BL_C_VBI Blank Chroma during VBI, Address 0x04 [2]
LTA[1:0] Luma Timing Adjust, Address 0x27 [1:0]
Setting BL_C_VBI high, the Cr and Cb values of all VBI lines
are blanked. This is done so any data that may arrive during VBI
is not decoded as color and output through Cr and Cb. As a
result, it is possible to send VBI lines into the decoder, then
output them through an encoder again, undistorted. Without
this blanking, any wrongly decoded color is encoded by the
video encoder; therefore, the VBI lines are distorted.
The Luma Timing Adjust register allows the user to specify a
timing difference between chroma and luma samples.
Note that there is a certain functionality overlap with the
CTA[2:0] register. For manual programming, use the following
defaults:
•
•
•
CVBS input LTA[1:0] = 00.
YC input LTA[1:0] = 01.
YPrPb input LTA[1:0] =01.
Setting BL_C_VBI to 0 decodes and outputs color during VBI.
Setting BL_C_VBI to 1 (default) blanks Cr and Cb values
during VBI.
Table 51. LTA Function
LTA[1:0]
Description
RANGE Range Selection, Address 0x04 [0]
00 (default)
No delay.
AV codes (as per ITU-R BT-656, formerly known as CCIR-656)
consist of a fixed header made up of 0xFF and 0x00 values.
These two values are reserved and therefore are not to be used
for active video. Additionally, the ITU specifies that the nominal
range for video should be restricted to values between 16 and
235 for luma and 16 to 240 for chroma.
01
10
11
Luma 1 clk (37 ns) delayed.
Luma 2clk (74 ns) early.
Luma 1 clk (37 ns) early.
CTA[2:0] Chroma Timing Adjust, Address 0x27 [5:3]
The RANGE bit allows the user to limit the range of values
output by the ADV7181B to the recommended value range. In
any case, it ensures that the reserved values of 255d (0xFF) and
00d (0x00) are not presented on the output pins unless they are
part of an AV code header.
The Chroma Timing Adjust register allows the user to specify a
timing difference between chroma and luma samples. This may
be used to compensate for external filter group delay differences
in the luma versus chroma path, and to allow a different number
of pipeline delays while processing the video downstream.
Review this functionality together with the LTA[1:0] register.
Table 50. RANGE Function
RANGE
Description
16 ≤ Y ≤ 235
1 ≤ Y ≤ 254
The chroma can be delayed/advanced only in chroma pixel
steps. One chroma pixel step is equal to two luma pixels. The
programmable delay occurs after demodulation, where one can
no longer delay by luma pixel steps.
0
16 ≤ C/P ≤ 240
1 ≤ C/P ≤ 254
1 (default)
AUTO_PDC_EN Automatic Programmed Delay Control,
Address 0x27 [6]
For manual programming, use the following defaults:
•
•
•
CVBS input CTA[2:0] = 011.
YC input CTA[2:0] = 101.
YPrPb input CTA[2:0] =110.
Enabling the AUTO_PDC_EN function activates a function
within the ADV7181B that automatically programs the
LTA[1:0] and CTA[2:0] to have the chroma and luma data
match delays for all modes of operation. If set, manual registers
LTA[1:0] and CTA[2:0] are not used. If the automatic mode is
disabled (via setting the AUTO_PDC_EN bit to 0), the values
programmed into LTA[1:0] and CTA[2:0] registers become
active.
Table 52. CTA Function
CTA[2:0]
Description
000
Not used.
001
010
011 (default)
100
101
Chroma + 2 chroma pixel (early).
Chroma + 1 chroma pixel (early).
No delay.
Chroma – 1 chroma pixel (late).
Chroma – 2 chroma pixel (late).
Chroma – 3 chroma pixel (late).
Not used.
When AUTO_PDC_EN is 0, the ADV7181 uses the LTA[1:0]
and CTA[2:0] values for delaying luma and chroma samples.
Refer to the LTA[1:0] Luma Timing Adjust, Address 0x27 [1:0]
and the CTA[2:0] Chroma Timing Adjust, Address 0x27 [5:3]
sections.
110
111
When AUTO_PDC_EN is 1 (default), the ADV7181
automatically determines the LTA and CTA values to have luma
and chroma aligned at the output.
Rev. 0 | Page 37 of 96
ADV7181B
HSE[10:0] HS End, Address 0x34 [2:0], Address 0x36 [7:0]
SYNCHRONIZATION OUTPUT SIGNALS
HS Configuration
The position of this edge is controlled by placing a binary
number into HSE[10:0]. The number applied offsets the edge
with respect to an internal counter that is reset to 0 immediately
after EAV code FF,00,00,XY (see Figure 19). HSE is set to
00000000000b, which is 0 LLC1 clock cycles from count[0].
The following controls allow the user to configure the behavior
of the HS output pin only:
•
•
•
Beginning of HS signal via HSB[10:0]
End of HS signal via HSE[10:0]
Polarity of HS using PHS
The default value of HSE[10:0] is 000, indicating that the HS
pulse ends 0 pixels after falling edge of HS.
For example:
The HS Begin and HS End registers allow the user to freely
position the HS output (pin) within the video line. The values in
HSB[10:0] and HSE[10:0] are measured in pixel units from the
falling edge of HS. Using both values, the user can program
both the position and length of the HS output signal.
1. To shift the HS toward active video by 20 LLC1s, add 20
LLC1s to both HSB and HSE, i.e., HSB[10:0] =
[00000010110], HSE[10:0] = [00000010100].
2. To shift the HS away from active video by 20 LLC1s, add
1696 LLC1s to both HSB and HSE (for NTSC), that is,
HSB[10:0] = [11010100010], HSE[10:0] = [11010100000].
1696 is derived from the NTSC total number of Pixels =
1716.
HSB[10:0] HS Begin, Address 0x34 [6:4], Address 0x35 [7:0]
The position of this edge is controlled by placing a binary
number into HSB[10:0]. The number applied offsets the edge
with respect to an internal counter that is reset to 0 immediately
after EAV code FF,00,00,XY (see Figure 19). HSB is set to
00000000010b, which is 2 LLC1 clock cycles from count[0].
To move 20 LLC1s away from active video is equal to subtracting
20 from 1716 and adding the result in binary to both HSB[10:0]
and HSE[10:0].
The default value of HSB[10:0] is 0x002, indicating that the HS
pulse starts 2 pixels after the falling edge of HS.
PHS Polarity HS, Address 0x37 [7]
The polarity of the HS pin can be inverted using the PHS bit.
When PHS is 0 (default), HS is active high.
When PHS is 1, HS is active low.
Table 53. HS Timing Parameters (see Figure 19)
Characteristic
HS Begin Adjust
(HSB[10:0])
(default)
HS to Active Video (LLC1
Clock Cycles)
(C in Figure 19) (default)
Active Video
Samples/Line
(D in Figure 19)
Total LLC1
Clock Cycles
(E in Figure 19)
HS End Adjust
(HSE[10:0])(default)
Standard
NTSC
00000000010b
00000000000b
00000000000b
00000000000b
272
276
284
720Y + 720C = 1440
640Y + 640C = 1280
720Y + 720C = 1440
1716
1560
1728
NTSC Square Pixel 00000000010b
PAL
00000000010b
LLC1
PIXEL
BUS
Cr
Y
FF
00
EAV
00
XY
80
10
80
10
80
10
FF
00
00
SAV
XY
Cb
Y
Cr
Y
Cb
Y
Cr
ACTIVE
VIDEO
H BLANK
ACTIVE VIDEO
HS
HSE[10:0]
4 LLC1
HSB[10:0]
C
D
D
E
E
Figure 19. HS Timing
Rev. 0 | Page 38 of 96
ADV7181B
VSBHO VS Begin Horizontal Position Odd, Address 0x32 [7]
VS and FIELD Configuration
The following controls allow the user to configure the behavior
of the VS and FIELD output pins, as well as the generation of
embedded AV codes:
The VSBHO and VSBHE bits select the position within a line at
which the VS pin (not the bit in the AV code) becomes active.
Some follow-on chips require the VS pin to only change state
when HS is high/low.
•
•
•
•
•
•
ADV encoder-compatible signals via NEWAVMODE
When VSBHO is 0 (default), the VS pin goes high at the middle
of a line of video (odd field).
PVS, PF
HVSTIM
When VSBHO is 1, the VS pin changes state at the start of a line
(odd field).
VSBHO, VSBHE
VSEHO, VSEHE
For NTSC control:
VSBHE VS Begin Horizontal Position Even, Address 0x32 [6]
The VSBHO and VSBHE bits select the position within a line at
which the VS pin (not the bit in the AV code) becomes active.
Some follow-on chips require the VS pin to only change state
when HS is high/low.
o
o
o
NVBEGDELO, NVBEGDELE, NVBEGSIGN,
NVBEG[4:0]
NVENDDELO, NVENDDELE, NVENDSIGN,
NVEND[4:0]
When VSBHE is 0 (default), the VS pin goes high at the middle
of a line of video (even field).
NFTOGDELO, NFTOGDELE, NFTOGSIGN,
NFTOG[4:0]
When VSBHE is 1, the VS pin changes state at the start of a line
(even field).
•
For PAL control:
VSEHO VS End Horizontal Position Odd, Address 0x33 [7]
o
o
o
PVBEGDELO, PVBEGDELE, PVBEGSIGN,
PVBEG[4:0]
The VSEHO and VSEHE bits select the position within a line at
which the VS pin (not the bit in the AV code) becomes active.
Some follow-on chips require the VS pin to only change state
when HS is high/low.
PVENDDELO, PVENDDELE, PVENDSIGN,
PVEND[4:0]
When VSEHO is 0 (default), the VS pin goes low (inactive) at
the middle of a line of video (odd field).
PFTOGDELO, PFTOGDELE, PFTOGSIGN,
PFTOG[4:0]
When VSEHO is 1, the VS pin changes state at the start of a line
(odd field).
NEWAVMODE New AV Mode, Address 0x31 [4]
When NEWAVMODE is 0, EAV/SAV codes are generated to
suit ADI encoders. No adjustments are possible.
VSEHE VS End Horizontal Position Even, Address 0x33 [6]
The VSEHO and VSEHE bits select the position within a line at
which the VS pin (not the bit in the AV code) becomes active.
Some follow-on chips require the VS pin to only change state
when HS is high/low.
Setting NEWAVMODE to 1 (default) enables the manual
position of the VSYNC, Field, and AV codes using Registers
0x34 to 0x37 and 0xE5 to 0xEA. Default register settings are
CCIR656 compliant; see Figure 20 for NTSC and Figure 25 for
PAL. For recommended manual user settings, see Table 54 and
Figure 21 for NTSC; see Table 55 and Figure 26 for PAL.
When VSEHE is 0 (default), the VS pin goes low (inactive) at
the middle of a line of video (even field).
When VSEHE is 1, the VS pin changes state at the start of a line
(even field).
HVSTIM Horizontal VS Timing, Address 0x31 [3]
The HVSTIM bit allows the user to select where the VS signal is
asserted within a line of video. Some interface circuitry may
require VS to go low while HS is low.
PVS Polarity VS, Address 0x37 [5]
The polarity of the VS pin can be inverted using the PVS bit.
When PVS is 0 (default), VS is active high.
When PVS is 1, VS is active low.
When HVSTIM is 0 (default), the start of the line is relative to
HSE.
When HVSTIM is 1, the start of the line is relative to HSB.
Rev. 0 | Page 39 of 96
ADV7181B
PF Polarity FIELD, Address 0x37 [3]
The polarity of the FIELD pin can be inverted using the PF bit.
FIELD pin can be inverted using the PF bit.
When PF is 0 (default), FIELD is active high.
When PF is 1, FIELD is active low.
FIELD 1
525
1
2
3
4
5
6
7
8
9
10
11
12
13
19
20
21
22
OUTPUT
VIDEO
H
V
NVBEG[4:0] = 0x5
NVEND[4:0] = 0x4
*BT.656-4
REG 0x04, BIT 7 = 1
F
NFTOG[4:0] = 0x3
FIELD 2
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
283
284
285
OUTPUT
VIDEO
H
V
*BT.656-4
REG 0x04, BIT 7 = 1
NVBEG[4:0] = 0x5
NVEND[4:0] = 0x4
F
NFTOG[4:0] = 0x3
*APPLIES IF NEMAVMODE = 0:
MUST BE MANUALLY SHIFTED IF NEWAVMODE = 1.
Figure 20. NTSC Default (BT.656). The polarity of H, V, and F is embedded in the data.
FIELD 1
525
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
21
22
OUTPUT
VIDEO
HS
OUTPUT
VS
OUTPUT
FIELD
OUTPUT
NVBEG[4:0] = 0x0
NVEND[4:0] = 0x3
NFTOG[4:0] = 0x5
FIELD 2
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
284
285
OUTPUT
VIDEO
HS
OUTPUT
VS
OUTPUT
NVBEG[4:0] = 0x0
NVEND[4:0] = 0x3
FIELD
OUTPUT
NFTOG[4:0] = 0x5
Figure 21. NTSC Typical VSync/Field Positions Using Register Writes in Table 54
Rev. 0 | Page 40 of 96
ADV7181B
Table 54. Recommended User Settings for NTSC
(See Figure 21)
NVBEGSIGN NTSC VSync Begin Sign, Address 0xE5 [5]
Setting NVBEGSIGN to 0 delays the start of VSync. Set for user
manual programming.
Register
Register Name
VSync Field Control 1
VSync Field Control 2
VSync Field Control 3
Polarity
Write
0x12
0x81
0x84
0x29
0x0
0x31
0x32
Setting NVBEGSIGN to 1 (default) advances the start of VSync.
Not recommended for user programming.
0x33
0x37
0xE5
NTSV_V_Bit_Beg
NTSC_V_Bit_End
NTSC_F_Bit_Tog
NVBEG[4:0] NTSC VSync Begin, Address 0xE5 [4:0]
0xE6
0x3
The default value of NVBEG is 00101, indicating the NTSC
VSync begin position.
0xE7
0x85
For all NTSC/PAL VSync timing controls, both the V bit in the
AV code and the VSync on the VS pin are modified.
1
NVBEGSIGN
0
ADVANCE BEGIN OF
VSYNC BY NVBEG[4:0]
DELAY BEGIN OF
VSYNC BY NVBEG[4:0]
1
NVENDSIGN
0
NOT VALID FOR USER
PROGRAMMING
ADVANCE END OF
VSYNC BY NVEND[4:0]
DELAY END OF VSYNC
BY NVEND[4:0]
ODD FIELD?
YES
NO
NOT VALID FOR USER
PROGRAMMING
ODD FIELD?
NVBEGDELO
1
NVBEGDELE
1
YES
NO
0
0
NVENDDELO
1
NVENDDELE
1
ADDITIONAL
DELAY BY
1 LINE
ADDITIONAL
DELAY BY
1 LINE
0
0
ADDITIONAL
DELAY BY
1 LINE
ADDITIONAL
DELAY BY
1 LINE
VSBHO
1
VSBHE
1
0
0
VSEHO
1
VSEHE
1
ADVANCE BY
0.5 LINE
ADVANCE BY
0.5 LINE
0
0
ADVANCE BY
0.5 LINE
ADVANCE BY
0.5 LINE
VSYNC BEGIN
Figure 22. NTSC VSync Begin
VSYNC END
NVBEGDELO NTSC VSync Begin Delay on Odd Field,
Address 0xE5 [7]
Figure 23. NTSC VSync End
When NVBEGDELO is 0 (default), there is no delay.
NVENDDELO NTSC VSync End Delay on Odd Field,
Address 0xE6 [7]
Setting NVBEGDELO to 1 delays VSync going high on an odd
field by a line relative to NVBEG.
When NVENDDELO is 0 (default), there is no delay.
NVBEGDELE NTSC Vsync Begin Delay on Even Field,
Address 0xE5 [6]
Setting NVENDDELO to 1 delays VSync from going low on an
odd field by a line relative to NVEND.
When NVBEGDELE is 0 (default), there is no delay.
Setting NVBEGDELE to 1 delays VSync going high on an even
field by a line relative to NVBEG.
Rev. 0 | Page 41 of 96
ADV7181B
NVENDDELE NTSC VSync End Delay on Even Field,
Address 0xE6 [6]
1
NFTOGSIGN
0
When NVENDDELE is set to 0 (default), there is no delay.
ADVANCE TOGGLE OF
FIELD BY NFTOG[4:0]
DELAY TOGGLE OF
FIELD BY NFTOG[4:0]
Setting NVENDDELE to 1 delays VSync from going low on an
even field by a line relative to NVEND.
NOT VALID FOR USER
PROGRAMMING
ODD FIELD?
NVENDSIGN NTSC VSync End Sign, Address 0xE6 [5]
YES
NO
Setting NVENDSIGN to 0 (default) delays the end of VSync. Set
for user manual programming.
NFTOGDELO
1
NFTOGDELE
1
Setting NVENDSIGN to 1 advances the end of VSync. Not
recommended for user programming.
0
0
ADDITIONAL
DELAY BY
1 LINE
ADDITIONAL
DELAY BY
1 LINE
NVEND NTSC[4:0] VSync End, Address 0xE6 [4:0]
The default value of NVEND is 00100, indicating the NTSC
VSync end position.
FIELD
For all NTSC/PAL VSync timing controls, both the V bit in the
AV code and the VSync on the VS pin are modified.
TOGGLE
Figure 24. NTSC FIELD Toggle
NFTOGDELO NTSC Field Toggle Delay on Odd Field,
Address 0xE7 [7]
NFTOGSIGN NTSC Field Toggle Sign, Address 0xE7 [5]
Setting NFTOGSIGN to 0 delays the field transition. Set for
user manual programming.
When NFTOGDELO is 0 (default), there is no delay.
Setting NFTOGDELO to 1 delays the field toggle/transition on
an odd field by a line relative to NFTOG.
Setting NFTOGSIGN to 1 (default) advances the field
transition. Not recommended for user programming.
NFTOGDELE NTSC Field Toggle Delay on Even Field,
Address 0xE7 [6]
NFTOG[4:0] NTSC Field Toggle, Address 0xE7 [4:0]
The default value of NFTOG is 00011, indicating the NTSC
Field toggle position.
When NFTOGDELE is 0, there is no delay.
Setting NFTOGDELE to 1 (default) delays the field toggle/
transition on an even field by a line relative to NFTOG.
For all NTSC/PAL Field timing controls, both the F bit in the
AV code and the Field signal on the FIELD/DE pin are modified.
Table 55. Recommended User Settings for PAL
(see Figure 26)
Register
Register Name
VSync Field Control 1
VSync Field Control 2
VSync Field Control 3
Polarity
Write
0x12
0x81
0x84
0x29
0x1
0x31
0x32
0x33
0x37
0xE8
PAL_V_Bit_Beg
PAL_V_Bit_End
PAL_F_Bit_Tog
0xE9
0x4
0xEA
0x6
Rev. 0 | Page 42 of 96
ADV7181B
FIELD 1
622
623
624
625
1
2
3
4
5
6
7
8
9
10
22
23
24
OUTPUT
VIDEO
H
V
PVBEG[4:0] = 0x5
PVEND[4:0] = 0x4
F
PFTOG[4:0] = 0x3
FIELD 2
310
311
312
313
314
315
316
317
318
319
320
321
322
335
336
337
OUTPUT
VIDEO
H
V
PVBEG[4:0] = 0x5
PVEND[4:0] = 0x4
F
PFTOG[4:0] = 0x3
Figure 25. PAL Default (BT.656). The polarity of H, V, and F is embedded in the data.
FIELD 1
622
623
624
1
2
3
4
5
6
7
8
9
10
11
23
24
625
OUTPUT
VIDEO
HS
OUTPUT
VS
OUTPUT
PVBEG[4:0] = 0x1
PVEND[4:0] = 0x4
FIELD
OUTPUT
PFTOG[4:0] = 0x6
FIELD 2
310
311
312
314
315
316
317
318
319
320
321
322
323
336
337
313
OUTPUT
VIDEO
HS
OUTPUT
VS
OUTPUT
PVBEG[4:0] = 0x1
PVEND[4:0] = 0x4
FIELD
OUTPUT
PFTOG[4:0] = 0x6
Figure 26. PAL Typical VSync/Field Positions Using Register Writes in Table 55
Rev. 0 | Page 43 of 96
ADV7181B
PVBEG[4:0] PAL VSync Begin, Address 0xE8 [4:0]
PVBEGSIGN
1
0
The default value of PVBEG is 00101, indicating the PAL VSync
begin position.
ADVANCE BEGIN OF
VSYNC BY PVBEG[4:0]
DELAY BEGIN OF
VSYNC BY PVBEG[4:0]
For all NTSC/PAL VSync timing controls, both the V bit in the
AV code and the VSync on the VS pin are modified.
NOT VALID FOR USER
PROGRAMMING
ODD FIELD?
1
PVENDSIGN
0
YES
NO
ADVANCE END OF
VSYNC BY PVEND[4:0]
DELAY END OF VSYNC
BY PVEND[4:0]
PVBEGDELO
1
PVBEGDELE
1
0
0
NOT VALID FOR USER
PROGRAMMING
ODD FIELD?
ADDITIONAL
DELAY BY
1 LINE
ADDITIONAL
DELAY BY
1 LINE
YES
NO
PVENDDELO
1
PVENDDELE
1
VSBHO
1
VSBHE
1
0
0
0
0
ADDITIONAL
DELAY BY
1 LINE
ADDITIONAL
DELAY BY
1 LINE
ADVANCE BY
0.5 LINE
ADVANCE BY
0.5 LINE
VSEHO
1
VSEHE
1
VSYNC BEGIN
0
0
Figure 27. PAL VSync Begin
PVBEGDELO PAL VSync Begin Delay on Odd Field,
Address 0xE8 [7]
ADVANCE BY
0.5 LINE
ADVANCE BY
0.5 LINE
When PVBEGDELO is 0 (default), there is no delay.
VSYNC END
Setting PVBEGDELO to 1 delays VSync going high on an odd
field by a line relative to PVBEG.
Figure 28. PAL VSync End
PVENDDELO PAL VSync End Delay on Odd Field,
Address 0xE9,[7]
PVBEGDELE PAL VSync Begin Delay on Even Field,
Address 0xE8 [6]
When PVENDDELO is 0 (default), there is no delay.
When PVBEGDELE is 0, there is no delay.
Setting PVENDDELO to 1 delays VSync going low on an odd
field by a line relative to PVEND.
Setting PVBEGDELE to 1 (default) delays VSync going high on
an even field by a line relative to PVBEG.
PVENDDELE PAL VSync End Delay on Even Field,
Address 0xE9,[6]
PVBEGSIGN PAL VSync Begin Sign, Address 0xE8 [5]
Setting PVBEGSIGN to 0 delays the beginning of VSync. Set for
user manual programming.
When PVENDDELE is 0 (default), there is no delay.
Setting PVENDDELE to 1 delays VSync going low on an even
field by a line relative to PVEND.
Setting PVBEGSIGN to 1(default) advances the beginning of
VSync. Not recommended for user programming.
Rev. 0 | Page 44 of 96
ADV7181B
PVENDSIGN PAL VSync End Sign, Address 0xE9 [5]
1
PFTOGSIGN
0
Setting PVENDSIGN to 0 (default) delays the end of VSync. Set
for user manual programming.
ADVANCE TOGGLE OF
FIELD BY PTOG[4:0]
DELAY TOGGLE OF
FIELD BY PFTOG[4:0]
Setting PVENDSIGN to 1 advances the end of VSync. Not
recommended for user programming.
NOT VALID FOR USER
PROGRAMMING
ODD FIELD?
PVEND[4:0] PAL VSync End, Address 0xE9,[4:0]
YES
NO
The default value of PVEND is 10100, indicating the PAL VSync
end position.
PFTOGDELO
1
PFTOGDELE
1
For all NTSC/PAL VSync timing controls, both the V bit in the
AV code and the VSync on the VS pin are modified.
0
0
ADDITIONAL
DELAY BY
1 LINE
ADDITIONAL
DELAY BY
1 LINE
PFTOGDELO PAL Field Toggle Delay on Odd Field,
Address 0xEA [7]
When PFTOGDELO is 0 (default), there is no delay.
FIELD
Setting PFTOGDELO to 1 delays the F toggle/transition on an
odd field by a line relative to PFTOG.
TOGGLE
Figure 29. PAL F Toggle
SYNC PROCESSING
PFTOGDELE PAL Field Toggle Delay on Even Field,
Address 0xEA [6]
The ADV7181B has two additional sync processing blocks that
postprocess the raw synchronization information extracted
from the digitized input video. If desired, the blocks can be
disabled via the following two I2C bits.
When PFTOGDELE is 0, there is no delay.
Setting PFTOGDELE to 1 (default) delays the F
toggle/transition on an even field by a line relative to PFTOG.
ENHSPLL Enable HSync Processor, Address 0x01 [6]
PFTOGSIGN PAL Field Toggle Sign, Address 0xEA [5]
The HSYNC processor is designed to filter incoming HSyncs
that have been corrupted by noise, providing improved per-
formance for video signals with stable time bases but poor SNR.
Setting PFTOGSIGN to 0 delays the Field transition. Set for
user manual programming.
Setting ENHSPLL to 0 disables the HSync processor.
Setting PFTOGSIGN to 1 (default) advances the Field
transition. Not recommended for user programming.
Setting ENHSPLL to 1 (default) enables the HSync processor.
PFTOG PAL Field Toggle, Address 0xEA [4:0]
ENVSPROC Enable VSync Processor, Address 0x01 [3]
The default value of PFTOG is 00011, indicating the PAL Field
toggle position.
This block provides extra filtering of the detected VSyncs to
give improved vertical lock.
For all NTSC/PAL Field timing controls, the F bit in the AV
code and the Field signal on the FIELD/DE pin are modified.
Setting ENVSPROC to 0 disables the VSync processor.
Setting ENVSPROC to 1(default) enables the VSync processor.
Rev. 0 | Page 45 of 96
ADV7181B
CCAPD Closed Caption Detected, Address 0x90 [1]
VBI DATA DECODE
The following low data rate VBI signals can be decoded by the
ADV7181B:
Logic 1 for this bit indicates that the data in the CCAP1 and
CCAP2 registers is valid.
The CCAPD bit goes high if the rising edge of the start bit is
detected within a time window, and if the polarity of the parity
bit matches the transmitted data.
•
•
•
•
•
Wide screen signaling (WSS)
Copy generation management systems (CGMS)
Closed captioning (CCAP)
When CCAPD is 0, no CCAP signals are detected and
confidence in the decoded data is low.
EDTV
When CCAPD is 1, the CCAP sequence is detected and
confidence in the decoded data is high.
Gemstar 1×- and 2×-compatible data recovery
The presence of any of the above signals is detected and, if
applicable, a parity check is performed. The result of this testing
is contained in a confidence bit in the VBI Info[7:0] register.
Users are encouraged to first examine the VBI Info register
before reading the corresponding data registers. All VBI data
decode bits are read-only.
EDTVD EDTV Sequence Detected, Address 0x90 [2]
Logic 1 for this bit indicates that the data in the EDTV1, 2, 3
registers is valid.
The EDTVD bit goes high if the rising edge of the start bit is
detected within a time window, and if the polarity of the parity
bit matches the transmitted data.
All VBI data registers are double-buffered with the field signals.
This means that data is extracted from the video lines and
appears in the appropriate I2C registers with the next field
transition. They are then static until the next field.
When EDTVD is 0, no EDTV sequence is detected. Confidence
in decoded data is low.
The user should start an I2C read sequence with VS by first
examining the VBI Info register. Then, depending on what data
was detected, the appropriate data registers should be read.
When EDTVD is 1, an EDTV sequence is detected. Confidence
in decoded data is high.
CGMSD CGMS-A Sequence Detected, Address 0x90 [3]
The data registers are filled with decoded VBI data even if their
corresponding detection bits are low; it is likely that bits within
the decoded data stream are wrong.
Logic 1 for this bit indicates that the data in the CGMS1, 2, 3
registers is valid. The CGMSD bit goes high if a valid CRC
checksum has been calculated from a received CGMS packet.
The closed captioning data (CCAP) is available in the I2C
registers, and is also inserted into the output video data stream
during horizontal blanking.
When CGMSD is 0, no CGMS transmission is detected and
confidence in decoded data is low.
The Gemstar-compatible data is not available in the I2C
registers, and is inserted into the data stream only during
horizontal blanking.
When CGMSD is 1, the CGMS sequence is decoded and
confidence in decoded data is high.
CRC_ENABLE CRC CGMS-A Sequence, Address 0xB2 [2]
WSSD Wide Screen Signaling Detected, Address 0x90 [0]
For certain video sources, the CRC data bits may have an
invalid format. In such circumstances, the CRC checksum
validation procedure can be disabled. The CGMSD bit goes
high if the rising edge of the start bit is detected within a time
window.
Logic 1 for this bit indicates that the data in the WSS1 and
WSS2 registers is valid.
The WSSD bit goes high if the rising edge of the start bit is
detected within a time window, and if the polarity of the parity
bit matches the transmitted data.
When CRC_ENABLE is 0, no CRC check is performed. The
CGMSD bit goes high if the rising edge of the start bit is
detected within a time window.
When WSSD is 0, no WSS is detected and confidence in the
decoded data is low.
When CRC_ENABLE is 1 (default), CRC checksum is used to
validate the CGMS sequence. The CGMSD bit goes high for a
valid checksum. ADI recommended setting.
When WSSD is 1, WSS is detected and confidence in the
decoded data is high.
Rev. 0 | Page 46 of 96
ADV7181B
Wide Screen Signaling Data
EDTV Data Registers
WSS1[7:0], Address 0x91 [7:0],
WSS2[7:0], Address 0x92 [7:0]
EDTV1[7:0], Address 0x93 [7:0],
EDTV2[7:0], Address 0x94 [7:0],
EDTV3[7:0], Address 0x95 [7:0]
Figure 30 shows the bit correspondence between the analog
video waveform and the WSS1/WSS2 registers. WSS2[7:6] are
undetermined and should be masked out by software.
Figure 31 shows the bit correspondence between the analog
video waveform and the EDTV1/EDTV2/EDTV3 registers.
EDTV3[7:6] are undetermined and should be masked out by
software. EDTV3[5] is reserved for future use and, for now,
contains a 0. The three LSBs of the EDTV waveform are
currently not supported.
WSS1[7:0]
WSS2[5:0]
0
1
2
3
4
5
6
7
0
1
2
3
4
5
RUN-IN
SEQUENCE
START
CODE
ACTIVE
VIDEO
11.0µs
38.4µs
42.5µs
Figure 30.WSS Data Extraction
Table 56. WSS Access Information
Signal Name
WSS1 [7:0]
WSS2 [5:0]
Register Location
Address
Register Default Value
Readback Only
Readback Only
WSS 1 [7:0]
WSS 2 [5:0]
145d
146d
0x91
0x92
EDTV1[7:0]
EDTV2[7:0]
EDTV3[5:0]
0
1
2
NOT SUPPORTED
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
Figure 31. EDTV Data Extraction
Table 57. EDTV Access Information
Signal Name
EDTV1[7:0]
EDTV2[7:0]
EDTV3[7:0]
Register Location
Address
Register Default Value
Readback Only
Readback Only
EDTV 1 [7:0]
EDTV 2 [7:0]
EDTV 3 [7:0]
147d
148d
149d
0x93
0x94
0x95
Readback Only
Rev. 0 | Page 47 of 96
ADV7181B
CGMS Data Registers
Closed Caption Data Registers
CGMS1[7:0], Address 0x96 [7:0],
CGMS2[7:0], Address 0x97 [7:0],
CGMS3[7:0], Address 0x98 [7:0]
CCAP1[7:0], Address 0x99 [7:0],
CCAP2[7:0], Address 0x9A [7:0]
Figure 33 shows the bit correspondence between the analog
video waveform and the CCAP1/CCAP2 registers.
Figure 32 shows the bit correspondence between the analog
video waveform and the CGMS1/CGMS2/CGMS3 registers.
CGMS3[7:4] are undetermined and should be masked out by
software.
CCAP1[7] contains the parity bit from the first word.
CCAP2[7] contains the parity bit from the second word.
Refer to the GDECAD Gemstar Decode Ancillary Data Format,
Address 0x4C [0] section.
+100 IRE
REF
CGMS1[7:0]
CGMS2[7:0]
CGMS3[3:0]
+70 IRE
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
0 IRE
49.1µs
± 0.5µs
–40 IRE
11.2µs
CRC SEQUENCE
2.235µs
± 20ns
Figure 32. CGMS Data Extraction
Table 58. CGMS Access Information
Signal Name
CGMS1[7:0]
CGMS2[7:0]
CGMS3[3:0]
Register Location
Address
Register Default Value
Readback Only
Readback Only
CGMS 1 [7:0]
CGMS 2 [7:0]
CGMS 3 [3:0]
150d
151d
152d
0x96
0x97
0x98
Readback Only
10.5
±
0.25µs
12.91µs
7 CYCLES
OF 0.5035MHz
(CLOCK RUN-IN)
CCAP1[7:0]
3 4 5 6
CCAP2[7:0]
4 5
0
1
2
7
0 1
2
3
6
7
S
T
A
R
T
P
A
R
I
T
Y
P
A
R
I
T
Y
50 IRE
40 IRE
BYTE 0
BYTE 1
REFERENCE COLOR BURST
(9 CYCLES)
FREQUENCY = F = 3.579545MHz
SC
AMPLITUDE = 40 IRE
10.003µs
27.382µs
33.764µs
Figure 33. Closed Caption Data Extraction
Table 59. CCAP Access Information
Signal Name
CCAP1[7:0]
CCAP2[7:0]
Register Location
Address
Register Default Value
Readback Only
Readback Only
CCAP 1 [7:0]
CCAP 2 [7:0]
153d
154d
0x99
0x9A
Rev. 0 | Page 48 of 96
ADV7181B
LB_LCT[7:0] Letterbox Line Count Top, Address 0x9B [7:0];
LB_LCM[7:0] Letterbox Line Count Mid, Address 0x9C [7:0];
LB_LCB[7:0] Letterbox Line Count Bottom, Address 0x9D [7:0]
Letterbox Detection
Incoming video signals may conform to different aspect ratios
(16:9 wide screen of 4:3 standard). For certain transmissions in
the wide screen format, a digital sequence (WSS) is transmitted
with the video signal. If a WSS sequence is provided, the aspect
ratio of the video can be derived from the digitally decoded bits
WSS contains.
Table 60. LB_LCx Access Information
Signal Name
LB_LCT[7:0]
LB_LCM[7:0]
LB_LCB[7:0]
Address
Register Default Value
0x9B
0x9C
0x9D
Readback only
Readback only
Readback only
In the absence of a WSS sequence, letterbox detection may be
used to find wide screen signals. The detection algorithm
examines the active video content of lines at the start and end of
a field. If black lines are detected, this may indicate that the
currently shown picture is in wide screen format.
LB_TH[4:0] Letterbox Threshold Control, Address 0xDC [4:0]
Table 61. LB_TH Function
LB_TH[4:0]
Description
The active video content (luminance magnitude) over a line of
video is summed together. At the end of a line, this accumulated
value is compared with a threshold, and a decision is made as to
whether or not a particular line is black. The threshold value
needed may depend on the type of input signal; some control is
provided via LB_TH[4:0].
01100 (default) Default threshold for detection of black lines.
01101 to
10000
Increase threshold (need larger active video
content before identifying non-black lines).
00000 to
01011
Decrease threshold (even small noise levels
can cause the detection of non-black lines).
Detection at the Start of a Field
LB_SL[3:0] Letterbox Start Line, Address 0xDD [7:4]
The ADV7181B expects a section of at least six consecutive
black lines of video at the top of a field. Once those lines are
detected, Register LB_LCT[7:0] reports back the number of
black lines that were actually found. By default, the ADV7181B
starts looking for those black lines in sync with the beginning of
active video, for example, straight after the last VBI video line.
LB_SL[3:0] allows the user to set the start of letterbox detection
from the beginning of a frame on a line-by-line basis. The
detection window closes in the middle of the field.
The LB_SL[3:0] bits are set at 0100b by default. This means that
letterbox detection window starts after the EDTV VBI data line.
For an NTSC signal, this window is from Line 23 to Line 286.
Changing the bits to 0101, the detection window starts on
Line 24 and ends on Line 287.
LB_EL[3:0] Letterbox End Line, Address 0xDD [3:0]
The LB_EL[3:0] bits are set at 1101b by default. This means that
letterbox detection window ends with the last active video line.
For an NTSC signal, this window is from Line 262 to Line 525.
Detection at the End of a Field
The ADV7181B expects at least six continuous lines of black
video at the bottom of a field before reporting back the number
of lines actually found via the LB_LCB[7:0] value. The activity
window for letterbox detection (end of field) starts in the mid-
dle of an active field. Its end is programmable via LB_EL[3:0].
Changing the bits to 1100, the detection window starts on
Line 261 and ends on Line 254.
Gemstar Data Recovery
The Gemstar-compatible data recovery block (GSCD) supports
1× and 2× data transmissions. In addition, it can also serve as a
closed caption decoder. Gemstar-compatible data transmissions
can only occur in NTSC. Closed caption data can be decoded in
both PAL and NTSC.
Detection at the Midrange
Some transmissions of wide screen video include subtitles
within the lower black box. If the ADV7181B finds at least two
black lines followed by some more nonblack video, for example,
the subtitle, and is then followed by the remainder of the bottom
black block, it reports back a midcount via LB_LCM[7:0]. If no
subtitles are found, LB_LCM[7:0] reports the same number as
LB_LCB[7:0].
The block is configured via I2C in the following way:
•
•
•
GDECEL[15:0] allow data recovery on selected video lines
on even fields to be enabled and disabled.
GDECOL[15:0] enable the data recovery on selected lines
for odd fields.
GDECAD configures the way in which data is embedded
in the video data stream.
There is a 2-field delay in the reporting of any line count
parameters.
The recovered data is not available through I2C, but is inserted
into the horizontal blanking period of an ITU-R. BT656-com-
patible data stream. The data format is intended to comply with
There is no “letterbox detected” bit. The user is asked to read the
LB_LCT[7:0] and LB_LCB[7:0] register values and to conclude
whether or not the letterbox-type video is present in software.
Rev. 0 | Page 49 of 96
ADV7181B
the recommendation by the International Telecommunications
Union, ITU-R BT.1364. See Figure 34. For more information,
see the ITU website at www.itu.ch.
Entries within the packet are as follows:
•
•
Fixed preamble sequence of 0x00, 0xFF, 0xFF.
The format of the data packet depends on the following criteria:
Data identification word (DID). The value for the DID
marking a Gemstar or CCAP data packet is 0x140
(10-bit value).
•
•
Transmission is 1× or 2×
Data is output in 8-bit or 4-bit format (see the description
of the GDECAD Gemstar Decode Ancillary Data Format,
Address 0x4C [0] bit)
•
Secondary data identification word (SDID) contains
information about the video line from which data was
retrieved, whether the Gemstar transmission was of 1× or
2× format, and whether it was retrieved from an even or
odd field.
•
Data is closed caption (CCAP) or Gemstar-compatible
Data packets are output if the corresponding enable bit is set
(see the GDECEL and GDECOL descriptions), and if the
decoder detects the presence of data. This means that for video
lines where no data has been decoded, no data packet is output
even if the corresponding line enable bit is set.
•
Data count byte, giving the number of user data-words that
follow.
•
•
User data section.
Optional padding to ensure that the length of the user
data-word section of a packet is a multiple of four bytes,
requirement as set in ITU-R BT.1364.
Each data packet starts immediately after the EAV code of the
preceding line. Figure 34 and Table 62 show the overall
structure of the data packet.
•
Checksum byte.
Table 62 lists the values within a generic data packet that is
output by the ADV7181B in 8-bit format. In 8-bit systems,
Bits D1 and D0 in the data packets are disregarded.
DATA IDENTIFICATION
SECONDARY DATA IDENTIFICATION
DATA
COUNT
OPTIONAL PADDING CHECK
00
FF
FF
DID
SDID
USER DATA
BYTES
SUM
PREAMBLE FOR ANCILLARY DATA
USER DATA (4 OR 8 WORDS)
Figure 34. Gemstar and CCAP Embedded Data Packet (Generic)
Table 62. Generic Data Output Packet
Byte
D[9]
D[8]
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
0
D[0]
0
Description
0
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
Fixed preamble
Fixed preamble
Fixed preamble
DID
1
1
1
1
1
1
1
2
1
1
1
1
1
1
3
0
1
0
1
0
0
4
!EP
!EP
!EP
!EP
!EP
!EP
!EP
!EP
!EP
!EP
!CS[8]
EP
EP
EP
EP
EP
EP
EP
EP
EP
EP
CS[8]
EF
0
2X
0
line[3:0]
0
0
SDID
5
0
0
DC[1]
word1[7:4]
word1[3:0]
word2[7:4]
word2[3:0]
word3[7:4]
word3[3:0]
word4[7:4]
word4[3:0]
DC[0]
0
0
Data count (DC)
User data-words
User data-words
User data-words
User data-words
User data-words
User data-words
User data-words
User data-words
Checksum
6
0
0
0
0
7
0
0
0
0
8
0
0
0
0
9
0
0
0
0
10
11
12
13
14
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CS[7]
CS[6]
CS[5]
CS[4]
CS[3]
CS[2]
0
0
Rev. 0 | Page 50 of 96
ADV7181B
Table 63. Data Byte Allocation
Raw Information Bytes
Retrieved from the Video Line
User Data-Words
(Including Padding)
2×
1
1
0
0
GDECAD
Padding Bytes
DC[1:0]
10
01
01
01
4
4
2
2
0
1
0
1
8
4
4
4
0
0
0
2
Gemstar Bit Names
•
CS[8:2]. The checksum is provided to determine the
integrity of the ancillary data packet. It is calculated by
summing up D[8:2] of DID, SDID, the Data Count byte,
and all UDWs, and ignoring any overflow during the
summation. Since all data bytes that are used to calculate
the checksum have their 2 LSBs set to 0, the CS[1:0] bits are
also always 0.
•
•
DID. The data identification value is 0x140 (10-bit value).
Care has been taken that in 8-bit systems, the 2 LSBs do
not carry vital information.
EP and !EP. The EP bit is set to ensure even parity on the
data-word D[8:0]. Even parity means there is always an
even number of 1s within the D[8:0] bit arrangement. This
includes the EP bit. !EP describes the logic inverse of EP
and is output on D[9]. The !EP is output to ensure that the
reserved codes of 00 and FF cannot happen.
!CS[8] describes the logic inversion of CS[8]. The value
!CS[8] is included in the checksum entry of the data packet
to ensure that the reserved values of 0x00 and 0xFF do not
occur.
•
•
•
EF. Even field identifier. EF = 1 indicates that the data was
recovered from a video line on an even field.
Table 64 to Table 67 outline the possible data packages.
Gemstar 2× Format, Half-Byte Output Mode
2X. This bit indicates whether the data sliced was in
Gemstar 1× or 2× format. A high indicates 2× format.
Half-byte output mode is selected by setting CDECAD = 0; full-
byte output mode is selected by setting CDECAD = 1. See the
GDECAD Gemstar Decode Ancillary Data Format, Address
0x4C [0] section.
line[3:0]. This entry provides a code that is unique for each
of the possible 16 source lines of video from which
Gemstar data may have been retrieved. Refer to Table 72
and Table 73.
Gemstar 1× Format
Half-byte output mode is selected by setting CDECAD = 0, full-
byte output mode is selected by setting CDECAD = 1. See the
GDECAD Gemstar Decode Ancillary Data Format, Address
0x4C [0] section.
•
•
DC[1:0]. Data count value. The number of User Data
Words in the packet divided by 4. The number of user data
words (UDW) in any packet must be an integral number of
4. Padding is required at the end, if necessary (requirement
as set in ITU-R BT.1364). Refer to Table 63.
The 2X bit determines whether the raw information
retrieved from the video line was 2 or 4 bytes. The state of
the GDECAD bit affects whether the bytes are transmitted
straight (i.e., two bytes transmitted as two bytes) or
whether they are split into nibbles (i.e., two bytes
transmitted as four half bytes). Padding bytes are then
added where necessary.
Rev. 0 | Page 51 of 96
ADV7181B
Table 64. Gemstar 2× Data, Half-Byte Mode
Byte
D[9]
D[8]
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
Description
0
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
Fixed preamble
Fixed preamble
Fixed preamble
DID
1
1
1
1
1
1
1
2
1
1
1
1
1
1
3
0
1
0
1
0
0
4
!EP
!EP
!EP
!EP
!EP
!EP
!EP
!EP
!EP
!EP
!CS[8]
EP
EP
EP
EP
EP
EP
EP
EP
EP
EP
CS[8]
EF
0
line[3:0]
0
0
SDID
1
5
0
0
0
0
0
Data count
1
0
6
0
0
Gemstar word1[7:4]
Gemstar word1[3:0]
Gemstar word2[7:4]
Gemstar word2[3:0]
Gemstar word3[7:4]
Gemstar word3[3:0]
Gemstar word4[7:4]
Gemstar word4[3:0]
0
0
User data-words
User data-words
User data-words
User data-words
User data-words
User data-words
User data-words
User data-words
Checksum
7
0
0
0
0
8
0
0
0
0
9
0
0
0
0
10
11
12
13
14
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CS[7]
CS[6]
CS[5]
CS[4]
CS[3]
CS[2]
CS[1]
CS[0]
Table 65. Gemstar 2× Data, Full-Byte Mode
Byte
D[9]
D[8]
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
0
D[0]
Description
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
0
1
1
0
0
Fixed preamble
Fixed preamble
Fixed preamble
DID
1
1
1
1
1
1
1
2
1
1
1
1
1
1
3
0
1
0
0
line[3:0]
0
0
0
4
!EP
!EP
EP
EP
EF
0
0
0
SDID
5
0
0
0
0
Data count
1
6
Gemstar word1[7:0]
Gemstar word2[7:0]
Gemstar word3[7:0]
Gemstar word4[7:0]
0
0
User data-words
User data-words
User data-words
User data-words
Checksum
7
0
0
8
0
0
9
0
0
10
!CS[8]
CS[8]
CS[7]
CS[6]
CS[5]
CS[4]
CS[3]
CS[2]
CS[1]
CS[0]
Table 66. Gemstar 1× Data, Half-Byte Mode
Byte
D[9]
D[8]
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
0
Description
Fixed preamble
Fixed preamble
Fixed preamble
DID
0
0
0
0
0
0
1
1
0
0
1
1
0
0
0
1
1
0
0
1
1
1
1
1
1
1
1
2
1
1
1
1
1
1
1
3
0
1
0
1
0
line[3:0]
0
0
0
4
!EP
!EP
!EP
!EP
!EP
!EP
!CS[8]
EP
EP
EP
EP
EP
EP
CS[8]
EF
0
0
SDID
0
5
0
0
0
0
0
0
Data count
1
6
0
0
Gemstar word1[7:4]
Gemstar word1[3:0]
Gemstar word2[7:4]
Gemstar word2[3:0]
0
0
User data-words
User data-words
User data-words
User data-words
7
0
0
0
0
8
0
0
0
0
9
0
0
0
0
10
CS[7]
CS[6]
CS[5]
CS[4]
CS[3]
CS[2]
CS[1]
CS[0]
Checksum
Rev. 0 | Page 52 of 96
ADV7181B
Table 67. Gemstar 1× Data, Full-Byte Mode
Byte
D[9]
D[8]
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
Description
0
0
0
0
0
1
1
1
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
Fixed preamble
Fixed preamble
Fixed preamble
DID
1
1
1
1
1
1
2
1
1
1
1
1
3
0
1
0
0
0
4
!EP
!EP
EP
EP
EF
0
line[3:0]
0
0
SDID
5
0
0
0
0
Data count
0
1
6
Gemstar word1[7:0]
Gemstar word2[7:0]
0
0
User data-words
User data-words
UDW padding 0x200
UDW padding 0x200
Checksum
7
0
0
8
1
0
0
0
0
0
0
0
0
0
9
1
0
0
0
0
0
0
0
0
0
10
!CS[8]
CS[8]
CS[7]
CS[6]
CS[5]
CS[4]
CS[3]
CS[2]
CS[1]
CS[0]
Table 68. NTSC CCAP Data, Half-Byte Mode
Byte
D[9]
D[8]
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
Description
Fixed preamble
Fixed preamble
Fixed preamble
DID
0
0
0
0
0
0
1
1
0
1
0
0
1
1
0
0
0
0
1
1
0
1
0
0
1
1
0
1
1
0
0
1
1
1
1
1
1
1
2
1
1
1
1
1
1
3
0
1
0
1
0
0
4
!EP
!EP
!EP
!EP
!EP
!EP
!CS[8]
EP
EP
EP
EP
EP
EP
CS[8]
EF
0
0
SDID
0
5
0
0
0
0
Data count
6
0
0
CCAP word1[7:4]
CCAP word1[3:0]
CCAP word2[7:4]
CCAP word2[3:0]
0
0
User data-words
User data-words
User data-words
User data-words
Checksum
7
0
0
0
0
8
0
0
0
0
9
0
0
0
0
10
CS[7]
CS[6]
CS[5]
CS[4]
CS[3]
CS[2]
CS[1]
CS[0]
Table 69. NTSC CCAP Data, Full-Byte Mode
Byte
D[9]
D[8]
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
Description
Fixed preamble
Fixed preamble
Fixed preamble
DID
0
0
0
0
0
1
1
1
0
0
0
1
1
0
1
0
0
1
1
0
0
0
0
1
1
0
1
0
0
1
1
0
1
1
0
0
1
1
1
1
1
1
2
1
1
1
1
1
3
0
1
0
0
0
4
!EP
!EP
EP
EP
EF
0
0
0
SDID
5
0
0
Data count
6
CCAP word1[7:0]
CCAP word2[7:0]
0
0
User data-words
User data-words
UDW padding 0x200
UDW padding 0x200
Checksum
7
0
0
8
1
0
0
0
0
0
0
0
0
0
9
1
0
0
0
0
0
0
0
0
0
10
!CS[8]
CS[8]
CS[7]
CS[6]
CS[5]
CS[4]
CS[3]
CS[2]
CS[1]
CS[0]
Rev. 0 | Page 53 of 96
ADV7181B
NTSC CCAP Data
PAL CCAP Data
Half-byte output mode is selected by setting CDECAD = 0, the
full-byte mode is enabled by CDECAD = 1. Refer to the
GDECAD Gemstar Decode Ancillary Data Format, Address
0x4C [0] section. The data packet formats are shown in Table 68
and Table 69.
Half-byte output mode is selected by setting CDECAD = 0, full-
byte output mode is selected by setting CDECAD = 1. See the
GDECAD Gemstar Decode Ancillary Data Format, Address
0x4C [0] section. Table 70 and Table 71 list the bytes of the data
packet.
NTSC closed caption data is sliced on Line 21d on even and
odd fields. The corresponding enable bit has to be set high. See
the GDECEL[15:0] Gemstar Decoding Even Lines, Address
0x48 [7:0]; Address 0x49 [7:0]and the GDECOL[15:0] Gemstar
Decoding Odd Lines, Address 0x4A [7:0]; Address 0x4B [7:0]
sections.
PAL closed caption data is sliced from Lines 22 and 335. The
corresponding enable bits have to be set.
See the GDECEL[15:0] Gemstar Decoding Even Lines, Address
0x48 [7:0]; Address 0x49 [7:0] and the GDECOL[15:0] Gemstar
Decoding Odd Lines, Address 0x4A [7:0]; Address 0x4B [7:0]
sections.
Table 70. PAL CCAP Data, Half-Byte Mode
Byte
D[9]
D[8]
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
Description
Fixed preamble
Fixed preamble
Fixed preamble
DID
0
0
0
0
0
0
1
1
0
1
0
0
1
1
0
0
0
0
1
1
0
1
0
0
1
1
0
0
1
0
0
1
1
1
1
1
1
1
2
1
1
1
1
1
1
3
0
1
0
1
0
0
4
!EP
!EP
!EP
!EP
!EP
!EP
!CS[8]
EP
EP
EP
EP
EP
EP
CS[8]
EF
0
0
SDID
0
5
0
0
0
0
Data count
6
0
0
CCAP word1[7:4]
CCAP word1[3:0]
CCAP word2[7:4]
CCAP word2[3:0]
0
0
User data-words
User data-words
User data-words
User data-words
Checksum
7
0
0
0
0
8
0
0
0
0
9
0
0
0
0
10
CS[7]
CS[6]
CS[5]
CS[4]
CS[3]
CS[2]
CS[1]
CS[0]
Table 71. PAL CCAP Data, Full-Byte Mode
Byte
D[9]
D[8]
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
0
D[0]
Description
0
0
0
0
0
1
1
1
0
0
0
1
1
0
1
0
0
1
1
0
0
0
0
1
1
0
1
0
0
1
1
0
0
1
0
Fixed preamble
Fixed preamble
Fixed preamble
DID
1
1
1
1
1
1
2
1
1
1
1
1
3
0
1
0
0
0
4
!EP
!EP
EP
EP
EF
0
0
0
SDID
5
0
0
Data Count
6
CCAP word1[7:0]
CCAP word2[7:0]
0
0
User data-words
User data-words
UDW padding 0x200
UDW padding 0x200
Checksum
7
0
0
8
1
0
0
0
0
0
0
0
0
0
9
1
0
0
0
0
0
0
0
0
0
10
!CS[8]
CS[8]
CS[7]
CS[6]
CS[5]
CS[4]
CS[3]
CS[2]
CS[1]
CS[0]
Rev. 0 | Page 54 of 96
ADV7181B
GDECEL[15:0] Gemstar Decoding Even Lines,
Address 0x48 [7:0]; Address 0x49 [7:0]
When GDECAD is 0, the data is split into half-bytes and
inserted (default).
The 16 bits of the GDECEL[15:0] are interpreted as a collection
of 16 individual line decode enable signals. Each bit refers to a
line of video in an even field. Setting the bit enables the decoder
block trying to find Gemstar or closed caption-compatible data
on that particular line. Setting the bit to 0 prevents the decoder
from trying to retrieve data. See Table 72 and Table 73.
When GDECAD is 1, the data is output straight in 8-bit format.
Table 72. NTSC Line Enable Bits and
Corresponding Line Numbering
Line Number
line[3:0]
(ITU-R BT.470)
Enable Bit
GDECOL[0]
GDECOL[1]
GDECOL[2]
GDECOL[3]
GDECOL[4]
GDECOL[5]
GDECOL[6]
GDECOL[7]
GDECOL[8]
GDECOL[9]
GDECOL[10]
GDECOL[11]
Comment
Gemstar
Gemstar
Gemstar
Gemstar
Gemstar
Gemstar
Gemstar
Gemstar
Gemstar
Gemstar
Gemstar
0
1
2
3
4
5
6
7
8
9
10
11
10
11
12
13
14
15
16
17
18
19
20
21
To retrieve closed caption data services on NTSC (Line 284),
GDECEL[11] must be set.
To retrieve closed caption data services on PAL (Line 335),
GDECEL[14] must be set.
The default value of GDECEL[15:0] is 0x0000. This setting
instructs the decoder not to attempt to decode Gemstar or
CCAP data from any line in the even field.
GDECOL[15:0] Gemstar Decoding Odd Lines, Address 0x4A
[7:0]; Address 0x4B [7:0]
Gemstar or
closed caption
12
13
14
15
0
1
2
3
4
5
6
7
8
9
10
11
22
23
24
25
GDECOL[12]
GDECOL[13]
GDECOL[14]
GDECOL[15]
GDECEL[0]
GDECEL[1]
GDECEL[2]
GDECEL[3]
GDECEL[4]
GDECEL[5]
GDECEL[6]
GDECEL[7]
GDECEL[8]
GDECEL[9]
GDECEL[10]
GDECEL[11]
Gemstar
Gemstar
Gemstar
Gemstar
Gemstar
Gemstar
Gemstar
Gemstar
Gemstar
Gemstar
Gemstar
Gemstar
Gemstar
Gemstar
Gemstar
The 16 bits of the GDECOL[15:0] form a collection of 16
individual line decode enable signals. See Table 72 and Table 73.
To retrieve closed caption data services on NTSC (Line 21),
GDECOL[11] must be set.
273 (10)
274 (11)
275 (12)
276 (13)
277 (14)
278 (15)
279 (16)
280 (17)
281 (18)
282 (19)
283 (20)
284 (21)
To retrieve closed caption data services on PAL (Line 22),
GDECOL[14] must be set.
The default value of GDEC0L[15:0] is 0x0000. This setting
instructs the decoder not to attempt to decode Gemstar or
CCAP data from any line in the odd field.
GDECAD Gemstar Decode Ancillary Data Format,
Address 0x4C [0]
Gemstar or
closed caption
Gemstar
Gemstar
Gemstar
Gemstar
The decoded data from Gemstar-compatible transmissions or
closed caption transmissions is inserted into the horizontal
blanking period of the respective line of video. A potential
problem may arise if the retrieved data bytes have the value
0x00 or 0xFF. In an ITU-R BT.656-compatible data stream,
those values are reserved and used only to form a fixed
preamble.
12
13
14
15
285 (22)
286 (23)
287 (24)
288 (25)
GDECEL[12]
GDECEL[13]
GDECEL[14]
GDECEL[15]
The GDECAD bit allows the data to be inserted into the
horizontal blanking period in two ways:
•
Insert all data straight into the data stream, even the reserved
values of 0x00 and 0xFF, if they occur. This may violate the
output data format specification ITU-R BT.1364.
•
Split all data into nibbles and insert the half-bytes over
double the number of cycles in a 4-bit format.
Rev. 0 | Page 55 of 96
ADV7181B
6
4
Table 73. PAL Line Enable Bits and
Corresponding Line Numbering
Line Number
2
line[3:0] (ITU-R BT.470)
Enable Bit
Comment
Not valid
Not valid
Not valid
Not valid
Not valid
Not valid
Not valid
Not valid
Not valid
Not valid
Not valid
Not valid
Not valid
Not valid
Closed caption
Not valid
Not valid
Not valid
Not valid
Not valid
Not valid
Not valid
Not valid
Not valid
Not valid
Not valid
Not valid
Not valid
Not valid
Not valid
Closed caption
Not valid
0
12
13
14
15
0
1
2
3
4
5
6
7
8
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
321 (8)
322 (9)
323 (10)
324 (11)
325 (12)
326 (13)
327 (14)
328 (15)
329 (16)
330 (17)
331 (18)
332 (19)
333 (20)
334 (21)
335 (22)
336 (23)
GDECOL[0]
GDECOL[1]
GDECOL[2]
GDECOL[3]
GDECOL[4]
GDECOL[5]
GDECOL[6]
GDECOL[7]
GDECOL[8]
GDECOL[9]
GDECOL[10]
GDECOL[11]
GDECOL[12]
GDECOL[13]
GDECOL[14]
GDECOL[15]
GDECEL[0]
GDECEL[1]
GDECEL[2]
GDECEL[3]
GDECEL[4]
GDECEL[5]
GDECEL[6]
GDECEL[7]
GDECEL[8]
GDECEL[9]
GDECEL[10]
GDECEL[11]
GDECEL[12]
GDECEL[13]
GDECEL[14]
GDECEL[15]
–2
–4
–6
–8
–10
–12
2.0
2.5
3.0
3.5
4.0
4.5
5.0
FREQUENCY (MHz)
Figure 35. NTSC IF Compensation Filter Responses
6
4
9
10
11
12
13
14
15
0
1
2
3
4
5
6
7
8
9
10
11
2
0
–2
–4
–6
–8
3.0
3.5
4.0
4.5
5.0
5.5
6.0
FREQUENCY (MHz)
Figure 36. PAL IF Compensation Filter Responses
I2C Interrupt System
The ADV7181B has a comprehensive interrupt register set. This
map is located in Register Access Page 2. See Table 82 or details
of the interrupt register map.
IF Compensation Filter
How to access this map is described in Figure 37.
IFFILTSEL[2:0] IF Filter Select Address 0xF8 [2:0]
2
COMMON I C SPACE
ADDRESS 0x00 => 0x3F
The IFFILTSEL[2:0] register allows the user to compensate for
SAW filter characteristics on a composite input as would be
observed on tuner outputs. Figure 35 and Figure 36 show IF
filter compensation for NTSC and PAL.
ADDRESS 0x0E BIT 6,5 = 00b
ADDRESS 0x0E BIT 6,5 = 01b
2
2
I C SPACE
I C SPACE
The options for this feature are as follows:
REGISTER ACCESS PAGE 1
ADDRESS 0x40 => 0xFF
REGISTER ACCESS PAGE 2
ADDRESS 0x40 => 0x4C
•
•
•
Bypass mode (default)
NORMAL REGISTER SPACE
INTERRUPT REGISTER SPACE
Figure 37. Register Access —Page 1 and Page 2
NTSC—consists of three filter characteristics
PAL—consists of three filter characteristics
See Table 84 for programming details.
Rev. 0 | Page 56 of 96
ADV7181B
Interrupt Request Output Operation
INTRQ_OP_SEL[1:0], Interrupt Duration Select
Address 0x40 (Interrupt Space) [1:0]
INTRQ
When an interrupt event occurs, the interrupt pin
goes low with a programmable duration given by
INTRQ_DUR_SEL[1:0]
Table 75. INTRQ_OP_SEL
INTRQ_OP_SEL[1:0] Description
00
01
10
11
Open Drain (default)
Drive Low when Active
Drive High when active
Reserved
INTRQ_DURSEL[1:0], Interrupt Duration Select
Address 0x40 (Interrupt Space) [7:6]
Table 74. INTRQ_DUR_SEL
INTRQ_DURSEL[1:0] Description
Multiple Interrupt Events
00
01
10
11
3 Xtal Periods (default)
15 Xtal Periods
63 Xtal Periods
If Interrupt Event 1 occurs and then Interrupt Event 2 occurs
before the system controller has cleared or masked Interrupt
Event 1, the ADV7181B does not generate a second interrupt
signal. The system controller should check all unmasked
interrupt status bits since more than one may be active.
Active until Cleared
When the “Active until Cleared” interrupt duration is selected
and the event that caused the interrupt is no longer in force, the
interrupt persists until it is masked or cleared.
Macrovision Interrupt Selection Bits
For example, if the ADV7181B loses lock, an interrupt is
The user can select between pseudo sync pulse and color stripe
detection as follows:
INTRQ
generated and the
pin goes low. If the ADV7181B
INTRQ
returns to the locked state,
continues to drive low
until the SD_LOCK bit is either masked or cleared.
MV_INTRQ_SEL[1:0], Macrovision Interrupt Selection Bits
Address 0x40 (Interrupt Space) [5:4]
Interrupt Drive Level
Table 76. MV_INTRQ_SEL
MV_INTRQ_SEL
[1:0]
The ADV7181B resets with open drain enabled and all interrupts
Description
INTRQ
masked off. Therefore,
reset. 01 or 10 must to be written to INTRQ_OP_SEL[1:0] for a
INTRQ
is in a high impedance state after
00
01
10
Reserved
Pseudo Sync Only (default)
Color Stripe Only
logic level to be driven out from the
pin.
It is also possible to write to a register in the ADV7181B that
11
Either Pseudo Sync or Color Stripe
INTRQ
manually asserts the
pin. This bit is MPU_STIM_INTRQ.
Additional information relating to the interrupt system is
detailed in Table 82.
Rev. 0 | Page 57 of 96
ADV7181B
PIXEL PORT CONFIGURATION
The ADV7181B has a very flexible pixel port that can be config-
ured in a variety of formats to accommodate downstream ICs.
Table 77 and Table 78 summarize the various functions that the
ADV7181B pins can have in different modes of operation.
LLC1 Output Selection, LLC_PAD_SEL[2:0],
Address 0x8F [6:4]
The following I2C write allows the user to select between the
LLC1 (nominally at 27 MHz) and LLC2 (nominally at
13.5 MHz).
The ordering of components , for example, Cr versus Cb,
CHA/B/C, can be changed. Refer to the SWPC Swap Pixel
Cr/Cb, Address 0x27 [7] section. Table 77 indicates the default
positions for the Cr/Cb components.
The LLC2 signal is useful for LLC2-compatible wide bus
(16-bit) output modes. See OF_SEL[3:0] Output Format
Selection, Address 0x03 [5:2] for additional information. The
LLC2 signal and data on the data bus are synchronized. By
default, the rising edge of LLC1/LLC2 is aligned with the Y data;
the falling edge occurs when the data bus holds C data. The
polarity of the clock, and therefore the Y/C assignments to the
clock edges, can be altered by using the Polarity LLC pin.
OF_SEL[3:0] Output Format Selection, Address 0x03 [5:2]
The modes in which the ADV7181B pixel port can be configured
are under the control of OF_SEL[3:0]. See Table 78 for details.
The default LLC frequency output on the LLC1 pin is approxi-
mately 27 MHz. For modes that operate with a nominal data
rate of 13.5 MHz (0001, 0010), the clock frequency on the LLC1
pin stays at the higher rate of 27 MHz. For information on
outputting the nominal 13.5 MHz clock on the LLC1 pin, see
the LLC1 Output Selection, LLC_PAD_SEL[2:0],
When LLC_PAD_SEL is 000, the output is nominally 27 MHz
LLC on the LLC1 pin (default).
When LLC_PAD_SEL is 101, the output is nominally 13.5 MHz
LLC on the LLC1 pin.
Address 0x8F [6:4] section.
SWPC Swap Pixel Cr/Cb, Address 0x27 [7]
This bit allows Cr and Cb samples to be swapped.
When SWPC is 0 (default), no swapping is allowed.
When SWPC is 1, the Cr and Cb values can be swapped.
Table 77. P15–P0 Output/Input Pin Mapping
Data Port Pins P[15:0]
Format and Mode
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Video Out, 8-Bit, 4:2:2
Video Out, 16-Bit, 4:2:2
YCrCb[7:0]OUT
Y[7:0]OUT
CrCb[7:0] OUT
Table 78. Standard Definition Pixel Port Modes
P[15: 0]
P[7: 0]
OF_SEL[3:0]
0010
Format
16-Bit @LLC2 4:2:2
P[15:8]
Y[7:0]
CrCb[7:0]
0011
8-Bit @LLC1 4:2:2 (default)
Reserved
YCrCb[7:0]
Three-State
0110-1111
Reserved. Do not use.
Rev. 0 | Page 58 of 96
ADV7181B
MPU PORT DESCRIPTION
The ADV7181B supports a 2-wire (I2C-compatible) serial inter-
face. Two inputs, serial data (SDA) and serial clock (SCLK),
carry information between the ADV7181B and the system I2C
master controller. Each slave device is recognized by a unique
address. The ADV7181B’s I2C port allows the user to set up and
configure the decoder and to read back captured VBI data. The
ADV7181B has four possible slave addresses for both read and
write operations, depending on the logic level on the ALSB pin.
These four unique addresses are shown in Table 79. The
ADV7181B’s ALSB pin controls Bit 1 of the slave address. By
altering the ALSB, it is possible to control two ADV7181Bs in
an application without having a conflict with the same slave
address. The LSB (Bit 0) sets either a read or write operation.
Logic 1 corresponds to a read operation; Logic 0 corresponds to
a write operation.
address. The R/W bit determines the direction of the data. Logic
0 on the LSB of the first byte means that the master writes
information to the peripheral. Logic 1 on the LSB of the first
byte means that the master reads information from the
peripheral.
The ADV7181B acts as a standard slave device on the bus. The
data on the SDA pin is eight bits long, supporting the 7-bit
addresses plus the R/W bit. The ADV7181B has 249 subad-
dresses to enable access to the internal registers. It therefore
interprets the first byte as the device address and the second
byte as the starting subaddress. The subaddresses auto-
increment, allowing data to be written to or read from the
starting subaddress. A data transfer is always terminated by a
stop condition. The user can also access any unique subaddress
register on a one-by-one basis without updating all the registers.
Table 79. I2C Address for ADV7181B
Stop and start conditions can be detected at any stage during the
data transfer. If these conditions are asserted out of sequence with
normal read and write operations, they cause an immediate
jump to the idle condition. During a given SCLK high period,
the user should only issue one start condition, one stop condition,
or a single stop condition followed by a single start condition. If
an invalid subaddress is issued by the user, the ADV7181B does
not issue an acknowledge and returns to the idle condition.
ALSB
R/W
Slave Address
0x40
0x41
0x42
0x43
0
0
1
1
0
1
0
1
To control the device on the bus, a specific protocol must be
followed. First, the master initiates a data transfer by establish-
ing a start condition, which is defined by a high-to-low
If in auto-increment mode the user exceeds the highest
subaddress, the following action is taken:
transition on SDA while SCLK remains high. This indicates that
an address/data stream follows. All peripherals respond to the
start condition and shift the next eight bits (7-bit address +
R/W bit). The bits are transferred from MSB down to LSB. The
peripheral that recognizes the transmitted address responds by
pulling the data line low during the ninth clock pulse; this is
known as an acknowledge bit. All other devices withdraw from
the bus at this point and maintain an idle condition. The idle
condition is where the device monitors the SDA and SCLK
lines, waiting for the start condition and the correct transmitted
1. In read mode, the highest subaddress register contents
continue to be output until the master device issues a no-
acknowledge. This indicates the end of a read. A no-
acknowledge condition is when the SDA line is not pulled
low on the ninth pulse.
2. In write mode, the data for the invalid byte is not loaded
into any subaddress register, a no acknowledge is issued by
the ADV7181B, and the part returns to the idle condition.
SDATA
SCLOCK
S
P
1–7
8
9
1–7
8
9
1–7
DATA
8
9
START ADDR R/W ACK SUBADDRESS ACK
ACK
STOP
Figure 38. Bus Data Transfer
WRITE
S
S
SLAVE ADDR A(S) SUB ADDR
LSB = 0
A(S)
A(S)
DATA
A(S)
DATA
A(M)
A(S) P
SEQUENCE
LSB = 1
READ
SEQUENCE
SLAVE ADDR A(S) SUB ADDR
S
SLAVE ADDR A(S)
DATA
DATA
A(M) P
S = START BIT
P = STOP BIT
A(S) = ACKNOWLEDGE BY SLAVE
A(M) = ACKNOWLEDGE BY MASTER
A(S) = NO-ACKNOWLEDGE BY SLAVE
A(M) = NO-ACKNOWLEDGE BY MASTER
Figure 39: Read and Write Sequence
Rev. 0 | Page 59 of 96
ADV7181B
REGISTER ACCESSES
I2C SEQUENCER
An I2C sequencer is used when a parameter exceeds eight bits,
and is therefore distributed over two or more I2C registers, for
example, HSB [11:0].
The MPU can write to or read from all of the ADV7181B’s
registers, except the Subaddress register, which is write-only.
The Subaddress register determines which register the next read
or write operation accesses. All communications with the part
through the bus start with an access to the Subaddress register.
Then, a read/write operation is performed from/to the target
address, which then increments to the next address until a stop
command on the bus is performed.
When such a parameter is changed using two or more I2C write
operations, the parameter may hold an invalid value for the
time between the first I2C being completed and the last I2C
being completed. In other words, the top bits of the parameter
may already hold the new value while the remaining bits of the
parameter still hold the previous value.
REGISTER PROGRAMMING
The following sections describe each register in terms of its
configuration. The Communications register is an 8-bit, write-
only register. After the part has been accessed over the bus and a
read/write operation is selected, the subaddress is set up. The
Subaddress register determines to/from which register the
operation takes place. Table 81 lists the various operations
under the control of the Subaddress register for the control port.
To avoid this problem, the I2C sequencer holds the already
updated bits of the parameter in local memory; all bits of the
parameter are updated together once the last register write
operation has completed.
The correct operation of the I2C sequencer relies on the
following:
Register Select (SR7–SR0)
•
All I2C registers for the parameter in question must be
written to in order of ascending addresses. For example, for
HSB[10:0], write to Address 0x34 first, followed by 0x35.
These bits are set up to point to the required starting address.
•
No other I2C taking place between the two (or more) I2C
writes for the sequence. For example, for HSB[10:0], write
to Address 0x34 first, immediately followed by 0x35.
Rev. 0 | Page 60 of 96
ADV7181B
I2C REGISTER MAPS
Table 80. Common and Normal (Page 1) Register Map Details
Subaddress
Hex
Register Name
Input Control
Reset Value
0000 0000
1100 1000
0000 0100
0000 1100
01xx 0101
0000 0000
0000 0010
0111 1111
1000 0000
1000 0000
0000 0000
0000 0000
0011 0110
0111 1100
0000 0000
0000 0000
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
0001 0010
0100 xxxx
xxxx xxxx
0000 0001
1001 0011
1111 0001
xxxx xxxx
0000 0xxx
xxxx xxxx
0101 1000
xxxx xxxx
1110 0001
1010 1110
1111 0100
0000 0000
1111 xxxx
xxxx xxxx
0001 0010
0100 0001
1000 0100
0000 0000
0000 0010
0000 0000
0000 0001
1000 0000
1100 0000
0001 0000
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
r
Dec
0
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
Video Selection
Reserved
1
2
Output Control
Extended Output Control
Reserved
3
4
5
Reserved
6
Autodetect Enable
Contrast
7
8
Reserved
9
Brightness
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26–28
29
30-38
39
40-42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
Hue
Default Value Y
Default Value C
ADI Control
Power Management
Status 1
Ident
r
Status 2
r
Status 3
r
Analog Clamp Control
Digital Clamp Control 1
Reserved
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Shaping Filter Control
Shaping Filter Control 2
Comb Filter Control
Reserved
0x1A–0x1C
0x1D
ADI Control 2
Reserved
0x1E-0x26
0x27
Pixel Delay Control
Reserved
0x28–0x2A
0x2B
Misc Gain Control
AGC Mode Control
Chroma Gain Control 1
Chroma Gain Control 2
Luma Gain Control 1
Luma Gain Control 2
VSync Field Control 1
VSync Field Control 2
VSync Field Control 3
HSync Position Control 1
HSync Position Control 2
HSync Position Control 3
Polarity
0x2C
0x2D
0x2E
0x2F
0x30
0x31
0x32
0x33
0x34
0x35
0x36
0x37
NTSC Comb Control
PAL Comb Control
ADC Control
0x38
0x39
0x3A
Rev. 0 | Page 61 of 96
ADV7181B
Subaddress
Hex
Register Name
Reserved
Reset Value
xxxx xxxx
0100 0011
xxxx xxxx
0100 0001
xxxx xxxx
00000000
0000 0000
0000 0000
0000 0000
xxxx xxx0
1110 1111
0000 1000
xxxx xxxx
0000 1000
0010 0100
xxxx xxxx
0000 0000
0000 0000
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
0001 1100
xxxx xxxx
xxxx xxxx
0xxx xxxx
xxxx xxxx
1010 1100
0100 1100
0000 0000
0000 0000
0001 0100
1000 0000
1000 0000
1000 0000
1000 0000
0010 0101
0000 0100
0110 0011
0110 0101
0001 0100
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
w
Dec
59–60
61
0x3B–0x3C
Manual Window Control
Reserved
0x3D
0x3E–0x40
0x41
62–64
65
Resample Control
Reserved
66-71
72
0x42-0x47
0x48
Gemstar Ctrl 1
Gemstar Ctrl 2
Gemstar Ctrl 3
Gemstar Ctrl 4
GemStar Ctrl 5
CTI DNR Ctrl 1
CTI DNR Ctrl 2
Reserved
73
0x49
74
0x4A
75
0x4B
76
0x4C
77
0x4D
0x4E
78
79
0x4F
CTI DNR Ctrl 4
Lock Count
Reserved
80
0x50
81
0x51
82–142
143
144
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158-177
178
179–194
195
196
197–219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
0x52–0x8E
0x8F
Free Run Line Length 1
Reserved
w
0x90
VBI Info
r
0x90
WSS 1
r
0x91
WSS 2
r
0x92
EDTV 1
r
0x93
EDTV 2
r
0x94
EDTV 3
r
0x95
CGMS 1
r
0x96
CGMS 2
r
0x97
CGMS 3
r
0x98
CCAP 1
r
0x99
CCAP 2
r
0x9A
Letterbox 1
Letterbox 2
Letterbox 3
Reserved
r
0x9B
r
0x9C
r
0x9D
0x9E–0xB1
0xB2
rw
w
CRC Enable
Reserved
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
0xB2–0xC2
0xC3
ADC Switch 1
ADC Switch 2
Reserved
0xC4
0xC5–0xDB
0xDC
0xDD
0xDE
0xDF
0xE0
Letterbox Control 1
Letterbox Control 2
Reserved
Reserved
Reserved
SD Offset Cb
SD Offset Cr
SD Saturation Cb
SD Saturation Cr
NTSC V Bit Begin
NTSC V Bit End
NTSC F Bit Toggle
PAL V Bit Begin
PAL V Bit End
0xE1
0xE2
0xE3
0xE4
0xE5
0xE6
0xE7
0xE8
0xE9
Rev. 0 | Page 62 of 96
ADV7181B
Subaddress
Hex
Register Name
PAL F Bit Toggle
Reserved
Reset Value
0110 0011
xxxx xxxx
rw
rw
rw
rw
rw
rw
rw
Dec
234
0xEA
235-243
244
0xEB-0xF3
0xF4
Drive Strength
Reserved
xx01 0101
xxxx xxxx
245-247
248
0xF5-0xF7
0xF8
IF Comp Control
VS Mode Control
0000 0000
0000 0000
249
0xF9
Table 81. Common and Normal (Page 1) Register Map Bit Names
Register
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Input Control
VID_SEL.3
VID_SEL.2
ENHSPLL
VID_SEL.1
BETACAM
VID_SEL.0
INSEL.3
INSEL.2
INSEL.1
INSEL.0
Video
ENVSPROC
Selection
Reserved
Output
Control
VBI_EN
TOD
OF_SEL.3
OF_SEL.2
OF_SEL.1
TIM_OE
OF_SEL.0
BL_C_VBI
SD_DUP_AV
RANGE
Extended
Output
BT656-4
EN_SFL_PI
Control
Reserved
Reserved
Autodetect
Enable
AD_SEC525_EN
CON.7
AD_SECAM_EN
CON.6
AD_N443_EN
CON.5
AD_P60_EN
CON.4
AD_PALN_EN
CON.3
AD_PALM_EN
CON.2
AD_NTSC_EN
CON.1
AD_PAL_EN
CON.0
Contrast
Reserved
Brightness
Hue
BRI.7
BRI.6
BRI.5
BRI.4
BRI.3
BRI.2
BRI.1
BRI.0
HUE.7
DEF_Y.5
HUE.6
DEF_Y.4
HUE.5
DEF_Y.3
HUE.4
DEF_Y.2
HUE.3
DEF_Y.1
HUE.2
DEF_Y.0
HUE.1
HUE.0
Default Value Y
DEF_VAL_
AUTO_EN
DEF_VAL_EN
Default Value C
ADI Control
DEF_C.7
RES
DEF_C.6
DEF_C.5
PWRDN
DEF_C.4
DEF_C.3
DEF_C.2
PDBP
DEF_C.1
DEF_C.0
SUB_USR_EN.0
Power
Management
Status 1
Ident
COL_KILL
IDENT.7
AD_RESULT.2
IDENT.6
AD_RESULT.1
IDENT.5
AD_RESULT.0
IDENT.4
FOLLOW_PW
IDENT.3
FSC_LOCK
IDENT.2
LOST_LOCK
IDENT.1
IN_LOCK
IDENT.0
Status 2
Status 3
FSC NSTD
LL NSTD
MV AGC DET
MV PS DET
SD_OP_50 Hz
MVCS T3
GEMD
MVCS DET
INST_HLOCK
PAL SW LOCK
INTERLACE
DCT.1
STD FLD LEN
FREE_RUN_ACT
CCLEN
Analog Clamp
Control
Digital Clamp
Control 1
DCT.0
Reserved
Shaping Filter
Control
CSFM.2
CSFM.1
CSFM.0
YSFM.4
YSFM.3
YSFM.2
YSFM.1
YSFM.0
Shaping Filter
Control 2
WYSFMOVR
WYSFM.4
WYSFM.3
NSFSEL.1
WYSFM.2
NSFSEL.0
WYSFM.1
PSFSEL.1
WYSFM.0
PSFSEL.0
Comb Filter
Control
Reserved
VS_JIT_COMP_EN
CTA.2
ADI Control 2
Reserved
TRI_LLC
SWPC
EN28XTAL
Pixel Delay
Control
AUTO_PDC_EN
CTA.1
CTA.0
LTA.1
LTA.0
Reserved
Misc Gain
Control
CKE
PW_UPD
CAGC.0
CMG.8
AGC Mode
Control
LAGC.2
CAGT.0
CMG.6
LAGC.1
CMG.5
LAGC.0
CMG.4
CAGC.1
CMG.9
CMG.1
Chroma Gain
Control 1
CAGT.1
CMG.7
CMG.11
CMG.3
CMG.10
CMG.2
Chroma Gain
Control 2
CMG.0
Rev. 0 | Page 63 of 96
ADV7181B
Register
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Luma Gain
Control 1
LAGT.1
LGAT.0
LMG.11
LMG.10
LMG.9
LMG.8
Luma Gain
Control 2
LMG.7
LMG.6
LMG.5
LMG.4
LMG.3
LMG.2
LMG.1
LMG.0
VSync Field
Control 1
NEWAVMODE
HVSTIM
VSync Field
Control 2
VSBHO
VSEHO
VSBHE
VSEHE
HSB.10
VSync Field
Control 3
HSync
HSB.9
HSB.5
HSE.5
HSB.8
HSB.4
HSE.4
HSE.10
HSB.2
HSE.2
HSE.9
HSB.1
HSE.1
HSE.8
HSB.0
HSE.0
Position
Control 1
HSync
Position
Control 2
HSB.7
HSE.7
HSB.6
HSE.6
HSB.3
HSE.3
HSync
Position
Control 3
Polarity
PHS
PVS
PF
PCLK
NTSC Comb
Control
CTAPSN.1
CTAPSN.0
CTAPSP.0
CCMN.2
CCMN.1
CCMP.1
CCMN.0
YCMN.2
YCMN.1
YCMN.0
PAL Comb
Control
CTAPSP.1
CCMP.2
CCMP.0
YCMP.2
YCMP.1
YCMP.0
ADC Control
Reserved
PWRDN_AD C_0
PWRDN_AD C_1
PWRDN_ADC_2
Manual
Window
Control
CKILLTHR.2
SFL_INV
CKILLTHR.1
CKILLTHR.0
Reserved
Resample
Control
Reserved
Gemstar Ctrl 1
Gemstar Ctrl 2
Gemstar Ctrl 3
Gemstar Ctrl 4
Gemstar Ctrl 5
CTI DNR Ctrl 1
CTI DNR Ctrl 2
Reserved
GDECEL.15
GDECEL.7
GDECOL.15
GDECOL.7
GDECEL.14
GDECEL.6
GDECOL.14
GDECOL.6
GDECEL.13
GDECEL.5
GDECOL.13
GDECOL.5
GDECEL.12
GDECEL.4
GDECOL.12
GDECOL.4
GDECEL.11
GDECEL.3
GDECOL.11
GDECOL.3
GDECEL.10
GDECEL.2
GDECOL.10
GDECOL.2
GDECEL.9
GDECEL.1
GDECOL.9
GDECOL.1
GDECEL.8
GDECEL.0
GDECOL.8
GDECOL.0
GDECAD
CTI_EN
DNR_EN
CTI_AB.1
CTI_AB.0
CTI_AB_EN
CTI_C_TH.1
CTI_C_TH.7
CTI_C_TH.6
CTI_C_TH.5
CTI_C_TH.4
CTI_C_TH.3
CTI_C_TH.2
CTI_C_TH.0
CTI DNR Ctrl 4
Lock Count
DNR_TH.7
FSCLE
DNR_TH.6
SRLS
DNR_TH.5
COL.2
DNR_TH.4
COL.1
DNR_TH.3
COL.0
DNR_TH.2
CIL.2
DNR_TH.1
CIL.1
DNR_TH.0
CIL.0
Reserved
Free Run Line
Length 1
LLC_PAD_SEL.2
LLC_PAD_SEL.1
LLC_PAD_SEL.0
Reserved
VBI Info
CGMSD
EDTVD
CCAPD
WSSD
WSS 1
WSS1.7
WSS1.6
WSS1.5
WSS1.4
WSS1.3
WSS1.2
WSS1.1
WSS1.0
WSS 2
WSS2.7
WSS2.6
WSS2.5
WSS2.4
WSS2.3
WSS2.2
WSS2.1
WSS2.0
EDTV 1
EDTV1.7
EDTV2.7
EDTV3.7
CGMS1.7
CGMS2.7
CGMS3.7
CCAP1.7
CCAP2.7
LB_LCT.7
LB_LCM.7
LB_LCB.7
EDTV1.6
EDTV2.6
EDTV3.6
CGMS1.6
CGMS2.6
CGMS3.6
CCAP1.6
CCAP2.6
LB_LCT.6
LB_LCM.6
LB_LCB.6
EDTV1.5
EDTV2.5
EDTV3.5
CGMS1.5
CGMS2.5
CGMS3.5
CCAP1.5
CCAP2.5
LB_LCT.5
LB_LCM.5
LB_LCB.5
EDTV1.4
EDTV2.4
EDTV3.4
CGMS1.4
CGMS2.4
CGMS3.4
CCAP1.4
CCAP2.4
LB_LCT.4
LB_LCM.4
LB_LCB.4
EDTV1.3
EDTV2.3
EDTV3.3
CGMS1.3
CGMS2.3
CGMS3.3
CCAP1.3
CCAP2.3
LB_LCT.3
LB_LCM.3
LB_LCB.3
EDTV1.2
EDTV2.2
EDTV3.2
CGMS1.2
CGMS2.2
CGMS3.2
CCAP1.2
CCAP2.2
LB_LCT.2
LB_LCM.2
LB_LCB.2
EDTV1.1
EDTV2.1
EDTV3.1
CGMS1.1
CGMS2.1
CGMS3.1
CCAP1.1
CCAP2.1
LB_LCT.1
LB_LCM.1
LB_LCB.1
EDTV1.0
EDTV2.0
EDTV3.0
CGMS1.0
CGMS2.0
CGMS3.0
CCAP1.0
CCAP2.0
LB_LCT.0
LB_LCM.0
LB_LCB.0
EDTV 2
EDTV 3
CGMS 1
CGMS 2
CGMS 3
CCAP 1
CCAP 2
Letterbox 1
Letterbox 2
Letterbox 3
Reserved
CRC Enable
Reserved
ADC Switch 1
CRC_ENABLE
ADC0_SW.2
ADC1_SW.3
ADC1_SW.2
ADC1_SW.1
ADC1_SW.0
ADC0_SW.3
ADC0_SW.1
ADC0_SW.0
Rev. 0 | Page 64 of 96
ADV7181B
Register
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ADC Switch 2
Reserved
ADC_SW_M AN
ADC2_SW.3
ADC2_SW.2
ADC2_SW.1
ADC2_SW.0
Letterbox
Control 1
LB_TH.4
LB_SL.0
LB_TH.3
LB_EL.3
LB_TH.2
LB_EL.2
LB_TH.1
LB_EL.1
LB_TH.0
LB_EL.0
Letterbox
Control 2
LB_SL.3
LB_SL.2
LB_SL.1
Reserved
Reserved
Reserved
SD Offset Cb
SD Offset Cr
SD_OFF_CB.7
SD_OFF_CR.7
SD_SAT_CB.7
SD_OFF_CB.6
SD_OFF_CR.6
SD_SAT_CB.6
SD_OFF_CB.5
SD_OFF_CR.5
SD_SAT_CB.5
SD_OFF_CB.4
SD_OFF_CR.4
SD_SAT_CB.4
SD_OFF_CB.3
SD_OFF_CR.3
SD_SAT_CB.3
SD_OFF_CB.2
SD_OFF_CR.2
SD_SAT_CB.2
SD_OFF_CB.1
SD_OFF_CR .1
SD_SAT_CB.1
SD_OFF_CB.0
SD_OFF_CR.0
SD_SAT_CB.0
SD Saturation
Cb
SD Saturation
Cr
SD_SAT_CR.7
NVBEGDEL O
NVENDDEL O
NFTOGDEL O
PVBEGDEL O
SD_SAT_CR.6
NVBEGDEL E
NVENDDEL E
NFTOGDEL E
PVBEGDEL E
SD_SAT_CR.5
NVBEGSIGN
NVENDSIGN
NFTOGSIGN
PVBEGSIGN
SD_SAT_CR.4
NVBEG.4
SD_SAT_CR.3
NVBEG.3
SD_SAT_CR.2
NVBEG.2
SD_SAT_CR.1
NVBEG.1
SD_SAT_CR.0
NVBEG.0
NTSC V Bit
Begin
NTSC V Bit
End
NVEND.4
NFTOG.4
PVBEG.4
NVEND.3
NFTOG.3
PVBEG.3
NVEND.2
NFTOG.2
PVBEG.2
NVEND.1
NFTOG.1
PVBEG.1
NVEND.0
NFTOG.0
PVBEG.0
NTSC F Bit
Toggle
PAL V Bit
Begin
PAL V Bit End
PVENDDEL O
PFTOGDEL O
PVENDDEL E
PFTOGDEL E
PVENDSIGN
PFTOGSIGN
PVEND.4
PFTOG.4
PVEND.3
PFTOG.3
PVEND.2
PFTOG.2
PVEND.1
PFTOG.1
PVEND.0
PFTOG.0
PAL F Bit
Toggle
Reserved
Drive
DR_STR.1
DR_STR.0
DR_STR_C.1
DR_STR_C.0
DR_STR_S.1
DR_STR_S.0
Strength
Reserved
IF Comp
Control
IFFILTSEL.2
IFFILTSEL.1
IFFILTSEL.0
VS Mode
Control
VS_COAST_
MODE.1
VS_COAST_
MODE.0
EXTEND_VS_
MIN_FREQ
EXTEND_VS_
MAX_FREQ
Rev. 0 | Page 65 of 96
ADV7181B
I2C REGISTER MAP DETAILS
The following registers are located in Register Access Page 2.
Table 82. Interrupt Register Map Details4
Subaddress
Register
Name
Reset
Value
rw
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Dec
Hex
MV_INTRQ
_SEL.1
MV_INTRQ
_SEL.0
INTRQ_
DUR_SEL.1
INTRQ_
DUR_SEL.0
MPU_
STIM_INTRQ
INTRQ_
OP_SEL.1
INTRQ_
OP_SEL.0
Interrupt
Config 0
0001 x000
rw
64
0x40
Reserved
65
66
0x41
0x42
SD_
UNLOCK_Q
SD_LOCK_
Q
MV_PS_
CS_Q
SD_FR_
CHNG_Q
Interrupt
Status 1
r
MV_PS_
CS_CLR
SD_FR_
SD_UNLO
CK_CLR
SD_LOCK
_CLR
Interrupt
Clear 1
x000 0000
x000 0000
w
rw
67
68
0x43
0x44
CHNG_CLR
MV_PS_
CS_MSKB
SD_FR_
CHNG_
MSKB
SD_
UNLOCK_
MSKB
SD_LOCK
_MSKB
Interrupt
Maskb 1
Reserved
69
70
0x45
0x46
WSS_
CHNGD_Q
CGMS_
CHNGD_Q
MPU_
STIM_
GEMD_Q
CCAPD_Q
Interrupt
Status 2
r
INTRQ_Q
MPU_
STIM_INT
RQ_CLR
WSS_
CHNGD_
CLR
CGMS_
CHNGD_
CLR
GEMD_
CLR
CCAPD_
CLR
Interrupt
Clear 2
0xxx 0000
0xxx 0000
w
rw
71
72
0x47
0x48
MPU_
STIM_INT
RQ_MSKB
WSS_CHN CGMS_
GD_MSKB
GEMD_
MSKB
CCAPD_
MSKB
Interrupt
Maskb 2
CHNGD_
MSKB
SCM_
LOCK
SD_H_
LOCK
SD_V_
LOCK
SD_OP_
50HZ
Raw Status 3
r
r
73
74
0x49
0x4A
PAL_SW_
LK_
CHNG_Q
SCM_
LOCK_
CHNG_Q
SD_AD_
CHNG_Q
SD_H_
LOCK_
CHNG_Q
SD_V_
LOCK_
CHNG_Q
SD_OP_
CHNG_Q
Interrupt
Status 3
PAL_SW_
LK_CHNG
_CLR
SCM_
LOCK_
CHNG_CLR
SD_AD_
CHNG_
CLR
SD_H_
LOCK_
CHNG_CLR
SD_V_LO SD_OP_
CK_CHNG CHNG_CLR
_CLR
Interrupt
Clear 3
xx00 0000
xx00 0000
w
75
76
0x4B
0x4C
PAL_SW_
LK_CHNG
_MSKB
SCM_
LOCK_CH
NG_MSKB
SD_AD_
CHNG_
MSKB
SD_H_
LOCK_CH
NG_MSKB
SD_V_
SD_OP_
CHNG_
MSKB
Interrupt
Maskb 3
rw
LOCK_CH
NG_MSKB
4 To access the Interrupt Register Map, the Register Access page [1:0] bits in Register Address 0x0E must be programmed to 01b.
Table 83. Interrupt Register Map Details
Bit
Subaddress Register
Bit Description
7
6
5
4
3
2
1
0
0
1
1
0
0
1
0
1
Comments
Notes
0x40
Interrupt
Config 1
INTRQ_OP_SEL[1:0].
Interrupt Drive Level Select
Open drain
Drive low when active
Drive high when active
Reserved
Register
Access
Page 2
MPU_STIM_INTRQ[1:0].
Manual Interrupt Set Mode
0
1
Manual interrupt mode disabled
Manual interrupt mode enabled
Not used
Reserved
x
MV_INTRQ_SEL[1:0].
Macrovision Interrupt Select
0
0
1
1
0
1
0
1
Reserved
Pseudo sync only
Color stripe only
Pseudo sync or color stripe
3 Xtal periods
INTRQ_DUR_SEL[1:0].
Interrupt duration Select
0
0
1
1
0
1
0
1
15 Xtal periods
63 Xtal periods
Active until cleared
Rev. 0 | Page 66 of 96
ADV7181B
Bit
3
Subaddress Register
Bit Description
7
6
5
4
2
1
0
x
Comments
Notes
0x41
0x42
Reserved
x
x
x
x
x
x
x
Interrupt
Status 1
SD_LOCK_Q
0
1
No change
These bits
can be
cleared or
masked in
Resisters
0x43 and
0x44,
SD input has caused the decoder
to go from an unlocked state to
a locked state
Read-Only
SD_UNLOCK_Q
0
1
No change
SD input has caused the
decoder to go from a locked
state to an unlocked state
Register
Access
Page 2
respectively.
Reserved
x
Reserved
x
Reserved
x
SD_FR_CHNG_Q
0
1
No change
Denotes a change in the free-
run status
MV_PS_CS_Q
0
1
No change
Pseudo sync/color striping
detected. See Reg 0x40
MV_INTRQ_SEL[1:0] for
selection
Reserved
x
0x43
0x44
0x45
Interrupt
Clear 1
SD_LOCK_CLR
0
1
Do not clear
Clears SD_LOCK_Q bit
Do not clear
SD_UNLOCK_CLR
0
1
Write-Only
Clears SD_UNLOCK_Q bit
Not used
Reserved
0
Register
Access
Page 2
Reserved
0
Not used
Reserved
0
Not used
SD_FR_CHNG_CLR
0
1
Do not clear
Clears SD_FR_CHNG_Q bit
Do not clear
MV_PS_CS_CLR
0
1
Clears MV_PS_CS_Q bit
Not used
Reserved
x
Interrupt
Mask 1
SD_LOCK_MSKB
0
1
Masks SD_LOCK_Q bit
Do not mask
SD_UNLOCK_MSKB
0
1
Masks SD_UNLOCK_Q bit
Do not mask
Read/Write
Register
Reserved
0
Not used
Reserved
0
Not used
Register
Access
Page 2
Reserved
0
x
Not used
SD_FR_CHNG_MSKB
0
1
Masks SD_FR_CHNG_Q bit
Do not mask
MV_PS_CS_MSKB
Reserved
0
1
Masks MV_PS_CS_Q bit
Do not mask
x
x
Not used
Reserved
x
x
x
x
x
x
Rev. 0 | Page 67 of 96
ADV7181B
Bit
3
Subaddress Register
Bit Description
7
6
5
4
2
1
0
Comments
Notes
0x46
Interrupt
Status 2
CCAPD_Q
0
Closed captioning not detected
in the input video signal
These bits
can be
cleared or
masked by
Registers
0x47 and
0x48,
1
Closed captioning data detected
in the video input signal
Read-Only
Register
GEMD_Q
0
1
Gemstar data not detected in
the input video signal
Gemstar data detected in the
input video signal
Register
Access
Page 2
respectively.
CGMS_CHNGD_Q
0
1
No change detected in CGMS
data in the input video signal
A change is detected in the
CGMS data in the input video
signal
WSS_CHNGD_Q
0
1
No change detected in WSS
data in the input video signal
A change is detected in the WSS
data in the input video signal
Reserved
x
x
0
Not used
Reserved
x
x
0
Not used
Reserved
x
x
0
Not used
MPU_STIM_INTRQ_Q
0
1
Manual interrupt not set
Manual interrupt set
Do not clear
0x47
Interrupt
Clear 2
CCAPD_CLR
0
1
Clears CCAPD_Q bit
Do not clear
GEMD_CLR
0
1
Write-Only
Clears GEMD_Q bit
Do not clear
CGMS_CHNGD_CLR
WSS_CHNGD_CLR
0
1
Register
Access
Page 2
Clears CGMS_CHNGD_Q bit
Do not clear
0
1
Clears WSS_CHNGD_Q bit
Not used
Reserved
Reserved
Not used
Reserved
Not used
MPU_STIM_INTRQ_CLR
0
1
Do not clear
Clears MPU_STIM_INTRQ_Q bit
Do not mask
0x48
Interrupt
Mask 2
CCAPD_MSKB
0
1
Masks CCAPD_Q bit
Do not mask
GEMD_MSKB
0
1
Read /
Write
Masks GEMD_Q bit
Do not mask
CGMS_CHNGD_MSKB
WSS_CHNGD_MSKB
0
1
Masks CGMS_CHNGD_Q bit
Do not mask
Register
Access
Page 2
0
1
Masks WSS_CHNGD_Q bit
Not used
Reserved
Reserved
Not used
Reserved
Not used
MPU_STIM_INTRQ_MSKB
0
Do not mask
Masks MPU_STIM_INTRQ_Q bit
Rev. 0 | Page 68 of 96
ADV7181B
Bit
3
Subaddress Register
Bit Description
7
6
5
4
2
1
0
0
1
Comments
Notes
0x49
Raw
Status 3
SD_OP_50Hz
SD 60/50Hz frame rate at
output
SD 60 Hz signal output
SD 50 Hz signal output
These bits
cannot be
cleared or
masked.
Register
0x4A is used
for this
SD_V_LOCK
SD_H_LOCK
Reserved
0
1
SD vertical sync lock not
established
Read Only
Register
SD vertical sync lock
established
Register
Access
Page 2
purpose.
0
1
SD horizontal sync lock not
established
SD horizontal sync lock
established
x
Not used
SCM_LOCK
SECAM Lock
0
1
SECAM Lock not established
SECAM Lock established
Not used
Reserved
x
Reserved
x
Not used
Reserved
x
Not used
0x4A
Interrupt
Status 3
SD_OP_CHNG_Q
SD 60/50 Hz frame rate at
input
0
1
No Change in SD signal
standard detected at the input
These bits
can be
cleared and
masked by
registers
0x4B and
0x4C,
A Change in SD signal standard
is detected at the input
Read Only
Register
SD_V_LOCK_CHNG_Q
0
1
No Change in SD vertical sync
lock status
SD vertical sync lock status has
changed.
Register
Access
Page 2
respectively.
SD_H_LOCK_CHNG_Q
0
1
No change in SD horizontal sync
lock status.
SD horizontal sync lock status
has changed
SD_AD_CHNG_Q
SD autodetect changed
x
No change in AD_RESULT[2:0]
bits in Status Register 1.
AD_RESULT[2:0] bits in Status
Register 1 have changed
SCM_LOCK_CHNG_Q
SECAM Lock
0
1
No Change in SECAM Lock
status
SECAM lock status has changed
PAL_SW_LK_CHNG_Q
x
No change in PAL swinging
burst lock status
PAL swinging burst lock status
has changed
Reserved
Reserved
x
Not used
Not used
x
Rev. 0 | Page 69 of 96
ADV7181B
Bit
3
Subaddress Register
Bit Description
7
x
x
6
5
4
2
1
0
0
1
Comments
Notes
0x4B
Interrupt
Clear 3
SD_OP_CHNG_CLR
Do not clear
Clears SD_OP_CHNG_Q bit
Do not clear
SD_V_LOCK_CHNG_CLR
SD_H_LOCK_CHNG_CLR
SD_AD_CHNG_CLR
0
1
Write Only
register
Clears SD_V_LOCK_CHNG_Q bit
Do not clear
0
1
Clears SD_H_LOCK_CHNG_Q bit
Do not clear
Register
Access
Page 2
0
1
Clears SD_AD_CHNG_Q bit
Do not clear
SCM_LOCK_CHNG_CLR
PAL_SW_LK_CHNG_CLR
0
1
Clears SCM_LOCK_CHNG_Q bit
Do not clear
0
1
Clears PAL_SW_LK_CHNG_Q bit
Not used
Reserved
x
Reserved
Not used
0x4C
Interrupt
Mask 2
SD_OP_CHNG_MSKB
0
1
Do not mask
Masks SD_OP_CHNG_Q bit
Do not mask
SD_V_LOCK_CHNG_MSKB
SD_H_LOCK_CHNG_MSKB
SD_AD_CHNG_MSKB
0
1
Read /
Write
Register
Masks SD_V_LOCK_CHNG_Q bit
Do not mask
0
1
Masks SD_H_LOCK_CHNG_Q bit
Do not mask
0
1
Register
Access
Page 2
Masks SD_AD_CHNG_Q bit
Do not mask
SCM_LOCK_CHNG_MSKB
PAL_SW_LK_CHNG_MSKB
0
1
Masks SCM_LOCK_CHNG_Q bit
Do not mask
0
1
Masks PAL_SW_LK_CHNG_Q bit
Not used
Reserved
Reserved
x
Not used
Rev. 0 | Page 70 of 96
ADV7181B
Table 84. Common and Normal (Page 1) Register Map Details
Bits
Subaddress Register
Bit Description
Comments
Composite
Reserved
Reserved
Reserved
Reserved
Reserved
S-Video
Notes
7
6
5
4
3
2
0
0
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
0
1
1
0
0
1
0
0
1
0
1
0
1
0
1
0
1
0
0x00
Input
INSEL [3:0]. The INSEL bits allow the
user to select an input channel as
well as the input format.
0
0
0
0
0
0
0
0
1
1
1
Control
Reserved
Reserved
YPrPb
Reserved
1
1
1
1
1
0
1
1
1
1
1
0
0
1
1
1
0
1
0
1
Reserved
Reserved
Reserved
Reserved
Reserved
VID_SEL [3:0]. The VID_SEL bits
allow the user to select the input
video standard.
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
Autodetect PAL (BGHID),
NTSC (without pedestal),
SECAM
Autodetect PAL (BGHID),
NTSC (M) (with pedestal),
SECAM
Autodetect PAL (N), NTSC
(M) (without pedestal),
SECAM
Autodetect PAL (N), NTSC
(M) (with pedestal),
SECAM
0
0
0
0
1
1
1
1
1
1
0
0
0
0
1
1
0
0
0
1
0
1
0
1
NTSC(J)
NTSC(M)
PAL 60
NTSC 4.43
PAL BGHID
PAL N (BGHID without
pedestal)
1
1
1
1
1
1
0
0
1
1
1
1
1
1
0
0
1
1
0
1
0
1
0
1
PAL M (without pedestal)
PAL M
PAL combination N
PAL combination N
SECAM (with pedestal)
SECAM (with pedestal)
Set to default
0x01
Video
Reserved
0
0
0
Selection
ENVSPROC
0
1
Disable VSync processor
Enable VSync processor
Set to default
Reserved
BETACAM
0
0
1
Standard video input
Betacam input enable
Disable HSync processor
Enable HSync processor
Set to default
ENHSPL
0
1
Reserved
1
Rev. 0 | Page 71 of 96
ADV7181B
Bits
Subaddress Register
Bit Description
Comments
Notes
7
6
5
4
3
2
1
0
0x03
Output
Control
SD_DUP_AV. Duplicates the AV
codes from the Luma into the
chroma path.
0
AV codes to suit 8-bit
interleaved data output
1
AV codes duplicated (for
16-bit interfaces)
Reserved
0
Set as default
Reserved
OF_SEL [3:0]. Allows the user to
choose from a set of output formats.
0
0
0
0
0
0
1
0
0
0
1
1
0
1
0
1
Reserved
16-bit @ LLC1 4:2:2
8-bit @ LLC1 4:2:2
ITU-R BT.656
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
Not used
Not used
Not used
Not used
Not used
Not used
Not used
Not used
Not used
Not used
Not used
Not used
Output pins enabled
TOD. Three-state output drivers.
This bit allows the user to three-
state the output drivers: P[19:0], HS,
VS, FIELD, and SFL.
0
1
See also TIM_OE
and TRI_LLC
Drivers three-stated
VBI_EN. Allows VBI data (Lines 1 to
21) to be passed through with only
a minimum amount of filtering
performed.
0
1
All lines filtered and scaled
Only active video region
filtered
0x04
Extended
Output
Control
RANGE. Allows the user to select the
range of output values. Can be
BT656-compliant, or can fill the
whole accessible number range.
0
1
16 < Y < 235, 16 < C < 240
1 < Y < 254, 1 < C < 254
ITU-R BT.656
Extended range
EN_SFL_PIN
0
1
SFL output is disabled
SFL output enables
encoder and
decoder to be
SFL information output on
the SFL pin
connected directly
BL_C_VBI. Blank chroma during VBI.
If set, enables data in the VBI region
to be passed through the decoder
undistorted.
0
1
Decode and output color
Blank Cr and Cb
During VBI
TIM_OE. Timing signals output
enable.
0
1
HS, VS, F three-stated
HS, VS, F forced active
Controlled by TOD
Reserved
Reserved
x
x
1
BT656-4. Allows the user to select an
output mode-compatible with
ITU- R BT656-3/4.
0
1
BT656-3-compatible
BT656-4-compatible
Rev. 0 | Page 72 of 96
ADV7181B
Bits
Subaddress Register
Bit Description
Comments
Disable
Notes
7
6
5
4
3
2
1
0
0
1
Autodetect
Enable
0x07
AD_PAL_EN. PAL B/G/I/H autodetect
enable.
Enable
AD_NTSC_EN. NTSC autodetect
enable.
0
1
Disable
Enable
Disable
AD_PALM_EN. PAL M autodetect
enable.
0
1
Enable
Disable
AD_PALN_EN. PAL N autodetect
enable.
0
1
Enable
Disable
AD_P60_EN. PAL 60 autodetect
enable.
0
1
Enable
Disable
AD_N443_EN. NTSC443 autodetect
enable.
0
1
Enable
Disable
AD_SECAM_EN. SECAM autodetect
enable.
0
1
Enable
Disable
AD_SEC525_EN. SECAM 525
autodetect enable.
0
1
1
Enable
0x08
Contrast
Register
CON[7:0]. Contrast adjust. This is the
user control for contrast adjustment.
0
0
0
0
0
0
0
Luma gain = 1
0x00 Gain = 0;
0x80 Gain = 1;
0xFF Gain = 2
0x09
0x0A
Reserved
Reserved
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Brightness
Register
BRI[7:0]. This register controls the
brightness of the video signal.
0x00 = 0IRE;
0x7F = 100IRE;
0x80 = –100IRE
0x0B
0x0C
Hue
Register
HUE[7:0]. This register contains the
value for the color hue adjustment.
0
0
0
0
0
0
0
0
0
1
Hue range =
–90° to +90°
Default
Value Y
DEF_VAL_EN. Default value enable.
DEF_VAL_AUTO_EN. Default value.
Free-run mode dependent
on DEF_VAL_AUTO_EN
Force Free-run mode on
and output blue screen
0
1
Disable Free-run mode
When lock is lost,
Free-run mode can
be enabled to
Enable Automatic Free-
run mode (blue screen)
output stable
timing, clock, and a
set color.
DEF_Y[5:0]. Default value Y. This
register holds the Y default value.
0
0
0
1
1
1
1
1
0
1
1
1
Y[7:0] = {DEF_Y[5:0],0, 0}
Default Y value
output in Free-run
mode.
Cr[7:0] = DEF_C[7:4],0, 0, 0, 0}
Cb[7:0] = DEF_C[3:0], 0, 0,
0, 0}
0x0D
0x0E
Default
Value C
DEF_C[7:0]. Default value C. The Cr
and Cb default values are defined in
this register.
0
0
0
0
Default Cb/Cr value
output in Free-run
mode. Default
values give blue
screen output.
ADI
Reserved
0
0
0
Set as Default
Control
SUB_USR_EN. Enables the user to
access the Interrupt map
0
1
Access User Reg Map
Access Interrupt Reg Map
Set as default
See Figure 37
Reserved
0
0
Rev. 0 | Page 73 of 96
ADV7181B
Bits
Subaddress Register
Bit Description
Comments
Notes
7
6
5
4
3
2
1
0
0x0F
Power
Management
Reserved
0
0
Set to default
PDBP. Power-down bit priority
selects between PWRDN bit or PIN.
0
1
Chip power-down
controlled by pin
Bit has priority (pin
disregarded)
Reserved
0
0
Set to default
PWRDN. Power-down places the
decoder in a full power-down mode.
0
1
System functional
Powered down
Set to default
See PDBP, 0x0F Bit 2.
Reserved
0
RES. Chip reset loads all I2C bits with
default values.
0
1
Normal operation
Start reset sequence
Executing reset
takes approx. 2 ms.
This bit is self-
clearing.
0x10
Status
Register 1.
IN_LOCK
x
In lock (right now) = 1
Lost lock (since last read) = 1
Fsc lock (right now) = 1
Provides
information about
the internal status of
the decoder.
LOST_LOCK
FSC_LOCK
FOLLOW_PW
x
Read-Only
x
x
Peak white AGC mode
active = 1
AD_RESULT[2:0]. Autodetection
result reports the standard of the
Input video.
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
NTSM-MJ
Detected standard.
NTSC-443
PAL-M
PAL-60
PAL-BGHID
SECAM
PAL combination N
SECAM 525
Color kill is active = 1
COL_KILL.
x
x
Color Kill.
0x11
0x12
IDENT
IDENT[7:0] Provides identification
on the revision of the part.
x
x
x
x
x
x
x
x
x
x
x
ADV7181B = 0x13
Read-Only
Status
MVCS DET
MVCS T3
MV color striping detected 1 = Detected
Register 2.
Read-Only.
MV color striping type
0 = Type 2,
1 = Type 3
MV PS DET
MV AGC DET
LL NSTD
MV pseudo sync detected
MV AGC pulses detected
Nonstandard line length
1 = Detected
1 = Detected
1 = Detected
1 = Detected
x
FSC NSTD
x
Fsc frequency
nonstandard
Reserved
x
x
0x13
Status
Register 3.
Read-Only.
INST_HLOCK
x
1 = horizontal lock
achieved
Unfiltered
GEMD
x
1 = Gemstar data detected
SD 60 Hz detected
SD_OP_50HZ
Reserved
x
SD Field rate detect
Blue screen output
x
SD 50 Hz detected
FREE_RUN_ACT
STD FLD_LEN
x
1 = Free-run mode active
1 = Field length standard
x
Correct Field length
found
INTERLACED
PAL_SW_LOCK
Reserved
x
1 = Interlaced video
detected
Field sequence
found
x
1 = Swinging burst
detected
Reliable swinging
burst sequence
0x14
Analog
Clamp
Control
0
0
1
0
Set to default.
CCLEN. Current clamp enable allows
the user to switch off the current
sources in the analog front.
0
1
Current sources switched
off
Current sources enabled
Set to default
Reserved
0
0
0
Rev. 0 | Page 74 of 96
ADV7181B
Bits
Subaddress Register
Bit Description
Comments
Notes
7
6
5
4
3
2
1
0
0x15
Digital
Clamp
Control 1
Reserved
0
x
x
x
x
Set to default
DCT[1:0]. Digital clamp timing
determines the time constant of the
digital fine clamp circuitry.
0
0
1
1
0
1
0
1
Slow (TC = 1 s)
Medium (TC = 0.5 s)
Fast (TC = 0.1 s)
TC dependent on video
Set to default
Reserved
0
0x17
Shaping
Filter
Control
YSFM[4:0]. Selects Y Shaping Filter
mode when in CVBS only mode.
0
0
0
0
0
0
0
0
0
1
Auto wide notch for poor
quality sources or wide-
band filter with Comb for
good quality input
Auto narrow notch for
poor quality sources or
wideband filter with comb
for good quality input
SVHS 1
SVHS 2
SVHS 3
SVHS 4
SVHS 5
SVHS 6
SVHS 7
SVHS 8
SVHS 9
SVHS 10
SVHS 11
SVHS 12
SVHS 13
SVHS 14
SVHS 15
SVHS 16
SVHS 17
SVHS 18 (CCIR601)
PAL NN1
PAL NN2
PAL NN3
PAL WN 1
PAL WN 2
NTSC NN1
NTSC NN2
NTSC NN3
NTSC WN1
NTSC WN2
NTSC WN3
Reserved
Auto selection 15. MHz
Auto selection 2.17 MHz
Decoder selects
optimum Y shaping
filter depending on
CVBS quality.
Allows the user to select a wide
range of low-pass and notch filters.
If either auto mode is selected, the
decoder selects the optimum Y filter
depending on the CVBS video
source quality (good vs. bad).
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
If one of these
modes is selected,.
the decoder does
not change filter
modes. Depending
on video quality, a
fixed filter response
(the one selected) is
used for good and
bad quality video.
CSFM[2:0].
0
0
0
0
0
1
Automatically
selects a C filter
based on video
standard and
quality.
Selects a C filter for
all video standards
and for good and
bad video.
C Shaping Filter mode allows the
selection from a range of low-pass
chrominance filters.
If either auto mode is selected, the
decoder selects the optimum C filter
depending on the CVBS video
source quality (good vs. bad). Non-
auto settings force a C filter for all
standards and quality of CVBS video.
0
0
1
1
1
1
1
1
0
0
1
1
0
1
0
1
0
1
SH1
SH2
SH3
SH4
SH5
Wideband mode
Rev. 0 | Page 75 of 96
ADV7181B
Bits
Subaddress Register
Bit Description
Comments
Reserved. Do not use.
Reserved. Do not use.
SVHS 1
Notes
7
6
5
4
3
2
0
0
0
0
1
1
1
0
0
1
1
0
0
0
0
1
0
1
0
1
0x18
Shaping
Filter
WYSFM[4:0]. Wideband Y Shaping
Filter mode allows the user to select
which Y shaping filter is used for the
Y component of Y/C, YPbPr, B/W
input signals; it is also used when a
good quality input CVBS signal is
detected. For all other inputs, the Y
shaping filter chosen is controlled
by YSFM[4:0].
0
0
0
0
0
0
0
0
0
0
0
0
Control 2
SVHS 2
SVHS 3
SVHS 4
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
~
1
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
~
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
~
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
~
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
~
1
SVHS 5
SVHS 6
SVHS 7
SVHS 8
SVHS 9
SVHS 10
SVHS 11
SVHS 12
SVHS 13
SVHS 14
SVHS 15
SVHS 16
SVHS 17
SVHS 18 (CCIR 601)
Reserved. Do not use.
Reserved. Do not use.
Reserved. Do not use.
Reserved
0
0
Set to default
WYSFMOVR. Enables the use of
automatic WYSFN filter.
0
1
Manual select filter using
WYSFM[4:0]
Autoselection of best filter
Narrow
0x19
Comb
Filter
PSFSEL[1:0]. Controls the signal
bandwidth that is fed to the comb
filters (PAL).
0
0
1
1
0
1
0
1
Medium
Control
Wide
Widest
NSFSEL[1:0]. Controls the signal
bandwidth that is fed to the comb
filters (NTSC).
0
0
1
1
0
1
0
1
Narrow
Medium
Medium
Wide
Reserved
1
1
1
1
0
Set as default
Set to default
Enabled
0x1D
ADI
Control 2
Reserved
0
x
x
x
VS_JIT_COMP_EN
0
1
Disabled
EN28XTAL
TRI_LLC
0
1
Use 27 MHz crystal
Use 28 MHz crystal
LLC pin active
0
1
LLC pin three-stated
Rev. 0 | Page 76 of 96
ADV7181B
Bits
Subaddress Register
Bit Description
Comments
Notes
7
6
5
4
3
2
1
0
0x27
Pixel Delay
Control
LTA[1:0]. Luma timing adjust allows
the user to specify a timing difference
between chroma and luma samples.
0
0
No Delay
CVBS mode
LTA[1:0] = 00b;
S-Video mode
LTA[1:0]= 01b,
YPrPb mode
LTA[1:0] = 01b
1
1
0
0
Luma 1 clk (37 nS) delayed
Luma 2 clk (74 nS) early
1
1
Luma 1 clk (37 nS) early
Reserved
0
Set to Zero
CTA[2:0]. Chroma timing adjust
allows a specified timing difference
between the luma and chroma
samples
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Not valid setting
CVBS mode
CTA[2:0] = 011b
Chroma +2 pixels (early)
Chroma +1 pixel (early)
No delay
S-Video mode
CTA[2:0] = 101b
Chroma -1 pixel (late)
Chroma -2 pixels (late)
Chroma -3 pixels (late)
Not valid setting
YPrPb mode
CTA[2:0] = 110b
AUTO_PDC_EN. Automatically
programs the LTA/CTA values so
that luma and chroma are aligned at
the output for all modes of
operation.
0
1
Use values in LTA[1:0] and
CTA[2:0] for delaying
luma/chroma
LTA and CTA values
determined automatically
SWPC. Allows the Cr and Cb samples
to be swapped.
0
1
No Swapping
See
Swap_CR_CB_WB,
Addr 0x89
Swap the Cr and Cb O/P
samples
0x2B
Misc Gain
Control
PW_UPD. Peak white update
determines the rate of gain.
0
1
Update once per video
line
Peak white must be
enabled. See
LAGC[2:0]
Update once per field
Reserved
1
0
0
0
0
Set to default
CKE. Color kill enable allows the
color kill function to be switched on
and off.
0
1
Color kill disabled
Color kill enabled
For SECAM color kill,
threshold is set at
8%
See CKILLTHR[2:0]
Reserved
1
Set to default
0x2C
AGC Mode
Control
CAGC[1:0]. Chroma automatic gain
control selects the basic mode of
operation for the AGC in the chroma
path.
0
0
1
1
0
1
0
1
Manual fixed gain
Use luma gain for chroma
Automatic gain
Freeze chroma gain
Set to 1
Use CMG[11:0]
Based on color burst
Reserved
1
1
LAGC[2:0]. Luma automatic gain
control selects the mode of
operation for the gain control in the
luma path.
0
0
0
0
0
1
Manual fixed gain
Use LMG[11:0]
AGC no override through
peak white. Man IRE
control.
Blank level to sync
tip
0
0
1
1
1
0
0
1
0
AGC auto-override
through peak white. Man
IRE control.
Blank level to sync
tip
AGC no override through
peak white. Auto IRE
control.
Blank level to sync
tip
AGC auto-override through Blank level to sync
peak white. Auto IRE
control.
tip
1
1
1
0
1
1
1
0
1
AGC active video with
peak white
AGC active video with
average video
Freeze gain
Set to 1
Reserved
1
Rev. 0 | Page 77 of 96
ADV7181B
Bits
Subaddress Register
Bit Description
Comments
Notes
7
6
5
4
3
2
1
0
0x2D
Chroma
Gain
Control 1
CMG[11:8]. Chroma manual gain can
be used to program a desired
manual chroma gain. Reading back
from this register in AGC mode gives
the current gain.
0
1
0
0
CAGC[1:0] settings
decide in which
mode CMG[11:0]
operates
Reserved
1
0
1
0
Set to 1
CAGT[1:0]. Chroma automatic gain
timing allows adjustment of the
chroma AGC tracking speed.
0
0
1
1
0
0
1
0
1
0
Slow (TC = 2 s)
Medium (TC = 1 s)
Fast (TC = 0.2 s)
Adaptive
Has an effect only if
CAGC[1:0] is set to
auto gain (10)
0x2E
0x2F
Chroma
Gain
Control 2
CMG[7:0]. Chroma manual gain
lower 8 bits. See CMG[11:8] for
description.
0
x
0
x
0
x
0
x
CMG[11:0] = 750d; gain is
1 in NTSC
CMG[11:0] = 741d; gain is
1 in PAL
Min value is 0dec
(G = –60 dB)
Max value is 3750
(Gain = 5)
Luma Gain
Control 1
LMG[11:8]. Luma manual gain can
be used program a desired manual
chroma gain, or to read back the
actual gain value used.
LAGC[1:0] settings decide
in which mode LMG[11:0]
operates
Reserved
1
x
1
x
Set to 1
LAGT[1:0]. Luma automatic gain
timing allows adjustment of the
luma AGC tracking speed.
0
0
1
1
x
0
1
0
1
x
Slow (TC = 2 s)
Medium (TC = 1 s)
Fast (TC = 0.2 s)
Adaptive
Only has an effect if
LAGC[1:0] is set to
auto gain (001, 010,
011,or 100)
0x30
0x31
Luma Gain
Control 2
LMG[7:0]. Luma manual gain can be
used to program a desired manual
chroma gain or read back the actual
used gain value.
x
x
x
x
LMG[11:0] = 1234d; gain is
1 in NTSC LMG[11:0] =
1266d; gain is 1 in PAL
Min value
NTSC 1024 (G = 0.85)
PAL (G = 0.81)
Max value
NTSC 2468 (G = 2),
PAL = 2532 (G = 2)
VS and
FIELD
Control 1
Reserved
0
1
0
Set to default
HVSTIM. Selects where within a line
of video the VS signal is asserted.
0
1
Start of line relative to HSE HSE = Hsync end
Start of line relative to HSB HSB = Hsync begin
NEWAVMODE. Sets the EAV/SAV
mode.
0
1
EAV/SAV codes generated
to suit ADI encoders
Manual VS/Field position
controlled by registers
0x32, 0x33, and 0xE5–0xEA
Reserved
Reserved
VSBHE
0
0
0
0
Set to default
0x32
VSync
Field
Control 2
0
0
0
0
1
Set to default
NEWAVMODE bit
must be set high.
0
1
VS goes high in the middle
of the line (even field)
VS changes state at the
start of the line (even field)
VSBHO
0
1
VS goes high in the middle
of the line (odd field)
VS changes state at the
start of the line (odd field)
0x33
VSync
Field
Control 3
Reserved
VSEHE
0
0
0
1
0
0
Set to default
0
1
VS goes low in the middle
of the line (even field)
NEWAVMODE bit
must be set high.
VS changes state at the
start of the line (even
field)
VSEHO
0
1
VS goes low in the middle
of the line (odd field)
VS changes state at the
start of the line odd field
Rev. 0 | Page 78 of 96
ADV7181B
Bits
Subaddress Register
Bit Description
Comments
Notes
7
6
5
4
3
2
1
0
0x34
HS
Position
Control 1
HSE[10:8]. HS end allows the
positioning of the HS output within
the video line.
0
0
0
HS output ends HSE[10:0]
pixels after the falling edge
of HSync
Using HSB and HSE
the user can
program the
position and length
of the output HSync
Reserved
0
Set to 0
HSB[10:8]. HS begin allows the
positioning of the HS output within
the video line.
0
0
0
HS output starts HSB[10:0]
pixels after the falling edge
of HSync
Reserved
0
0
Set to 0
0x35
HS
HSB[7:0] See above, using HSB[10:0]
and HSE[10:0], the user can program
the position and length of HS output
signal.
0
0
0
0
0
0
0
0
0
0
1
0
0
0
Position
Control 2
0x36
0x37
HS
Position
Control 3
HSE[7:0] See above.
0
Polarity
PCLK. Sets the polarity of LLC1.
0
1
Invert polarity
Normal polarity as per the
timing diagrams
Reserved
0
0
Set to 0
PF. Sets the FIELD polarity.
0
1
Active high
Active low
Set to 0
Reserved
0
PVS. Sets the VS Polarity.
0
1
Active high
Active low
Set to 0
Reserved
0
PHS. Sets HS Polarity.
0
1
Active high
Active low
Rev. 0 | Page 79 of 96
ADV7181B
Bits
Subaddress Register
Bit Description
Comments
Notes
7
6
5
4
3
2
0
1
1
1
1
1
0
0
0
1
1
0
0
0
1
0
1
0x38
NTSC
Comb
Control
YCMN[2:0]. Luma
Comb Mode, NTSC.
Adaptive 3-line, 3-tap luma
Use low-pass notch
Top lines of memory
All lines of memory
Fixed luma comb (2-line)
Fixed luma comb (3-Line)
Fixed luma comb (2-line)
Bottom lines of
memory
CCMN[2:0]. Chroma
Comb Mode, NTSC.
0
0
0
3-line adaptive for
CTAPSN = 01
4-line adaptive for
CTAPSN = 10
5-line adaptive for
CTAPSN = 11
1
1
0
0
0
1
Disable chroma comb
Fixed 2-line for
CTAPSN = 01
Top lines of memory
All lines of memory
Fixed 3-line for
CTAPSN = 10
Fixed 4-line for
CTAPSN = 11
1
1
1
1
0
1
Fixed 3-line for
CTAPSN = 01
Fixed 4-line for
CTAPSN = 10
Fixed 5-line for
CTAPSN = 11
Fixed 2-line for
CTAPSN = 01
Bottom lines of
memory
Fixed 3-line for
CTAPSN = 10
Fixed 4-line for
CTAPSN = 11
CTAPSN[1:0]. Chroma
Comb Taps, NTSC.
0
0
1
1
0
1
0
1
Adapts 3 lines – 2 lines
Not used
Adapts 5 lines – 3 lines
Adapts 5 lines – 4 lines
Rev. 0 | Page 80 of 96
ADV7181B
Bits
Subaddress Register
Bit Description
Comments
Notes
7
6
5
4
3
2
1
0
0x39
PAL Comb
Control
YCMP[2:0]. Luma Comb mode, PAL.
0
0
0
Adaptive 5-line, 3-tap
luma comb
1
1
1
1
0
1
1
1
0
0
0
1
Use low-pass notch
Top lines of memory
All lines of memory
Fixed luma comb
Fixed luma comb (5-line)
Fixed luma comb (3-line)
Bottom lines of
memory
CCMP[2:0]. Chroma Comb mode,
PAL.
0
0
0
3-line adaptive for
CTAPSN = 01
4-line adaptive for
CTAPSN = 10
5-line adaptive for
CTAPSN = 11
1
1
0
0
0
1
Disable chroma comb
Fixed 2-line for CTAPSN = 01
Fixed 3-line for CTAPSN = 10
Fixed 4-line for CTAPSN = 11
Fixed 3-line for CTAPSN = 01
Fixed 4-line for CTAPSN = 10
Fixed 5-line for CTAPSN = 11
Fixed 2-line for CTAPSN = 01
Top lines of memory
All lines of memory
1
1
1
1
0
1
Bottom lines of
memory
Fixed 3-line for CTAPSN = 10
Fixed 4-line for CTAPSN = 11
CTAPSP[1:0]. Chroma comb taps, PAL.
0
0
Adapts 5-lines – 2 lines
(2 taps)
0
1
1
0
Not used
Adapts 5 lines – 3 lines
(3 taps)
1
1
Adapts 5 lines – 4 lines
(4 taps)
0x3A
Reserved
0
Set as default
ADC2 normal operation
Power down ADC2
ADC1 normal operation
Power down ADC1
ADC0 normal operation
Power down ADC0
Set as default
Set to default
Kill at 0.5%
PWRDN_ADC_2. Enables power-
down of ADC2.
0
1
PWRDN_ADC_1. Enables power-
down of ADC1.
0
1
PWRDN_ADC_0. Enables power-
down of ADC0.
0
1
Reserved
0
0
0
1
0x3D
Manual
Window
Control
Reserved
0
0
1
1
CKILLTHR[2:0].
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
CKE = 1 enables the
color kill function
and must be
enabled for
CKILLTHR[2:0] to
take effect.
Kill at 1.5%
Kill at 2.5%
Kill at 4%
Kill at 8.5%
Kill at 16%
Kill at 32%
Reserved
Reserved
0
Set to default
Rev. 0 | Page 81 of 96
ADV7181B
Bits
Subaddress Register
Bit Description
Comments
Notes
7
6
5
4
3
2
1
0
0x41
Resample
Control
Reserved
0
1
0
0
0
0
Set to default
SFL_INV. Controls the behavior of
the PAL switch bit.
0
SFL compatible with
ADV7190/ADV7191/
ADV7194 encoders
1
SFL compatible with
ADV717x/ADV7173x
encoders
Reserved
0
0
Set to default
0x48
0x49
Gemstar
Control 1
GDECEL[15:8]. See the Comments
column.
0
0
0
0
0
0
0
0
0
0
0
0
0
0
GDECEL[15:0]. 16
LSB = Line 10 MSB =
Line 25
individual enable bits that
select the lines of video
(even field Lines 10–25)
that the decoder checks
for Gemstar-compatible
data.
Default = Do not
check for Gemstar-
compatible data on
any lines [10–25] in
even fields
Gemstar
Control 2
GDECEL[7:0]. See above.
0
0x4A
0x4B
Gemstar
Control 3
GDECOL[15:8]. See the Comments
column.
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
GDECOL[15:0]. 16
LSB = Line 10 MSB =
Line 25
individual enable bits that
select the lines of video
(odd field Lines 10–25)
that the decoder checks
for Gemstar-compatible
data.
Default = Do not
check for Gemstar-
compatible data on
any lines [10–25] in
odd fields
Gemstar
Control 4
GDECOL[7:0]. See above.
0x4C
Gemstar
Control 5
GDECAD. Controls the manner in
which decoded Gemstar data is
inserted into the horizontal blanking
period.
0
1
Split data into half byte
To avoid 00/FF code.
Output in straight 8-bit
format
Reserved
x
x
x
x
x
x
x
Undefined
0x4D
CTI DNR
Control 1
CTI_EN. CTI enable
0
1
Disable CTI
Enable CTI
CTI_AB_EN. Enables the mixing of
the transient improved chroma with
the original signal.
0
1
Disable CTI alpha blender
Enable CTI alpha blender
CTI_AB[1:0]. Controls the behavior
of the alpha-blend circuitry.
0
0
1
0
1
Sharpest mixing
Sharp mixing
0
1
1
Smooth
Smoothest
Reserved
0
Set to default
DNR_EN. Enable or bypass the DNR
block.
0
1
Bypass the DNR block
Enable the DNR block
Set to default
Reserved
1
0
1
0
0x4E
0x50
CTI DNR
Control 2
CTI_CTH[7:0]. Specifies how big the
amplitude step must be to be
steepened by the CTI block.
0
0
0
0
1
1
0
0
0
0
0
0
Set to 0x04 for A/V input;
set to 0x0A for tuner input
CTI DNR
Control 4
DNR_TH[7:0]. Specifies the
0
0
maximum edge that is interpreted
as noise and is therefore blanked.
Rev. 0 | Page 82 of 96
ADV7181B
Bits
Subaddress Register
Bit Description
Comments
Notes
7
6
5
4
3
2
0
0
0
0
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0x51
Lock Count CIL[2:0]. Count-into-lock determines
the number of lines the system must
remain in lock before showing a
locked status.
1 line of video
2 lines of video
5 lines of video
10 lines of video
100 lines of video
500 lines of video
1000 lines of video
100000 lines of video
1 line of video
COL[2:0]. Count-out-of-lock
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
determines the number of lines the
system must remain out-of-lock
before showing a lost-locked status.
1
0
1
0
1
0
1
2 lines of video
5 lines of video
10 lines of video
100 lines of video
500 lines of video
1000 lines of video
100000 lines of video
SRLS. Select raw lock signal. Selects
the determination of the lock.
Status.
0
1
Over field with vertical
info
Line-to-line evaluation
FSCLE. Fsc lock enable.
0
1
Lock status set only by
horizontal lock
Lock status set by
horizontal lock and
subcarrier lock.
0x8F
0x90
Free Run
Line
Length 1
Reserved
0
0
0
0
Set to default
LLC_PAD_SEL [2:0]. Enables manual
selection of clock for LLC1 pin.
0
1
0
0
0
1
LLC1 (nominal 27 MHz)
selected out on LLC1 pin
LLC2 (nominally 13.5 MHz) For 16-bit 4:2:2 out,
selected out on LLC1 pin
OF_SEL[3:0] = 0010
Reserved
0
Set to default
VBI Info
(Read
Only)
WSSD. Screen signaling detected.
0
1
No WSS detected
Read-only status
bits
WSS detected
CCAPD. Closed caption data.
EDTVD. EDTV sequence
0
1
No CCAP signals detected
CCAP sequence detected
0
1
No EDTV sequence
detected
EDTV sequence detected
CGMSD. CGMS sequence
Reserved
0
1
No CGMS transition
detected
CGMS sequence decoded
x
x
x
x
x
x
x
x
0x91
0x92
0x93
0x94
0x95
0x96
0x97
0x98
WSS1
WSS1[7:0]
Wide screen signaling data.
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
(Read Only)
WSS2
(Read Only)
WSS2[7:0]
Wide screen signaling data.
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
WSS2[7:6] are
undetermined
EDTV1
(Read Only)
EDTV1[7:0]
EDTV data register.
EDTV2
(Read Only)
EDTV2[7:0]
EDTV data register.
EDTV3
(Read Only)
EDTV3[7:0]
EDTV data register.
EDTV3[7:6] are
undetermined
EDTV3[5] is reserved
for future use
CGMS1
(Read Only)
CGMS1[7:0]
CGMS data register.
CGMS2
(Read Only)
CGMS2[7:0]
CGMS data register.
CGMS3
(Read Only)
CGMS3[7:0]
CGMS data register.
CGMS3[7:4] are
undetermined
Rev. 0 | Page 83 of 96
ADV7181B
Bits
Subaddress Register
Bit Description
Comments
Notes
7
6
5
4
3
2
1
0
0x99
0x9A
0x9B
CCAP1
CCAP1[7:0]
Closed caption data register.
x
x
x
x
x
x
x
x
x
x
CCAP1[7] contains parity
bit for byte 0
(Read Only)
CCAP2
(Read Only)
CCAP2[7:0]
Closed caption data register.
x
x
x
x
x
x
x
x
x
x
x
x
x
x
CCAP2[7] contains parity
bit for byte 0
Letterbox 1
(Read Only)
LB_LCT[7:0]
Letterbox data register.
Reports the number of
black lines detected at the
top of active video.
This feature
examines the active
video at the start
and at the end of
each field. It enables
format detection
even if the video is
not accompanied by
a CGMS or WSS
sequence.
Letterbox 2
(Read Only)
Reports the number of
black lines detected in the
bottom half of active video
if subtitles are detected.
0x9C
LB_LCM[7:0]
Letterbox data register.
x
x
x
x
x
x
x
x
x
x
x
x
x
x
Letterbox 3.
(Read Only)
Reports the number of
black lines detected at the
bottom of active video.
0x9D
0xB2
LB_LCB[7:0]
Letterbox data register.
x
0
x
0
CRC
Reserved
Set as default
Enable
Write
Register
CRC_ENABLE. Enable CRC checksum
decoded from CGMS packet to
validate CGMSD.
0
1
Turn off CRC check
CGMSD goes high with
valid checksum
Reserved
0
0
0
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Set as default
No connection
AIN2
0xC3
ADC
SWITCH 1
ADC0_SW[3:0]. Manual muxing
control for ADC0.
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
SETADC_sw_
man_en = 1
No connection
No connection
AIN4
AIN6
No connection
No connection
No connection
AIN1
No connection
No connection
AIN3
AIN5
No connection
No connection
No connection
No connection
No connection
No connection
AIN4
ADC1_SW[3:0]. Manual muxing
control for ADC1.
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
SETADC_sw_
man_en = 1
AIN6
No connection
No connection
No connection
No connection
No connection
No connection
AIN3
AIN5
No connection
No connection
Rev. 0 | Page 84 of 96
ADV7181B
Bits
Subaddress Register
Bit Description
Comments
Notes
7
6
5
4
3
2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0xC4
ADC
SWITCH 2
ADC2_SW[3:0]. Manual muxing
control for ADC2.
0
No connection
No connection
No connection
No connection
No connection
AIN6
SETADC_sw_
man_en = 1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
No connection
No connection
No connection
No connection
No connection
No connection
No connection
AIN5
No connection
No connection
Reserved
x
x
x
ADC_SW_MAN_EN. Enable manual
setting of the input signal muxing.
0
1
Disable
Enable
0xDC
0xDD
Letterbox
Control 1
LB_TH [4:0]. Sets the threshold value
that determines if a line is black.
0
1
1
1
1
0
0
0
0
Default threshold for the
detection of black lines.
Reserved
1
0
0
1
1
0
Set as default
Letterbox
Control 2
LB_EL[3:0]. Programs the end line of
the activity window for LB detection
(end of field).
LB detection ends with
the last line of active video
on a field.
1100b: 262/525.
LB_SL[3:0]. Program the start line of
the activity window for LB detection
(start of field).
0
Letterbox detection
aligned with the start of
active video,
0100b: 23/286 NTSC.
0xDE
0xDF
0xE0
0xE1
Reserved
Reserved
Reserved
0
0
0
1
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
SD Offset
Cb
SD_OFF_CB [7:0]. Adjusts the hue by
selecting the offset for the Cb
channel.
0xE2
0xE3
0xE4
0xE5
SD Offset
Cr
SD_OFF_CR [7:0]. Adjusts the hue by
selecting the offset for the Cr
channel.
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
SD
Saturation
Cb
SD_SAT_CB [7:0]. Adjusts the
saturation of the picture by
affecting gain on the Cb channel.
Chroma gain = 0 dB
Chroma gain = 0 dB
NTSC default (BT.656)
SD
Saturation
Cr
SD_SAT_CR [7:0]. Adjusts the
saturation of the picture by
affecting gain on the Cr channel.
NTSC V Bit
Begin
NVBEG[4:0]. How many lines after
lCOUNT rollover to set V high.
NVBEGSIGN
0
1
Set to low when manual
programming
Not suitable for user
programming
NVBEGDELE. Delay V bit going high
by one line relative to NVBEG (even
field).
0
1
No delay
Additional delay by 1 line
NVBEGDELO. Delay V bit going high
by one line relative to NVBEG (odd
field).
0
1
No delay
Additional delay by 1 line
Rev. 0 | Page 85 of 96
ADV7181B
Bits
Subaddress Register
Bit Description
Comments
Notes
7
6
5
4
3
2
1
0
0xE6
0xE7
0xE8
0xE9
0xEA
NTSC V Bit
End
NVEND[4:0]. How many lines after
0
0
0
1
0
0
1
0
0
NTSC default (BT.656)
lCOUNT rollover to set V low.
NVENDSIGN
0
1
Set to low when manual
programming
Not suitable for user
programming
NVENDDELE. Delay V bit going low
by one line relative to NVEND (even
field).
0
1
No delay
Additional delay by 1 line
NVENDDELO. Delay V bit going low
by one line relative to NVEND (odd
field).
0
1
No delay
Additional delay by 1 line
NTSC F Bit
Toggle
NFTOG[4:0]. How many lines after
0
0
0
0
0
1
1
0
1
0
0
1
1
1
0
1
NTSC default
lCOUNT rollover to toggle F signal.
NFTOGSIGN
0
1
Set to low when manual
programming
Not suitable for user
programming
NFTOGDELE. Delay F transition by
one line relative to NFTOG (even
field).
0
1
No delay
Additional delay by 1 line
NFTOGDELO. Delay F transition by
one line relative to NFTOG (odd
field).
0
1
No delay
Additional delay by 1 line
PAL V Bit
Begin
PVBEG[4:0]. How many lines after
PAL default (BT.656)
lCOUNT rollover to set V high.
PVBEGSIGN
0
1
Set to low when manual
programming
Not suitable for user
programming
PVBEGDELE. Delay V bit going high
by one line relative to PVBEG (even
field).
0
1
No delay
Additional delay by 1 line
PVBEGDELO. Delay V bit going high
by one line relative to PVBEG (odd
field).
0
1
No delay
Additional delay by 1 line
PAL V Bit
End
PVEND[4:0]. How many lines after
PAL default (BT.656)
lCOUNT rollover to set V low.
PVENDSIGN
0
1
Set to low when manual
programming
Not suitable for user
programming
PVENDDELE. Delay V bit going low
by one line relative to PVEND (even
field).
0
1
No delay
Additional delay by 1 line
PVENDDELO. Delay V bit going low
by one line relative to PVEND (odd
field).
0
1
No delay
Additional delay by 1 line
PAL F Bit
Toggle
PFTOG[4:0]. How many lines after
PAL default (BT.656)
lCOUNT rollover to toggle F signal.
PFTOGSIGN
0
1
Set to low when manual
programming
Not suitable for user
programming
PFTOGDELE. Delay F transition by
one line relative to PFTOG (even
field).
0
1
No delay
Additional delay by 1 line
PFTOGDELO. Delay F transition by
one line relative to PFTOG (odd
field).
0
1
No delay
Additional delay by 1 line
Rev. 0 | Page 86 of 96
ADV7181B
Bits
Subaddress Register
Bit Description
Comments
Notes
7
6
5
4
3
2
1
0
0
0
0
1
0xF4
Drive
Strength
DR_STR_S[1:0] Select the drive
strength for the Sync output signals.
Low drive strength (1x)
Medium-low drive
strength (2x)
1
1
0
1
Medium-high drive
strength (3x)
High drive strength (4x)
Low drive strength (1x)
DR_STR_C[1:0] Select the drive
strength for the Clock output signal.
0
0
1
0
1
1
Medium-low drive
strength (2x)
0
1
Medium-high drive
strength (3x)
High drive strength (4x)
Low drive strength (1x)
DR_STR[1:0] Select the drive
strength for the data output signals.
Can be increased or decreased for
EMC or crosstalk reasons.
0
0
0
1
Medium-low drive
strength (2x)
1
1
0
1
Medium-high drive
strength (3x)
High drive strength (4x)
No delay
Reserved
x
x
0xF8
IF Comp
Control
IFFILTSEL[2:0] IF filter selection for
Pal and NTSC
0
0
0
0
0
1
Bypass mode
0 dB
2 MHz
5 MHz
NTSC dilters
−3 dB
−2 dB
0
0
1
1
1
0
0
1
0
+3.5 dB
+5 dB
−6 dB
−10 dB
Reserved
3 MHz
−2 dB
6 MHz
+2 dB
+3 dB
+5 dB
PAL Filters
1
1
1
0
1
1
1
0
1
−5 dB
−7 dB
Reserved
0
0
0
0
0
0xF9
VS Mode
Control
EXTEND_VS_MAX_FREQ
0
1
Limit Maximum Vsync
frequency to 66.25 Hz
(475 lines/frame)
Limit Maximum Vsync
frequency to 70.09 Hz
(449 lines/frame)
EXTEND_VS_MIN_FREQ
0
1
Limit Minimum Vsync
frequency to 42.75 Hz
(731 lines/frame)
Limit Minimum Vsync
frequency to 39.51 Hz
(791 lines/frame)
VS_COAST_MODE[1:0]
Reserved
0
0
1
1
0
1
0
1
Auto Coast mode
50 Hz Coast Mode
60 Hz Coast Mode
Reserved
This value sets up
the output coast
frequency.
0
0
0
0
Rev. 0 | Page 87 of 96
ADV7181B
I2C PROGRAMMING EXAMPLES
MODE 1 CVBS INPUT (COMPOSITE VIDEO ON AIN6)
All standards are supported through autodetect, 8-bit, 4:2:2, ITU-R BT.656 output on P15–P8.
Table 85. Mode 1 CVBS Input
Register Address
Register Value
Notes
0x15
0x17
0x3A
0x50
0xC3
0xC4
0x0E
0x00
0x41
0x16
0x04
0x05
0x80
0x80
Slow down digital clamps.
Set CSFM to SH1.
Power down ADC 1 and ADC 2.
Set DNR threshold.
Man mux AIN6 to ADC0 (0101).
Enable manual muxing.
ADI recommended programming sequence. This sequence must be followed exactly when
setting up the decoder.
0x50
0x52
0x58
0x77
0x7C
0x7D
0xD0
0xD5
0xD7
0xE4
0xEA
0x0E
0x20
0x18
0xED
0xC5
0x93
0x00
0x48
0xA0
0xEA
0x3E
0x0F
0x00
Recommended setting.
Recommended setting.
Recommended setting.
Recommended setting.
Recommended setting.
Recommended setting.
Recommended setting.
Recommended setting.
Recommended setting.
Recommended setting.
Recommended setting.
Recommended setting.
MODE 2 S-VIDEO INPUT (Y ON AIN1 AND C ON AIN4)
All standards are supported through autodetect, 8-bit, ITU-R BT.656 output on P15–P8.
Table 86. Mode 2 S-Video Input
Register Address
Register Value
Notes
0x00
0x15
0x3A
0x50
0xC3
0xC4
0x0E
0x06
0x00
0x12
0x04
0x41
0x80
0x80
S-Video input
Slow down digital clamps.
Power down ADC 2.
Set DNR threshold.
Man mux AIN2 to ADC0 (0001), AIN4 to ADC1 (0100).
Enable manual muxing
ADI recommended programming sequence. This sequence must be followed exactly when
setting up the decoder.
0x50
0x52
0x58
0x77
0x7C
0x7D
0xD0
0xD5
0xD7
0xE4
0xEA
0x0E
0x20
0x18
0xED
0xC5
0x93
0x00
0x48
0xA0
0xEA
0x3E
0x0F
0x00
Recommended setting.
Recommended setting.
Recommended setting.
Recommended setting.
Recommended setting.
Recommended setting.
Recommended setting.
Recommended setting.
Recommended setting.
Recommended setting.
Recommended setting.
Recommended setting.
Rev. 0 | Page 88 of 96
ADV7181B
MODE 3 525I/625I YPRPB INPUT (Y ON AIN1, PR ON AIN3, AND PB ON AIN5)
All standards are supported through autodetect, 8-bit, ITU-R BT.656 output on P15–P8.
Table 87. Mode 3 YPrPb Input 525i/625i
Register Address
Register Value
Notes
0x00
0x50
0xC3
0xC4
0x0E
0x0A
0x04
0xC9
0x8D
YPrPb Input
Set DNR threshold.
Man mux AIN1 to ADC0 (1001), AIN3 to ADC1 (1100).
Enable manual muxing, Man mux AIN5 to ADC2 (1101)
ADI recommended programming sequence. This sequence must be followed exactly when
setting up the decoder.
0x80
0x52
0x58
0x77
0x7C
0x7D
0xD0
0xD5
0xE4
0x0E
0x18
0xED
0xC5
0x93
0x00
0x48
0xA0
0x3E
0x00
Recommended setting.
Recommended setting.
Recommended setting.
Recommended setting.
Recommended setting.
Recommended setting.
Recommended setting.
Recommended setting.
Recommended setting.
MODE 4 CVBS TUNER INPUT CVBS PAL ON AIN6
8-bit, ITU-R BT.656 output on P15–P8.
Table 88. Mode 4 Tuner Input CVBS PAL Only
Register Address
Register Value
Notes
0x00
0x07
0x15
0x17
0x19
0x3A
0x50
0xC3
0xC4
0x0E
0x80
0x01
0x00
0x41
0xFA
0x16
0x0A
0x05
0x80
0x80
Force PAL input only mode.
Enable PAL autodetection only.
Slow down digital clamps.
Set CSFM to SH1.
Stronger dot crawl reduction.
Power down ADC 1 and ADC 2.
Set higher DNR threshold.
Man mux AIN6 to ADC0 (0101).
Enable manual muxing
ADI recommended programming sequence. This sequence must be followed exactly when
setting up the decoder.
0x50
0x52
0x58
0x77
0x7C
0x7D
0xD0
0xD5
0xD7
0xE4
0xEA
0x0E
0x20
0x18
0xED
0xC5
0x93
0x00
0x48
0xA0
0xEA
0x3E
0x0F
0x00
Recommended setting.
Recommended setting.
Recommended setting.
Recommended setting.
Recommended setting.
Recommended setting.
Recommended setting.
Recommended setting.
Recommended setting.
Recommended setting.
Recommended setting.
Recommended setting.
Rev. 0 | Page 89 of 96
ADV7181B
PCB LAYOUT RECOMMENDATIONS
The ADV7181B is a high precision, high speed mixed-signal
device. To achieve the maximum performance from the part, it
is important to have a well laid-out PCB board. The following is
a guide for designing a board using the ADV7181B.
It is also recommended to use a single ground plane for the
entire board. This ground plane should have a space between
the analog and digital sections of the PCB (see Figure 41).
ADV7181B
ANALOG INTERFACE INPUTS
ANALOG
SECTION
DIGITAL
SECTION
Care should be taken when routing the inputs on the PCB.
Track lengths should be kept to a minimum, and 75 Ω trace
impedances should be used when possible. Trace impedances
other than 75 Ω also increase the chance of reflections.
Figure 41. PCB Ground Layout
Experience has repeatedly shown that the noise performance is
the same or better with a single ground plane. Using multiple
ground planes can be detrimental because each separate ground
plane is smaller, and long ground loops can result.
POWER SUPPLY DECOUPLING
It is recommended to decouple each power supply pin with
0.1 µF and 10 nF capacitors. The fundamental idea is to have a
decoupling capacitor within about 0.5 cm of each power pin.
Also, avoid placing the capacitor on the opposite side of the PC
board from the ADV7181B, as doing so interposes resistive vias
in the path. The decoupling capacitors should be located
between the power plane and the power pin. Current should
flow from the power plane to the capacitor to the power pin. Do
not make the power connection between the capacitor and the
power pin. Placing a via underneath the 100 nF capacitor pads,
down to the power plane, is generally the best approach (see
Figure 40).
In some cases, using separate ground planes is unavoidable. For
those cases, it is recommended to place a single ground plane
under the ADV7181B. The location of the split should be under
the ADV7181B. For this case, it is even more important to place
components wisely because the current loops are much longer
(current takes the path of least resistance). An example of a
current loop: power plane to ADV7181B to digital output trace
to digital data receiver to digital ground plane to analog ground
plane.
PLL
Place the PLL loop filter components as close as possible to the
ELPF pin. Do not place any digital or other high frequency
traces near these components. Use the values suggested in the
data sheet with tolerances of 10ꢀ or less.
VDD
GND
VIA TO SUPPLY
VIA TO GND
10nF
100nF
DIGITAL OUTPUTS (BOTH DATA AND CLOCKS)
Figure 40. Recommended Power Supply Decoupling
Try to minimize the trace length that the digital outputs have to
drive. Longer traces have higher capacitance, which requires
more current, which causes more internal digital noise. Shorter
traces reduce the possibility of reflections.
It is particularly important to maintain low noise and good
stability of PVDD. Careful attention must be paid to regulation,
filtering, and decoupling. It is highly desirable to provide
separate regulated supplies for each of the analog circuitry
groups (AVDD, DVDD, DVDDIO, and PVDD).
Adding a 30 Ω to 50 Ω series resistor can suppress reflections,
reduce EMI, and reduce the current spikes inside the ADV7181B.
If series resistors are used, place them as close as possible to the
ADV7181B pins. However, try not to add vias or extra length to
the output trace to make the resistors closer.
Some graphic controllers use substantially different levels of
power when active (during active picture time) and when idle
(during horizontal and vertical sync periods). This can result in
a measurable change in the voltage supplied to the analog
supply regulator, which can, in turn, produce changes in the
regulated analog supply voltage. This can be mitigated by
regulating the analog supply, or at least PVDD, from a different,
cleaner power source, for example, from a 12 V supply.
If possible, limit the capacitance that each of the digital outputs
drives to less than 15 pF. This can easily be accomplished by
keeping traces short and by connecting the outputs to only one
device. Loading the outputs with excessive capacitance increases
the current transients inside the ADV7181B, creating more
digital noise on its power supplies.
Rev. 0 | Page 90 of 96
ADV7181B
The ac-coupling capacitor at the input to the buffer creates a
DIGITAL INPUTS
high-pass filter with the biasing resistors for the transistor. This
filter has a cut-off of:
The digital inputs on the ADV7181B are designed to work with
3.3 V signals, and are not tolerant of 5 V signals. Extra compo-
nents are needed if 5 V logic signals are required to be applied
to the decoder.
{2 × π × (R39||R89) × C93}–1 = 0.62 Hz
It is essential that the cutoff of this filter be less than 1 Hz to
ensure correct operation of the internal clamps within the part.
These clamps ensure that the video stays within the 5 V range of
the op amp used.
ANTIALIASING FILTERS
For inputs from some video sources that are not bandwidth
limited, signals outside the video band can alias back into the
video band during A/D conversion and appear as noise on the
output video. The ADV7181B oversamples the analog inputs by
a factor of 4. This 54 MHz sampling frequency reduces the
requirement for an input filter; for optimal performance it is
recommended that an antialiasing filter be employed. The
recommended low cost circuit for implementing this buffer and
filter circuit for all analog input signals is shown in Figure 43.
0
–20
–40
–60
The buffer is a simple emitter-follower using a single npn
transistor. The antialiasing filter is implemented using passive
components. The passive filter is a third-order Butterworth
filter with a −3 dB point of 9 MHz. The frequency response of
the passive filter is shown in Figure 42. The flat pass band up to
6 MHz is essential. The attenuation of the signal at the output of
the filter due to the voltage divider of R24 and R63 is compen-
sated for in the ADV7181B part using the automatic gain control.
–80
–100
–120
100k
300k
1M
3M
10M
30M
100M
300M
1G
FREQUENCY (Hz)
Figure 42. Third-Order Butterworth Filter Response
Rev. 0 | Page 91 of 96
ADV7181B
TYPICAL CIRCUIT CONNECTION
Examples of how to connect the ADV7181B video decoder are shown in Figure 43 and Figure 44. For a detailed schematic diagram for
the ADV7181B, refer to the ADV7181B evaluation note.
AVDD_5V
R43
0Ω
BUFFER
R39
4.7kΩ
C93
100µF
C
B
FILTER
Q6
R53
56Ω
L10
12µH
E
R38
75Ω
R89
5.6kΩ
R24
470Ω
R63
820Ω
C95
22pF
C102
10pF
AGND
Figure 43. ADI Recommended Antialiasing Circuit for All Input Channels
Rev. 0 | Page 92 of 96
ADV7181B
FERRITE BEAD
DVDDIO
(3.3V)
POWER SUPPLY
DECOUPLING FOR
EACH POWER PIN
33µF
10µF
0.1µF
0.01µF
DGND
DGND
DGND
DGND
FERRITE BEAD
PVDD
(1.8V)
POWER SUPPLY
DECOUPLING FOR
EACH POWER PIN
33µF
10µF
0.1µF
0.01µF
AGND
AGND
AGND
AGND
FERRITE BEAD
AVDD
(3.3V)
POWER SUPPLY
DECOUPLING FOR
EACH POWER PIN
33µF
10µF
0.1µF
0.01µF
AGND
AGND
AGND
AGND
FERRITE BEAD
DVDD
(1.8V)
POWER SUPPLY
DECOUPLING FOR
EACH POWER PIN
33µF
10µF
0.1µF
0.01µF
AGND DGND
DGND
DGND
DGND
DGND
100nF
S-VIDEO
P0
P1
AIN2
P2
P3
P4
P5
P6
P7
P8
P9
P10
P11
P12
P13
P14
P15
100nF
100nF
100nF
100nF
100nF
AIN1
AIN3
AIN4
AIN5
AIN6
Y
Pr
MULTI-
FORMAT
PIXEL
ADV7181B
Pb
PORT
P15–P8 8-BIT ITU-R BT.656 PIXEL DATA @ 27MHz
P7–P0 Cb AND Cr 16-BIT ITU-R BT.656 PIXEL DATA @ 13.5MHz
P15–P8 Y1 AND Y2 16-BIT ITU-R BT.656 PIXEL DATA @ 13.5MHz
CBVS
AGND
CAPY1
CAPY2
+
0.1µF
0.1µF
10µF
10µF
+
0.1µF
0.1nF
0.1nF
LLC
27MHz OUTPUT CLOCK
AGND
+
0.1µF
CAPC2
AGND
CML
+
10µF
0.1µF
10µF
REFOUT
0.1µF
INTERRUPT O/P
SFL O/P
INTRQ
SFL
HS
AGND
15pF
XTAL
HS O/P
27MHz
VS
VS O/P
XTAL1
DVDDIO
FIELD
FIELD O/P
DGND
DVDDIO
15pF
2
SELECT I C
ADDRESS
DGND
PWRDN
ALSB
DVSS
ELPF
DVDDIO DVDDIO
1.7kΩ
10nF
2kΩ
2kΩ
82nF
33Ω
33Ω
SCLK
SDA
MPU INTERFACE
CONTROL LINES
PVDD
DVDDIO
4.7kΩ
100nF
DGND
RESET
RESET
AGND
AGND
DGND
DGND
Figure 44. Typical Connection Diagram
Rev. 0 | Page 93 of 96
ADV7181B
OUTLINE DIMENSIONS
0.30
0.25
0.18
9.00
BSC SQ
0.60 MAX
PIN 1
INDICATOR
0.60 MAX
49
48
64
1
PIN 1
INDICATOR
7.25
7.10 SQ*
6.95
8.75
BSC SQ
EXPOSED PAD
(BOTTOM VIEW)
TOP
VIEW
0.45
0.40
0.35
33
32
16
17
0.25 MIN
7.50
REF
0.80 MAX
0.65 TYP
1.00
0.85
0.80
12° MAX
0.05 MAX
0.02 NOM
0.50 BSC
0.20 REF
SEATING
PLANE
*
COMPLIANT TO JEDEC STANDARDS MO-220-VMMD
EXCEPT FOR EXPOSED PAD DIMENSION
Figure 45. 64-Lead Lead Frame Chip Scale Package [LFCSP]
9 mm × 9 mm Body
(CP-64-3)
Dimensions shown in millimeters
0.75
0.60
0.45
12.00
BSC SQ
1.60
MAX
64
49
1
48
SEATING
PLANE
PIN 1
10.00
BSC SQ
TOP VIEW
(PINS DOWN)
10°
6°
2°
1.45
1.40
1.35
0.20
0.09
VIEW A
7°
3.5°
16
33
0.15
0.05
0°
17
32
SEATING
PLANE
0.08 MAX
COPLANARITY
0.27
0.22
0.17
0.50
BSC
VIEW A
ROTATED 90° CCW
COMPLIANT TO JEDEC STANDARDS MS-026BCD
Figure 46. 64-Lead Low Profile Quad Flat Package [LQFP]
(ST-64-2)
Dimensions shown in Millimeters
Note that the exposed metal paddle on the bottom of the LFCSP package must be soldered to PCB ground for proper heat dissipation and
also for noise and mechanical strength benefits.
Rev. 0 | Page 94 of 96
ADV7181B
ORDERING GUIDE
Model
ADV7181BBCPZ1
ADV7181BBSTZ1
EVAL-ADV7181BEBM
Temperature Range
–40°C to +85°C
–40°C to +85°C
Package Description
Package Option
Lead Frame Chip Scale Package (LFCSP)
Low Profile Quad Flat Package (LQFP)
Evaluation Board
CP-64-3
ST-64-2
1 Z = Pb-free part.
The ADV7181B is a Pb-free environmentally friendly product. It is manufactured using the most up-to-date materials and processes. The
coating on the leads of each device is 100ꢀ pure Sn electroplate. The device is suitable for Pb-free applications, and can withstand surface-
mount soldering at up to 255°C ( 5°C).
In addition, it is backward-compatible with conventional SnPb soldering processes. This means the electroplated Sn coating can be
soldered with Sn/Pb solder pastes at conventional reflow temperatures of 220°C to 235°C.
Rev. 0 | Page 95 of 96
ADV7181B
NOTES
Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent
Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
©
2004 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D04984–0–7/04(0)
Rev. 0 | Page 96 of 96
相关型号：
©2020 ICPDF网 联系我们和版权申明