EVAL-AD5590EBZ_技术文档

16 Input, 16 Output Analog I/O Port

with Integrated Amplifiers

AD5590

Offset voltage: 2.2 mV maximum

Low input bias current: 1 pA maximum

Single supply operation

Low noise: 22 nV/√Hz

Unity gain stable

Flexible serial interface

SPI-/QSPI-/MICROWIRE-/DSP-compatible

−40°C to +85°C operation

FEATURES

Input channels

12-bit successive approximation ADC

16 inputs with sequencer

Fast throughput rate: 1 MSPS

Wide input bandwidth: 70 dB SNR at f_IN= 50 kHz

Output channels

16 outputs with 12-bit DACs

On-chip 2.5 V reference

APPLICATIONS

Hardware LDAC and LDAC override function

CLR function to programmable code

Rail-to-rail operation

Optical line cards

Base stations

General-purpose analog I/O

Monitoring and control

Operational amplifiers

FUNCTIONAL BLOCK DIAGRAM

V

REFIN1/VREFOUT1

V1– V2–

ADCV^DDDACVDD (×2)

V1+ V2+

POWER-ON

RESET

POWER-DOWN

LOGIC

1.25V/2.5V

REF

LDAC

BUFFER

DAC

STRING

DAC 0

INPUT

VOUT0

VOUT7

DSCLK

DSYNC1

DSYNC2

DDIN

REGISTER

BUFFER

DAC

REGISTER

STRING

DAC 7

INPUT

REGISTER

DAC

INTERFACE

LOGIC

LDAC

BUFFER

CLR

DAC

STRING

DAC 8

INPUT

VOUT8

REGISTER

DAC

REGISTER

STRING

DAC 15

INPUT

REGISTER

VOUT15

POWER-DOWN

LOGIC

1.25V/2.5V

REF

VDRIVE

V

REFIN2/VREFOUT2

VIN0

ASCLK

ASYNC

SEQUENCER

ADC

INTERFACE

LOGIC

12-BIT

INPUT

MUX

SUCCESSIVE

APPROXIMATION

ADC

ADIN

T/H

ADOUT

VINI5

AD5590

V

REFA

IN7(–) IN7(+)

OUT7

IN0(–) IN0(+)

OUT0

DACGND (×2)

ADCGND

Figure 1.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registeredtrademarks arethe property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.461.3113

www.analog.com

AD5590

TABLE OF CONTENTS

Features .............................................................................................. 1

DAC.............................................................................................. 14

ADC ............................................................................................. 18

Amplifier ..................................................................................... 19

Terminology.................................................................................... 23

Theory of Operation ...................................................................... 26

DAC Section................................................................................ 26

ADC Section ............................................................................... 27

ADC Converter Operation ....................................................... 27

Amplifier Section ....................................................................... 29

Serial Interface ................................................................................ 30

Accessing the DAC Block.......................................................... 30

Accessing the ADC Block ......................................................... 34

Outline Dimensions....................................................................... 42

Ordering Guide .......................................................................... 42

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

General Description......................................................................... 3

Specifications..................................................................................... 4

ADC Specifications ...................................................................... 4

DAC Specifications....................................................................... 6

Operational Amplifier Specifications ........................................ 8

Timing Specifications .................................................................. 9

Absolute Maximum Ratings.......................................................... 11

Thermal Resistance .................................................................... 11

ESD Caution................................................................................ 11

Pin Configuration and Function Descriptions........................... 12

Typical Performance Characteristics ........................................... 14

REVISION HISTORY

10/08—Revision 0: Initial Version

Rev. 0 | Page 2 of 44

AD5590

GENERAL DESCRIPTION

The AD5590 is a 16-channel input and 16-channel output

analog I/O port with eight uncommitted amplifiers, operating

from a single 4.5 V to 5.25 V supply. The AD5590 comprises

16 input channels multiplexed into a 1 MSPS, 12-bit successive

approximation ADC with a sequencer to allow a preprogrammed

selection of channels to be converted sequentially. The ADC

contains a low noise, wide bandwidth track-and-hold amplifier

that can handle input frequencies in excess of 1 MHz.

The DAC section of the AD5590 comprises sixteen 12-bit DACs

divided into two groups of eight. Each group has an on-chip

reference. The on-board references are off at power-up, allowing

the use of external references. The internal references are enabled

via a software write.

The AD5590 incorporates a power-on reset circuit that ensures

that the DAC outputs power up to 0 V and remain powered up

at this level until a valid write takes place. The DAC contains a

power-down feature that reduces the current consumption of

the device and provides software-selectable output loads while

in power-down mode for any or all DAC channels. The outputs

The conversion process and data acquisition are controlled using

ASYNC

and the serial clock signal, allowing the device to easily

interface with microprocessors or DSPs. The input signal is

ASYNC

LDAC

of all DACs can be updated simultaneously using the

sampled on the falling edge of

and conversion is also

function, with the added functionality of user-selectable DAC

channels to simultaneously update. There is also an asynchronous

initiated at this point. There are no pipeline delays associated

with the ADC. By setting the relevant bits in the control register,

the analog input range for the ADC can be selected to be a 0 V

to V_REFAinput or a 0 V to 2 × V_REFAwith either straight binary

or twos complement output coding. The conversion time is

determined by the ASCLK frequency because it is also used

as the master clock to control the conversion.

CLR

that updates all DACs to a user-programmable code: zero

scale, midscale, or full scale.

The AD5590 contains eight low noise, single-supply amplifiers.

These amplifiers can be used for signal conditioning for the

ADCs, DACs, or other independent circuitry, if required.

Rev. 0 | Page 3 of 44

AD5590

SPECIFICATIONS

ADC SPECIFICATIONS

1

ADCV_DD= V_DRIVE= 2.7 V to 5.25 V_REFA= 2.5 V, f_SCLK= 20 MHz, T_A= T_MINto T_MAX, unless otherwise noted.

Table 1.

Parameter

Min

68.5

69

Typ

Max

Unit

Test Conditions/Comments²

DYNAMIC PERFORMANCE

Signal-to-(Noise + Distortion) (SINAD)³

f_IN= 50 kHz sine wave, f_SCLK= 20 MHz

@ 5 V

@ 3 V

@ 5 V

@ 3 V

@ 5 V

@ 3 V

@ 5 V

70

70.5

70

70.5

−82

−86

−80

dB

Signal-to-Noise Ratio (SNR)³

Total Harmonic Distortion (THD)³

Peak Harmonic or Spurious Noise (SFDR)³

−74

−75

@ 3 V

Intermodulation Distortion (IMD)^{3, 4}

Second-Order Terms

fa = 40.1 kHz, fb = 41.5 kHz

−85

10

dB

ns

ps

Third-Order Terms

Aperture Delay⁴

Aperture Jitter⁴

50

Channel-to-Channel Isolation^{3, 4}

Full Power Bandwidth⁴

−82

8.2

1.6

dB

MHz

f_IN= 400 kHz

@ 3 dB

@ 0.1 dB

DC ACCURACY³

Resolution

12

Bits

LSB

Integral Nonlinearity

Differential Nonlinearity

0 V to V_REFAInput Range

Offset Error

Offset Error Match

Gain Error

−1

+1

+1.5

Guaranteed no missing codes to 12 bits

Straight binary output coding

−10

0.6

+10

3.5

+2

LSB

−2

−0.8

Gain Error Match

0 V to 2 × V_REFAInput Range

+0.8

−V_REFAto +V_REFAbiased about V_REFAwith

twos complement output coding offset

Positive Gain Error

Positive Gain Error Match

Zero-Code Error

−2

−0.8

−8

+2

+0.8

+8

2

+1

LSB

0.6

Zero-Code Error Match

Negative Gain Error

Negative Gain Error Match

ANALOG INPUT

−1

−0.8

+0.8

Input Voltage Ranges

0 to V_REFA

0 to 2 × V_REFA

V

Range bit set to 1

Range bit set to 0, ADCV_DD/V_DRIVE= 4.75 V

to 5.25 V for 0 V to 2 × V_REFAS

DC Leakage Current

Input Capacitance⁴

REFERENCE INPUT

V_REFAInput Voltage

DC Leakage Current

V_REFAInput Impedance⁴

−1

+1

μA

pF

20

2.5

36

V

μA

kΩ

1ꢀ specified performance

f_SAMPLE= 1 MSPS

Rev. 0 | Page 4 of 44

AD5590

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments²

LOGIC INPUTS

Input High Voltage, V_INH

Input Low Voltage, V_INL

Input Current, I_IN

Input Capacitance, C_IN

LOGIC OUTPUTS

0.7 × V_DRIVE

−1

V

μA

pF

0.3 × V_DRIVE

+1

10

Typically 10 nA

1, 4

Output High Voltage, V_OH

Output Low Voltage, V_OL

Floating State Leakage Current

Floating State Output Capacitance⁴

Output Coding

V_DRIVE− 0.2

V

μA

pF

I_SOURCE= 200 μA; V_DD= 2.7 V to 5.25 V

I_SINK= 200 μA

weak/TRI bit set to 0

coding bit set to 1

0.4

10

Straight (Natural) Binary

Twos Complement

coding bit set to 0

CONVERSION RATE⁴

Conversion Time

800

300

1

ns

16 ASCLK cycles, ASCLK = 20 MHz

Sine wave input

Full-scale step input

Track-and-Hold Acquisition Time³

Throughput Rate

MSPS @ 5 V (see the Serial Interface section)

POWER REQUIREMENTS

ADCV_DD

V_DRIVE

2.7

5.25

0.15

V

μA

I_DRIVE

5

I_DD

Digital inputs = 0 V or V_DRIVE

Normal Mode, Static

Normal Mode, Operational

(f_S= Maximum Throughput)

750

μA

mA

V_DD= 4.75 V to 5.25 V, ASCLK on or off

V_DD= 4.75 V to 5.25 V, f_SCLK= 20 MHz

2.5

Autostandby Mode

1.55

100

960

0.5

mA

μA

f_SAMPLE= 500 kSPS

Static

f_SAMPLE= 250 kSPS

Static

Autoshutdown Mode

Full Shutdown Mode

Power Dissipation

0.02

0.5

ASCLK on or off

Normal Mode, Operational

Autostandby Mode, Static

Autoshutdown Mode, Static

Full Shutdown Mode

12.5

500

2.5

mW

μW

ADCV_DD= 5 V, f_SCLK= 20 MHz

ADCV_DD= 5 V

2.5

ADCV_DD= 5 V

¹Specifications apply for f_SCLKup to 20 MHz. For serial interfacing requirements, see the Timing Specifications section.

²Temperature range: −40°C to +85°C.

³See the Terminology section.

⁴Guaranteed by design and characterization. Not production tested.

⁵See the ADC Power vs. Throughput Rate section.

Rev. 0 | Page 5 of 44

AD5590

DAC SPECIFICATIONS

DACV_DD= 4.5 V to 5.25 V, R_L= 2 kΩ to DACGND, C_L= 200 pF to DACGND, V_REFIN1= V_REFIN1= DACV_DD. All specifications T_MINto T_MAX

,

unless otherwise noted.

Table 2.

Parameter

STATIC PERFORMANCE²

Min

Typ Max

Unit

Conditions/Comments¹

Resolution

12

Bits

Integrated Nonlinearity (INL)

Differential Nonlinearity (DNL)

Zero-Code Error

−3

−0.25

0.5 +3

+0.25

LSB

mV

μV/°C

ꢀ FSR

ppm

mV

See Figure 6

Guaranteed monotonic by design; see Figure 7

All 0s loaded to DAC register; see Figure 11

1

12

Zero-Code Error Drift³

2

−0.2

Full-Scale Error

Gain Error

Gain Temperature Coefficient³

Offset Error

−1

All 1s loaded to DAC register

Of FSR/°C

+1

2.5

5

−11

+11

DC Power Supply Rejection Ratio³

DC Crosstalk³

–80

dB

DACV_DD10ꢀ

External Reference

10

μV

Due to full-scale output change, R_L= 2 kΩ to DACGND or

DACV_DD

5

10

25

μV/mA

μV

Due to load current change

Due to powering down (per channel)

Due to full-scale output change, R_L= 2 kΩ to DACGND or

DACV_DD

Internal Reference

10

μV/mA

Due to load current change

OUTPUT CHARACTERISTICS³

Output Voltage Range

0

DACV_DD

V

Capacitive Load Stability

2

nF

Ω

mA

μs

R_L= ∞

R_L= 2 kΩ

10

0.5

30

4

DC Output Impedance

Short-Circuit Current

Power-Up Time

DACV_DD= 5 V

Coming out of power-down mode, DACV_DD= 5 V

REFERENCE INPUTS

Reference Current

40

50

DACV_DD

μA

V

kΩ

V_REFINx= DACV_DD= 5.5 V (per DAC channel)

Reference Input Range

Reference Input Impedance³

REFERENCE OUTPUT

Output Voltage

0

14.6

2.495

2.505

V

At ambient

Reference Temperature Coefficient³

Reference Output Impedance³

LOGIC INPUTS

10

7.5

ppm/°C

kΩ

Input Current

−3

2

+3

0.8

μA

V

All digital inputs

DACV_DD= 5 V

Input Low Voltage, V_INL

Input High Voltage, V_INH

Pin Capacitance³

5

pF

Rev. 0 | Page 6 of 44

AD5590

Parameter

Min

Typ Max

Unit

Conditions/Comments¹

POWER REQUIREMENTS

DACV_DD

4.5

5.5

V

All digital inputs at 0 or DACV_DD, DAC active, excludes load

current

V_IH= DACV_DD= 4.5 V to 5.5 V, V_IL= DACGND

Internal reference off

I_DD(Normal Mode)⁴

2.6

4

3.2

5

mA

Internal reference on

DACI_DD(All Power-Down Modes)⁵

DACV_DD

0.8

2

μA

V_IH= DACV_DD= 4.5 V to 5.5 V, V_IL= DACGND

¹Temperature range is −40°C to +85°C, typical at 25°C.

²Linearity calculated using a reduced code range of Code 32 to Code 4064. Output unloaded.

³Guaranteed by design and characterization; not production tested.

⁴Interface inactive. All DACs active. DAC outputs unloaded.

⁵All sixteen DACs powered down.

DAC AC Characteristics

DACV_DD= 4.5 V to 5.25 V, R_L= 2 kΩ to DACGND, C_L= 200 pF to DACGND, V_REFIN1= V_REFIN1= DACV_DD. All specifications T_MINto T_MAX

,

unless otherwise noted.

Table 3.

Parameter^{1, 2}

Min

Typ Max

Unit

μs

V/μs

nV-sec

dB

nV-sec

kHz

Conditions/Comments³

Output Voltage Settling Time

Slew Rate

Digital-to-Analog Glitch Impulse

Digital Feedthrough

Reference Feedthrough

Digital Crosstalk

6

10

¼ to ¾ scale settling to 2 LSB

1.5

4

1 LSB change around major carry (see Figure 17)

0.1

−90

0.5

2.5

3

340

−80

120

100

15

V_REFIN1= V_REFIN2= 2 V 0.1 V p-p, frequency = 10 Hz to 20 MHz

Analog Crosstalk

DAC-to-DAC Crosstalk

Multiplying Bandwidth

Total Harmonic Distortion

Output Noise Spectral Density

V_REFIN1= V_REFIN2= 2 V 0.2 V p-p

V_REFIN1= V_REFIN2= 2 V 0.1 V p-p, frequency = 10 kHz

dB

nV/√Hz DAC Code = 0x8400, 1 kHz

nV/√Hz DAC Code = 0x8400, 10 kHz

ꢁV p-p

Output Noise

0.1 Hz to 10 Hz

¹Guaranteed by design and characterization; not production tested.

²See the Terminology section.

³Temperature range is −40°C to +85°C, typical at 25°C.

Rev. 0 | Page 7 of 44

AD5590

OPERATIONAL AMPLIFIER SPECIFICATIONS

Electrical characteristics @ V_SY= 5 V, V_CM= V_SY/2, T_A= 25°C, unless otherwise noted.

Table 4.

Parameter

Symbol

Min

Typ

Max

Unit

Conditions

INPUT CHARACTERISTICS

Offset Voltage

V_OS

0.4

2.2

4.5

1

mV

μV/°C

pA

−0.3 V < V_CM< +5.3 V

−40°C < T_A< +85°C, −0.3 V < V_CM< +5.2 V

−40°C < T_A< +85°C

Offset Voltage Drift¹

Input Bias Current¹

∆V_OS/∆T

I_B

1

0.2

110

0.5

50

pA

dB

−40°C < T_A< +85°C

Input Offset Current¹

I_OS

0.1

95

−40°C < T_A< +85°C

0 V < V_CM< 5 V

Common-Mode Rejection Ratio

CMRR

68

235

dB

V/mV

pF

−40°C < T_A< +85°C

R_L= 10 kΩ, 0.5 V < V_OUT< 4.5 V

Large Signal Voltage Gain

Input Capacitance¹

A_VO

C_DIFF

C_CM

400

2

7

pF

OUTPUT CHARACTERISTICS

Output Voltage High

V_OH

4.95

4.9

4.98

4.7

V

I_L= 1 mA

−40°C to +85°C

I_L= 10 mA

4.50

V

−40°C to +85°C

I_L= 1 mA

−40°C to +85°C

I_L= 10 mA

Output Voltage Low

V_OL

20

30

50

275

335

mV

mA

Ω

190

−40°C to +85°C

Short-Circuit Current¹

Closed-Loop Output Impedance¹

POWER SUPPLY

I_SC

Z_OUT

80

15

f = 10 kHz, A_V= 1

Power Supply Span (V+ to V−)

Power Supply Rejection Ratio

5

94

V

PSRR

I_SY

67

64

dB

μA

1.8 V < V_SY< 5 V

−40°C < T_A< +85°C

V_OUT= V_SY/2

Supply Current per Amplifier

38

50

60

−40°C <T_A< +85°C

DYNAMIC PERFORMANCE¹

Slew Rate

Settling Time 0.1ꢀ

Gain Bandwidth Product

SR

t_S

GBP

0.1

23

400

350

70

V/μs

ꢁs

kHz

Degrees

R_L= 10 kΩ

G = 1, 2 V step, C_L= 20 pF, R_L= 1 kΩ

R_L= 100 kΩ

R_L= 10 kΩ

R_L= 10 kΩ, R_L= 100 kΩ, C_L= 20 pF

Phase Margin

Ø_O

NOISE PERFORMANCE¹

Peak-to-Peak Noise

Voltage Noise Density

2.3

25

22

3.5

μV

e_n

i_n

nV/√Hz

pA/√Hz

f = 1 kHz

f = 10 kHz

f = 1 kHz

Current Noise Density

0.05

¹Guaranteed by design and characterization. Not production tested.

Rev. 0 | Page 8 of 44

AD5590

TIMING SPECIFICATIONS

ADC Timing Characteristics

ADCV_DD= 2.7 V to 5.25 V, V_DRIVE≤ ADCV_DD, V_REFA= 2.5 V; All specifications T_MINto T_MAX, unless otherwise noted.

Table 5.

Parameter¹

Limit at T_MIN, T_MAX; ADCV_DD= 5 V

Unit

Conditions/Comments

2

f_SCLK

10

20

16 × t_ASCLK

50

kHz min

MHz min

MHz max

ns min

ns max

ns min

ns max

ns min

ns min/max

ns min

μs max

t_CONVERT

t_QUIET

t₂

10

ASYNC to ASCLK setup time

3

t₃

14

Delay from ASYNC until ADOUT three-state disabled

Data hold time

Data access time after ASCLK falling edge

ASCLK low pulse width

t₃b⁴

20

40

3

t₄

t₅

t₆

t₇

0.4 × t_ASCLK

ASCLK high pulse width

15

15/50

20

5

20

1

ASCLK to ADOUT valid hold time

ASCLK falling edge to ADOUT high impedance

ADIN setup time prior to ASCLK falling edge

ADIN Hold time prior to ASCLK falling edge

16^thASCLK falling edge to ASYNC high

5

t₈

t₉

t₁₀

t₁₁

t₁₂

Power-up time from full power-down/autoshutdown/

autostandby modes

¹Guaranteed by design and characterization. Not production tested. All input signals are specified with tr = tf = 5 ns (10ꢀ to 90ꢀ of ADCV_DD) and timed from a voltage

level of 1.6 V.

²Maximum ASCLK frequency is 50 MHz at ADCV_DD= 2.7 V to 5.5 V. Guaranteed by design and characterization; not production tested.

³Measured with the load circuit of Figure 3 and defined as the time required for the output to cross 0.4 V or 0.7 × V_DRIVE

.

⁴t₃b represents a worst-case figure for having ADD3 available on the ADOUT line, that is, if the ADC goes back into three-state at the end of a conversion and some

other device takes control of the bus between conversions, the user needs to wait a maximum time of t₃b before having ADD3 valid on the ADOUT line. If the ADOUT

ASYNC

line is weakly driven to ADD3 between conversions, then the user typically needs to wait 17 ns at 3 V and 12 ns at 5 V after the

valid on ADOUT.

falling edge before seeing ADD3

⁵t₈is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 3. The measured number is then extrapolated

back to remove the effects of charging or discharging the 25 pF capacitor. This means that the time, t₈, quoted in the timing characteristics, is the true bus relinquish

time of the part and is independent of bus loading.

ASYNC

B

t_CONVERT

t₂

t₆

1

2

3

4

5

6

13

14

t₅

15

16

ASCLK

ADOUT

t₃

b

t₄

t₇

t₁₁

t₃

t_QUIET

THREE-

ADD2

t₉

ADD1

ADD0

DB11

DB10

DB2

DB1

DB0

t₈

THREE-

STATE

t₁₀

STATE

FOUR IDENTIFICATION BITS

ADD3 ADD2

ADD3

WRITE

SEQ

ADD1

ADD0

DONTC

ADIN

Figure 2. ADC Timing Characteristics

200µA

I

OL

TO OUTPUT

1.6V

C

L

25pF

200µA

I

OH

Figure 3. Load Circuit for ADC Digital Output Timing Specifications

Rev. 0 | Page 9 of 44

AD5590

DAC Timing Characteristics

All input signals are specified with tr = tf = 1 ns/V (10% to 90% of V_DD) and timed from a voltage level of (V_IL+ V_IH)/2. See Figure 4.

DACV_DD= 4.5 V to 5.5 V. All specifications T_MINto T_MAX, unless otherwise noted.

Table 6.

Parameter¹

Limit at T_MIN, T_MAX; DACV_DD= 2.7 V to 5.5 V

Unit

Conditions/Comments

2

t₁

t₂

t₃

t₄

20

8

13

4

ns min

ns typ

DSCLK cycle time

DSCLK high time

DSCLK low time

DSYNC to DSCLK falling edge setup time

Data setup time

t₅

t₆

t₇

Data hold time

0

DSCLK falling edge to DSYNC rising edge

Minimum DSYNC high time

DSYNC rising edge to DSCLK fall ignore

DSCLK falling edge to DSYNC fall ignore

LDAC pulse width low

t₈

15

13

0

t₉

t₁₀

t₁₁

t₁₂

t₁₃

t₁₄

t₁₅

10

15

5

DSCLK falling edge to LDAC rising edge

CLR pulse width low

0

DSCLK falling edge to LDAC falling edge

CLR pulse activation time

300

¹Sample tested at 25°C to ensure compliance.

²Maximum DSCLK frequency is 50 MHz at V_DD= 2.7 V to 5.5 V. Guaranteed by design and characterization; not production tested.

t₁₀

t₁

t₉

DSCLK

t₂

t₈

t₇

t₃

t₄

DSYNCx

DDIN

t₆

t₅

DB31

DB0

t₁₄

t₁₁

1

LDAC

t₁₂

2

t₁₃

CLR

t₁₅

VOUTx

1

ASYNCHRONOUS LDAC UPDATE MODE.

SYNCHRONOUS LDAC UPDATE MODE.

2

Figure 4. DAC Timing Characteristics

Rev. 0 | Page 10 of 44

AD5590

ABSOLUTE MAXIMUM RATINGS

T_A= 25°C unless otherwise noted. V_DDrefers to DACV_DDor

ADCV_DD. GND refers to DACGND or ADCGND.

THERMAL RESISTANCE

θJA is specified for the worst-case conditions, that is, a device

soldered in a 4-layer JEDEC thermal test board for surface-

mount packages.

Table 7.

Parameter

Rating

V_DDto GND

V_DRIVEto GND

Op Amp Supply Voltage

Op Amp Input Voltage

−0.3 V to +7 V

−0.3 V to V_DD+ 0.3 V

6 V

(V1− or V2−) − 0.3 V to

(V1+ or V2+) + 0.3 V

Table 8. Thermal Resistance

Package Type

θ_JA

Unit

80-Ball CSP_BGA

40

°C/W

Op Amp Differential Input Voltage

Op Amp Output Short-Circuit

Duration to GND

Analog Input Voltage to GND

Digital Input Voltage to GND

Digital Output Voltage to GND

V_REFAto GND

V_REFIN/V_REFOUTto GND

Input Current to Any ADC Pin

Except Supplies

6 V

Indefinite

Table 9. Junction Temperature

Parameter

Junction Temperature^{1, 2}

Max Unit Comments

130 °C T_J= T_A+ P_TOTAL× θ_JA

−0.3 V to V_DD+ 0.3 V

−0.3 V to +7 V

−0.3 V to V_DD+0.3 V

10 mA

¹P_TOTALis the sum of ADC, DAC, and operational amplifier supply currents.

²θ_JAis the package thermal resistance.

ESD CAUTION

Operating Temperature Range

Storage Temperature Range

Junction Temperature (T_Jmax)

−40°C to +85°C

−65°C to +150°C

150°C

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

Rev. 0 | Page 11 of 44

AD5590

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

12

11

10

9

8

7

6

5

4

3

2

1

VOUT14 VOUT10 VOUT8 DACGND LDAC

DDIN

DSCLK DSYNC1 DACV

VOUT5 VOUT7 VOUT0

A

B

C

D

E

F

DD

VIN12

OUT7

VIN10 VOUT12 VOUT1 DACV

DSYNC2

CLR DACGND VOUT3

VIN9

VIN8

OUT2

IN2(+)

IN2(–)

IN3(+)

IN3(–)

OUT3

OUT1

IN1(–)

IN1(+)

OUT0

IN0(–)

DD

VOUT9

VOUT2

VOUT4

IN7(–) VOUT11

IN7(+) VOUT13

IN6(+) VOUT15

VOUT6

V_REFIN1

/

V_REFOUT1

V

/

REFIN2

IN6(–)

V2–

VIN5

G

H

J

V

REFOUT2

VIN15

V1–

VIN7

VIN6

VIN4

IN0(+)

OUT6

OUT5

IN5(–)

IN5(+)

V

REFA

VIN14

VIN11

IN4(+)

K

L

VIN13

IN4(–)

V2+

ADIN

ASCLK

V

VIN1

VIN3

VIN2

V1+

DRIVE

OUT4 ADCV

ASYNC ADOUT ADCGND VIN0

M

DD

Figure 5. Pin Configuration

Table 10. Pin Function Descriptions

Pin No.

Mnemonic Description

M7

ASYNC

Frame Synchronization Signal. Active low logic input. This input provides the dual function of

initiating ADC conversions and also frames the serial data transfer.

J11

M8

M5

V_REFA

Reference Input for the ADC Block. An external reference must be applied to this input. The voltage

range for the external reference is 2.5 V 1ꢀ for specified performance.

Power Supply Input for the ADC Block. The ADC can operate from 4.5 V to 5.25 V, and the supply

should be decoupled with a 10 μF in parallel with a 0.1 μF capacitor to ADCGND.

Ground Reference Point for the ADC Block. All ADC analog/digital input/output signals and any

external reference signal should be referred to this ADCGND voltage.

ADCV_DD

ADCGND

M4, L5, L3, L4, L2,

G2, K2, J2, B2, B3,

B11, L11, B12, L10,

K11, H11

VIN0 to

VIN15

Analog Input 0 through Analog Input 15. Sixteen single-ended analog input channels that are

multiplexed into the on-chip track and hold. The analog input channel to be converted is selected by

using the ADD3 through ADD0 address bits of the control register. The address bits in conjunction

with the SEQ and shadow bits allow the sequence register to be programmed. The input range for all

input channels can extend from 0 V to V_REFAor 0 V to 2 × V_REFA, as selected via the range bit in the

control register. Any unused input channels should be connected to GND to avoid noise pickup.

L8

ADIN

ADC Data In. Logic input. Data to be written to the control register of the ADC is provided on this input and

is clocked into the register on the falling edge of ASCLK (see the Accessing the ADC Block section).

M6

ADOUT

Data Out. Logic output. The conversion result from the ADC block is provided on this output as a serial

data stream. The bits are clocked out on the falling edge of the ASCLK input. The data stream consists

of four address bits indicating which channel the conversion result corresponds to, followed by the

12 bits of conversion data, which is provided MSB first. The output coding can be selected as straight

binary or twos complement via the coding bit in the control register.

Rev. 0 | Page 12 of 44

AD5590

Pin No.

Mnemonic Description

L7

ASCLK

Serial Clock. Logic input. ASCLK provides the serial clock for accessing data from the ADC block. This

clock input is also used as the clock source for the conversion process of the ADC.

L6

V_DRIVE

Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the serial

interface of the ADC block operates.

A4, B8

DACV_DD

Power Supply Input for the DAC Block. The DAC can operate from 4.5 V to 5.25 V, and the supply

should be decoupled with a 10 μF in parallel with a 0.1 μF capacitor to DACGND. The two DACV_DDpins

must be connected together.

A9, B5

A8

DACGND

LDAC

Ground Reference Point for the DAC Block. All DAC analog/digital input/output signals and any

external reference signal should be referred to this DACGND voltage. The two DACGND pins should be

connected together.

Pulsing this pin low allows any or all DAC registers to be updated if the input registers have new data.

This allows all DAC outputs to simultaneously update. Alternatively, this pin can be tied permanently

low.

A5

DSYNC1

Active Low Control Input. This is the frame synchronization signal for the input data of DAC channels

VOUT0 to VOUT7. When DSYNC1 goes low, it powers on the DSCLK and DDIN buffers and enables the

input shift register. Data is transferred in on the falling edges of the next 32 clocks. If DSYNC1 is taken

high before the 32^ndfalling edge, the rising edge of DSYNC1 acts as an interrupt and the write

sequence is ignored by the device.

B7

B6

DSYNC2

CLR

Active Low Control Input. This is the frame synchronization signal for the input data of DAC channels

VOUT8 to VOUT15. When DSYNC2 goes low, it powers on the DSCLK and DDIN buffers and enables the

input shift register. Data is transferred in on the falling edges of the next 32 clocks. If DSYNC2 is taken

high before the 32^ndfalling edge, the rising edge of DSYNC2 acts as an interrupt and the write

sequence is ignored by the device.

Asynchronous Clear Input. The CLR input is falling edge sensitive. When CLR is low, all LDAC pulses are

ignored. When CLR is activated, the input register and the DAC register are updated with the data

contained in the CLR code register—zero scale, midscale, or full scale. Default setting clears the output

to 0 V.

A7

A6

DDIN

DAC Data Input. This DAC has a 32-bit shift register. Data is clocked into the register on the falling

edge of the serial clock input.

DAC Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock

input. Data can be transferred at rates of up to 50 MHz.

DSCLK

A1, B9, C2, B4, D2,

A3, E2, A2

VOUT0 to

VOUT7

Analog Output Voltage from DAC0 to DAC7. DSYNC1 is the frame synchronization signal for writing

data to these DACs. The DAC is updated automatically if LDAC is low, or on the falling edge of LDAC if

it is high. The output amplifiers have rail-to-rail operation.

A10, C11, B11, D11, VOUT8 to

Analog Output Voltage from DAC8 to DAC15. DSYNC2 is the frame synchronization signal for writing

data to these DACs. The DAC is updated automatically if LDAC is low, or on the falling edge of LDAC if

it is high. The output amplifiers have rail to rail operation.

B10, E11, A12, F11

VOUT15

F2

V_REFIN1

V_REFOUT1

/

Reference Input/Output Pin for DAC0 to DAC7. The DACs have a common pin for reference input and

reference output. When using the internal reference, this is the reference output pin. When using an

external reference, this is the reference input pin. The default for this pin is as a reference input.

G11

M3

V_REFIN2

V_REFOUT2

/

Reference Input/Output Pin for DAC8 to DAC15. The DACs have a common pin for reference input and

reference output. When using the internal reference, this is the reference output pin. When using an

external reference, this is the reference input pin. The default for this pin is as a reference input.

Positive Supply Input for the amplifier 0 to amplifier 3. The supply for these amplifiers is independent

of other supplies and can be operated with a different supply if required. The pin should be decoupled

to V1− with a 10 μF in parallel with a 0.1 μF capacitor.

V1+

H2

L9

V1−

V2+

Negative Supply Input for Amplifier 0 to Amplifier 3.

Positive Supply Input for Amplifier 4 to Amplifier 7. The supply for these amplifiers is independent of

other supplies and can be operated with a different supply if required. The pin should be decoupled

to V2− with a 10 μF in parallel with a 0.1 μF capacitor.

H12

V2−

Negative Supply Input for Amplifier 4 to Amplifier 7.

M1, J1, D1, F1, M10, IN0(−) to

L12, G12, D12 IN7(−)

M2, K1, C1, E1, M11, IN0(+) to

Inverting Input Terminals for Operational Amplifier 0 to Amplifier 7.

Noninverting Input Terminals for Operational Amplifier 0 to Amplifier 7.

Output Terminals for Operational Amplifier 0 to Amplifier 7.

M12, F12, E12

IN7(+)

L1, H1, B1, G1, M9,

K12, J12, C12

OUT0 to

OUT7

Rev. 0 | Page 13 of 44

AD5590

TYPICAL PERFORMANCE CHARACTERISTICS

DAC

DACV_DDand ADCV_DD= 5 V, V_SY= 5 V, unless otherwise noted.

1.0

0.20

0.15

0.10

0.05

DACV

= V = 5V

REF

DD

= 25°C

DACV = 5V

DD

T

0.8

0.6

A

V

= 2.5V

REFOUT

T

= 25°C

A

0.4

0.2

0

–0.2

–0.4

–0.6

–0.8

–1.0

–0.05

–0.10

–0.15

–0.20

0

500

1000

1500 2000

CODE

2500 3000 3500 4000

0

500

1000

1500 2000 2500 3000

CODE

3500 4000

Figure 6. DAC INL, External Reference

Figure 9. DAC DNL, Internal Reference

0.20

0.15

0.10

0.05

0

–0.02

–0.04

–0.06

–0.08

DACV

= V = 5V

REF

DACV

= 5V

DD

= 25°C

T

A

GAIN ERROR

–0.10

–0.12

–0.05

–0.10

–0.15

–0.20

–0.14

–0.16

FULL-SCALE ERROR

–0.18

–0.20

–40

–20

0

20

40

60

80

100

500

1000 1500 2000 2500 3000 3500 4000

CODE

TEMPERATURE (

°

C)

Figure 7. DAC DNL, External Reference

Figure 10. DAC Gain Error and Full-Scale Error vs. Temperature

1.5

1.0

DACV = 5V

DD

V

T

= 2.5V

0.8

0.6

0.4

0.2

REFOUT

= 25°C

1.0

ZERO-SCALE ERROR

A

0.5

0

–0.5

–1.0

0

–0.2

–0.4

–0.6

–1.5

OFFSET ERROR

–2.0

–2.5

–0.8

–1.0

–40

–20

0

20

40

60

80

100

500

1000

1500 2000 2500 3000

CODE

3500 4000

TEMPERATURE (

°

C)

Figure 8. DAC INL, Internal Reference

Figure 11. DAC Zero-Scale Error and Offset Error vs. Temperature

Rev. 0 | Page 14 of 44

AD5590

0.50

DAC LOADED WITH

FULL-SCALE

SOURCING CURRENT

DAC LOADED WITH

ZERO-SCALE

SINKING CURRENT

DACV

= V

REFA

= 5V

DD

= 25°C

0.40

0.30

0.20

0.10

0

T

A

DACV

DD

–0.10

–0.20

–0.30

1

2

MAX(C2)*

420.0mV

DACV = 5V

DD

V

= 2.5V

REFOUT

–0.40

–0.50

VOUT

CH2 500mV

CH1 2.0V

M100µs 125MS/s

A CH1 1.28V

8.0ns/pt

–10

–8

–6

–4

–2

0

2

4

6

8

10

CURRENT (mA)

Figure 12. DAC Headroom at Rails vs. Source and Sink

Figure 15. DAC Power-On Reset to 0 V

6

5

4

3

DSYNC

DSCLK

DACV = 5V

DD

FULL SCALE

V

= 2.5V

REFOUT

= 25°C

T

A

1

3

3/4 SCALE

MIDSCALE

1/4 SCALE

2

1

VOUT

0

2

ZERO SCALE

DACV

= 5V

DD

–1

–30

CH1 5.0V

CH3 5.0V

CH2 500mV

M400ns

A CH1

1.4V

–20

–10

0

10

20

30

CURRENT (mA)

Figure 13. DAC Sink and Source Capability

Figure 16. DAC Exiting Power-Down to Midscale

2.505

2.504

2.503

2.502

2.501

2.500

2.499

2.498

2.497

2.496

2.495

2.494

2.493

2.492

2.491

2.490

2.489

2.488

2.487

2.486

2.485

DACV

= 5V

= 2.5V

DD

V

REFOUT

T

= 25°C

A

4ns/SAMPLE NUMBER

GLITCH IMPULSE = 3.55nV-sec

1 LSB CHANGE AROUND

MIDSCALE (0x8000 TO 0x7FFF)

DACV

= V = 5V

REFA

DD

= 25°C

T

A

FULL-SCALE CODE CHANGE

0x0000 TO 0xFFFF

OUTPUT LOADED WITH 2kΩ

AND 200pF TO GND

V

= 909mV/DIV

OUT

1

TIME BASE = 4µs/DIV

0

64

128

192

256

320

384

448

512

SAMPLE

Figure 17. DAC Digital-to-Analog Glitch Impulse (Negative)

Figure 14. DAC Full-Scale Settling Time

Rev. 0 | Page 15 of 44

AD5590

2.5000

2.4995

2.4990

2.4985

2.4980

2.4975

2.4970

2.4965

2.4960

2.4955

DACV

= 5V

= 2.5V

DD

V

REFOUT

T

= 25°C

A

DAC LOADED WITH MIDSCALE

1

DACV

= 5V

= 2.5V

DD

V

REFOUT

T

= 25°C

A

4ns/SAMPLE NUMBER

2.4950

0

5s/DIV

64

128

192

256

320 384 448 512

SAMPLE

Figure 20. 0.1 Hz to 10 Hz DAC Output Noise Plot, Internal Reference

Figure 18. DAC Analog Crosstalk

800

2.4900

2.4895

2.4890

2.4885

2.4880

2.4875

2.4870

2.4865

2.4860

T

= 25°C

A

MIDSCALE LOADED

700

600

500

400

300

200

DACV = 5V

DD

V

= 2.5V

REFOUT

DACV

= 5V

= 2.5V

DD

V

100

0

REFOUT

T

= 25°C

A

4ns/SAMPLE NUMBER

2.4855

0

100

1000

10000

FREQUENCY (Hz)

100000

1000000

64

128

192

256

SAMPLE

320 384 448 512

Figure 21. DAC Noise Spectral Density, Internal Reference

Figure 19. DAC-to-DAC Crosstalk

Rev. 0 | Page 16 of 44

AD5590

–20

–30

–40

5

0

DACV

= 5V

DACV

= 5V

DD

= 25°C

DD

= 25°C

T

A

T

A

DAC LOADED WITH FULL SCALE

= 2V ±0.3V p-p

V

REF

–5

–10

–15

–20

–25

–30

–35

–40

–50

–60

–70

–80

–90

–100

2k

4k

6k

8k

10k

100k

FREQUENCY (Hz)

1M

10M

FREQUENCY (Hz)

Figure 22. DAC Total Harmonic Distortion

Figure 24. DAC Multiplying Bandwidth

16

14

12

10

8

V

= DACV

DD

REFIN

= 25°C

T

A

DACV

= 5V

DD

6

4

0

1

2

3

4

5

6

7

8

9

10

CAPACITANCE (nF)

Figure 23. DAC Settling Time vs. Capacitive Load

Rev. 0 | Page 17 of 44

AD5590

ADC

DACV_DDand ADCV_DD= 5 V, V_SY= 5 V, unless otherwise noted.

–50

–55

–60

–65

–70

–75

–80

–85

5

8192 POINT FFT

f_SAMPLE= 1MSPS

f_IN= 50kHZ

SINAD = 70.697dB

THD = –79.171dB

f_S= 1MSPS

= 25°C

T

A

ADCV

= 5.25V

–15

DD

RANGE = 0V TO REF

IN

R

= 1000Ω

IN

SFDR = –79.93dB

–35

–55

–75

–95

R

= 100Ω

IN

R

= 5Ω

IN

R

= 10Ω

IN

10

100

INPUT FREQUENCY (Hz)

1000

4096

0

50

100 150 200 250 300 350 400 450 500

FREQUENCY (kHz)

Figure 28. ADC THD vs. Input Frequency for Various

Analog Source Impedances

Figure 25. ADC Dynamic Performance at 1 MSPS

1.0

0.8

75

70

65

60

55

ADCV

= V

= 5V

DD

DRIVE

TEMPERATURE = 25°C

ADCV

= V = 5.25V

DRIVE

DD

0.6

0.4

ADCV

= V = 4.75V

DRIVE

DD

0.2

0

–0.2

–0.4

–0.6

–0.8

–1.0

f_S= MAX THROUGHPUT

= 25°C

T

A

RANGE = 0V TO V

REFA

0

512

1024

1536

2048

2560

3072

3584

10

100

INPUT FREQUENCY (kHz)

1000

CODE

Figure 29. ADC Typical INL

Figure 26. ADC SINAD vs. Analog Input Frequency

for Various Supply Voltages at 1 MSPS

1.0

0.8

–50

–55

–60

–65

–70

–75

–80

–85

–90

f_S= MAX THROUGHPUT

= 25°C

RANGE = 0V TO REF

IN

ADCV

= V

= 5V

DD

DRIVE

T

TEMPERATURE = 25°C

A

0.6

0.4

0.2

0

–0.2

–0.4

–0.6

–0.8

–1.0

ADCV

= V

= 4.75V

= 5.25V

DD

DRIVE

0

512

1024

1536

2048

2560

3072

3584

10

100

INPUT FREQUENCY (kHz)

1000

CODE

Figure 27. THD vs. Analog Input Frequency for Various Supplies at 1 MSPS

Figure 30. ADC Typical DNL

Rev. 0 | Page 18 of 44

AD5590

AMPLIFIER

DACV_DDand ADCV_DD= 5 V, V_SY= 5 V, unless otherwise noted.

1800

400

350

300

250

200

150

100

50

V

= 5.5V

SY

–0.5V < V

V

= 5V

SY

< +5.5V

CM

= 25°C

1600

1400

1200

1000

800

600

400

200

0

T

A

0

25

50

75

100

125

150

TEMPERATURE (°C)

INPUT OFFSET VOLTAGE (µV)

Figure 31. Amplifier Input Offset Voltage Distribution

Figure 34. Amplifier Input Bias Current vs. Temperature

40

35

30

25

20

15

10

5

50

–40°C < T < +125°C

A

V

= ±2.5V

SY

V

= 2.5V

CM

40

30

20

10

0

1

2

3

4

5

6

7

8

9

10

–40

–10

20

50

80

110

TCV (µV/°C)

OS

TEMPERATURE (°C)

Figure 32. Amplifier Input Offset Voltage Drift Distribution

Figure 35. Amplifier Supply Current vs. Temperature

2000

1500

1000

500

1k

100

10

V

T

= 5V

V

T

= 5V

SY

= 25°C

SY

= 25ºC

A

V

– V

OH

SY

SOURCE

0

1

–500

–1000

–1500

–2000

SINK

V

OL

0.1

0.01

–0.5

0

0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

INPUT COMMON-MODE VOLTAGE (V)

0.001

0.01

0.1

LOAD CURRENT (mA)

1

10

Figure 33. Amplifier Input Offset Voltage vs. Input Common-Mode Voltage

Figure 36. Amplifier Output Saturation Voltage vs. Load Current

Rev. 0 | Page 19 of 44

AD5590

40

V

120

100

80

60

40

20

0

V

= 5V

SY

= 25°C

SY

T

A

30

20

10

0

V

– V @ 1mA

OH

SY

V

@ 1mA

OL

–40 –25 –10

5

20

35

50

65

80

95 110 125

100

1k

10k

100k

1M

TEMPERATURE (°C)

FREQUENCY (Hz)

Figure 37. Amplifier Output Saturation Voltage vs. Temperature (I_L= 1 mA)

Figure 40. Amplifier CMRR vs. Frequency

350

120

100

80

60

40

20

0

V

= 5V

V

= ±2.5V

= 25°C

SY

T

A

300

250

200

150

100

50

V

– V @ 10mA

OH

DD

V

@ 10mA

OL

0

–40 –25 –10

5

20

35

50

65

80

95 110 125

100

1k

10k

100k

1M

TEMPERATURE (°C)

FREQUENCY (Hz)

Figure 38. Amplifier Output Saturation Voltage vs. Temperature (I_L= 10 mA)

Figure 41. Amplifier PSRR vs. Frequency

135

90

45

0

60

50

1k

100

10

1

A

= 100

V

40

30

A

= 10

V

A

= 1

V

20

Ф

M

10

0

V

R

C

= ±2.5V

= 100kΩ

= 20pF

SY

–10

–20

L

V

= 5V

SY

–45

1M

0

100

1k

10k

100k

1k

10k

FREQUENCY (Hz)

100k

1M

FREQUENCY (Hz)

Figure 39. Amplifier Open-Loop Gain and Phase vs. Frequency

Figure 42. Amplifier Closed-Loop Output Impedance vs. Frequency

Rev. 0 | Page 20 of 44

AD5590

50

45

40

35

30

25

20

15

10

5

V

= 5V

SY

= 25°C

0

T

A

V

A

= ±2.5V

= –50

SY

V

–2.5

100

0

–OS

+OS

0

10

TIME (20µs/DIV)

100

LOAD CAPACITANCE (pF)

1000

Figure 43. Small Signal Overshoot vs. Load Capacitance

Figure 46. Amplifier Positive Overload Recovery

V

= 5V

= 1

= 10kΩ

= 200pF

V

= ±2.5V

A = –50

V

SY

2.5

A

R

C

V

L

0

–100

TIME (4µs/DIV)

TIME (20µs/DIV)

Figure 44. Amplifier Small Signal Transient Response

Figure 47. Amplifier Negative Overload Recovery

V

= 5V

= 1

= 10kΩ

= 200pF

SY

V

IN

A

R

C

V

L

V

OUT

V

= ±2.5V

SY

A

R

= 1

= 10kΩ

V

L

V

= 6V p-p

IN

TIME (20µs/DIV)

Figure 45. Amplifier Large Signal Transient Response

Figure 48. Amplifier, No Phase Reversal

Rev. 0 | Page 21 of 44

AD5590

140

120

100

80

V

= 5V

SY

V

= 5V

SY

60

40

20

0

100

TIME (1s/DIV)

1k

10k

100k

1M

FREQUENCY (Hz)

Figure 51. Amplifier Channel Separation

Figure 49. Amplifier 0.1 Hz to 10 Hz Input Voltage Noise

1000

100

10

V

= 5V

SY

= 25°C

T

A

1/F CORNER @ 100Hz

1

10

100

1000

10000

FREQUENCY (Hz)

Figure 50. Amplifier Voltage Noise Density

Rev. 0 | Page 22 of 44

AD5590

TERMINOLOGY

DAC Integrated Nonlinearity

DAC DC Power Supply Rejection Ratio (PSRR)

For the DAC, relative accuracy, or integral nonlinearity (INL),

is a measure of the maximum deviation in LSBs from a straight

line passing through the endpoints of the DAC transfer function.

PSRR indicates how the output of the DAC is affected by changes

in the supply voltage. PSRR is the ratio of the change in V_OUT

to a change in DACV_DDfor full-scale output of the DAC. It is

measured in decibels. V_REFINis held at 2 V, and DACV_DDis

varied 10%.

DAC Differential Nonlinearity

Differential nonlinearity (DNL) is the difference between the

measured change and the ideal 1 LSB change between any two

adjacent codes. A specified differential nonlinearity of 1 LSB

maximum ensures monotonicity. The DAC is guaranteed

monotonic by design.

DAC DC Crosstalk

DC crosstalk is the dc change in the output level of one DAC

in response to a change in the output of another DAC. It is

measured with a full-scale output change on one DAC (or

soft power-down and power-up) while monitoring another

DAC kept at midscale. It is expressed in microvolts.

DAC Offset Error

Offset error is a measure of the difference between the actual

V

_OUTand the ideal V_OUT, expressed in millivolts in the linear

DC crosstalk due to load current change is a measure of the

impact that a change in load current on one DAC has to

another DAC kept at midscale. It is expressed in microvolts

per milliamp.

region of the transfer function. It can be negative or positive

and is expressed in millivolts.

DAC Zero-Code Error

Zero-code error is a measure of the output error when zero

code (0x0000) is loaded into the DAC register. Ideally, the

output should be 0 V. The zero-code error is always positive

because the output of the DAC cannot go below 0 V. It is due

to a combination of the offset errors in the DAC and output

amplifier. Zero-code error is expressed in millivolts.

Reference Feedthrough

Reference feedthrough is the ratio of the amplitude of the signal

at the DAC output to the reference input when the DAC output

is not being updated (that is,

decibels.

LDAC

is high). It is expressed in

DAC Digital Feedthrough

DAC Gain Error

Digital feedthrough is a measure of the impulse injected into

the analog output of a DAC from the digital input pins of the

device, but is measured when the DAC is not being written to

Gain error is a measure of the span error of the DAC. It is the

deviation in slope of the DAC transfer characteristic from the

ideal, expressed as a percentage of the full-scale range.

SYNC

(

held high). It is specified in nV-sec and measured with

a full-scale change on the digital input pins, that is, from all 0s

to all 1s or vice versa.

DAC Zero-Code Error Drift

Zero-code error drift is a measure of the change in zero-code

error with a change in temperature. It is expressed in microvolts

per degree Celsius.

DAC Digital Crosstalk

Digital crosstalk is the glitch impulse transferred to the output

of one DAC at midscale in response to a full-scale code change

(all 0s to all 1s or vice versa) in the input register of another

DAC. It is measured in standalone mode and is expressed in

nV-sec.

DAC Gain Error Drift

Gain error drift is a measure of the change in gain error with

changes in temperature. It is expressed in ppm of full-scale

range per degree Celsius.

DAC Analog Crosstalk

DAC Full-Scale Error

Analog crosstalk is the glitch impulse transferred to the output

of one DAC due to a change in the output of another DAC. It is

measured by loading one of the input registers with a full-scale

Full-scale error is a measure of the output error when full-scale

code (0xFFFF) is loaded into the DAC register. Ideally, the out-

put should be V_DD− 1 LSB. Full-scale error is expressed as a

percentage of the full-scale range. Figure 10 shows a plot of

typical full-scale error vs. temperature.

LDAC

code change (all 0s to all 1s or vice versa) while keeping

LDAC

high, and then pulsing

low and monitoring the output

of the DAC whose digital code has not changed. The area of the

glitch is expressed in nV-sec.

DAC Digital-to-Analog Glitch Impulse

Digital-to-analog glitch impulse is the impulse injected into the

analog output when the input code in the DAC register changes

state. It is normally specified as the area of the glitch in nV-sec

and is measured when the digital input code is changed by 1

LSB at the major carry transition (0x7FFF to 0x8000).

DAC-to-DAC Crosstalk

DAC-to-DAC crosstalk is the glitch impulse transferred to the

output of one DAC due to a digital code change and subsequent

output change of another DAC. This includes both digital and

analog crosstalk. It is measured by loading one of the DACs with a

LDAC

full-scale code change (all 0s to all 1s or vice versa) with

low and monitoring the output of another DAC. The energy of

the glitch is expressed in nV-sec.

Rev. 0 | Page 23 of 44

AD5590

Multiplying Bandwidth

ADC Negative Gain Error

The amplifiers within the DAC have a finite bandwidth. The

multiplying bandwidth is a measure of this. A sine wave on the

reference (with full-scale code loaded to the DAC) appears on

the output. The multiplying bandwidth is the frequency at

which the output amplitude falls to 3 dB below the input.

This applies when using the twos complement output coding

option, in particular to the 2 × V_REFAinput range with −V_REFA

to +V_REFAbiased about the V_REFApoint. It is the deviation of

the first code transition (100…000 to 100…001) from the

ideal (that is, −V_REFA+ 1 LSB) after the ADC zero-code error

has been adjusted out.

DAC Total Harmonic Distortion (THD)

Total harmonic distortion is the difference between an ideal

sine wave and its attenuated version using the DAC. The sine

wave is used as the reference for the DAC, and the THD is a

measure of the harmonics present on the DAC output. It is

measured in decibels.

ADC Negative Gain Error Match

This is the difference in negative gain error between any two

channels.

ADC Channel-to-Channel Isolation

Channel-to-channel isolation is a measure of the level of

crosstalk between channels. It is measured by applying a full-

scale 400 kHz sine wave signal to all 15 nonselected input

channels and determining how much that signal is attenuated

in the selected channel with a 50 kHz signal. The figure is given

worst case across all 16 channels for the ADC.

ADC Differential Nonlinearity

This is the difference between the measured and the ideal 1 LSB

change between any two adjacent codes in the ADC.

ADC Integral Nonlinearity

This is the maximum deviation from a straight line passing

through the endpoints of the ADC transfer function. The

endpoints of the transfer function are zero scale, a point 1 LSB

below the first code transition, and full scale, a point 1 LSB

above the last code transition.

ADC PSR (Power Supply Rejection)

Variations in power supply affect the full scale transition, but

not the linearity of the converter. Power supply rejection is the

maximum change in full-scale transition point due to a change

in power supply voltage from the nominal value (see the Typical

Performance Characteristics section).

ADC Offset Error

This is the deviation of the first code transition (00…000 to

00…001) from the ideal, that is, ADCGND + 1 LSB.

ADC Track-and-Hold Acquisition Time

The track-and-hold amplifier returns into track on the 14^th

ASCLK falling edge. Track-and-hold acquisition time is the

minimum time required for the track-and-hold amplifier to

remain in track mode for its output to reach and settle to within

1 LSB of the applied input signal, given a step change to the

input signal.

ADC Offset Error Match

This is the difference in offset error between any two channels.

ADC Gain Error

This is the deviation of the last code transition (111…110

to 111…111) from the ideal (that is, V_REFA− 1 LSB) after the

offset error has been adjusted out.

ADC Signal-to-(Noise + Distortion) Ratio

ADC Gain Error Match

This is the difference in gain error between any two channels.

This is the measured ratio of signal to (noise + distortion) at the

output of the analog-to-digital converter. The signal is the rms

amplitude of the fundamental. Noise is the sum of all nonfunda-

mental signals up to half the sampling frequency (f_S/2), excluding

dc. The ratio is dependent on the number of quantization levels

in the digitization process; the more levels, the smaller the quanti-

zation noise. The theoretical signal-to-(noise + distortion) ratio

for an ideal N-bit converter with a sine wave input is given by

ADC Zero-Code Error

This applies when using the twos complement output coding

option, in particular to the 2 × V_REFAinput range with−V_REFA

to +V_REFAbiased about the V_REFApoint. It is the deviation of the

midscale transition (all 0s to all 1s) from the ideal V_INvoltage,

that is, V_REFA− 1 LSB.

ADC Zero-Code Error Match

This is the difference in ADC zero-code error between any two

channels.

Signal −to −(Noise + Distortion) = 6.02N +1.76 [dB]

Thus, for a 12-bit converter, this is 74 dB.

ADC Total Harmonic Distortion

Total harmonic distortion (THD) is the ratio of the rms sum of

harmonics to the fundamental. For the ADC, it is defined as

ADC Positive Gain Error

This applies when using the twos complement output coding

option, in particular to the 2 × V_REFAinput range with −V_REFA

to +V_REFAbiased about the V_REFApoint. It is the deviation of the

last code transition (011…110 to 011…111) from the ideal (that

is, +V_REFA− 1 LSB) after the zero-code error has been adjusted out.

2

V₂+V₃+V₄+V₅+V₆

THD[dB] = 20× log

V₁

where V₁is the rms amplitude of the fundamental and V₂, V₃,

V₄, V₅, and V₆are the rms amplitudes of the second through the

sixth harmonics.

ADC Positive Gain Error Match

This is the difference in ADC positive gain error between any

two channels.

Rev. 0 | Page 24 of 44

AD5590

ADC Peak Harmonic or Spurious Noise

example, the second-order terms include (fa + fb) and (fa − fb),

while the third-order terms include (2fa + fb), (2fa − fb), (fa +

2fb), and (fa − 2fb).

Peak harmonic or spurious noise is defined as the ratio of the

rms value of the next largest component in the ADC output

spectrum (up to f_S/2 and excluding dc) to the rms value of the

fundamental. Normally, the value of this specification is deter-

mined by the largest harmonic in the spectrum, but for ADCs

where the harmonics are buried in the noise floor, it is a

noise peak.

The ADC is tested using the CCIF standard where two input

frequencies near the top end of the input bandwidth are used.

In this case, the second-order terms are usually distanced in

frequency from the original sine waves whereas the third-order

terms are usually at a frequency close to the input frequencies.

As a result, the second- and third-order terms are specified

separately. The calculation of the intermodulation distortion

is as per the THD specification, where it is the ratio of the rms

sum of the individual distortion products to the rms amplitude

of the sum of the fundamentals expressed in decibels.

ADC Intermodulation Distortion

With inputs consisting of sine waves at two frequencies, fa

and fb, any active device with nonlinearities creates distortion

products at sum and difference frequencies of mfa nfb, where

m, n = 0, 1, 2, 3, and so on. Intermodulation distortion terms

are those for which neither m nor n are equal to zero. For

Rev. 0 | Page 25 of 44

AD5590

THEORY OF OPERATION

The AD5590 is an analog I/O module. The output port contains

sixteen 12-bit voltage output DAC channels. The DAC channels

are divided into two groups of eight DACs, each of which can be

programmed independently. Each group of DACs contains its

own internal 2.5 V reference. The references are powered down

by default allowing the use of external references, if required.

Resistor String

The resistor string section is shown in Figure 53. It is simply

a string of resistors, each of Value R. The code loaded into

the DAC register determines at which node on the string the

voltage is tapped off to be fed into the output amplifier. The

voltage is tapped off by closing one of the switches connecting

the string to the amplifier. Because it is a string of resistors, it is

guaranteed monotonic.

Either internal reference can be powered up and used as a refer-

ence for the ADC section. This is achieved by connecting the

appropriate V_REFINx/V_REFOUTxpin to V_REFA. Because the V_REFINx

/

V_REFOUTxpins have different input and output impedances it is

not possible to use one internal reference for both DAC groups

without buffering.

R

The input port comprises a single, 12-bit, 1 MSPS ADC with

16 multiplexed input channels. The ADC contains a sequencer

that allows it to sample any combination of the sixteen channels.

TO OUTPUT

R

AMPLIFIER

The AD5590 also contains eight rail-to-rail low noise amplifiers.

These amplifiers can be used independently or as part of signal

condition for the input or output ports.

DAC SECTION

R

Sixteen DACs make up the output port of the AD5590. Each

DAC consists of a string of resistors followed by an output

buffer amplifier. The sixteen DACs are divided into two groups

of eight with each group having its own internal 2.5 V reference

with an internal gain of 2. Figure 52 shows a block diagram of

the DAC architecture.

Figure 53. Resistor String

DAC Internal Reference

DACV

DD

The DAC section has two on-chip 2.5 V references with

an internal gain of 2, giving a full-scale output of 5 V. The

on-board reference is off at power-up, allowing the use of

an external reference. The internal references are enabled

via a write to the appropriate control register (see Table 11).

REF (+)

RESISTOR

STRING

VOUTx

DAC REGISTER

REF (–)

OUTPUT

AMPLIFIER

(GAIN = +2)

GND

The internal references associated with each group of DACs

are available at the V_REFIN1/V_REFOUT1and V_REFIN2/V_REFOUT2pins. A

buffer is required if the reference output is used to drive external

loads. When using the internal reference, it is recommended

that a 100 nF capacitor be placed between the reference output

and DACGND for reference stability.

Figure 52. DAC Architecture

Because the input coding to the DAC is straight binary, the ideal

output voltage when using an external reference is given by

D

⎛

⎜

⎝

⎞

⎟

⎠

V_OUT=V_REFIN

×

2^N

Individual channel power-down is not supported while using

the internal reference.

The ideal output voltage when using the internal reference is

given by

DAC Output Amplifier

D

⎛

⎜

⎝

⎞

⎟

⎠

V_OUT= 2×V_REFOUT

×

2^N

The output buffer amplifier can generate rail-to-rail voltages on

its output, which gives an output range of 0 V to DACV_DD. The

amplifier is capable of driving a load of 2 kΩ in parallel with

1000 pF to DACGND. The source and sink capabilities of the

output amplifier can be seen in Figure 13. The slew rate is

1.5 V/μs with a ¼ to ¾ scale settling time of 10 μs.

where:

D = decimal equivalent of the binary code that is loaded to the

DAC register (0 to 4095).

N = 12.

Rev. 0 | Page 26 of 44

AD5590

ADC SECTION

CAPACITIVE

DAC

The ADC section is a fast, 16-channel, 12-bit, single-supply,

analog-to-digital converter. The ADC is capable of throughput

rates of up to 1 MSPS when provided with a 20 MHz clock.

A

4kΩ

VIN0

CONTROL

LOGIC

SW1

B

SW2

The ADC section provides the user with an on-chip track-

and-hold, analog-to-digital converter. The ADC section has

16 single-ended input channels with a channel sequencer,

allowing the user to select a sequence of channels through

VIN15

COMPARATOR

ADCGND

Figure 55. ADC Conversion Phase

Analog Input

ASYNC

which the ADC can cycle with each consecutive

falling

edge. The serial clock input accesses data from the ADC, controls

the transfer of data written to the ADC, and provides the clock

source for the successive approximation ADC converter. The

analog input range for the ADC is 0 V to V_REFAor 0 V to 2 ×

V_REFAdepending on the status of Bit 1 in the control register.

The ADC provides flexible power management options to

allow the user to achieve the best power performance for a

given throughput rate. These options are selected by program-

ming the power management bits in the ADC control register.

Figure 56 shows an equivalent circuit of the analog input structure

of the ADC. The two diodes, D1 and D2, provide ESD protection

for the analog inputs. Care must be taken to ensure that the analog

input signal never exceed the supply rails by more than 200 mV.

This causes these diodes to become forward biased and start

conducting current into the substrate. 10 mA is the maximum

current these diodes can conduct without causing irreversible

damage to the ADC. Capacitor C1 in Figure 56 is typically about

4 pF and can primarily be attributed to pin capacitance. Resistor

R1 is a lumped component made up of the on resistance of a

switch (track-and-hold switch) and also includes the on resis-

tance of the input multiplexer.

ADC CONVERTER OPERATION

The ADC is a 12-bit successive approximation analog-to-digital

converter based around a capacitive DAC. The ADC can convert

analog input signals in the range 0 V to V_REFAor 0 V to 2 × V_REFA

Figure 54 and Figure 55 show simplified schematics of the ADC.

The ADC comprises control logic, SAR, and a capacitive DAC,

which are used to add and subtract fixed amounts of charge

from the sampling capacitor to bring the comparator back

into a balanced condition. Figure 54 shows the ADC during

its acquisition phase. SW2 is closed and SW1 is in Position

A. The comparator is held in a balanced condition and the

sampling capacitor acquires the signal on the selected VIN

channel.

ADCV

DD

.

C2

30pF

D1

R1

VINx

C1

4pF

D2

CONVERSION PHASE—SWITCH OPEN

TRACK PHASE—SWITCH CLOSED

Figure 56. Equivalent Analog Input Circuit

The total resistance is typically about 400 Ω. Capacitor C2 is

the ADC sampling capacitor and typically has a capacitance of

30 pF. For ac applications, removing high frequency components

from the analog input signal is recommended by use of an RC

low-pass filter on the relevant analog input pin. In applications

where harmonic distortion and signal-to-noise ratio are critical,

drive the analog input from a low impedance source. Large

source impedances significantly affect the ac performance of

the ADC. This may necessitate the use of an input buffer

amplifier. The choice of the op amp is a function of the

particular application.

CAPACITIVE

DAC

A

4kΩ

VIN0

CONTROL

LOGIC

SW1

B

SW2

VIN15

COMPARATOR

ADCGND

Figure 54. ADC Acquisition Phase

When the ADC starts a conversion (see Figure 55), SW2 opens

and SW1 moves to Position B, causing the comparator to become

unbalanced. The control logic and the capacitive DAC are used

to add and subtract fixed amounts of charge from the sampling

capacitor to bring the comparator back into a balanced condi-

tion. When the comparator is rebalanced, the conversion is

complete. The control logic generates the ADC output code.

Figure 57 shows the ADC transfer function.

When no amplifier is used to drive the analog input, limit the

source impedance to low values. The maximum source impedance

depends on the amount of total harmonic distortion (THD) that

can be tolerated. The THD increases as the source impedance

increases, and performance degrades (see Figure 28).

Rev. 0 | Page 27 of 44

AD5590

ADC Transfer Function

has been initiated. The write bit must be set to 0 to ensure

the ADC control register is not accidentally overwritten, or

the sequence operation interrupted. If the ADC control register

is written to at any time during the sequence, then it must be

ensured that the SEQ and shadow bits are set to 1 and 0,

respectively to avoid interrupting the automatic conversion

sequence. This pattern continues until the ADC is written to

and the SEQ and shadow bits are configured with any bit

combination except 1, 0. On completion of the sequence, the

ADC sequencer returns to the first selected channel in the shadow

register and commence the sequence again if uninterrupted.

The output coding of the ADC is either straight binary or twos

complement, depending on the status of the LSB (range bit) in

the ADC control register. The designed code transitions occur

midway between successive LSB values (that is, 1 LSB, 2 LSBs,

and so on). The LSB size is equal to V_REFA/4096. The ideal transfer

characteristic for the ADC when straight binary coding is selected

is shown in Figure 57.

111...111

111...110

Rather than selecting a particular sequence of channels, a number

of consecutive channels beginning with Channel 0 can also be

programmed via the control register alone, without needing

to write to the shadow register. This is possible if the SEQ and

shadow bits are set to 1, 1. The channel address bits, ADD3

through ADD0, then determine the final channel in the consec-

utive sequence. The next conversion is on Channel 0, then

Channel 1, and so on until the channel selected via the ADD3

through ADD0 address bits is reached. The cycle begins again

on the next serial transfer provided the write bit is set to low

or, if high, that the SEQ and shadow bits are set to 1, 0; then,

the ADC continues its preprogrammed automatic sequence

uninterrupted. Regardless of which channel selection method

is used, the 16-bit word output from the ADC during each

conversion always contains the channel address that the conver-

sion result corresponds to, followed by the 12-bit conversion

result (see the Serial Interface section).

111...000

1LSB = V

REF

/4096

011...111

000...010

000...001

000...000

1LSB

+V – 1LSB

REF

0V

ANALOG INPUT

OR 2 × V

V

IS EITHER V

REFA

REF

REFA

Figure 57. Straight Binary Transfer Characteristic

011...111

011...110

000...001

000...000

111...111

Digital Inputs

1LSB = 2 × V

/4096

REFA

100...010

100...001

100...000

The digital inputs applied to the ADC are not limited by the

maximum ratings that limit the analog inputs. Instead, the

digital inputs applied can go to 7 V and are not restricted

by the ADCV_DD+ 0.3 V limit found on the analog inputs.

–V

+ 1LSB

+V

– 1LSB

REFA

V

– 1LSB

REFA

ANALOG INPUT

Figure 58. Twos Complement Transfer Characteristic with

V_REFAV_REFAInput Range

ASYNC

Another advantage of ASCLK, ADIN, and

restricted by the ADCV_DD+ 0.3 V limit is the fact that power

ASYNC

not being

Analog Input Selection

supply sequencing issues are avoided. If

, ADIN, or

ASCLK is applied before ADCV_DD, there is no risk of latch-up

as there would be on the analog inputs if a signal greater than

0.3 V was applied prior to ADCV_DD.

Any one of 16 analog input channels can be selected for conversion

by programming the multiplexer with the ADD3 to ADD0

address bits in the ADC control register. The channel configura-

tions are shown in Table 23. The ADC can also be configured to

automatically cycle through a number of channels as selected.

The sequencer feature is accessed via the SEQ and shadow bits

in the ADC control register (see Table 21). The ADC can be

programmed to continuously convert on a selection of channels

in ascending order. The analog input channels to be converted

on are selected through programming the relevant bits in the

shadow register (see Table 26). The next serial transfer then acts

on the sequence programmed by executing a conversion on the

lowest channel in the selection.

V_DRIVE

The ADC has the V_DRIVEfeature, which controls the voltage at

which the serial interface operates. V_DRIVEallows the ADC to

easily interface to both 3 V and 5 V processors. For example, if

the ADC is operated with a V_DDof 5 V, the V_DRIVEpin could be

powered from a 3 V supply. The ADC has better dynamic perfor-

mance with a V_DDof 5 V while still being able to interface to 3 V

processors. Care should be taken to ensure that V_DRIVEdoes not

exceed ADCV_DDby more than 0.3 V (see the Absolute Maximum

Ratings section).

The next serial transfer results in a conversion on the next

highest channel in the sequence, and so on. It is not necessary

to write to the ADC control register once a sequencer operation

Rev. 0 | Page 28 of 44

AD5590

Reference Section

The parts are fully specified to operate from a single 5.0 V

supply, or 2.5 V dual supplies. The ability to swing rail-to-rail

at both the input and output enables designers to buffer CMOS

ADCs, DACs, ASICs, and other wide output swing devices in

low power, single-supply systems. The amplifiers in the AD5590

are fully independent of the DAC and ADC sections. If some or

all of the amplifiers are not required, connect them as a

grounded unity-gain buffer, as shown in Figure 59.

An external reference source should be used to supply the 2.5 V

reference to the ADC. Errors in the reference source results in

gain errors in the ADC transfer function and adds to the specified

full-scale errors of the ADC. A capacitor of at least 0.1 μF should

be placed on the V_REFApin. Suitable reference sources for the

ADC include the AD780, REF193, and the AD1852.

If 2.5 V is applied to the V_REFApin, the analog input range can

either be 0 V to 2.5 V or 0 V to 5 V, depending on the range bit

in the control register.

AMPLIFIER SECTION

Figure 59. Configuration for Unused Amplifiers

The operational amplifiers in the AD5590 are micropower,

rail-to-rail input and output amplifiers that feature low supply

current, low input voltage, and low current noise.

Rev. 0 | Page 29 of 44

AD5590

SERIAL INTERFACE

The AD5590 contains independent serial interfaces for the

DSYNCx

line can be kept low

of operation. At this stage, the

ASYNC

ADC and DAC sections. The ADC uses the

, ASCLK,

or be brought high. In either case, it must be brought high for

a minimum of 15 ns before the next write sequence so that a

ADIN, and ADOUT pins. The V_DRIVEpin allows the user to

determine the output voltage of logic high signals. The DAC

DSYNCx

falling edge of

can initiate the next write sequence.

DSYNC1 DSYNC2 LDAC

CLR

uses DSCLK, DDIN,

,

, and

.

DAC Input Shift Register

The 16 analog input channels use the ADC interface. The 16

output channels use the DAC interface. The 16 output channels

are divided into two groups of eight channels, which can be

controlled independently. Each group has its own set of control

registers. When addressing the DAC control registers, the serial

The input shift register is 32 bits wide (see Figure 61). The first

four bits are don’t cares. The next four bits are the command

bits, C3 to C0 (see Table 11), followed by the 4-bit DAC address,

A3 to A0 (see Table 12), and finally the 12-bit data-word. The

data-word comprises the 12-bit input code followed by eight

don’t care bits. These data bits are transferred to the DAC

register on the 32^ndfalling edge of DSCLK.

DSYNC1

data should be framed by

to access the control registers

DSYNC2

for DAC0 to DAC7 and framed by

registers for DAC8 to DAC15.

to access the control

Table 11. DAC Command Definitions

Command

The interfaces are compatible with SPI®, QSPI™, MICROWIRE™,

and most DSPs.

C3 C2 C1 C0 Description

ACCESSING THE DAC BLOCK

0

1

0

1

0

Write to Input Register n

Update DAC Register n

Write to Input Register n, update all

(Software LDAC)

Figure 4 shows a timing diagram of a typical write sequence to

the DAC block. The write sequence begins by bringing one or

DSYNC

DSYNC1

both of the

data is written to the DAC block containing DAC0 to DAC7.

DSYNC2

lines low. If

is brought low, the

0

1

0

1

0

1

0

Write to and update DAC Channel n

Power down/power up DAC

Load clear code register

Load LDAC register

Reset (power-on reset)

Set up internal REF register

Reserved

If

is brought low, the data is written to the DAC block

DSYNC1 DSYNC2

containing DAC8 to DAC15. If both

and

are

brought low, the data is written into both blocks simultaneously.

Figure 60 shows how the serial interface is arranged.

0

1

0

1

0

1

0

1

CLR

LDAC

…

1

…

1

…

1

…

1

Reserved

DSYNC1

DSCLK

DAC 0

DAC 7

VOUT0

VOUT7

GROUP 1

CONTROL

REGISTERS

Table 12. DAC Address Commands

Address (n) Selected DAC Channel

DDIN

DSYNC1 Low

DSYNC2 Low

A3

0

A2

0

A1

0

A0

0

DAC0

DAC8

DAC 8

VOUT8

GROUP 2

CONTROL

REGISTERS

0

1

0

DAC1

DAC2

DAC9

DAC10

DSYNC2

DAC 15

VOUT15

0

1

DAC3

DAC11

Figure 60. DAC Serial Interface Configuration

0

1

0

DAC4

DAC12

0

1

0

1

0

1

DAC5

DAC6

DAC7

DAC0 to DAC7

DAC13

DAC14

DAC15

DAC8 to DAC15

Data from the DDIN line is clocked into the 32-bit shift register

on the falling edge of DSCLK. The serial clock frequency can be

as high as 50 MHz, making the AD5590 compatible with high

speed DSPs. On the 32^ndfalling clock edge, the last data bit is

clocked in and the programmed function is executed, that is,

a change in DAC register contents and/or a change in the mode

DB31 (MSB)

DB0 (LSB)

X

C3 C2 C1 C0 A3 A2 A1 A0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

DATA BITS

X

COMMAND BITS

ADDRESS BITS

Figure 61. DAC Input Register Contents

Rev. 0 | Page 30 of 44

AD5590

Table 11). These modes are software-programmable by setting

Bit DB9 and Bit DB8 in the control register.

DSYNC

Interrupt

In a normal write sequence, the

32 falling edges of DSCLK, and the DAC is updated on the 32^nd

DSYNCx DSYNCx

DSYNCx

line is kept low for

Table 15 shows how the state of the bits corresponds to the mode

of operation of the device. Any or all DACs (DAC0 to DAC7 in

Block 1 or DAC8 to DAC15 in Block 2) can be powered down to

the selected mode by setting the corresponding eight bits to 1. See

Table 16 for the contents of the input shift register during power-

down/power-up operation. When using the internal reference,

only all channel power-down to the selected modes is supported.

falling edge and rising edge of

. However, if

is

brought high before the 32^ndfalling edge, this acts as an interrupt

to the write sequence. The shift register is reset, and the write

sequence is seen as invalid. Neither an update of the DAC

register contents nor a change in the operating mode occurs

(see Figure 63).

When both bits are set to 0, each block works normally with its

normal power consumption of 1.3 mA at 5 V. However, for the

three power-down modes, the supply current of each block falls

to 0.4 μA at 5 V. Not only does the supply current fall, but the

output stage is also internally switched from the output of the

amplifier to a resistor network of known values. This has the

advantage that the output impedance of the DAC is known

while it is in power-down mode. There are three different

options. The output is connected internally to GND through

either a 1 kΩ or a 100 kΩ resistor, or it is left open-circuited

(three-state). The output stage is illustrated in Figure 62.

DAC Internal Reference Register

The on-board references in the DAC blocks are off at power-up

by default. This allows the use of an external reference if the

application requires it. The on-board references can be turned

on or off by a user-programmable internal REF register by

setting Bit DB0 high or low (see Table 13). Command 1000 is

reserved for setting the internal REF register (see Table 11).

DAC Power-On Reset

The DAC blocks contain a power-on reset circuit that controls

the output voltage during power-up. The DAC outputs power

up to 0 V. The output remains powered up at this level until a

valid write sequence is made to the DAC. This is useful in appli-

cations where it is important to know the state of the output of

the DAC while it is in the process of powering up. There is also

a software executable reset function that resets the DAC to the

power-on reset code. Command 0111 is reserved for this reset

LDAC CLR

RESISTOR

STRING DAC

AMPLIFIER

V

OUT

POWER-DOWN

CIRCUITRY

RESISTOR

NETWORK

function (see Table 11). Any events on

power-on reset are ignored.

or

during

Figure 62. Output Stage During Power-Down

DAC Power-Down Modes

The DAC block contains four separate modes of operation.

Command 0100 is reserved for the power-down function (see

DSCLK

DSYNCx

DB31

DB0

DB31

DB0

DDIN

INVALID WRITE SEQUENCE:

SYNC HIGH BEFORE 32ND FALLING EDGE

VALID WRITE SEQUENCE, OUTPUT UPDATES

ON THE 32ND FALLING EDGE

SYNC

Figure 63.

Interrupt Facility

Table 13. DAC Internal Reference Register

Internal REF Register (DB0)

Action

0

1

Reference off (default)

Reference on

Table 14. DAC 32-Bit Input Shift Register Contents for Reference Setup Command

MSB

LSB

DB0

1/0

DB31 to DB28

X

DB27

DB26

DB25

DB24

DB23

DB22

DB21

DB20

DB19 to DB1

X

1

0

X

Don’t care

Command bits (C3 to C0)

Address bits (A3 to A0)—don’t care

Don’t care

Internal REF register

Rev. 0 | Page 31 of 44

AD5590

The bias generator of the selected DAC(s), output amplifier,

resistor string, and other associated linear circuitry are shut

down when the power-down mode is activated. The internal

reference is powered down only when all channels are powered

down. However, the contents of the DAC register are unaffected

when in power-down. The time to exit power-down is typically

4 μs for DACV_DD= 5 V.

CLR

register and sets the analog outputs

the user-configurable

accordingly. This function can be used in system calibration to

load zero scale, midscale, or full scale to all channels together.

These clear code values are user-programmable by setting Bit DB1

CLR

and Bit DB0 in the

control register (see Table 17). The

default setting clears the outputs to 0 V. Command 0101 is

reserved for loading the clear code register (see Table 11).

The DAC exits clear code mode on the 32^ndfalling edge of

Any combination of DACs can be powered up by setting PD1

and PD0 to 0 (normal operation). The output powers up to the

CLR

the next write to the DAC. If

sequence, the write is aborted.

CLR

is activated during a write

LDAC

value in the input register (

low) or to the value in the

LDAC

DAC register before powering down (

high).

CLR

The

pulse activation time—the falling edge of

to

DAC Clear Code Register

when the output starts to change—is typically 280 ns. However,

if outside the DAC linear region, it typically takes 520 ns after

CLR

The DAC blocks have a hardware

pin that is an asynchron-

CLR

executing

for the output to start changing.

CLR

ous clear input for all 16 DACs. The

input is falling edge

CLR

sensitive. Bringing the

line low clears the contents of the

See Table 18 for contents of the input shift register during the

loading clear code register operation.

input register and the DAC registers to the data contained in

Table 15. DAC Power-Down Modes of Operation

DB9

DB8

Operating Mode

Normal operation

Power-down modes:

1 kΩ to GND

100 kΩ to GND

Three-state

0

1

0

1

Table 16. DAC 32-Bit Input Shift Register Contents for Power-Down/Power-Up Function

MSB

LSB

DB31 to

DB28

DB19

DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 to DB10 DB9

DB8

DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

X

0

1

0

X

PD1

PD0

DAC DAC DAC DAC DAC DAC DAC DAC

H

G

F

E

D

C

B

A

Don’t care

Command bits (C3 to C0)

Address bits (A3 to A0)— Don’t

don’t care care

Power-down

mode

Power-down/power-up channel selection—set bit to 1

to select

Table 17. DAC Clear Code Register

Clear Code Register

DB1

CR1

0

1

DB0

CR0

0

1

0

Clears to Code

0x0000

0x0800

0x0FFF

1

No operation

Table 18. DAC 32-Bit Input Shift Register Contents for Clear Code Function

MSB

LSB

DB0

CR0

DB31 to DB28

X

DB27

DB26

DB25

DB24

DB23

DB22

DB21

DB20

DB19 to DB2

X

DB1

0

1

0

1

X

CR1

Don’t care

Command bits (C3 to C0)

Address bits (A3 to A0)—don’t care

Don’t care

Clear code register

Rev. 0 | Page 32 of 44

AD5590

select which combination of channels to simultaneously update

LDAC

Function

LDAC

when the hardware

register to 0 for a DAC channel means that this channel’s update

LDAC

pin is executed. Setting the

bit

The outputs of all DACs can be updated simultaneously using

LDAC

the hardware

Synchronous

pin.

is controlled by the

updates synchronously; that is, the DAC register is updated

LDAC

pin. If this bit is set to 1, this channel

: After new data is read, the DAC registers

nd

LDAC

are updated on the falling edge of the 32 DSCLK pulse.

can be permanently low or pulsed as in Figure 4.

after new data is read, regardless of the state of the

pin.

pin as being tied low. (See

register mode of operation.) This

LDAC

It effectively registers the

LDAC

Asynchronous

: The outputs are not updated at the same

Table 19 for the

LDAC

time that the input registers are written to. When

goes

flexibility is useful in applications where the user wants to

simultaneously update select channels while the rest of the

channels are synchronously updating.

low, the DAC registers are updated with the contents of the

input register.

Alternatively, the outputs of all DACs can be updated simulta-

Writing to the DAC using Command 0110 loads the 8-bit

LDAC

0, that is, the

neously using the software

Register n and updating all DAC registers. Command 0011 is

LDAC

function by writing to Input

register (DB7 to DB0). The default for each channel is

LDAC

pin works normally. Setting the bits to 1

reserved for this software

function.

register gives the user extra flexibility and control

LDAC

means the DAC channel is updated regardless of the state of

LDAC

the

pin. See Table 20 for the contents of the input shift

LDAC

An

over the hardware

register during the

register mode of operation.

pin. This register allows the user to

Table 19.

Register

LDAC

LDAC Bits (DB7 to DB0)

LDAC Pin

1/0

LDAC Operation

Determined by LDAC pin.

DAC channels update, overriding the LDAC pin. DAC channels see LDAC as 0.

0

1

X—don’t care

Table 20. DAC 32-Bit Input Shift Register Contents for

Register Function

LDAC

MSB

LSB

DB31

DB19

to DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 to DB8 DB7

DB6 DB5 DB4 DB3

DB2 DB1 DB0

X

0

1

0

X

DAC H DAC G DAC F DAC E DAC D DAC C DAC B DAC A

Setting LDAC bit to 1 overrides LDAC pin

Don’t

care

Command bits (C3 to C0)

Address bits (A3 to A0)— Don’t

don’t care

care

Rev. 0 | Page 33 of 44

AD5590

ASYNC

The conversion is initiated on the falling edge of

and

ACCESSING THE ADC BLOCK

the track-and-hold enters hold mode as described in the Serial

Interface section. The data presented to the ADC on the ADIN

line during the first 12 clock cycles of the data transfer is loaded

to the ADC control register (provided the write bit is 1). If the

previous write had SEQ = 0 and shadow = 1, the data presented on

the ADIN line on the next 16 ASCLK cycles is loaded into the

shadow register. The ADC remains fully powered up in normal

mode at the end of the conversion as long as PM1 and PM0 are

set to 1 in the write transfer during that conversion. To ensure

continued operation in normal mode, PM1 and PM0 are both

loaded with 1 on every data transfer. Sixteen serial clock cycles

are required to complete the conversion and access the conver-

sion result. The track-and-hold returns to track on the 14^th

The ADC register can be accessed via the serial interface using

ASYNC

the ASCLK , ADIN, ADOUT, and

pins. The V_DRIVEpin

can be used to dictate the logic levels of the output pins, allow-

ing the ADC to be interfaced to a 3 V DSP while the ADC is

operating at 5 V.

ADC Modes of Operation

The ADC has a number of different modes of operation. These

modes are designed to provide flexible power management options.

These options can be chosen to optimize the power dissipation/

throughput rate ratio for differing application requirements.

The mode of operation of the ADC is controlled by the power

management bits, PM1 and PM0, in the ADC control register,

as detailed in Table 21. When power supplies are first applied to

the ADC, ensure that the ADC is placed in the required mode

of operation (see the Powering Up the ADC section).

ASYNC

ASCLK falling edge.

conversion or can idle low until sometime prior to the next

ASYNC

can then idle high until the next

conversion, (effectively idling

low).

Normal Mode (PM1 = PM0 = 1)

When a data transfer is complete (ADOUT has returned to

TRI

three-state, weak/

bit = 0), another conversion can be

ASYNC

This mode is intended for the fastest throughput rate perfor-

mance because the user does not have to worry about any

power-up times with the ADC remaining fully powered at all

times. Figure 64 shows the general diagram of the operation of

the ADC in this mode.

initiated by bringing

_QUIET, has elapsed.

low again after the quiet time,

t

Full Shutdown (PM1 = 1, PM0 = 0)

In this mode, all internal circuitry on the ADC is powered

down. The ADC retains information in the ADC control

register during full shutdown. The ADC remains in full

shutdown until the power management bits in the control

register, PM1 and PM0, are changed.

ASYNC

1

12

16

ASCLK

ADOUT

CHANNEL IDENTIFIER BITS + CONVERSION RESULT

DATA IN TO CONTROL/SHADOW REGISTER

If a write to the ADC control register occurs while the ADC is

in full shutdown, with the power management bits changed to

PM0 = PM1 = 1, normal mode, the ADC begins to power up

ADIN

NOTES

1. CONTROL REGISTER DATA IS LOADED ON FIRST 12 SCLK CYCLES.

2. SHADOW REGISTER DATA IS LOADED ON FIRST 16 SCLK CYCLES.

ASYNC

on the

rising edge. The track-and-hold that was in hold

while the ADC was in full shutdown return to track on the 14^th

ASCLK falling edge.

Figure 64. ADC Normal Mode Operation

To ensure that the ADC is fully powered up, t_POWER-UP(t₁₂)

ASYNC

should elapse before the next

falling edge. Figure 65

shows the general diagram for this sequence.

PART IS IN FULL PART BEGINS TO POWER UP ON ASYNC PART IS FULLY POWERED UP

SHUTDOWN

RISING EDGE AS PM1 = 1, PM0 = 1

ONCE T

HAS ELAPSED

POWER UP

t₁₂

ASYNC

1

14 16

1

14 16

ASCLK

ADOUT

CHANNEL IDENTIFIER BITS + CONVERSION RESULT

DATA IN TO CONTROL/SHADOW REGISTER

ADIN

DATA IN TO CONTROL REGISTER

CONTROL REGISTER IS LOADED ON THE

FIRST 12 CLOCKS, PM1 = 1, PM0 = 1

TO KEEP PART IN NORMAL MODE, LOAD

PM1 = 1, PM0 = 1 IN CONTROL REGISTER

Figure 65. Full Shutdown Mode Operation

Rev. 0 | Page 34 of 44

AD5590

AutoShutdown (PM1 = 0, PM0 = 1)

Autostandby (PM1 = PM0 = 0)

In this mode, the ADC automatically enters shutdown at the

end of each conversion when the ADC control register is updated.

When the ADC is in shutdown, the track-and-hold is in hold

mode. Figure 66 shows the general diagram of the operation of

the ADC in this mode. In shutdown mode, all internal circuitry

on the ADC is powered down. The ADC retains information in

the ADC control register during shutdown. The ADC remains

In this mode, the ADC automatically enters standby mode at

the end of each conversion when the ADC control register is

updated. Figure 67 shows the general diagram of the operation

of the ADC in this mode. When the ADC is in standby, portions

of the ADC are powered down, but the on-chip bias generator

remains powered up. The ADC retains information in the ADC

control register during standby. The ADC remains in standby

ASYNC

in shutdown until the next

falling edge it receives. On

until it receives the next

falling edge. On this

ASYNC

falling edge, the track and hold that was in hold while the ADC

was in standby returns to track. Wake-up time from standby is 1

μs; the user should ensure that 1 μs has elapsed before attempting a

valid conversion on the ADC in this mode. When running the

ADC with a 20 MHz clock, one dummy cycle of 16 × ASCLKs

should be sufficient to ensure the ADC is fully powered up.

During this dummy cycle, the contents of the ADC control register

should remain unchanged; therefore, the write bit should be set

to 0 on the ADIN line. This dummy cycle effectively halves the

throughput rate of the ADC with every other conversion result

being valid. In this mode, the power consumption of the ADC

is greatly reduced with the ADC entering standby at the end of

each conversion. When the ADC control register is programmed

to move into autostandby, it does so at the end of the conver-

sion. The user can move the ADC in and out of the low power

this

falling edge, the track-and-hold that was in hold

while the ADC was in shutdown returns to track. Wake-up time

from autoshutdown is 1 μs, and the user should ensure that 1 μs

has elapsed before attempting a valid conversion. When running

the ADC with a 20 MHz clock, one dummy cycle of 16 × ASCLKs

should be sufficient to ensure that the ADC is fully powered up.

During this dummy cycle, the contents of the ADC control

register should remain unchanged; therefore, the write bit

should be 0 on the ADIN line. This dummy cycle effectively

halves the throughput rate of the ADC, with every other

conversion result being valid. In this mode, the power

consumption of the ADC is greatly reduced with the ADC

entering shutdown at the end of each conversion. When the

ADC control register is programmed to move into

autoshutdown, it does so at the end of the conversion. The user

can move the ADC in and out of the low power state by

ASYNC

state by controlling the

signal.

ASYNC

controlling the

signal.

PART ENTERS

SHUTDOWN ON ASYNC

RISING EDGE AS

PART BEGINS

TO POWER

UP ON ASYNC

FALLING EDGE

PART ENTERS

SHUTDOWN ON CS

RISING EDGE AS

PM1 = 0, PM0 = 1

PART IS FULLY

POWERED UP

PM1 = 0, PM0 = 1

DUMMY CONVERSION

ASYNC

1

16

1

16

1

16

ASCLK

ADOUT

ADIN

CHANNEL IDENTIFIER BITS + CONVERSION RELSTU

DATA IN TO CONTROL/SHADOW REGISTER

INVALID DATA

CHANNEL IDENTIFIER BITS + CONVERSION RELSTU

DATA IN TO CONTROL/SHADOW REGISTER

CONTROL REGISTER IS LOADED ON THE

FIRST 12 CLOCKS, PM1 = 0, PM0 = 1

CONTROL REGISTER CONTENTS SHOULD

NOT CHANGE, WRITE BIT = 0

TO KEEP PART IN THIS MODE, LOAD PM1 = 0, PM0 = 1

IN CONTROL REGISTER OR SET WRITE BIT = 0

Figure 66. Autoshutdown Mode Operation

PART ENTERS

STANDBY ON ASYNC

RISING EDGE AS

PART BEGINS

TO POWER

UP ON ASYNC

FALLING EDGE

PART ENTERS

STANDBY ON ASYNC

RISING EDGE AS

PM1 = 0, PM0 = 0

PART IS FULLY

POWERED UP

PM1 = 0, PM0 = 0

DUMMY CONVERSION

12

ASYNC

1

12

16

1

16

1

12

16

ASCLK

ADOUT

CHANNEL IDENTIFIER BITS + CONVERSION RESULT

INVALID DATA

ADIN

DATA IN TO CONTROL/SHADOW REGISTER

CONTROL REGISTER IS LOADED ON THE

FIRST 12 CLOCKS, PM1 = 0, PM0 = 0

CONTROL REGISTER CONTENTS SHOULD

REMAIN UNCHANGED, WRITE BIT = 0

TO KEEP PART IN THIS MODE, LOAD PM1 = 0,

PM0 = 0 IN CONTROL REGISTER

Figure 67. Autostandby Mode Operation

Rev. 0 | Page 35 of 44

AD5590

Powering Up the ADC

Interfacing to the ADC

When supplies are first applied to the ADC, the ADC can

power up in any of the operating modes of the ADC. To ensure

that the ADC is placed into the required operating mode, the

user should perform a dummy cycle operation, as outlined in

Figure 68.

Figure 2 shows the detailed timing diagram for serial inter-

facing to the ADC. The serial clock provides the conversion

clock and also controls the transfer of information to and from

the ADC during each conversion.

ASYNC

process. The falling edge of

The

signal initiates the data transfer and conversion

ASYNC

The three dummy conversion operations outlined in Figure 68

must be performed to place the ADC into either of the

automatic modes. The first two conversions of this dummy

cycle operation are performed with the ADIN line tied high,

and for the third conversion of the dummy cycle operation, the

user writes the desired control register configuration to the

ADC to place the ADC into the required automode. On the

puts the track and hold

into hold mode, takes the bus out of three-state, and the analog

input is sampled at this point. The conversion is also initiated

at this point and requires 16 ASCLK cycles to complete. The

track and hold returns to track on the 14^thASCLK falling edge

as shown in Figure 2 at Point B, except when the write is to the

shadow register, in which case the track and hold does not

ASYNC

third

rising edge after the supplies are applied, the

ASYNC

return to track until the rising edge of

in Figure 72. On the 16^thASCLK falling edge, the ADOUT line

TRI

, that is, Point C

control register contains the correct information and valid data

results from the next conversion.

goes back into three-state (assuming the weak/

bit is set

to 0). Sixteen serial clock cycles are required to perform the

conversion process and to access data from the ADC. The

12 bits of data are preceded by the four channel address bits

(ADD3 to ADD0), identifying which channel the conversion

Therefore, to ensure the ADC is placed into the correct

operating mode when supplies are first applied to the ADC,

the user must first issue two serial write operations with the

ADIN line tied high. On the third conversion cycle, the user

can then write to the ADC control register to place the ADC

into any of the operating modes. To guarantee that the ADC

control register contains the correct data, do not write to the

shadow register until the fourth conversion cycle after the

supplies are applied to the ADC.

ASYNC

result corresponds to.

going low provides Address

Bit ADD3 to be read in by the microprocessor or DSP. The

remaining address bits and data bits are then clocked out by

subsequent ASCLK falling edges beginning with the second

Address Bit ADD2; thus, the first ASCLK falling edge on the

serial clock has Address Bit ADD3 provided and also clocks out

Address Bit ADD2. The final bit in the data transfer is valid on

the 16^thfalling edge, having being clocked out on the previous

(15^th) falling edge.

If the user wants to place the ADC into either normal mode or

full shutdown mode, the second dummy cycle with ADIN tied

high can be omitted from the three dummy conversion opera-

tion outlined in Figure 68.

CORRECT VALUE IN CONTROL

REGISTER VALID DATA FROM

NEXT CONVERSION USER CAN

WRITE TO SHADOW REGISTER

IN NEXT CONVERSION

DUMMY CONVERSION

12

DUMMY CONVERSION

12

ASYNC

1

16

1

16

1

12

16

ASCLK

ADOUT

INVALID DATA

ADIN

DATA IN TO CONTROL

KEEP DIN LINE TIED HIGH FOR FIRST TWO DUMMY CONVERSIONS

CONTROL REGISTER IS LOADED ON THE

FIRST 12 CLOCK EDGES

Figure 68. Placing the ADC into the Required Operating Mode after Supplies are Applied

Rev. 0 | Page 36 of 44

AD5590

ADC Control Register

ASYNC

falling

time for the first ASCLK falling edge after the

TRI

edge. If the weak/

bit is set to 0 and the ADOUT line has

The control register on the ADC is a 12-bit, write-only register.

Data is loaded from the ADIN pin of the ADC on the falling

edge of ASCLK. The data is transferred on the ADIN line at the

same time as the conversion result is read from the ADC. The

data transferred on the ADIN line corresponds to the ADC

configuration for the next conversion. This requires 16 serial

clocks for every data transfer. Only the information provided

ASYNC

been in true three-state between conversions, then depending

on the particular DSP or microcontroller interfacing to the

ADC, the ADD3 address bit may not be set up in time for the

DSP/microcontroller to clock it in successfully. In this case,

ASYNC

ADD3 is only driven from the falling edge of

and must

then be clocked in by the DSP on the following falling edge of

TRI

ASCLK. However, if the weak/

bit had been set to 1, then

on the first 12 falling clock edges (after

falling edge) is

although ADOUT is driven with the ADD3 address bit from

the last conversion, it is nevertheless so weakly driven that

another device may still take control of the bus. It does not lead

to a bus contention (for example, a 10 kΩ pull-up or pull-down

resistor would be sufficient to overdrive the logic level of ADD3

between conversions), and all 16 channels may be identified.

However, if this does happen and another device takes control

of the bus, it is not guaranteed that ADOUT becomes fully

driven to ADD3 again in time for the read operation when

control of the bus is taken back.

loaded to the ADC control register. MSB denotes the first bit

in the data stream. The bit functions are outlined in Table 21.

Writing of information to the ADC control register takes place

on the first 12 falling edges of ASCLK in a data transfer, assuming

the MSB, that is, the write bit, has been set to 1. If the ADC

control register is programmed to use the shadow register,

writing of information to the shadow register takes place on

all 16 ASCLK falling edges in the next serial transfer (see

Figure 72). The shadow register is updated on the rising edge

ASYNC

of

channel selected in the sequence.

TRI

and the track-and-hold begins to track the first

This is especially useful if using an automatic sequence mode

to identify to which channel each result corresponds. Obviously,

if only the first eight channels are in use, the ADD3 address bit

does not need to be decoded, and whether it is successfully clocked

in as a 1 or 0 does not matter as long as it is still counted by the

DSP/microcontroller as the MSB of the 16-bit serial transfer.

If the weak/

bit in the ADC control register is set to 1, rather

than returning to true three-state upon the 16^thASCLK falling

edge, the ADOUT line is instead pulled weakly to the logic level

corresponding to ADD3 of the next serial transfer. This is done

to ensure that the MSB of the next serial transfer is set up in

Table 21. ADC Control Register

MSB

LSB

DB11

DB10

DB9

DB8

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

Write

SEQ

ADD3

ADD2

ADD1

ADD0

PM1

PM0

Shadow

Weak/TRI

Range

Coding

Table 22. ADC Control Register Bit Functions

Bit

Name

Description

11

Write

The value written to this bit of the control register determines whether the following 11 bits are loaded to the control

register or not. If this bit is a 1, the following 11 bits are written to the control register; if it is a 0, the remaining 11 bits

are not loaded to the control register, therefore it remains unchanged.

10

SEQ

The SEQ bit in the control register is used in conjunction with the shadow bit to control the use of the sequencer

function and to access the shadow register (see Table 25).

9:6

ADD3:ADD0 These four address bits are loaded at the end of the current conversion sequence and select which analog input

channel is to be converted on in the next serial transfer, or can select the final channel in a consecutive sequence, as

described in Table 25. The selected input channel is decoded as shown in Table 23. The address bits corresponding to

the conversion result are also output on ADOUT prior to the 12 bits of data (see the Serial Interface section). The next

channel to be converted on is selected by the mux on the 14^thASCLK falling edge.

5, 4

3

PM1, PM0

Shadow

These two power management bits decode the mode of operation of the ADC, as shown in Table 24.

The shadow bit in the control register is used in conjunction with the SEQ bit to control the use of the sequencer

function and access the shadow register (see Table 25).

2

1

0

Weak/TRI

Range

This bit selects the state of the ADOUT line at the end of the current serial transfer. If it is set to 1, the ADOUT line is

weakly driven to the ADD3 channel address bit of the ensuing conversion. If this bit is set to 0, ADOUT returns to three-

state at the end of the serial transfer. See the Serial Interface section for more details.

This bit selects the analog input range to be used on the ADC. If it is set to 0, then the analog input range extends from

0 V to 2 × V_REFA. If it is set to 1, then the analog input range extends from 0 V to V_REFA(for the next conversion). For 0 V to

2 × V_REFA, ADCV_DD= 4.75 V to 5.25 V.

Coding

This bit selects the type of output coding the ADC uses for the conversion result. If this bit is set to 0, the output coding

for the ADC is twos complement. If this bit is set to 1, the output coding from the ADC is straight binary (for the next

conversion).

Rev. 0 | Page 37 of 44

AD5590

Table 23. ADC Channel Selection

ADD3

ADD2

ADD1

ADD0

Analog Input Channel

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

VIN0

VIN1

VIN2

VIN3

VIN4

VIN5

VIN6

VIN7

VIN8

VIN9

VIN10

VIN11

VIN12

VIN13

VIN14

VIN15

Table 24. ADC Power Mode Selection

PM1 PM0 Mode

1

Normal operation. In this mode, the ADC remains in full power mode regardless of the status of any of the logic inputs. This

mode allows the fastest possible throughput rate from the ADC.

1

0

Full shutdown. In this mode, the ADC is in full shut down mode, with all circuitry on the ADC powered down. The ADC

retains the information in the control register while in full shutdown. The ADC remains in full shutdown until these bits are

changed in the control register.

0

1

0

Autoshutdown. In this mode, the ADC automatically enters shutdown mode at the end of each conversion when the control

register is updated. Wake-up time from shutdown is 1 μs and the user should ensure that 1 μs has elapsed before attempting

to perform a valid conversion on the ADC in this mode.

Autostandby. In this standby mode, portions of the ADC are powered down, but the on-chip bias generator remains

powered up. This mode is similar to autoshutdown and allows the ADC to power up within one dummy cycle, that is, 1 μs

with a 20 MHz ASCLK.

ADC Sequencer Operation

The configuration of the SEQ and shadow bits in the control register allows the user to select a particular mode of operation of the

sequencer function. Table 25 outlines the four modes of operation of the sequencer.

Table 25. ADC Sequence Selection

SEQ Shadow Sequence Type

0

This configuration means the sequence function is not used. The analog input channel selected for each individual

conversion is determined by the contents of the channel address bits, ADD0 to ADD3, in each prior write operation. This

mode of operation reflects the normal operation of a multichannel ADC, without sequencer function being used, where

each write to the ADC selects the next channel for conversion (see Figure 69).

0

1

This configuration selects the shadow register for programming. After the write to the control register, the following

write operation loads the contents of the shadow register. This programs the sequence of channels to be converted on

continuously with each successive valid ASYNC falling edge (see the shadow register, Table 26, and Figure 70). The

channels selected need not be consecutive.

1

0

1

If the SEQ and shadow bits are set in this way, the sequence function is not interrupted upon completion of the write

operation. This allows other bits in the control register to be altered while in a sequence without terminating the cycle.

This configuration is used in conjunction with the channel address bits, ADD3 to ADD0, to program continuous

conversions on a consecutive sequence of channels from Channel 0 through to a selected final channel, as determined

by the channel address bits in the control register (see Figure 71).

Rev. 0 | Page 38 of 44

AD5590

ADC Shadow Register

POWER ON

The shadow register on the ADC is a 16-bit, write-only register.

Data is loaded from the ADIN pin of the ADC on the falling

edge of ASCLK. The data is transferred on the ADIN line at the

same time as a conversion result is read from the ADC. This

requires 16 serial falling edges for the data transfer. The infor-

mation is clocked into the shadow register, provided that the

SEQ and shadow bits were set to 0 and 1, respectively, in the

previous write to the control register. MSB denotes the first bit

in the data stream. Each bit represents an analog input from

Channel 0 through to Channel 15. A sequence of channels can

be selected through which the ADC cycles with each consecutive

DUMMY CONVERSIONS

ADIN = ALL 1s

ADIN: WRITE TO CONTROL REGISTER,

WRITE BIT = 1,

SELECT CODING, RANGE, AND POWER MODE

SELECT CHANNEL ADD3 TO CHANNEL ADD0

FOR CONVERSION, SEQ = 0 SHADOW = 1

ASYNC

ADOUT: CONVERSION RESULT FROM

PREVIOUSLY SELECTED CHANNEL ADD3 TO

CHANNEL ADD0

ADIN: WRITE TO SHADOW REGISTER,

SELECTING WHICH CHANNELS TO CONVERT

ON; CHANNELS SELECTED NEED NOT BE

CONSECUTIVE

ASYNC

falling edge after the write to the shadow register. To

select a sequence of channels, the associated channel bit must

be set for each analog input. The ADC continuously cycles

through the selected channels in ascending order, beginning

with the lowest channel, until a write operation occurs (that is,

the write bit is set to 1) with the SEQ and shadow bits

configured in any way except 1, 0 (see Table 25). The bit

functions are outlined in Table 26.

WRITE BIT = 1,

WRITE BIT = 0

SEQ = 1, SHADOW = 0

CONTINUOUSLY

CONVERTS ON THE

SELECTED SEQUENCE

OF CHANNELS

CONVERTS ON THE

SELECTED SEQUENCE

OF CHANNELS BUT

ALLOWS RANGE,

ASYNC

CODING, AND SO ON,

TO CHANGE IN THE

CONTROL REGISTER

WITHOUT

WRITE

BIT = 0

WRITE BIT = 0

INTERRUPTING THE

SEQUENCE PROVIDED,

SEQ = 1 SHADOW = 0

Figure 69 reflects the normal operation of a multichannel ADC,

where each serial transfer selects the next channel for conversion.

In this mode of operation, the sequencer function is not used.

WRITE BIT = 1,

SEQ = 1,

SHADOW = 0

Figure 70 shows how to program the ADC to continuously

convert on a particular sequence of channels. To exit this mode

of operation and revert back to the normal mode of operation

of a multichannel ADC (as outlined in Figure 69), ensure the

write bit = 1 and the SEQ = shadow = 0 on the next serial

transfer.

Figure 70. Continuous Conversions

POWER ON

DUMMY CONVERSIONS

ADIN = ALL 1s

Figure 71 shows how a sequence of consecutive channels can

be converted without having to program the shadow register

or write to the ADC on each serial transfer. Again, to exit this

mode of operation and revert back to the normal mode of

operation of a multichannel ADC (as outlined in Figure 69),

ensure the write bit = 1 and the SEQ = shadow = 0 on

the next serial transfer.

ADIN: WRITE TO CONTROL REGISTER,

WRITE BIT = 1,

SELECT CODING, RANGE, AND POWER MODE

SELECT CHANNEL ADD3 TO CHANNEL ADD0

FOR CONVERSION, SEQ = 1 SHADOW = 1

ASYNC

ADOUT: CONVERSION RESULT FROM

CHANNEL 0

POWER ON

ASYNC

CONTINUOUSLY CONVERTS ON A

CONSECUTIVE SEQUENCE OF CHANNELS

FROM CHANNEL 0 UP TO AND INCLUDING

THE PREVIOUSLY SELECTED CHANNEL

ADD3 TO CHANNEL ADD0 IN THE CONTROL

REGISTER

WRITE

BIT = 0

DUMMY CONVERSIONS

ADIN = ALL 1s

WRITE BIT = 1,

SEQ = 1,

SHADOW = 0

ADIN: WRITE TO CONTROL REGISTER,

WRITE BIT = 1,

SELECT CODING, RANGE, AND POWER MODE

ASYNC

SELECT CHANNEL ADD3 TO CHANNEL ADD0

FOR CONVERSION,

SEQ = SHADOW = 0

CONTINUOUSLY CONVERTS ON THE

SELECTED SEQUENCE OF CHANNELS BUT

ALLOWS RANGE, CODING, AND SO ON, TO

CHANGE IN THE CONTROL REGISTER

WITHOUT INTERRUPTING THE SEQUENCE

PROVIDED, SEQ = 1, SHADOW = 0

ASYNC

WRITE BIT = 1,

SEQ = 1,

SHADOW = 0

ADOUT: CONVERSION RESULT FROM

PREVIOUSLY SELECTED CHANNEL ADD3 TO

CHANNEL ADD0

Figure 71. Continuous Conversion Without Programming

the Shadow Register

WRITE BIT = 1,

SEQ = SHADOW = 0

ASYNC

ADIN: WRITE TO CONTROL REGISTER,

WRITE BIT = 1,

SELECT CODING, RANGE, AND POWER MODE

SELECT CHANNEL ADD3 TO CHANNEL ADD0

FOR CONVERSION, SEQ = SHADOW = 0

Figure 69. Sequence Function Not Used

Rev. 0 | Page 39 of 44

AD5590

Table 26. ADC Shadow Register Bits

MSB

LSB

DB0

VIN15

DB15 DB14 DB13 DB12 DB11 DB10 DB9

DB8

DB7

DB6

DB5

DB4

DB3

DB2

DB1

VIN0

VIN1

VIN2

VIN3

VIN4

VIN5

VIN6 VIN7 VIN8 VIN9 VIN10 VIN11 VIN12

VIN13 VIN14

C

ASYNC

t_CONVERT

t₂

t₆

1

2

3

4

5

6

13

14

t₅

15

16

ASCLK

ADOUT

ADIN

t₁₁

t₄

t₇

t₃

ADD2

t₉

ADD1

ADD0

DB11

DB10

DB2

DB1

DB0

t₈

THREE-

STATE

THREE-

STATE

t₁₀

FOUR IDENTIFICATION BITS

ADD3

V

0

V

1

V

2

V

3

V

4

V

5

V

13

V

14

IN

V 15

IN

Figure 72. Writing to Shadow Register Timing Diagram

Rev. 0 | Page 40 of 44

AD5590

ADC Power vs. Throughput Rate

8 μs. If the throughput rate is 100 kSPS, the cycle time is 10 μs

and the average power dissipated during each conversion cycle is

By operating the ADC in autoshutdown or autostandby mode,

the average power consumption of the ADC decreases at lower

throughput rates. Figure 73 shows how, as the throughput rate is

reduced, the ADC remains in its shutdown state longer and the

average power consumption over time drops accordingly.

2

10

8

10

×12.5mW+ ×ꢀW = 2.868mW

Figure 73 shows the power vs. throughput rate when using the

autoshutdown mode and autostandby mode with 5 V supplies.

At the lower throughput rates, power consumption for the

autoshutdown mode is lower than that for the autostandby

mode, with the ADC dissipating less power when in shutdown

compared to standby. However, as the throughput rate is

increased, the ADC spends less time in power-down states;

thus, the difference in power dissipated is negligible between

modes.

For example, if the ADC is operated in a continuous sampling

mode with a throughput rate of 100 kSPS and an ASCLK of

20 MHz, with PM1 = 0 and PM0 = 1 (that is, the device is in

autoshutdown mode), the power consumption is calculated

as follows: the maximum power dissipation during normal

operation is 12.5 mW. If the power-up time from autoshutdown

is one dummy cycle, that is, 1 μs, and the remaining conversion

time is another cycle, that is, 1 μs, the ADC dissipates 12.5 mW

for 2 μs during each conversion cycle. For the remainder of the

conversion cycle, 8 μs, the ADC remains in shutdown mode. The

ADC dissipates 2.5 μW for the remaining 8 μs of the conversion

cycle. If the throughput rate is 100 kSPS, the cycle time is 10 μs

and the average power dissipated during each cycle is

10

ADCV

= 5V

DD

AUTOSTANDBY

AUTOSHUTDOWN

1

2

10

8

10

×12.5mW+ ×2.5ꢀW = 2.502mW

0.1

When operating the ADC in autostandby mode, PM1 = PM0 = 0

at 5 V, 100 kSPS, the ADC power dissipation is calculated as

follows: the maximum power dissipation is 12.5 mW at 5 V during

normal operation. The power-up time from autostandby is one

dummy cycle, 1 μs, and the remaining conversion time is another

dummy cycle, 1 μs. The ADC dissipates 12.5 mW for 2 μs during

each conversion cycle. For the remainder of the conversion cycle,

8 μs, the ADC remains in standby mode dissipating 460 μW for

0.01

0

50

100

150

200

250

300

350

THROUGHPUT (kSPS)

Figure 73. Power vs. Throughput Rate in Autoshutdown

and Autostandby Mode

Rev. 0 | Page 41 of 44

AD5590

OUTLINE DIMENSIONS

A1 CORNER

INDEX AREA

10.00

BSC SQ

12 11 10

7 6 5 4

9 8 3

2 1

A

B

C

D

E

F

G

H

J

2.50 SQ

BALL A1

PAD CORNER

8.80

BSC SQ

BOTTOM

VIEW

TOP VIEW

K

L

M

0.80 BSC

0.60 REF

DETAIL A

1.50

1.36

1.21

1.11

1.01

0.91

DETAIL A

0.65 REF

0.36 REF

0.35 NOM

0.30 MIN

0.12 MAX

COPLANARITY

*

0.50

0.45

0.40

SEATING

PLANE

BALL DIAMETER

*

COMPLIANT TO JEDEC STANDARDS MO-205-AC

WITH THE EXCEPTION TO BALL DIAMETER.

Figure 74. 80-Ball Chip Scale Package Ball Grid Array [CSP_BGA]

(BC-80-2)

Dimensions shown in millimeters

ORDERING GUIDE

Model

AD5590BBC

AD5590BBCZ¹

EVAL-AD5590EBZ¹

Temperature Range

Package Description

80-Ball CSP_BGA

Evaluation Board

Package Option

−40°C to +85°C

BC-80-2

¹Z = RoHS Compliant Part.

Rev. 0 | Page 42 of 44

AD5590

NOTES

Rev. 0 | Page 43 of 44

AD5590

NOTES

registered trademarks are the property of their respective owners.

D07691-0-10/08(0)

Rev. 0 | Page 44 of 44


型号：	EVAL-AD5590EBZ
厂家：	ADI
描述：	16 Input, 16 Output Analog I/O Port with Integrated Amplifiers 16输入， 16输出模拟量I / O端口带有集成放大器放大器
文件：	总44页 (文件大小：924K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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