EVAL-AD7621CB2 [ADI]

16-Bit, 2 LSB INL, 3 MSPS PulSAR® ADC; 16位, 2 LSB INL , 3 MSPS ADC PulSAR®
EVAL-AD7621CB2
型号: EVAL-AD7621CB2
厂家: ADI    ADI
描述:

16-Bit, 2 LSB INL, 3 MSPS PulSAR® ADC
16位, 2 LSB INL , 3 MSPS ADC PulSAR®

文件: 总32页 (文件大小:619K)
中文:  中文翻译
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16-Bit, 2 LSB INL, 3 MSPS PulSAR® ADC  
AD7621  
FEATURES  
Throughput  
FUNCTIONAL BLOCK DIAGRAM  
TEMP REFBUFIN REF REFGND  
DVDD DGND  
3 MSPS (wideband warp and warp mode)  
2 MSPS (normal mode)  
1.25 MSPS (impulse mode)  
AGND  
AVDD  
OVDD  
OGND  
AD7621  
REF  
REF AMP  
SERIAL  
PORT  
2.048 V internal reference  
16  
IN+  
IN–  
SWITCHED  
CAP DAC  
Differential input range: VREF (VREF up to 2.5 V)  
INL: 2 LSB maximum, 1 LSB typical  
16-bit resolution with no missing codes  
SINAD: 89 dB typical @ 100 kHz  
THD: 101 dB typical @ 100 kHz  
No pipeline delay (SAR architecture)  
Parallel (16- or 8-bit bus) and serial 5 V/3.3 V/2.5 V interface  
SPI®-/QSPI™-/MICROWIRE™-/DSP-compatible  
2.5 V single-supply operation  
D[15:0]  
SER/PAR  
BUSY  
PARALLEL  
INTERFACE  
PDREF  
PDBUF  
PD  
RD  
CLOCK  
CS  
CONTROL LOGIC AND  
CALIBRATION CIRCUITRY  
OB/2C  
BYTESWAP  
RESET  
WARP  
IMPULSE CNVST  
Figure 1.  
Power dissipation: 65 mW typical @ 3 MSPS  
48-lead LQFP and 48-lead LFCSP_VQ packages  
Speed upgrade of the AD7677  
Table 1. PulSAR Selection  
800 to  
100 to 250 500 to 570 1000  
AD7651 AD7650/52 AD7653  
AD7660/61 AD7664/66 AD7667  
Type/kSPS  
>1000  
Pseudo  
Differential  
APPLICATIONS  
Medical instruments  
High speed data acquisition  
Digital signal processing  
Communications  
Instrumentation  
True Bipolar  
True  
Differential  
18-Bit  
Multichannel/  
Simultaneous  
AD7663  
AD7665  
AD7671  
AD7675  
AD7678  
AD7676  
AD7679  
AD7677 AD7621  
AD7674 AD7641  
Spectrum analysis  
ATE  
AD7654  
AD7655  
GENERAL DESCRIPTION  
PRODUCT HIGHLIGHTS  
1. Fast Throughput.  
The AD7621 is a 16-bit, 3 MSPS, charge redistribution SAR,  
fully differential analog-to-digital converter (ADC) that  
operates from a single 2.5 V power supply. It contains a high  
speed 16-bit sampling ADC, an internal conversion clock, an  
internal reference (and buffer), error correction circuits, and  
both serial and parallel system interface ports. It features two  
very high sampling rate modes (wideband warp and warp), a  
fast mode (normal) for asynchronous rate applications, and a  
reduced power mode (impulse) for low power applications  
where the power is scaled with the throughput. Operation is  
specified from −40°C to +85°C.  
The AD7621 is a 3 MSPS, charge redistribution,  
16-bit SAR ADC.  
2. Superior Linearity.  
The AD7621 has no missing 16-bit code.  
3. Internal Reference.  
The AD7621 has a 2.048 V internal reference with a  
typical drift of 7 ppm/°C.  
4. Single-Supply Operation.  
The AD7621 operates from a 2.5 V single supply and  
typically dissipates 65 mW. In impulse mode, its power  
dissipation decreases with the throughput.  
5. Serial or Parallel Interface.  
Versatile parallel (16- or 8-bit bus) or 2-wire serial interface  
arrangement compatible with 2.5 V, 3.3 V, or 5 V logic.  
Rev. 0  
Information furnished by Analog Devices is believed to be accurate and reliable.  
However, no responsibility is assumed by Analog Devices for its use, nor for any  
infringements of patents or other rights of third parties that may result from its use.  
Specifications subject to change without notice. No license is granted by implication  
or otherwise under any patent or patent rights of Analog Devices. Trademarks and  
registered trademarks are the property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700  
Fax: 781.461.3113  
www.analog.com  
©2005 Analog Devices, Inc. All rights reserved.  
AD7621  
TABLE OF CONTENTS  
Specifications..................................................................................... 3  
Voltage Reference Input ............................................................ 18  
Power Supply............................................................................... 19  
Power Dissipation vs. Throughput .......................................... 20  
Conversion Control ................................................................... 20  
Interfaces.......................................................................................... 21  
Digital Interface.......................................................................... 21  
Parallel Interface......................................................................... 21  
Serial Interface............................................................................ 22  
Master Serial Interface............................................................... 22  
Slave Serial Interface .................................................................. 24  
Microprocessor Interfacing....................................................... 26  
Application ...................................................................................... 27  
Layout .......................................................................................... 27  
Evaluating the AD7621 Performance...................................... 27  
Outline Dimensions....................................................................... 28  
Ordering Guide .......................................................................... 29  
Timing Specifications....................................................................... 5  
Serial Clock Timing Specifications ............................................ 6  
Absolute Maximum Ratings............................................................ 7  
ESD Caution.................................................................................. 7  
Pin Configuration and Function Descriptions............................. 8  
Terminology .................................................................................... 11  
Typical Performance Characteristics ........................................... 12  
Theory of Operation ...................................................................... 15  
Circuit Information.................................................................... 15  
Converter Operation.................................................................. 15  
Modes of Operation ................................................................... 15  
Transfer Functions...................................................................... 16  
Typical Connection Diagram ................................................... 17  
Analog Inputs.............................................................................. 17  
Driver Amplifier Choice............................................................ 17  
REVISION HISTORY  
5/05 — Revision 0: Initial Version  
Rev. 0 | Page 2 of 32  
AD7621  
SPECIFICATIONS  
AVDD = DVDD = 2.5 V; OVDD = 2.3 V to 3.6 V; VREF = 2.5 V; all specifications TMIN to TMAX, unless otherwise noted.  
Table 2.  
Parameter  
Conditions  
Min  
Typ  
Max  
Unit  
RESOLUTION  
16  
Bits  
ANALOG INPUT  
Voltage Range  
−VREF  
−0.1  
VREF  
AVDD1  
V
VIN+ VIN−  
VIN+, VIN− to AGND  
fIN = 100 kHz  
Operating Input Voltage  
Analog Input CMRR  
Input Current  
V
dB  
μA  
55  
25  
3 MSPS throughput  
Input Impedance2  
THROUGHPUT SPEED  
Complete Cycle  
Throughput Rate  
Time Between Conversions  
Complete Cycle  
Throughput Rate  
Complete Cycle  
Throughput Rate  
Wideband warp, warp modes  
Wideband warp, warp modes  
Wideband warp, warp modes  
Normal mode  
Normal mode  
Impulse mode  
333  
3
1
500  
2
800  
1.25  
ns  
MSPS  
ms  
ns  
MSPS  
ns  
0.001  
0
0
Impulse mode  
MSPS  
DC ACCURACY  
All modes  
Integral Linearity Error3  
No Missing Codes  
Differential Linearity Error  
Transition Noise  
VREF = 2.048 V, PDREF = high  
VREF = 2.048 V, PDREF = high  
VREF = 2.048 V, PDREF = high  
VREF = 2.5 V  
−2  
16  
−1  
1
+2  
+2  
LSB4  
Bits  
LSB  
LSB  
LSB  
LSB  
0.69  
0.82  
Transition Noise  
Zero Error, TMIN to TMAX  
VREF = 2.048 V  
5
−30  
+30  
Zero Error Temperature Drift  
Gain Error, TMIN to TMAX  
Gain Error Temperature Drift  
Power Supply Sensitivity  
AC ACCURACY  
1
ppm/°C  
% of FSR  
ppm/°C  
LSB  
5
−0.38  
+0.38  
2
3
AVDD = 2.5 V 5%  
Dynamic Range  
Signal-to-Noise  
fIN = 20 kHz, VREF = 2.5 V  
fIN = 20 kHz, VREF = 2.5 V  
fIN = 20 kHz, VREF = 2.048 V  
fIN = 100 kHz, VREF = 2.5 V  
fIN = 20 kHz  
fIN = 100 kHz  
fIN = 20 kHz  
fIN = 100 kHz  
90.5  
90  
88  
dB6  
dB  
dB  
dB  
dB  
dB  
dB  
dB  
dB  
dB  
dB  
MHz  
88  
86  
89.2  
103  
101  
–102  
−100  
89.8  
87.5  
89  
Spurious-Free Dynamic Range  
Total Harmonic Distortion  
Signal-to-(Noise + Distortion)  
fIN = 20 kHz, VREF = 2.5 V  
fIN = 20 kHz, VREF = 2.048 V  
fIN = 100 kHz, VREF = 2.5 V  
87.5  
–3 dB Input Bandwidth  
SAMPLING DYNAMICS  
Aperture Delay  
50  
1
5
ns  
ps rms  
ns  
Aperture Jitter  
Transient Response  
INTERNAL REFERENCE  
Output Voltage  
Full-scale step  
50  
PDREF = PDBUF = low  
REF @ 25°C  
2.038  
2.048 2.058  
V
Temperature Drift  
Line Regulation  
–40°C to +85°C  
AVDD = 2.5 V 5%  
7
15  
ppm/°C  
ppm/V  
Rev. 0 | Page 3 of 32  
 
AD7621  
Parameter  
Conditions  
Min  
Typ  
5
1.2  
6.33  
Max  
Unit  
ms  
V
Turn-On Settling Time  
REFBUFIN Output Voltage  
REFBUFIN Output Resistance  
EXTERNAL REFERENCE  
Voltage Range  
Current Drain  
CREF = 10 μF  
REFBUFIN @ 25°C  
kΩ  
PDREF = PDBUF = high  
REF  
3 MSPS throughput  
PDREF = high, PDBUF = low  
1.8  
2.048 AVDD  
250  
V
μA  
REFERENCE BUFFER  
REFBUFIN Input Voltage Range  
TEMPERATURE PIN  
Voltage Output  
Temperature Sensitivity  
Output Resistance  
DIGITAL INPUTS  
Logic Levels  
1.05  
1.2  
1.30  
V
@ 25°C  
273  
0.85  
4.7  
mV  
mV/°C  
kΩ  
VIL  
VIH  
IIL  
IIH  
–0.3  
1.7  
–1  
+0.6  
5.25  
+1  
V
V
μA  
μA  
–1  
+1  
DIGITAL OUTPUTS  
Data Format7  
Pipeline Delay8  
VOL  
VOH  
ISINK = 500 μA  
ISOURCE = –500 μA  
0.4  
V
V
OVDD − 0.3  
POWER SUPPLIES  
Specified Performance  
AVDD  
2.37  
2.37  
2.309  
2.5  
2.5  
2.63  
2.63  
3.6  
V
V
V
DVDD  
OVDD  
Operating Current10  
AVDD11  
DVDD  
3 MSPS throughput  
With internal reference  
25.2  
3.6  
1
mA  
mA  
mA  
OVDD  
Power Dissipation11  
With Internal Reference10  
Without Internal Reference10  
With Internal Reference 12  
Without Internal Reference12  
In Power-Down Mode13  
TEMPERATURE RANGE14  
Specified Performance  
3 MSPS throughput  
3 MSPS throughput  
1.25 MSPS throughput  
1.25 MSPS throughput  
PD = high  
70  
65  
42  
37  
600  
86  
80  
55  
50  
mW  
mW  
mW  
mW  
μW  
TMIN to TMAX  
–40  
+85  
°C  
1 When using an external reference. With the internal reference, the input range is 0.1 V to VREF  
2 See the Analog Inputs section.  
.
3 Linearity is tested using endpoints, not best fit. Tested with an external reference at 2.048 V.  
4 LSB means least significant bit. With the 2.048 V input range, 1 LSB is 62.5 μV.  
5 See the Voltage Reference Input section. These specifications do not include the error contribution from the external reference.  
6 All specifications in dB are referred to a full-scale input FSR. Tested with an input signal at 0.5 dB below full-scale, unless otherwise specified.  
7 Parallel or serial 16-bit.  
8 Conversion results are available immediately after completed conversion.  
9 See the Absolute Maximum Ratings section.  
10 In warp mode. Tested in parallel reading mode.  
11 With internal reference, PDREF and PDBUF are low; without internal reference, PDREF and PDBUF are high.  
12 In impulse mode. Tested in parallel reading mode.  
13 With all digital inputs forced to OVDD.  
14 Consult factory for extended temperature range.  
Rev. 0 | Page 4 of 32  
 
 
 
 
 
 
 
 
 
 
 
AD7621  
TIMING SPECIFICATIONS  
AVDD = DVDD = 2.5 V; OVDD = 2.3 V to 3.6 V; VREF = 2.5 V; all specifications TMIN to TMAX, unless otherwise noted.  
Table 3.  
Parameter  
Symbol Min  
Typ  
Max  
701  
23  
Unit  
CONVERSION AND RESET (Refer to Figure 31 and Figure 32)  
Convert Pulse Width  
Time Between Conversions (Warp2 Mode/Normal Mode/Impulse Mode)3  
t1  
t2  
t3  
t4  
t5  
t6  
15  
ns  
ns  
ns  
333/500/800  
CNVST Low to BUSY High Delay  
BUSY High All Modes (Except Master Serial Read After Convert)  
Aperture Delay  
283/430/560 ns  
1
ns  
ns  
End of Conversion to BUSY Low Delay  
Conversion Time (Warp Mode/Normal Mode/Impulse Mode)  
Acquisition Time (Warp Mode/Normal Mode/Impulse Mode)  
RESET Pulse Width  
10  
t7  
t8  
t9  
t38  
t39  
283/430/560 ns  
50/70/50  
15  
ns  
ns  
ns  
ns  
RESET Low to BUSY High Delay4  
10  
600  
BUSY High Time from RESET Low4  
PARALLEL INTERFACE MODES (Refer to Figure 33 and Figure 35)  
CNVST Low to DATA Valid Delay  
t10  
283/430/560 ns  
ns  
20  
15  
(Warp Mode/Normal Mode/Impulse Mode)  
DATA Valid to BUSY Low Delay  
Bus Access Request to DATA Valid  
t11  
t12  
t13  
2
2
ns  
ns  
Bus Relinquish Time  
MASTER SERIAL INTERFACE MODES5 (Refer to Figure 37 and Figure 38)  
CS Low to SYNC Valid Delay  
CS Low to Internal SCLK Valid Delay5  
t14  
t15  
t16  
10  
10  
10  
ns  
ns  
ns  
CS Low to SDOUT Delay  
CNVST Low to SYNC Delay  
(Warp Mode/Normal Mode/Impulse Mode)  
SYNC Asserted to SCLK First Edge Delay  
Internal SCLK Period6  
t17  
t18  
t19  
t20  
t21  
t22  
t23  
t24  
t25  
t26  
t27  
t28  
t29  
t30  
12/137/263  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
0.5  
8
2
3
1
12  
Internal SCLK High6  
Internal SCLK Low6  
SDOUT Valid Setup Time6  
SDOUT Valid Hold Time6  
0
0
SCLK Last Edge to SYNC Delay6  
CS High to SYNC HI-Z  
10  
10  
10  
CS High to Internal SCLK HI-Z  
CS High to SDOUT HI-Z  
BUSY High in Master Serial Read after Convert6  
CNVST Low to SYNC Asserted Delay (All Modes)  
SYNC Deasserted to BUSY Low Delay  
See Table 4  
275/400/500  
13  
ns  
ns  
Rev. 0 | Page 5 of 32  
 
AD7621  
Parameter  
Symbol Min  
Typ  
Max  
Unit  
SLAVE SERIAL INTERFACE MODES5 (Refer to Figure 40 and Figure 41)  
External SCLK Setup Time  
External SCLK Active Edge to SDOUT Delay  
SDIN Setup Time  
SDIN Hold Time  
External SCLK Period  
t31  
t32  
t33  
t34  
t35  
t36  
t37  
5
1
5
5
12.5  
5
5
ns  
ns  
ns  
ns  
ns  
ns  
ns  
8
External SCLK High  
External SCLK Low  
1 See the Conversion Control section.  
2 All timings for wideband warp mode are the same as warp mode.  
3 In warp mode only, the time between conversions is 1 ms; otherwise, there is no required maximum time.  
4 See the Digital Interface, and RESET sections.  
5 In serial interface modes, the SYNC, SCLK, and SDOUT timings are defined with a maximum load CL of 10 pF; otherwise, the load is 60 pF maximum.  
6 In serial master read during convert mode. See Table 4 for serial master read after convert mode timing specifications.  
SERIAL CLOCK TIMING SPECIFICATIONS  
Table 4. Serial Clock Timings in Master Read After Convert Mode  
DIVSCLK[1]  
0
0
1
1
DIVSCLK[0]  
Symbol  
t18  
t19  
t19  
t20  
t21  
t22  
t23  
t24  
0
1
0
1
Unit  
SYNC to SCLK First Edge Delay Minimum  
Internal SCLK Period Minimum  
Internal SCLK Period Maximum  
Internal SCLK High Minimum  
0.5  
8
12  
2
3
1
0
0
3
3
3
64  
100  
31  
32  
5
28  
26  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
μs  
μs  
μs  
16  
25  
6
7
5
0.5  
0.5  
0.720  
0.870  
1.000  
32  
50  
15  
16  
5
10  
9
1.160  
1.310  
1.440  
Internal SCLK Low Minimum  
SDOUT Valid Setup Time Minimum  
SDOUT Valid Hold Time Minimum  
SCLK Last Edge to SYNC Delay Minimum  
BUSY High Width Maximum (Wideband and Warp Modes)  
BUSY High Width Maximum (Normal Mode)  
BUSY High Width Maximum (Impulse Mode)  
t28  
t28  
t28  
0.500  
0.650  
0.780  
2.040  
2.190  
2.320  
500μA  
I
OL  
2V  
0.8V  
tDELAY  
tDELAY  
TO OUTPUT  
PIN  
1.4V  
2V  
2V  
C
50pF  
0.8V  
L
0.8V  
Figure 3. Voltage Reference Levels for Timing  
500μA  
I
OH  
NOTE  
IN SERIAL INTERFACE MODES, THE SYNC, SCLK AND  
SDOUT ARE DEFINED WITH A MAXIMUM LOAD.  
C
OF 10pF; OTHERWISE, THE LOAD IS 60pF MAXIMUM.  
L
Figure 2. Load Circuit for Digital Interface Timing,  
SDOUT, SYNC, and SCLK Outputs, CL = 10 pF  
Rev. 0 | Page 6 of 32  
 
 
 
 
 
AD7621  
ABSOLUTE MAXIMUM RATINGS  
Table 5.  
Stresses above those listed under Absolute Maximum Ratings  
Parameter  
Rating  
may cause permanent damage to the device. This is a stress  
rating only; functional operation of the device at these or any  
other conditions above those indicated in the operational  
section of this specification is not implied. Exposure to absolute  
maximum rating conditions for extended periods may affect  
device reliability.  
Analog Inputs/Outputs  
IN+1, IN−, REF, REFBUFIN, TEMP, AVDD + 0.3 V to  
INGND, REFGND to AGND  
Ground Voltage Differences  
AGND, DGND, OGND  
Supply Voltages  
AGND − 0.3 V  
0.3 V  
AVDD, DVDD  
OVDD  
AVDD to DVDD  
–0.3 V to +2.7 V  
–0.3 V to +3.8 V  
2.8 V  
ESD CAUTION  
ESD (electrostatic discharge) sensitive device.  
Charged devices and circuit boards can discharge  
without detection. Although this product features  
patented or proprietary protection circuitry, damage may  
occur on devices subjected to high energy ESD.  
Therefore, proper ESD precautions should be taken to  
avoid performance degradation or loss of functionality.  
AVDD to OVDD  
+2.8 V to −3.8 V  
≤ +0.3 V if DVDD < 2.3 V  
−0.3 V to +5.5 V  
20 mA  
700 mW  
2.5 W  
OVDD to DVDD2  
Digital Inputs  
PDREF, PDBUF3  
Internal Power Dissipation4  
Internal Power Dissipation5  
Junction Temperature  
Storage Temperature Range  
125°C  
–65°C to +125°C  
1 See the Analog Inputs section.  
2 See the Power Supply section.  
3 See the Voltage Reference Input section.  
4 Specification is for the device in free air: 48-Lead LQFP; θJA = 91°C/W,  
θ
JC = 30°C/W.  
5 Specification is for the device in free air: 48-Lead LFCSP; θJA = 26°C/W.  
Rev. 0 | Page 7 of 32  
 
 
 
 
 
 
 
 
AD7621  
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS  
48 47 46 45 44 43 42 41 40 39 38 37  
1
2
AGND  
AVDD  
36 AGND  
35 CNVST  
34 PD  
PIN 1  
IDENTIFIER  
3
NC  
BYTESWAP  
OB/2C  
4
33  
RESET  
5
32 CS  
AD7621  
TOP VIEW  
(Not to Scale)  
WARP  
6
31  
30  
29  
28  
27  
26  
25  
RD  
IMPULSE  
7
DGND  
BUSY  
D15  
8
SER/PAR  
9
D0  
D1  
10  
11  
12  
D14  
D2/DIVSCLK[0]  
D3/DIVSCLK[1]  
D13  
D12  
13 14 15 16 17 18 19 20 21 22 23 24  
NC = NO CONNECT  
Figure 4. Pin Configuration  
Table 6. Pin Function Descriptions  
Pin No.  
1, 41, 42  
2, 44  
Mnemonic  
Type1 Description  
AGND  
AVDD  
NC  
P
P
Analog Power Ground Pin.  
Input Analog Power Pins. Nominally 2.5 V.  
No Connect.  
3, 40  
4
BYTESWAP  
DI  
DI  
DI  
Parallel Mode Selection (8-Bit/16-Bit). When high, the LSB is output on D[15:8] and the MSB is output  
on D[7:0]; when low, the LSB is output on D[7:0] and the MSB is output on D[15:8].  
Straight Binary/Binary Twos Complement Output. When high, the digital output is straight binary;  
when low, the MSB is inverted resulting in a twos complement output from its internal shift register.  
Conversion Mode Selection. When WARP = high and IMPULSE = high, this selects wideband mode  
with slightly improved linearity and THD. When WARP = high and IMPULSE = low, this selects warp  
mode. In either mode, these are the fastest modes; maximum throughput is achievable, and a  
minimum conversion rate must be applied in order to guarantee full specified accuracy.  
5
6
OB/2C  
WARP  
When WARP = low and IMPULSE = low, this input selects normal mode where full accuracy is  
maintained independent of the minimum conversion rate.  
7
8
IMPULSE  
SER/PAR  
DI  
DI  
Conversion Mode Selection. When IMPULSE = high and WARP = low, this input selects impulse mode,  
a reduced power mode. In this mode, the power dissipation is approximately proportional to the  
sampling rate.  
Serial/Parallel Selection Input. When high, the serial interface is selected and some bits of the data bus  
are used as a serial port; the remaining data bits are high impedance outputs. When SER/PAR = low,  
the parallel port is selected.  
9, 10  
11, 12  
D[0:1]  
D[2:3]  
DO  
DI/O  
Bit 0 and Bit 1 of the Parallel Port Data Output Bus.  
When SER/PAR = low, these outputs are used as Bit 2 and Bit 3 of the parallel port data output bus.  
or  
When SER/PAR = high, serial clock division selection. When using serial master read after convert  
mode (EXT/INT = low, RDC/SDIN = low) these inputs can be used to slow down the internally  
generated serial clock that clocks the data output. In other serial modes, these pins are high  
impedance outputs.  
DIVSCLK[0:1]  
13  
D4  
DI/O  
When SER/PAR = low, this output is used as Bit 4 of the parallel port data output bus.  
or EXT/INT  
When SER/PAR = high, serial clock source select. This input is used to select the internally generated  
(master ) or external (slave) serial data clock.  
When EXT/INT = low: master mode. The internal serial clock is selected on SCLK output.  
When EXT/INT = high: slave mode. The output data is synchronized to an external clock signal, gated  
by CS, connected to the SCLK input.  
Rev. 0 | Page 8 of 32  
 
AD7621  
Pin No.  
Mnemonic  
D5  
Type1 Description  
14  
DI/O  
When SER/PAR = low this output is used as Bit 5 of the parallel port data output bus.  
or INVSYNC  
When SER/PAR = high, invert sync select. In serial master mode (EXT/INT = low), this input is used to  
select the active state of the SYNC signal.  
When INVSYNC = low, SYNC is active high.  
When INVSYNC = high, SYNC is active low.  
15  
16  
D6  
DI/O  
DI/O  
PAR  
When SER/  
= low this output is used as Bit 6 of the parallel port data output bus.  
or INVSCLK  
D7  
Invert SCLK Select. In all serial modes, this input is used to invert the SCLK signal.  
Bit 7 of the Parallel Port Data Output Bus.  
or RDC  
When SER/PAR = high, read during convert. When using Serial Master mode (EXT/INT = low), RDC is  
used to select the read mode.  
When RDC = high, the previous conversion result is read during current conversion and the period of  
SCLK changes (see the Master Serial Interface section).  
When RDC = low (read after convert), the current result is read after conversion.  
or SDIN  
Serial Data In. When using serial slave mode, (EXT/INT = high), SDIN could be used as a data input to  
daisy-chain the conversion results from two or more ADCs onto a single SDOUT line. The digital data  
level on SDIN is output on SDOUT with a delay of 16 SCLK periods after the initiation of the read  
sequence.  
17  
18  
OGND  
OVDD  
P
P
Input/Output Interface Digital Power Ground.  
Input/Output Interface Digital Power. Nominally at the same supply as the supply of the host interface  
(2.5 V or 3 V).  
19  
20  
21  
DVDD  
DGND  
D8  
P
P
DO  
Digital Power. Nominally at 2.5 V.  
Digital Power Ground.  
When SER/PAR = low this output is used as Bit 8 of the parallel port data output bus.  
or SDOUT  
When SER/PAR = high, serial data output. In serial mode, this pin is used as the serial data output  
synchronized to SCLK. Conversion results are stored in an on-chip register. The AD7621 provides the  
conversion result, MSB first, from its internal shift register. The data format is determined by the logic  
level of OB/2C.  
In master mode (EXT/INT = low). SDOUT is valid on both edges of SCLK.  
In slave mode (EXT/INT = high):  
When INVSCLK = low, SDOUT is updated on SCLK rising edge and valid on the next falling edge.  
When INVSCLK = high, SDOUT is updated on SCLK falling edge and valid on the next rising edge.  
22  
23  
D9  
DI/O  
DO  
Parallel Port Data Output Bus Bit 9. When SER/PAR = low, this output is used as Bit 9 of the parallel port  
data output bus.  
Serial Clock. When SER/PAR = high, serial clock. In all serial modes, this pin is used as the serial data  
clock input or output, dependent upon the logic state of the EXT/INT pin. The active edge where the  
data SDOUT is updated depends upon the logic state of the INVSCLK pin.  
When SER/PAR = low, this output is used as Bit 10 of the parallel port data output bus.  
or SCLK  
D10  
or SYNC  
When SER/PAR = high, frame synchronization. In serial master mode (EXT/INT= low), this output is  
used as a digital output frame synchronization for use with the internal data clock.  
When a read sequence is initiated and INVSYNC = low, SYNC is driven high and remains high while  
SDOUT output is valid.  
When a read sequence is initiated and INVSYNC = high, SYNC is driven low and remains low while  
SDOUT output is valid.  
24  
D11  
DO  
Parallel Port Data Output Bus Bit 11. When SER/PAR = low, this output is used as Bit 11 of the parallel  
port data output bus.  
or RDERROR  
Read Error. When SER/PAR = high, read error. In serial slave mode (EXT/INT = high), this output is used  
as an incomplete read error flag. If a data read is started and not completed when the current  
conversion is complete, the current data is lost and RDERROR is pulsed high.  
25 to 28  
29  
D[12:15]  
BUSY  
DO  
DO  
Bit 12 to Bit 15 of the Parallel Port Data Output Bus.  
Busy Output. Transitions high when a conversion is started, and remains high until the conversion is  
complete and the data is latched into the on-chip shift register. The falling edge of BUSY can be used  
as a data ready clock signal.  
30  
31  
DGND  
RD  
P
DI  
Digital Power Ground.  
Read Data. When CS and RD are both low, the interface parallel or serial output bus is enabled.  
Rev. 0 | Page 9 of 32  
AD7621  
Pin No.  
Mnemonic  
Type1 Description  
32  
CS  
DI  
CS  
Chip Select. When CS and RD are both low, the interface parallel or serial output bus is enabled. is  
also used to gate the external clock in slave serial mode.  
33  
RESET  
DI  
Reset Input. When high, reset the AD7621. Current conversion if any is aborted. Falling edge of RESET  
enables the calibration mode indicated by pulsing BUSY high. Refer to the Digital Interface section. If  
not used, this pin can be tied to DGND.  
34  
35  
PD  
DI  
DI  
Power-Down Input. When high, power down the ADC. Power consumption is reduced and  
conversions are inhibited after the current one is completed.  
Conversion Start. A falling edge on CNVST puts the internal sample-and-hold into the hold state and  
CNVST  
initiates a conversion.  
36  
37  
AGND  
REF  
P
AI/O  
Analog Power Ground Pin.  
Reference Output/Input.  
When PDREF/PDBUF = low, the internal reference and buffer are enabled producing 2.048 V on this pin.  
When PDREF/PDBUF = high, the internal reference and buffer are disabled allowing an externally  
supplied voltage reference up to AVDD volts. Decoupling is required with or without the internal  
reference and buffer. Refer to the Voltage Reference Input section.  
38  
39  
43  
45  
46  
REFGND  
IN−  
IN+  
TEMP  
REFBUFIN  
AI  
AI  
AI  
AO  
AI/O  
Reference Input Analog Ground.  
Differential Negative Analog Input.  
Differential Positive Analog Input.  
Temperature Sensor Analog Output.  
Internal Reference Output/Reference Buffer Input.  
When PDREF/PDBUF = low, the internal reference and buffer are enabled producing the 1.2 V  
(typical) bandgap output on this pin, which needs external decoupling. The internal fixed gain  
reference buffer uses this to produce 2.048V on the REF pin.  
When using an external reference with the internal reference buffer (PDBUF = low, PDREF = high),  
applying 1.2 V on this pin produces 2.048 V on the REF pin. Refer to the Voltage Reference Input section.  
47  
48  
PDREF  
PDBUF  
DI  
DI  
Internal Reference Power-Down Input.  
When low, the internal reference is enabled.  
When high, the internal reference is powered down and an external reference must been used.  
Internal Reference Buffer Power-Down Input.  
When low, the buffer is enabled (must be low when using internal reference).  
When high, the buffer is powered-down.  
1 AI = analog input; AI/O = bidirectional analog; AO = analog output; DI = digital input; DI/O = bidirectional digital; DO = digital output; P = power.  
Rev. 0 | Page 10 of 32  
 
 
 
AD7621  
TERMINOLOGY  
Integral Nonlinearity Error (INL)  
Signal-to-(Noise + Distortion) Ratio (SINAD)  
Linearity error refers to the deviation of each individual code  
from a line drawn from negative full-scale through positive full-  
scale. The point used as negative full-scale occurs ½ LSB before  
the first code transition. Positive full-scale is defined as a level  
1½ LSBs beyond the last code transition. The deviation is  
measured from the middle of each code to the true straight line.  
SINAD is the ratio of the rms value of the actual input signal to  
the rms sum of all other spectral components below the Nyquist  
frequency, including harmonics but excluding dc. The value for  
SINAD is expressed in decibels.  
Spurious-Free Dynamic Range (SFDR)  
The difference, in decibels (dB), between the rms amplitude of  
the input signal and the peak spurious signal.  
Differential Nonlinearity Error (DNL)  
In an ideal ADC, code transitions are 1 LSB apart. Differential  
nonlinearity is the maximum deviation from this ideal value. It  
is often specified in terms of resolution for which no missing  
codes are guaranteed.  
Effective Number of Bits (ENOB)  
ENOB is a measurement of the resolution with a sine wave  
input. It is related to SINAD and is expressed in bits by  
ENOB = [(SINADdB 1.76)/6.02]  
Gain Error  
Aperture Delay  
Aperture delay is a measure of the acquisition performance  
measured from the falling edge of the  
the input signal is held for a conversion.  
The first transition (from 000…00 to 000…01) should occur for  
an analog voltage ½ LSB above the nominal negative full-scale  
(−2.0479688 V for the 2.048 V range). The last transition  
(from 111…10 to 111…11) should occur for an analog voltage  
1½ LSBs below the nominal full-scale (2.0479531 V for the  
2.048 V range). The gain error is the deviation of the  
difference between the actual level of the last transition and the  
actual level of the first transition from the difference between  
the ideal levels.  
CNVST  
input to when  
Transient Response  
The time required for the AD7621 to achieve its rated accuracy  
after a full-scale step function is applied to its input.  
Reference Voltage Temperature Coefficient  
Reference voltage temperature coefficient is derived from the  
typical shift of output voltage at 25°C on a sample of parts at the  
Zero Error  
The zero error is the difference between the ideal midscale  
input voltage (0 V) and the actual voltage producing the  
midscale output code.  
maximum and minimum reference output voltage (VREF  
)
measured at TMIN, T(25°C), and TMAX. It is expressed in ppm/°C as  
VREF (Max) – VREF (Min)  
TCVREF (ppm/°C) =  
×106  
Dynamic Range  
VREF (25°C) × (TMAX – TMIN  
)
Dynamic range is the ratio of the rms value of the full-scale to  
the rms noise measured with the inputs shorted together. The  
value for dynamic range is expressed in decibels.  
where:  
V
V
V
T
T
REF (Max) = maximum VREF at TMIN, T (25°C), or TMAX  
REF (Min) = minimum VREF at TMIN, T (25°C), or TMAX  
REF (25°C) = VREF at 25°C  
Signal-to-Noise Ratio (SNR)  
SNR is the ratio of the rms value of the actual input signal to the  
rms sum of all other spectral components below the Nyquist  
frequency, excluding harmonics and dc. The value for SNR is  
expressed in decibels.  
MAX = +85°C  
MIN = –40°C  
Total Harmonic Distortion (THD)  
THD is the ratio of the rms sum of the first five harmonic  
components to the rms value of a full-scale input signal and is  
expressed in decibels.  
Rev. 0 | Page 11 of 32  
 
AD7621  
TYPICAL PERFORMANCE CHARACTERISTICS  
2.0  
1.5  
1.0  
1.5  
1.0  
0.5  
0.5  
0
0
–0.5  
–1.0  
–1.5  
–2.0  
–0.5  
–1.0  
0
16384  
32768  
CODE  
49152  
65536  
0
16384  
32768  
CODE  
49152  
65536  
Figure 8. Differential Nonlinearity vs. Code  
Figure 5. Integral Nonlinearity vs. Code  
160000  
140000  
120000  
100000  
80000  
60000  
40000  
20000  
0
160000  
149969  
σ
= 0.82  
σ
= 0.69  
140000  
120000  
100000  
80000  
60000  
40000  
20000  
0
127317  
60842  
59637  
54791  
51847  
6644  
6376  
2415  
2080  
176  
128  
0
0
0
13  
5
0
7FFC 7FFD 7FFE 7FFF 8000 8001 8002 8003 8004  
CODE IN HEX  
7FFC 7FFD 7FFE 7FFF 8000 8001 8002 8003 8004  
CODE IN HEX  
Figure 9. Histogram of 261,120 Conversions of a DC Input  
at the Code Center (Internal Reference)  
Figure 6. Histogram of 261,120 Conversions of a DC Input  
at the Code Center (External Reference)  
10  
8
2.0530  
2.0525  
2.0520  
2.0515  
2.0510  
2.0505  
2.0500  
2.0495  
2.0490  
2.0485  
2.0480  
6
4
2
–FS  
0
–2  
–4  
ZERO ERROR  
–6  
–8  
+FS  
–10  
–55  
–35  
–15  
5
25  
45  
65  
85  
105  
125  
–55  
–35  
–15  
5
25  
45  
65  
85  
105  
125  
TEMPERATURE (°C)  
TEMPERATURE (°C)  
Figure 10. Zero Error, Positive and Negative Full Scale vs. Temperature  
Figure 7. Typical Reference Voltage Output vs. Temperature (3 Units)  
Rev. 0 | Page 12 of 32  
 
 
AD7621  
0
–20  
0
–20  
fS = 3MSPS  
fS = 3MSPS  
fIN = 20.1kHz  
fIN = 98.79kHz  
SNR = 89.9dB  
SNR = 90.1dB  
THD = –103.2dB  
SFDR = 103.8dB  
SINAD = 89.9dB  
THD = –104.9dB  
SFDR = 106.6dB  
SINAD = 89.8dB  
–40  
–40  
–60  
–60  
–80  
–80  
–100  
–120  
–140  
–160  
–180  
–100  
–120  
–140  
–160  
–180  
0
100 200 300 400 500 600 700 800 900 10001100 1200 1300 1400 1500  
FREQUENCY (kHz)  
0
100 200 300 400 500 600 700 800 900 10001100 1200 1300 1400 1500  
FREQUENCY (kHz)  
Figure 14. FFT 100 kHz  
Figure 11. FFT 20 kHz  
92  
16.0  
95  
16.0  
15.6  
93  
91  
89  
87  
85  
83  
81  
79  
77  
75  
91  
90  
89  
88  
87  
86  
85  
84  
SNR  
15.2  
SNR  
15.5  
14.8  
SINAD  
14.4  
SINAD  
15.0  
14.0  
ENOB  
13.6  
13.2  
12.8  
12.4  
12.0  
ENOB  
14.5  
14.0  
125  
–55  
–35  
–15  
5
25  
45  
65  
C)  
85  
105  
1
10  
100  
1000  
TEMPERATURE (  
°
FREQUENCY (kHz)  
Figure 12. SNR, SINAD and ENOB vs. Frequency  
Figure 15. SNR, SINAD, and ENOB vs. Temperature  
–70  
–75  
120  
–80  
–85  
110  
105  
100  
95  
SFDR  
110  
100  
90  
80  
70  
60  
50  
40  
30  
20  
SFDR  
–80  
–90  
–85  
–95  
–90  
–100  
–105  
–110  
–115  
–120  
–125  
–130  
90  
THD  
–95  
85  
–100  
–105  
–110  
–115  
–120  
80  
THD  
THIRD HARMONIC  
75  
THIRD  
SECOND HARMONIC  
HARMONIC  
70  
65  
SECOND  
HARMONIC  
60  
125  
1
10  
100  
1000  
–55  
–35  
–15  
5
25  
45  
65  
C)  
85  
105  
FREQUENCY (kHz)  
TEMPERATURE (  
°
Figure 13. THD, Harmonics, and SFDR vs. Frequency  
Figure 16. THD, Harmonics, and SFDR vs. Temperature  
Rev. 0 | Page 13 of 32  
 
AD7621  
91.0  
100k  
10k  
1k  
AVDD, WARP/NORMAL  
AVDD, IMPULSE  
SNR  
90.5  
90.0  
SINAD  
100  
10  
OVDD = 3.3V, ALL MODES  
DVDD, ALL MODES  
OVDD, 2.5V, ALL MODES  
PDREF = PDBUF = HIGH  
1
89.5  
–60  
0.1  
10  
–50  
–40  
–30  
–20  
–10  
0
100  
1k  
10k  
100M  
1M  
10M  
INPUT LEVEL (dB)  
SAMPLING RATE (SPS)  
Figure 17. SNR and SINAD vs. Input Level (Referred to Full Scale)  
Figure 19. Operating Current vs. Sample Rate  
16  
14  
12  
10  
8
280  
270  
260  
250  
240  
230  
220  
210  
200  
20  
18  
16  
14  
12  
10  
8
OVDD = 2.5V @ 85°C  
OVDD = 2.5V @ 25°C  
AVDD  
OVDD, 3.3V  
OVDD, 2.5V  
OVDD = 3.3V @ 85°C  
OVDD = 3.3V @ 25°C  
6
4
2
6
DVDD  
105  
0
–55  
4
–35  
–15  
5
25  
45  
65  
C)  
85  
125  
0
50  
100  
C
150  
200  
TEMPERATURE (  
°
(pF)  
L
Figure 18. Power-Down Operating Currents vs. Temperature  
Figure 20. Typical Delay vs. Load Capacitance CL  
Rev. 0 | Page 14 of 32  
AD7621  
THEORY OF OPERATION  
IN+  
AGND  
LSB  
SWITCHES  
CONTROL  
SW+  
MSB  
32,768C 16,384C  
4C  
4C  
2C  
2C  
C
C
C
C
BUSY  
REF  
CONTROL  
LOGIC  
COMP  
REFGND  
OUTPUT  
CODE  
32,768C 16,384C  
MSB  
SW–  
LSB  
CNVST  
AGND  
IN–  
Figure 21. ADC Simplified Schematic  
phase is applied to the comparator inputs, causing the  
comparator to become unbalanced. By switching each element  
of the capacitor array between REFGND and REF, the  
comparator input varies by binary weighted voltage steps  
(VREF/2, VREF/4 through VREF/65536). The control logic toggles  
these switches, starting with the MSB first, in order to bring the  
comparator back into a balanced condition. After the  
completion of this process, the control logic generates the ADC  
output code and brings BUSY output low.  
CIRCUIT INFORMATION  
The AD7621 is a very fast, low power, single-supply, precise,  
16-bit analog-to-digital converter (ADC) using successive  
approximation architecture. The AD7621 features different  
modes to optimize performances according to the applications.  
In warp mode, the AD7621 is capable of converting 3,000,000  
samples per second (3 MSPS).  
The AD7621 provides the user with an on-chip track-and-hold,  
successive approximation ADC that does not exhibit any  
pipeline or latency, making it ideal for multiple multiplexed  
channel applications.  
MODES OF OPERATION  
The AD7621 features four modes of operation: wideband warp,  
warp, normal, and impulse. Each of these modes is more  
suitable to specific applications.  
The AD7621 can be operated from a single 2.5 V supply and  
be interfaced to either 5 V, 3.3 V, or 2.5 V digital logic. It  
is housed in 48-lead LQFP or tiny LFCSP packages that  
combine space savings with flexibility, allowing the AD7621  
to be configured as either a serial or parallel interface. The  
AD7621 is pin-to-pin-compatible with, and a speed upgrade  
of, the AD7677.  
Wideband warp (WARP = high, IMPULSE = high) and warp  
(WARP = high, IMPULSE = low) modes allow the fastest  
conversion rate up to 3 MSPS. However, in these modes, the full  
specified accuracy is guaranteed only when the time between  
conversions does not exceed 1 ms. If the time between two  
consecutive conversions is longer than 1 ms (after power up),  
the first conversion result should be ignored. These modes  
make the AD7621 ideal for applications where both high  
accuracy and fast sample rate are required. Wideband warp  
mode offers slightly improved linearity and THD over warp  
mode.  
CONVERTER OPERATION  
The AD7621 is a successive approximation analog-to-digital  
converter (ADC) based on a charge redistribution DAC. Figure 21  
shows the simplified schematic of the ADC. The capacitive  
DAC consists of two identical arrays of 16 binary weighted  
capacitors which are connected to the two comparator inputs.  
Normal mode (WARP = low, IMPULSE = low) is the fastest  
mode (2 MSPS) without any limitation on time between  
conversions. This mode makes the AD7621 ideal for  
asynchronous applications such as data acquisition systems,  
where both high accuracy and fast sample rate are required.  
During the acquisition phase, terminals of the array tied to the  
comparator’s input are connected to AGND via SW+ and SW−.  
All independent switches are connected to the analog inputs.  
Thus, the capacitor arrays are used as sampling capacitors and  
acquire the analog signal on IN+ and IN− inputs. A conversion  
phase is initiated once the acquisition phase is complete and the  
Impulse mode (WARP = low, IMPULSE = high), the lowest  
power dissipation mode, allows power saving between  
conversions. The maximum throughput in this mode is  
1.25 MSPS. In this mode, the ADC powers down circuits after  
conversion making the AD7621 ideal for battery-powered  
applications.  
CNVST  
input goes low. When the conversion phase begins,  
SW+ and SW− are opened first. The two capacitor arrays are  
then disconnected from the inputs and connected to the  
REFGND input. Therefore, the differential voltage between the  
inputs (IN+ and IN−) captured at the end of the acquisition  
Rev. 0 | Page 15 of 32  
 
 
 
AD7621  
TRANSFER FUNCTIONS  
Table 7. Output Codes and Ideal Input Voltages  
Digital Output Code  
2C  
Using the OB/ digital input, the AD7621 offers two output  
codings: straight binary and twos complement. The LSB size  
with VREF = 2.048 V is 2 × VREF/65536, which is 62.5 μV. Refer to  
Figure 22 and Table 7 for the ideal transfer characteristic.  
Analog Input  
VREF = 2.048 V Binary  
Straight  
Twos  
Complement  
Description  
FSR −1 LSB  
FSR − 2 LSB  
Midscale + 1 LSB  
Midscale  
+2.047938 V  
+2.047875 V  
+62.5 μV  
0 V  
0xFFFF1  
0xFFFE  
0x8001  
0x8000  
0x7FFF  
0x0001  
0x00002  
0x7FFF1  
0x7FFE  
0x0001  
0x0000  
0xFFFF  
0x8001  
0x80002  
111...111  
111...110  
111...101  
Midscale − 1 LSB  
−FSR + 1 LSB  
−FSR  
−62.5 μV  
−2.047938 V  
−2.048 V  
1 This is also the code for overrange analog input (VIN+ − VIN− above  
VREF − VREFGND).  
2 This is also the code for underrange analog input (VIN+ − VIN− below  
−VREF + VREFGND).  
000...010  
000...001  
000...000  
–FSR+1 LSB  
+FSR–1 LSB  
+FSR–1.5 LSB  
ANALOG INPUT  
–FSR  
–FSR+0.5 LSB  
Figure 22. ADC Ideal Transfer Function  
DIGITAL  
SUPPLY (2.5V)  
NOTE 5  
10Ω  
DIGITAL  
INTERFACE  
SUPPLY  
ANALOG  
SUPPLY (2.5V)  
(2.5V OR 3.3V)  
100nF  
10μF  
10μF  
100nF  
100nF  
10μF  
AVDD AGND DGND  
REF  
DVDD  
OVDD  
OGND  
SERIAL  
PORT  
NOTE 3  
SCLK  
C
10μF  
REF  
REFBUFIN  
REFGND  
100nF  
SDOUT  
NOTE 4  
BUSY  
NOTE 7  
NOTE 2  
MICROCONVERTER/  
MICROPROCESSOR/  
DSP  
50Ω  
10Ω  
D
CNVST  
U1  
IN+  
50pF  
ANALOG  
INPUT +  
AD7621  
OB/2C  
C
1nF  
C
SER/PAR  
NOTE 1  
OVDD  
WARP  
IMPULSE  
NOTE 2  
U2  
CS  
RD  
10Ω  
CLOCK  
IN–  
ANALOG  
INPUT –  
NOTE 3  
C
C
1nF  
NOTE 1  
50pF  
PDREF PDBUF  
PD  
RESET  
10kΩ  
NOTE 6  
1. SEE ANALOG INPUT SECTION.  
2. THE AD8021 IS RECOMMENDED. SEE DRIVER AMPLIFIER CHOICE SECTION.  
3. THE CONFIGURATION SHOWN IS USING THE INTERNAL REFERENCE. SEE VOLTAGE REFERENCE INPUT SECTION.  
4. A 10μF CERAMIC CAPACITOR (X5R, 1206 SIZE) IS RECOMMENDED (e.g., PANASONIC ECJ3YB0J106M).  
SEE VOLTAGE REFERENCE INPUT SECTION.  
5. OPTION, SEE POWER SUPPLY SECTION.  
6. OPTION, SEE POWER UP SECTION.  
7. OPTIONAL LOW JITTER CNVST, SEE CONVERSION CONTROL SECTION.  
Figure 23. Typical Connection Diagram  
Rev. 0 | Page 16 of 32  
 
 
 
 
 
 
 
 
AD7621  
comprised of some serial resistors and the on resistance of the  
switches. CIN is typically 12 pF and is mainly the ADC sampling  
capacitor. During the conversion phase, when the switches are  
opened, the input impedance is limited to CPIN. RIN and CIN  
make a one-pole, low-pass filter that has a typical −3 dB cutoff  
frequency of 50 MHz, thereby reducing an undesirable aliasing  
effect while limiting noise from the inputs.  
TYPICAL CONNECTION DIAGRAM  
Figure 23 shows a typical connection diagram for the AD7621.  
Different circuitry from that shown in this diagram are optional  
and are discussed below.  
ANALOG INPUTS  
Figure 24 shows an equivalent circuit of the input structure of  
the AD7621.  
Since the input impedance of the AD7621 is very high, the  
AD7621 can be directly driven by a low impedance source  
without gain error. To further improve the noise filtering  
achieved by the AD7621 analog input circuit, an external, one-  
pole RC filter between the amplifiers outputs and the ADC  
analog inputs can be used, as shown in Figure 23. However,  
large source impedances significantly affect the ac performance,  
especially total harmonic distortion (THD). The maximum  
source impedance depends on the amount of THD that can be  
tolerated. The THD degrades as a function of the source  
impedance and the maximum input frequency, as shown in  
Figure 26.  
The two diodes, D1 and D2, provide ESD protection for the  
analog inputs, IN+ and IN−. Care must be taken to ensure that  
the analog input signal never exceeds the supply rails by more  
than 0.3 V as this causes the diodes to become forward-biased  
and start conducting current. These diodes can handle a  
forward-biased current of 100 mA maximum. For instance,  
these conditions could eventually occur when the input buffers  
U1 or U2 supplies are different from AVDD. In such a case, an  
input buffer with a short-circuit current limitation can be used  
to protect the part.  
AVDD  
–60  
PDBUF = PDREF = LOW  
–65  
D
1
2
C
IN  
R
IN  
IN+ OR IN–  
AGND  
–70  
C
D
PIN  
R
= 500Ω  
S
–75  
–80  
Figure 24. AD7621 Simplified Analog Input.  
–85  
R
= 100Ω  
S
The analog input of AD7621 is a true differential structure. By  
using this differential input, small signals common to both  
inputs are rejected, as shown in Figure 25, representing the  
typical CMRR over frequency with internal and external  
references.  
–90  
R
= 50Ω  
S
–95  
–100  
–105  
R
= 10Ω  
S
1
10  
100  
1k  
75  
70  
65  
INPUT FREQUENCY (kHz)  
Figure 26. THD vs. Analog Input Frequency and Source Resistance  
DRIVER AMPLIFIER CHOICE  
Although the AD7621 is easy to drive, the driver amplifier  
needs to meet the following requirements:  
EXT REF  
60  
Together, the driver amplifier and the AD7621 analog  
input circuit must be able to settle for a full-scale step of  
the capacitor array at a 16-bit level (0.0015%). In the  
amplifier data sheet, settling at 0.1% to 0.01% is more  
commonly specified. This could differ significantly from  
the settling time at a 16-bit level and should be verified  
prior to driver selection. The AD8021 op amp, which  
combines ultralow noise and high gain bandwidth, meets  
this settling time requirement even when used with gains  
up to 13.  
INT REF  
55  
50  
45  
1
10  
100  
1k  
10k  
FREQUENCY (kHz)  
Figure 25. Analog Input CMRR vs. Frequency  
During the acquisition phase for ac signals, the impedance of  
the analog inputs, IN+ and IN−, can be modeled as a parallel  
combination of Capacitor CPIN and the network formed by the  
series connection of RIN and CIN. CPIN is primarily the pin  
capacitance. RIN is typically 350 Ω and is a lumped component  
The noise generated by the driver amplifier needs to be  
kept as low as possible in order to preserve the SNR and  
transition noise performance of the AD7621. The noise  
Rev. 0 | Page 17 of 32  
 
 
 
 
 
 
 
AD7621  
coming from the driver is filtered by the AD7621 analog  
input circuit one-pole, low-pass filter made by RIN and CIN  
or by the external filter, if one is used. The SNR  
degradation due to the amplifier is  
U1  
ANALOG INPUT  
(UNIPOLAR 0V TO 2.048V)  
AD8021  
10pF  
590Ω  
590Ω  
10Ω  
1nF  
IN+  
53  
SNRLOSS = 20log  
2
AD7621  
2809 + πf3dB  
(
NeN  
)
10Ω  
1nF  
U2  
IN–  
1kΩ  
REF  
AD8021  
10pF  
where:  
1kΩ  
100nF  
f–3dB is the input bandwidth of the AD7621 (50 MHz) or  
the cutoff frequency of the input filter (16 MHz), if  
one is used.  
is the noise factor of the amplifier (+1 in buffer  
configuration).  
eN is the equivalent input voltage noise density of the op  
10μF  
Figure 27. Single-Ended-to-Differential Driver Circuit  
(Internal Reference Buffer Used)  
N
VOLTAGE REFERENCE INPUT  
The AD7621 allows the choice of either a very low temperature  
drift internal voltage reference or an external reference.  
amp, in nV/√Hz.  
For instance, a driver with an equivalent input noise  
density of 2.1 nV/√Hz, like the AD8021 with a noise gain  
of +1 when configured as a buffer, degrades the SNR by  
only 0.33 dB when using the RC filter in Figure 23, and by  
1 dB without.  
Unlike many ADCs with internal references, the internal  
reference of the AD7621 provides excellent performance and  
can be used in almost all applications.  
Internal Reference  
(PDBUF = Low, PDREF = Low)  
The driver needs to have a THD performance suitable to  
that of the AD7621. Figure 13 gives the THD vs. frequency  
that the driver should exceed.  
To use the internal reference, the PDREF and PDBUF inputs  
must be low. This produces a 1.2 V band gap output on  
REFBUFIN which, amplified by the internal buffer, results in a  
2.048 V reference on the REF pin.  
The AD8021 meets these requirements and is appropriate for  
almost all applications. The AD8021 needs a 10 pF external  
compensation capacitor that should have good linearity as an  
NPO ceramic or mica type. Moreover, the use of a noninverting  
+1 gain arrangement is recommended and helps to obtain the  
best signal-to-noise ratio.  
The internal reference is temperature-compensated to 2.048 V  
10 mV. The reference is trimmed to provide a typical drift of  
7 ppm/°C. This typical drift characteristic is shown in Figure 7.  
The output resistance of the REFBUFIN is 6.33 kΩ (minimum)  
when the internal reference is enabled. It is necessary to  
decouple this with a ceramic capacitor greater than 100 nF.  
Thus, the capacitor provides an RC filter for noise reduction.  
The AD8022 can also be used when a dual version is needed  
and a gain of 1 is present. The AD829 is an alternative in  
applications where high frequency (above 100 kHz) performance  
is not required. In applications with a gain of 1, an 82 pF  
compensation capacitor is required. The AD8610 is an option  
when low bias current is needed in low frequency applications.  
Since the output impedance of REFBUFIN is typically 6.33 kΩ,  
relative humidity (among other industrial contaminates) can  
directly affect the drift characteristics of the reference. Typically,  
a guard ring is used to reduce the effects of drift under such  
circumstances. However, since the AD7621 has a fine lead pitch,  
guarding this node is not practical. Therefore, in these  
industrial and other types of applications, it is recommended to  
use a conformal coating such as Dow Corning 1-2577 or  
Humiseal 1B73.  
Single-to-Differential Driver  
For applications using unipolar analog signals, a single-ended-  
to-differential driver, as shown in Figure 27, allows for a  
differential input into the part. This configuration, when  
provided an input signal of 0 to VREF, will produce a differential  
V
REF with midscale at VREF/2. The one-pole filter using R = 10 Ω  
External 1.2 V Reference and Internal Buffer  
(PDREF = High, PBBUF = Low)  
and C = 1 nF provides a corner frequency of 16 MHz.  
To use an external reference with the internal buffer, PDREF  
should be high and PDBUF should be low. This powers down  
the internal reference and allows the 1.2 V reference to be  
applied to REFBUFIN.  
If the application can tolerate more noise, the AD8139  
differential driver can be used.  
Rev. 0 | Page 18 of 32  
 
 
 
 
 
AD7621  
External Reference (PDBUF = High, PRBUF = High)  
To use an external reference directly on the REF pin, PDREF  
and PDBUF should both be high.  
Temperature Sensor  
The TEMP pin measures the temperature of the AD7621. To  
improve the calibration accuracy over the temperature range,  
the output of the TEMP pin is applied to one of the inputs of the  
analog switch (such as, ADG779), and the ADC itself is used to  
measure its own temperature. This configuration is shown in  
Figure 28.  
For improved drift performance, an external reference, such as  
the AD780 or ADR431, can be used. The advantages of directly  
using the external voltage reference are:  
SNR and dynamic range improvement (about 1.7 dB)  
resulting from the use of a reference voltage very close to  
the supply (2.5 V) instead of a typical 2.048 V reference  
when the internal reference is used. This is calculated by  
TEMP  
ADG779  
TEMPERATURE  
IN+  
ANALOG INPUT  
(UNIPOLAR)  
SENSOR  
AD7621  
C
AD8021  
C
2.048  
2.50  
SNR = 20log  
Figure 28. Use of the Temperature Sensor  
Power savings when the internal reference is powered  
down (PBREF = PDBUF = high).  
POWER SUPPLY  
The AD7621 uses three sets of power supply pins: an analog  
2.5 V supply AVDD, a digital 2.5 V core supply DVDD, and a  
digital input/output interface supply OVDD. The OVDD supply  
allows direct interface with any logic working between 2.3 V  
and 5.25 V. To reduce the number of supplies needed, the digital  
core (DVDD) can be supplied through a simple RC filter from  
the analog supply as shown in Figure 23.  
PDREF and PDBUF power down the internal reference and the  
internal reference buffer, respectively.  
Reference Decoupling  
Whether using an internal or external reference, the AD7621  
voltage reference input (REF) has a dynamic input impedance;  
therefore, it should be driven by a low impedance source with  
efficient decoupling between the REF and REFGND inputs.  
This decoupling depends on the choice of the voltage reference,  
but usually consists of a low ESR capacitor connected to REF  
and REFGND with minimum parasitic inductance. A 10 μF  
(X5R, 1206 size) ceramic chip capacitor (or 47 μF tantalum  
capacitor) is appropriate when using either the internal  
reference or one of these recommended reference voltages:  
Power Sequencing  
The AD7621 is independent of power supply sequencing once  
OVDD does not exceed DVDD by more than 0.3 V until  
DVDD = 2.3 V during any time; for instance, at power-up or  
power-down (see the Absolute Maximum Ratings section).  
Additionally, it is very insensitive to power supply variations  
over a wide frequency range as shown in Figure 29.  
75  
70  
65  
The low noise, low temperature drift ADR431 and AD780  
The low power ADR291  
The low cost AD1582  
The placement of the reference decoupling is also important to  
the performance of the AD7621. The decoupling capacitor  
should be mounted on the same side as the ADC right at the  
REF pin with a thick PCB trace. The REFGND should also  
connect to the reference decoupling capacitor with the shortest  
distance.  
EXT REF  
60  
INT REF  
55  
50  
45  
For applications that use multiple AD7621 devices, it is more  
effective to use the internal reference buffer in order to buffer  
the reference voltage.  
1
10  
100  
1k  
10k  
FREQUENCY (kHz)  
Figure 29. PSRR vs. Frequency  
The voltage reference temperature coefficient (TC) directly  
impacts full scale; therefore, in applications where full-scale  
accuracy matters, care must be taken with the TC. For instance,  
a 15 ppm/°C TC of the reference changes full-scale by 1 LSB/°C.  
Rev. 0 | Page 19 of 32  
 
 
 
 
AD7621  
Power-Up  
CONVERSION CONTROL  
At power-up, or returning to operational mode from the power-  
down mode (PD = high), the AD7621 engages an initialization  
process. During this time, the first 128 conversions should be  
ignored or the RESET input could be pulsed to engage a faster  
initialization process. Refer to the Digital Interface section for  
RESET and timing details.  
CNVST  
The AD7621 is controlled by the  
input. A falling edge  
CNVST  
on  
is all that is necessary to initiate a conversion.  
Detailed timing diagrams of the conversion process are shown  
in Figure 31. Once initiated, it cannot be restarted or aborted,  
even by the power-down input, PD, until the conversion is  
CNVST  
CS  
complete. The  
RD  
signal operates independently of  
and  
signals.  
A simple power-on reset circuit, as shown in Figure 23, can be  
used to minimize the digital interface. As OVDD powers up, the  
capacitor is shorted and brings RESET high; it is then charged  
returning RESET to low. However, this circuit only works when  
powering up the AD7621 because the power down mode (PD =  
high) does not power down any of the supplies. As a result,  
RESET is low.  
t2  
t1  
t1  
CNVST  
BUSY  
t4  
POWER DISSIPATION VS. THROUGHPUT  
t3  
t5  
t6  
In impulse mode, the AD7621 automatically reduces its power  
consumption at the end of each conversion phase. During the  
acquisition phase, the operating currents are very low which  
allows a significant power saving when the conversion rate is  
reduced (see Figure 30). This feature makes the AD7621 ideal  
for very low power, battery-operated applications.  
MODE ACQUIRE  
CONVERT  
t7  
ACQUIRE  
t8  
CONVERT  
Figure 31. Basic Conversion Timing  
CNVST  
For optimal performance, the rising edge of  
should not  
CNVST  
occur after the maximum  
of conversion.  
low time, t1, or until the end  
It should be noted that the digital interface remains active even  
during the acquisition phase. To reduce the operating digital  
supply currents even further, drive the digital inputs close to the  
power rails (that is, OVDD and OGND).  
CNVST  
Although  
is a digital signal, it should be designed with  
special care with fast, clean edges, and levels with minimum  
overshoot, undershoot, or ringing.  
100k  
WARP MODE POWER  
CNVST  
The  
trace should be shielded with ground and a low  
value (such as 50 Ω) serial resistor termination should be added  
close to the output of the component that drives this line. Also,  
a 60 pF capacitor is recommended to further reduce the effects  
of overshoot and undershoot as shown in Figure 23.  
10k  
IMPULSE MODE POWER  
1k  
CNVST  
For applications where SNR is critical, the  
have very low jitter. This can be achieved by using a dedicated  
CNVST CNVST  
with a  
signal should  
oscillator for  
generation, or by clocking  
high frequency, low jitter clock, as shown in Figure 23.  
PDREF = PDBUF = HIGH  
100  
100  
1k  
10k  
100k  
1M  
10M  
SAMPLING RATE (SPS)  
Figure 30. Power Dissipation vs. Sample Rate  
Rev. 0 | Page 20 of 32  
 
 
 
 
 
AD7621  
INTERFACES  
DIGITAL INTERFACE  
PARALLEL INTERFACE  
The AD7621 has a versatile digital interface that can be set up  
as either a serial or parallel interface with the host system. The  
serial interface is multiplexed on the parallel data bus. The  
AD7621 digital interface also accommodates 2.5 V, 3.3 V, or 5 V  
logic with either OVDD at 2.5 V or 3.3 V. OVDD defines the  
logic high output voltage. In most applications, the OVDD  
supply pin of the AD7621 is connected to the host system  
interface 2.5 V or 3.3 V digital supply. Finally, by using the  
The AD7621 is configured to use the parallel interface when  
PAR  
SER/  
is held low.  
Master Parallel Interface  
Data can be continuously read by tying  
CS  
RD  
low thus  
and  
requiring minimal microprocessor connections. However, in  
this mode the data bus is always driven and cannot be used in  
shared bus applications (unless the device is held in RESET).  
Figure 33 details the timing for this mode.  
2C  
OB/ input pin, both twos complement or straight binary  
CS = RD = 0  
coding can be used.  
t1  
CNVST  
CS  
RD  
, control the interface. When at least  
The two signals,  
one of these signals is high, the interface outputs are in high  
CS  
and  
t10  
impedance. Usually,  
multicircuit applications and is held low in a single AD7621  
RD  
allows the selection of each AD7621 in  
BUSY  
t4  
t3  
t11  
design.  
is generally used to enable the conversion result on  
DATA  
BUS  
the data bus.  
PREVIOUS CONVERSION DATA  
NEW DATA  
Figure 33. Master Parallel Data Timing for Reading (Continuous Read)  
RESET  
The RESET input is used to reset the AD7621 and generate a  
fast initialization. A rising edge on RESET aborts the current  
conversion (if any) and tristates the data bus. The falling edge of  
RESET clears the data bus and engages the initialization process  
indicated by pulsing BUSY high. Conversions can take place  
after the falling edge of BUSY. Refer to Figure 32 for the RESET  
timing details.  
Slave Parallel Interface  
In slave parallel reading mode, the data can be read either after  
each conversion, which is during the next acquisition phase, or  
during the following conversion, as shown in Figure 34 and  
Figure 35, respectively. When the data is read during the  
conversion, it is recommended that it is read-only during the  
first half of the conversion phase. This avoids any potential  
feedthrough between voltage transients on the digital interface  
and the most critical analog conversion circuitry.  
t9  
RESET  
CNVST  
DATA  
BUSY  
CS  
RD  
t38  
t39  
t8  
BUSY  
Figure 32. RESET Timing  
DATA  
BUS  
CURRENT  
CONVERSION  
t12  
t13  
Figure 34. Slave Parallel Data Timing for Reading (Read After Convert)  
Rev. 0 | Page 21 of 32  
 
 
 
 
 
 
 
AD7621  
CS = 0  
SERIAL INTERFACE  
CNVST,  
RD  
t1  
The AD7621 is configured to use the serial interface when  
PAR  
SER/  
is held high. The AD7621 outputs 16 bits of data,  
MSB first, on the SDOUT pin. This data is synchronized with  
the 16 clock pulses provided on the SCLK pin. The output data  
is valid on both the rising and falling edge of the data clock.  
BUSY  
t4  
t3  
MASTER SERIAL INTERFACE  
Internal Clock  
DATA  
BUS  
PREVIOUS  
CONVERSION  
The AD7621 is configured to generate and provide the serial  
t12  
t13  
INT  
data clock SCLK when the EXT/  
pin is held low. The  
Figure 35. Slave Parallel Data Timing for Reading (Read During Convert)  
AD7621 also generates a SYNC signal to indicate to the host  
when the serial data is valid. The serial clock SCLK and the  
SYNC signal can be inverted, if desired. Depending on the read  
during convert input, RDC/SDIN, the data can be read after  
each conversion or during the following conversion. Figure 37  
and Figure 38 show detailed timing diagrams of these two  
modes.  
8-Bit Interface (Master or Slave)  
The BYTESWAP pin allows a glueless interface to an 8-bit bus.  
As shown in Figure 36, when BYTESWAP is low, the LSB byte is  
output on D[7:0] and the MSB is output on D[15:8]. When  
BYTESWAP is high, the LSB and MSB bytes are swapped, and  
the LSB is output on D[15:8] and the MSB is output on D[7:0].  
By connecting BYTESWAP to an address line, the 16-bit data  
can be read in two bytes on either D[15:8] or D[7:0]. This  
interface can be used in both master and slave parallel reading  
modes.  
Usually, because the AD7621 is used with a fast throughput, the  
master read during conversion mode is the most recommended  
serial mode. In this mode, the serial clock and data toggle at  
appropriate instants, minimizing potential feedthrough between  
digital activity and critical conversion decisions. In this mode,  
the SCLK period changes since the LSBs require more time to  
settle and the SCLK is derived from the SAR conversion cycle.  
CS  
RD  
In read after conversion mode, unlike other modes, the BUSY  
signal returns low after the 16 data bits are pulsed out and not at  
the end of the conversion phase resulting in a longer BUSY  
width. As a result, the maximum throughput cannot be  
achieved in this mode.  
BYTESWAP  
HI-Z  
HI-Z  
HI-Z  
HI-Z  
PINS D[15:8]  
PINS D[7:0]  
HIGH BYTE  
LOW BYTE  
t12  
LOW BYTE  
t12  
t13  
HIGH BYTE  
Figure 36. 8-Bit and 16-Bit Parallel Interface  
Rev. 0 | Page 22 of 32  
 
 
 
 
 
AD7621  
RDC/SDIN = 0  
INVSCLK = INVSYNC = 0  
EXT/INT = 0  
CS, RD  
CNVST  
t3  
t28  
BUSY  
SYNC  
t30  
t29  
t25  
t18  
t19  
t14  
t24  
t20  
t21  
2
t26  
1
3
14  
15  
16  
SCLK  
t15  
t27  
SDOUT  
D15  
D14  
t23  
D2  
D1  
D0  
X
t16  
t22  
Figure 37. Master Serial Data Timing for Reading (Read After Convert)  
EXT/INT = 0  
RDC/SDIN = 1  
INVSCLK = INVSYNC = 0  
CS, RD  
CNVST  
t1  
t3  
BUSY  
SYNC  
t17  
t25  
t19  
t20 t21  
t14  
t24  
t26  
t15  
SCLK  
1
2
3
14  
15  
16  
t18  
t27  
SDOUT  
X
D15  
D14  
t23  
D2  
D1  
D0  
t16  
t22  
Figure 38. Master Serial Data Timing for Reading (Read Previous Conversion During Convert)  
Rev. 0 | Page 23 of 32  
 
 
 
AD7621  
CNVST  
common  
signal. It should be noted that the RDC/SDIN  
SLAVE SERIAL INTERFACE  
input is latched on the edge of SCLK opposite to the one used to  
shift out the data on SDOUT. Hence, the MSB of the upstream  
converter just follows the LSB of the downstream converter on  
the next SCLK cycle.  
External Clock  
The AD7621 is configured to accept an externally supplied  
INT  
serial data clock on the SCLK pin when the EXT/  
held high. In this mode, several methods can be used to read  
CS CS  
pin is  
BUSY  
OUT  
the data. The external serial clock is gated by . When  
and  
are both low, the data can be read after each conversion or  
RD  
BUSY  
BUSY  
during the following conversion. The external clock can be  
either a continuous or a discontinuous clock. A discontinuous  
clock can be either normally high or normally low when  
inactive. Figure 40 and Figure 41 show the detailed timing  
diagrams of these methods.  
AD7621  
AD7621  
#2  
#1  
(UPSTREAM)  
(DOWNSTREAM)  
DATA  
OUT  
RDC/SDIN  
SDOUT  
RDC/SDIN  
SDOUT  
CNVST  
CS  
CNVST  
CS  
While the AD7621 is performing a bit decision, it is important  
that voltage transients be avoided on digital input/output pins  
or degradation of the conversion result could occur. This is  
particularly important during the second half of the conversion  
phase because the AD7621 provides error correction circuitry  
that can correct for an improper bit decision made during the  
first half of the conversion phase. For this reason, it is  
recommended that when an external clock is being provided, it  
is a discontinuous clock that is toggling only when BUSY is low  
or, more importantly, that it does not transition during the latter  
half of BUSY high.  
SCLK  
SCLK  
SCLK IN  
CS IN  
CNVST IN  
Figure 39. Two AD7621 Devices in a Daisy-Chain Configuration  
External Clock Data Read During Previous Conversion  
Figure 41 shows the detailed timing diagrams of this method.  
CS  
RD  
During a conversion, while both  
and  
are low, the result  
of the previous conversion can be read. The data is shifted out,  
MSB first, with 16 clock pulses and is valid on both the rising  
and falling edge of the clock. The 16 bits have to be read before  
the current conversion is complete, otherwise; RDERROR is  
pulsed high and can be used to interrupt the host interface to  
prevent incomplete data reading. There is no daisy-chain  
feature in this mode and RDC/SDIN input should always be  
tied either high or low.  
External Discontinuous Clock Data Read After  
Conversion  
Though the maximum throughput cannot be achieved using  
this mode, it is the most recommended of the serial slave  
modes. Figure 40 shows the detailed timing diagrams of this  
method. After a conversion is complete, indicated by BUSY  
returning low, the conversion result can be read while both  
CS  
and  
are low. Data is shifted out MSB first with 16 clock  
RD  
To reduce performance degradation due to digital activity, a fast  
discontinuous clock (at least 30 MHz when impulse mode is  
used, 60 MHz when normal mode is used, or 80 MHz when  
warp mode is used) is recommended to ensure that all the bits  
are read during the first half of the SAR conversion phase.  
pulses and is valid on the rising and falling edges of the clock.  
Among the advantages of this method is the fact that  
conversion performance is not degraded because there are no  
voltage transients on the digital interface during the conversion  
process. Another advantage is the ability to read the data at any  
speed up to 80 MHz, which accommodates both the slow digital  
host interface and the fastest serial reading.  
It is also possible to begin to read data after conversion and  
continue to read the last bits after a new conversion has been  
initiated. However, this is not recommended when using the  
fastest throughput of any mode since the acquisition times are  
only 70 ns, 100 ns, and 50 ns for warp, normal, and impulse  
modes.  
Finally, in this mode only, the AD7621 provides a daisy-chain  
feature using the RDC/SDIN pin for cascading multiple  
converters together. This feature is useful for reducing  
component count and wiring connections when desired, as, for  
instance, in isolated multiconverter applications.  
If the maximum throughput is not used, thus allowing more  
acquisition time, then the use of a slower clock speed can be  
used to read the data.  
An example of the concatenation of two devices is shown in  
Figure 39. Simultaneous sampling is possible by using a  
Rev. 0 | Page 24 of 32  
 
 
AD7621  
RD = 0  
EXT/INT = 1  
INVSCLK = 0  
CS  
BUSY  
SCLK  
t35  
t36 t37  
1
2
3
14  
15  
16  
17  
18  
t31  
t32  
X
D15  
t34  
D14  
D13  
X13  
D1  
X1  
X15  
Y15  
X14  
Y14  
SDOUT  
SDIN  
D0  
X0  
t16  
X15  
X14  
t33  
Figure 40. Slave Serial Data Timing for Reading (Read After Convert)  
RD = 0  
EXT/INT = 1  
INVSCLK = 0  
CS  
CNVST  
BUSY  
t3  
t35  
t36 t37  
SCLK  
1
2
3
14  
15  
16  
t31  
t32  
X
D1  
SDOUT  
D15  
D14  
D13  
D0  
t16  
Figure 41. Slave Serial Data Timing for Reading (Read Previous Conversion During Convert)  
Rev. 0 | Page 25 of 32  
 
 
 
AD7621  
going low) using an interrupt line of the DSP. The serial  
peripheral interface (SPI) on the ADSP-219x is configured for  
master mode (MSTR) = 1, clock polarity bit (CPOL) = 0, clock  
phase bit (CPHA) = 1, and SPI interrupt enable (TIMOD) = 00  
by writing to the SPI control register (SPICLTx). It should be  
noted that to meet all timing requirements, the SPI clock should  
be limited to 17 Mb/s allowing it to read an ADC result in less  
than 1 μs. When a higher sampling rate is desired, use one of  
the parallel interface modes.  
MICROPROCESSOR INTERFACING  
The AD7621 is ideally suited for traditional dc measurement  
applications supporting a microprocessor, and ac signal  
processing applications interfacing to a digital signal processor.  
The AD7621 is designed to interface with a parallel 8-bit or  
16-bit wide interface, or with a general-purpose serial port or  
I/O ports on a microcontroller. A variety of external buffers can  
be used with the AD7621 to prevent digital noise from coupling  
into the ADC. The following section illustrates the use of the  
AD7621 with an ADSP-219x SPI-equipped DSP.  
DVDD  
AD7621*  
ADSP-219x*  
SPI Interface (ADSP-219x)  
SER/PAR  
BUSY  
CS  
PFx  
Figure 42 shows an interface diagram between the AD7621 and  
an SPI-equipped DSP, ADSP-219x. To accommodate the slower  
speed of the DSP, the AD7621 acts as a slave device and data  
must be read after conversion. This mode also allows the daisy-  
chain feature. The convert command could be initiated in  
response to an internal timer interrupt. The reading process can  
be initiated in response to the end-of-conversion signal (BUSY  
EXT/INT  
SPIxSEL (PFx)  
MISOx  
SDOUT  
SCLK  
CNVST  
RD  
SCKx  
PFx OR TFSx  
INVSCLK  
*ADDITIONAL PINS OMITTED FOR CLARITY  
Figure 42. Interfacing the AD7621 to SPI Interface  
Rev. 0 | Page 26 of 32  
 
 
AD7621  
APPLICATION  
LAYOUT  
The DVDD supply of the AD7621 can be either a separate  
supply or come from the analog supply, AVDD, or from the  
digital interface supply, OVDD. When the system digital supply  
is noisy, or fast switching digital signals are present, and no  
separate supply is available, it is recommended to connect the  
DVDD digital supply to the analog supply AVDD through an  
RC filter, and to connect the system supply to the interface  
digital supply OVDD and the remaining digital circuitry. Refer  
to Figure 23 for an example of this configuration. When DVDD  
is powered from the system supply, it is useful to insert a bead  
to further reduce high frequency spikes.  
While the AD7621 has very good immunity to noise on the  
power supplies, exercise care with the grounding layout. To  
facilitate the use of ground planes that can be easily separated,  
design the printed circuit board that houses the AD7621 so that  
the analog and digital sections are separated and confined to  
certain areas of the board. Digital and analog ground planes  
should be joined in only one place, preferably underneath the  
AD7621, or as close as possible to the AD7621. If the AD7621 is  
in a system where multiple devices require analog-to-digital  
ground connections, the connections should still be made at  
one point only, a star ground point, established as close as  
possible to the AD7621.  
The AD7621 has four different ground pins: REFGND, AGND,  
DGND, and OGND. REFGND senses the reference voltage and,  
because it carries pulsed currents, should be a low impedance  
return to the reference. AGND is the ground to which most  
internal ADC analog signals are referenced; it must be  
connected with the least resistance to the analog ground plane.  
DGND must be tied to the analog or digital ground plane  
depending on the configuration. OGND is connected to the  
digital system ground.  
To prevent coupling noise onto the die, avoid radiating noise,  
and to reduce feedthrough:  
Do not run digital lines under the device.  
Do run the analog ground plane under the AD7621.  
CNVST  
Do shield fast switching signals, like  
or clocks, with  
digital ground to avoid radiating noise to other sections of  
the board, and never run them near analog signal paths.  
The layout of the decoupling of the reference voltage is  
important. To minimize parasitic inductances, place the  
decoupling capacitor close to the ADC and connect it with  
short, thick traces.  
Avoid crossover of digital and analog signals.  
Run traces on different but close layers of the board, at right  
angles to each other, to reduce the effect of feedthrough  
through the board.  
EVALUATING THE AD7621 PERFORMANCE  
A recommended layout for the AD7621 is outlined in the  
documentation of the EVAL-AD7621CB evaluation board for  
the AD7621. The evaluation board package includes a fully  
assembled and tested evaluation board, documentation, and  
software for controlling the board from a PC via the EVAL-  
CONTROLBRD3.  
The power supply lines to the AD7621 should use as large a  
trace as possible to provide low impedance paths and reduce the  
effect of glitches on the power supply lines. Good decoupling is  
also important to lower the impedance of the supplies presented  
to the AD7621, and to reduce the magnitude of the supply  
spikes. Decoupling ceramic capacitors, typically 100 nF, should  
be placed on each of the power supplies pins, AVDD, DVDD,  
and OVDD. The capacitors should be placed close to, and  
ideally right up against, these pins and their corresponding  
ground pins. Additionally, low ESR 10 μF capacitors should be  
located in the vicinity of the ADC to further reduce low  
frequency ripple.  
Rev. 0 | Page 27 of 32  
 
AD7621  
OUTLINE DIMENSIONS  
0.75  
0.60  
0.45  
9.00 BSC  
SQ  
1.60  
MAX  
37  
48  
36  
1
PIN 1  
7.00  
BSC SQ  
TOP VIEW  
(PINS DOWN)  
1.45  
1.40  
1.35  
0.20  
0.09  
7°  
3.5°  
0°  
25  
12  
0.15  
0.05  
13  
24  
SEATING  
PLANE  
0.08 MAX  
COPLANARITY  
0.27  
0.22  
0.17  
VIEW A  
0.50  
BSC  
LEAD PITCH  
VIEW A  
ROTATED 90° CCW  
COMPLIANT TO JEDEC STANDARDS MS-026BBC  
Figure 43. 48-Lead Low Profile Quad Flatpack (LQFP)  
[ST-48]  
Dimensions shown in millimeters  
0.30  
0.23  
0.18  
7.00  
BSC SQ  
0.60 MAX  
0.60 MAX  
PIN 1  
INDICATOR  
37  
36  
48  
1
PIN 1  
INDICATOR  
EXPOSED  
5.25  
5.10 SQ  
4.95  
TOP  
VIEW  
6.75  
BSC SQ  
(BOTTOM VIEW)  
0.50  
0.40  
0.30  
25  
24  
12  
13  
0.25 MIN  
5.50  
REF  
PADDLE CONNECTED TO GND.  
THIS CONNECTION IS NOT  
REQUIRED TO MEET THE  
0.80 MAX  
0.65 TYP  
1.00  
0.85  
0.80  
12° MAX  
0.05 MAX  
0.02 NOM  
ELECTRICAL PERFORMANCES  
COPLANARITY  
0.08  
0.50 BSC  
0.20 REF  
SEATING  
PLANE  
COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2  
Figure 44. 48-Lead Lead Frame Chip Scale Package (LFCSP_VQ)  
7 mm × 7 mm Body, Very Thin Quad  
[CP-48-1]  
Dimensions shown in millimeters  
Rev. 0 | Page 28 of 32  
 
AD7621  
ORDERING GUIDE  
Model  
AD7621ACP  
Temperature Range  
−40°C to +85°C  
−40°C to +85°C  
−40°C to +85°C  
−40°C to +85°C  
−40°C to +85°C  
−40°C to +85°C  
−40°C to +85°C  
−40°C to +85°C  
Package Description  
Package Option  
CP-48-1  
CP-48-1  
CP-48-1  
CP-48-1  
ST-48  
ST-48  
ST-48  
ST-48  
48-Lead Lead Frame Chip Scale (LFCSP_VQ)  
48-Lead Lead Frame Chip Scale (LFCSP_VQ)  
48-Lead Lead Frame Chip Scale (LFCSP_VQ)  
48-Lead Lead Frame Chip Scale (LFCSP_VQ)  
48-Lead Low Profile Quad Flatpack (LQFP)  
48-Lead Low Profile Quad Flatpack (LQFP)  
48-Lead Low Profile Quad Flatpack (LQFP)  
48-Lead Low Profile Quad Flatpack (LQFP)  
Evaluation Board  
AD7621ACPRL  
AD7621ACPZ1  
AD7621ACPZRL1  
AD7621AST  
AD7621ASTRL  
AD7621ASTZ1  
AD7621ASTZRL1  
EVAL-AD7621CB2  
EVAL-CONTROLBRD33  
Controller Board  
1 Z = Pb-free part.  
2 This board can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL BRD3 for evaluation/demonstration purposes.  
3 This board allows a PC to control and communicate with all Analog Devices, Inc. evaluation boards ending in the CB designators.  
Rev. 0 | Page 29 of 32  
 
 
 
AD7621  
NOTES  
Rev. 0 | Page 30 of 32  
AD7621  
NOTES  
Rev. 0 | Page 31 of 32  
AD7621  
NOTES  
©2005 Analog Devices, Inc. All rights reserved. Trademarks and  
registered trademarks are the property of their respective owners.  
D04565–0–5/05(0)  
Rev. 0 | Page 32 of 32  

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