EVAL-ADCMP580BCPZ [ADI]
Ultrafast SiGe Voltage Comparators; 超快的SiGe电压比较器
| 型号： | EVAL-ADCMP580BCPZ |
| 厂家： | 
ADI |
| 描述： | Ultrafast SiGe Voltage Comparators |
| 文件： | 总16页 (文件大小：437K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Ultrafast SiGe
Voltage Comparators
ADCMP580/ADCMP581/ADCMP582
FEATURES
FUNCTIONAL BLOCK DIAGRAM
V
CCI
180 ps propagation delay
25 ps overdrive and slew rate dispersion
8 GHz equivalent input rise time bandwidth
100 ps minimum pulse width
37 ps typical output rise/fall
10 ps deterministic jitter (DJ)
V
TERMINATION
TP
V
CCO
V
NONINVERTING
INPUT
P
Q OUTPUT
Q OUTPUT
ADCMP580/
ADCMP581/
ADCMP582
CML/ECL/
PECL
200 fs random jitter (RJ)
V
INVERTING
INPUT
N
−2 V to +3 V input range with +5 V/−5 V supplies
On-chip terminations at both input pins
Resistor-programmable hysteresis
Differential latch control
V
EE
V
TERMINATION
HYS
TN
LE INPUT
LE INPUT
Power supply rejection > 70 dB
V
EE
Figure 1.
APPLICATIONS
Automatic test equipment (ATE)
High speed instrumentation
Pulse spectroscopy
Medical imaging and diagnostics
High speed line receivers
Threshold detection
Peak and zero-crossing detectors
High speed trigger circuitry
Clock and data signal restoration
GENERAL DESCRIPTION
The ADCMP580/ADCMP581/ADCMP582 are ultrafast voltage
comparators fabricated on the Analog Devices, Inc. proprietary
XFCB3 Silicon Germanium (SiGe) bipolar process. The
ADCMP580 features CML output drivers, the ADCMP581
features reduced swing ECL (negative ECL) output drivers, and
the ADCMP582 features reduced swing PECL (positive ECL)
output drivers.
The CML output stage is designed to directly drive 400 mꢀ into
50 Ω transmission lines terminated to ground. The NECL output
stages are designed to directly drive 400 mꢀ into 50 Ω terminated
to −2 ꢀ. The PECL output stages are designed to directly drive
400 mꢀ into 50 Ω terminated to ꢀCCO − 2 ꢀ. High speed latch
and programmable hysteresis are also provided. The differential
latch input controls are also 50 Ω terminated to an independent
ꢀ
TT pin to interface to either CML or ECL or to PECL logic.
All three comparators offer 180 ps propagation delay and 100 ps
minimum pulse width for 10 Gbps operation with 200 fs random
jitter (RJ). Overdrive and slew rate dispersion are typically less
than 15 ps.
The ADCMP580/ADCMP581/ADCMP582 are available in a
16-lead LFCSP_ꢀQ.
The 5 ꢀ power supplies enable a wide −2 ꢀ to +3 ꢀ input
range with logic levels referenced to the CML/NECL/PECL
outputs. The inputs have 50 Ω on-chip termination resistors
with the optional capability to be left open (on an individual
pin basis) for applications requiring high impedance input.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2005–2007 Analog Devices, Inc. All rights reserved.
ADCMP580/ADCMP581/ADCMP582
TABLE OF CONTENTS
Features .............................................................................................. 1
Typical Application Circuits ......................................................... 10
Application Information................................................................ 11
Power/Ground Layout and Bypassing..................................... 11
ADCMP58x Family of Output Stages ..................................... 11
Using/Disabling the Latch Feature........................................... 11
Optimizing High Speed Performance ..................................... 12
Comparator Propagation Delay Dispersion............................... 12
Comparator Hysteresis .............................................................. 13
Minimum Input Slew Rate Requirement................................ 13
Outline Dimensions....................................................................... 14
Ordering Guide .......................................................................... 14
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Information ......................................................................... 5
Absolute Maximum Ratings............................................................ 6
Thermal Considerations.............................................................. 6
ESD Caution.................................................................................. 6
Pin Configurations and Function Descriptions ........................... 7
Typical Performance Characteristics ............................................. 8
REVISION HISTORY
8/07—Rev. 0 to Rev. A
Changes to Figure 1.......................................................................... 1
Changes to Table 4............................................................................ 7
Changes to Figure 9.......................................................................... 8
Changes to Figure 21, Figure 22, and Figure 23 ......................... 10
Changes to Using/Disabling the Latch Feature .......................... 11
Changes to Comparator Hysteresis Section and Figure 29....... 13
Changes to Ordering Guide .......................................................... 14
7/05—Revision 0: Initial Version
Rev. A | Page 2 of 16
ADCMP580/ADCMP581/ADCMP582
SPECIFICATIONS
ꢀCCI = 5.0 ꢀ; ꢀEE = −5.0 ꢀ; ꢀCCO = 3.3 ꢀ; TA = 25°C, unless otherwise noted.
Table 1.
Parameter
Symbol
Condition
Min
Typ
Max
Unit
DC INPUT CHARACTERISTICS
Input Voltage Range
Input Differential Range
Input Offset Voltage
VP, VN
−2.0
−2.0
−10.0
+3.0
+2.0
+10.0
V
V
VOS
±±
mV
μV/°C
μA
nA/°C
μA
Ω
kΩ
kΩ
dB
Offset Voltage Temperature Coefficient
Input Bias Current
Input Bias Current Temperature Coefficient
Input Offset Current
ΔVOS/dT
IP, IN
ΔIB/dT
10
15
50
+2
±7 to 53
50
500
±8
Open termination
30.0
±5.0
Input Resistance
Input Resistance, Differential Mode
Input Resistance, Common Mode
Active Gain
Open termination
Open termination
AV
Common-Mode Rejection Ratio
Hysteresis
CMRR
VCM = −2.0 V to +3.0 V
RHYS = ∞
60
1
dB
mV
LATCH ENABLE CHARACTERISTICS
Latch Enable Input Impedance
Latch-to-Output Delay
Latch Minimum Pulse Width
ADCMP580 (CML)
ZIN
Each pin, VTT at ac ground
±7 to 53
175
100
Ω
ps
ps
tPLOH, tPLOL VOD = 200 mV
tPL
VOD = 200 mV
Latch Enable Input Range
Latch Enable Input Differential
Latch Setup Time
−0.8
0.2
0
0.5
V
V
ps
ps
0.±
95
−90
tS
tH
VOD = 200 mV
VOD = 200 mV
Latch Hold Time
ADCMP581 (NECL)
Latch Enable Input Range
Latch Enable Input Differential
Latch Setup Time
−1.8
0.2
+0.8
0.5
V
V
ps
ps
0.±
70
−65
tS
tH
VOD = 200 mV
VOD = 200 mV
Latch Hold Time
ADCMP582 (PECL)
Latch Enable Input Range
Latch Enable Input Differential
Latch Setup Time
VCCO − 1.8
0.2
VCCO − 0.8
0.5
V
V
ps
ps
0.±
30
−25
tS
tH
VOD = 200 mV
VOD = 200 mV
Latch Hold Time
DC OUTPUT CHARACTERISTICS
ADCMP580 (CML)
Output Impedance
ZOUT
VOH
VOL
50
0
−0.±0
395
Ω
V
V
mV
Output Voltage High Level
Output Voltage Low Level
Output Voltage Differential
ADCMP581 (NECL)
50 Ω to GND
50 Ω to GND
50 Ω to GND
−0.10
−0.50
3±0
+0.03
−0.35
±50
Output Voltage High Level
Output Voltage High Level
Output Voltage High Level
Output Voltage Low Level
Output Voltage Low Level
Output Voltage Low Level
Output Voltage Differential
VOH
VOH
VOH
VOL
VOL
VOL
50 Ω to −2 V, TA = 125°C
50 Ω to −2 V, TA = 25°C
50 Ω to −2 V, TA = −55°C
50 Ω to −2 V, TA = 125°C
50 Ω to −2 V, TA = 25°C
50 Ω to −2 V, TA = −55°C
50 Ω to −2.0 V
−0.99
−1.06
−1.11
−1.±3
−1.50
−1.55
3±0
−0.87
−0.9±
−0.99
−1.26
−1.33
−1.38
395
−0.75
−0.82
−0.87
−1.13
−1.20
−1.25
±50
V
V
V
V
V
V
mV
Rev. A | Page 3 of 16
ADCMP580/ADCMP581/ADCMP582
Parameter
Symbol
Condition
Min
Typ
Max
Unit
ADCMP582 (PECL)
VCCO = 3.3 V
Output Voltage High Level
Output Voltage High Level
Output Voltage High Level
Output Voltage Low Level
Output Voltage Low Level
Output Voltage Low Level
Output Voltage Differential
AC PERFORMANCE
VOH
VOH
VOH
VOL
VOL
VOL
50 Ω to VCCO − 2 V, TA = 125°C
50 Ω to VCCO − 2 V, TA = 25°C
50 Ω to VCCO − 2 V, TA = −55°C
50 Ω to VCCO − 2 V, TA = 125°C
50 Ω to VCCO − 2 V, TA = 25°C
50 Ω to VCCO − 2 V, TA = −55°C
50 Ω to VCCO − 2.0 V
VCCO − 0.99 VCCO − 0.87 VCCO − 0.75
VCCO − 1.06 VCCO − 0.9± VCCO − 0.82
VCCO − 1.11 VCCO − 0.99 VCCO − 0.87
VCCO − 1.±3 VCCO − 1.26 VCCO − 1.13
VCCO − 1.50 VCCO − 1.33 VCCO − 1.20
VCCO − 1.55 VCCO − 1.35 VCCO − 1.25
V
V
V
V
V
V
mV
3±0
395
±50
Propagation Delay
Propagation Delay Temperature Coefficient ΔtPD/dT
Propagation Delay Skew—Rising
Transition to Falling Transition
tPD
VOD = 500 mV
180
0.25
10
ps
ps/°C
ps
VOD = 500 mV, 5 V/ns
Overdrive Dispersion
50 mV < VOD < 1.0 V
10 mV < VOD < 200 mV
2 V/ns to 10 V/ns
100 ps to 5 ns
1.0 V/ns, 15 MHz, VCM = 0.0 V
VOD = 0.2 V, −2 V < VCM < 3 V
10
15
15
15
10
5
ps
ps
ps
ps
ps
ps/V
GHz
Slew Rate Dispersion
Pulse Width Dispersion
Duty Cycle Dispersion 5% to 95%
Common-Mode Dispersion
Equivalent Input Bandwidth1
BWEQ
0.0 V to ±00 mV input,
tR = tF = 25 ps, 20/80
8
Toggle Rate
Deterministic Jitter
>50% output swing
12.5
15
Gbps
ps
DJ
DJ
VOD = 500 mV, 5 V/ns,
PRBS31 − 1 NRZ, 5 Gbps
Deterministic Jitter
VOD = 200 mV, 5 V/ns,
25
ps
PRBS31 − 1 NRZ, 10 Gbps
RMS Random Jitter
Minimum Pulse Width
Minimum Pulse Width
Rise/Fall Time
RJ
VOD = 200 mV, 5 V/ns, 1.25 GHz
ΔtPD < 5 ps
ΔtPD < 10 ps
0.2
100
80
ps
ps
ps
ps
PWMIN
PWMIN
tR, tF
20/80
37
POWER SUPPLY
Positive Supply Voltage
Negative Supply Voltage
ADCMP580 (CML)
VCCI
VEE
+±.5
−5.5
+5.0
−5.0
+5.5
−±.5
V
V
Positive Supply Current
Negative Supply Current
Power Dissipation
IVCCI
IVEE
PD
VCCI = 5.0 V, 50 Ω to GND
VEE = −5.0 V, 50 Ω to GND
50 Ω to GND
6
−±0
230
8
−3±
260
mA
mA
mW
−50
ADCMP581 (NECL)
Positive Supply Current
Negative Supply Current
Power Dissipation
IVCCI
IVEE
PD
VCCI = 5.0 V, 50 Ω to −2 V
VEE = −5.0 V, 50 Ω to −2 V
50 Ω to −2 V
6
−25
155
8
−19
200
mA
mA
mW
−35
+2.5
−35
ADCMP582 (PECL)
Logic Supply Voltage
Input Supply Current
Output Supply Current
Negative Supply Current
Power Dissipation
Power Supply Rejection (VCCI
Power Supply Rejection (VEE)
Power Supply Rejection (VCCO
VCCO
IVCCI
IVCCO
IVEE
+3.3
6
±±
−25
310
−75
−60
−75
+5.0
8
55
−19
350
V
VCCI = 5.0 V, 50 Ω to VCCO − 2 V
VCCO = 5.0 V, 50 Ω to VCCO − 2 V
VEE = −5.0 V, 50 Ω to VCCO − 2 V
50 Ω to VCCO − 2 V
VCCI = 5.0 V + 5%
VEE = −5.0 V + 5%
mA
mA
mA
mW
dB
PD
)
PSRVCCI
PSRVEE
PSRVCCO
dB
dB
)
VCCO = 3.3 V + 5% (ADCMP582)
1 Equivalent input bandwidth assumes a simple first-order input response and is calculated with the following formula: BWEQ = 0.22/(trCOMP2 – trIN2), where trIN is the 20/80
transition time of a quasi-Gaussian input edge applied to the comparator input and trCOMP is the effective transition time digitized by the comparator.
Rev. A | Page ± of 16
ADCMP580/ADCMP581/ADCMP582
TIMING INFORMATION
Figure 2 shows the ADCMP580/ADCMP581/ADCMP582 compare and latch timing relationships. Table 2 provides the definitions of the
terms shown in Figure 2.
LATCH ENABLE
50%
LATCH ENABLE
tS
tPL
tH
V
N
DIFFERENTIAL
INPUT VOLTAGE
V
± V
OS
N
V
OD
tPDL
tPLOH
Q OUTPUT
50%
50%
tF
tPDH
Q OUTPUT
tPLOL
tR
Figure 2. Comparator Timing Diagram
Table 2. Timing Descriptions
Symbol
Timing
Description
tPDH
Input-to-Output High Delay
Propagation delay measured from the time the input signal crosses the reference
(± the input offset voltage) to the 50% point of an output low-to-high transition.
tPDL
tPLOH
tPLOL
tH
Input-to-Output Low Delay
Propagation delay measured from the time the input signal crosses the reference
(± the input offset voltage) to the 50% point of an output high-to-low transition.
Propagation delay measured from the 50% point of the latch enable signal low-to-high
transition to the 50% point of an output low-to-high transition.
Propagation delay measured from the 50% point of the latch enable signal low-to-high
transition to the 50% point of an output high-to-low transition.
Minimum time after the negative transition of the latch enable signal that the input
signal must remain unchanged to be acquired and held at the outputs.
Latch Enable-to-Output High Delay
Latch Enable-to-Output Low Delay
Minimum Hold Time
tPL
tS
Minimum Latch Enable Pulse Width
Minimum Setup Time
Minimum time that the latch enable signal must be high to acquire an input signal change.
Minimum time before the negative transition of the latch enable signal that an input
signal change must be present to be acquired and held at the outputs.
tR
tF
Output Rise Time
Output Fall Time
Amount of time required to transition from a low to a high output as measured at the
20% and 80% points.
Amount of time required to transition from a high to a low output as measured at the
20% and 80% points.
VN
VOD
Normal Input Voltage
Voltage Overdrive
Difference between the input voltages VP and VN for output true.
Difference between the input voltages VP and VN for output false.
Rev. A | Page 5 of 16
ADCMP580/ADCMP581/ADCMP582
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rating
SUPPLY VOLTAGES
Positive Supply Voltage (VCCI to GND)
Negative Supply Voltage (VEE to GND)
Logic Supply Voltage (VCCO to GND)
INPUT VOLTAGES
−0.5 V to +6.0 V
–6.0 V to +0.5 V
−0.5 V to +6.0 V
Input Voltage
−3.0 V to +±.0 V
−2 V to +2 V
−2.5 V to +5.5 V
THERMAL CONSIDERATIONS
Differential Input Voltage
Input Voltage, Latch Enable
HYSTERESIS CONTROL PIN
Applied Voltage (HYS to VEE)
Maximum Input/Output Current
OUTPUT CURRENT
The ADCMP580/ADCMP581/ADCMP582 16-lead LFCSP
option has a θJA (junction-to-ambient thermal resistance) of
70°C/W in still air.
−5.5 V to +0.5 V
1 mA
ESD CAUTION
ADCMP580 (CML)
ADCMP581 (NECL)
ADCMP582 (PECL)
−25 mA
−±0 mA
−±0 mA
TEMPERATURE
Operating Temperature Range, Ambient
Operating Temperature, Junction
Storage Temperature Range
−±0°C to +125°C
125°C
−65°C to +150°C
Rev. A | Page 6 of 16
ADCMP580/ADCMP581/ADCMP582
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
PIN 1
INDICATOR
PIN 1
INDICATOR
PIN 1
INDICATOR
12 GND
11 Q
12 V
CCO
V
1
2
3
4
V
1
2
3
4
TP
TP
12 GND
11 Q
V
1
2
3
4
TP
11 Q
10 Q
V
V
P
P
V
V
P
ADCMP581
TOP VIEW
(Not to Scale)
ADCMP582
TOP VIEW
(Not to Scale)
ADCMP580
TOP VIEW
(Not to Scale)
V
10 Q
V
N
N
10 Q
N
V
V
TN
9
GND
9 V
CCO
TN
V
9
GND
TN
Figure 4. ADCMP581 Pin Configuration
Figure 5. ADCMP582 Pin Configuration
Figure 3. ADCMP580 Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
2
VTP
VP
Termination Resistor Return Pin for VP Input.
Noninverting Analog Input.
3
VN
Inverting Analog Input.
±
5, 16
6
VTN
VCCI
LE
Termination Resistor Return Pin for VN Input.
Positive Supply Voltage.
Latch Enable Input Pin, Inverting Side. In compare mode (LE = low), the output tracks changes at the input of
the comparator. In latch mode (LE = high), the output reflects the input state just prior to the comparator being
placed into latch mode. LE must be driven in complement with LE.
7
8
LE
Latch Enable Input Pin, Noninverting Side. In compare mode (LE = high), the output tracks changes at the
input of the comparator. In latch mode (LE = low), the output reflects the input state just prior to the
comparator being placed into latch mode. LE must be driven in complement with LE.
VTT
Termination Return Pin for the LE/LE Input Pins.
For the ADCMP580 (CML output stage), this pin should be connected to the GND ground.
For the ADCMP581 (ECL output stage), this pin should be connected to the –2 V termination potential.
For the ADCMP582 (PECL output stage), this pin should be connected to the VCCO – 2 V termination potential.
Digital Ground Pin/Positive Logic Power Supply Terminal.
For the ADCMP580/ADCMP581, this pin should be connected to the GND pin.
For the ADCMP582, this pin should be connected to the positive logic power VCCO supply.
Inverting Output. Q is logic low if the analog voltage at the noninverting input, VP, is greater than the analog
voltage at the inverting input, VN, provided that the comparator is in compare mode. See the LE/LE descriptions
(Pin 6 to Pin 7) for more information.
9, 12
10
GND/VCCO
Q
Q
11
Noninverting Output. Q is logic high if the analog voltage at the noninverting input, VP, is greater than the
analog voltage at the inverting input, VN, provided that the comparator is in compare mode. See the LE/LE
descriptions (Pin 6 to Pin 7) for more information.
13
1±
VEE
HYS
Negative Power Supply.
Hysteresis Control. Leave this pin disconnected for zero hysteresis. Connect this pin to the VEE supply with a
suitably sized resistor to add the desired amount of hysteresis. Refer to Figure 9 for proper sizing of the HYS
hysteresis control resistor.
15
GND
Analog Ground.
Heat Sink N/C
Paddle
The metallic back surface of the package is not electrically connected to any part of the circuit. It can be left
floating for optimal electrical isolation between the package handle and the substrate of the die. It can also
be soldered to the application board if improved thermal and/or mechanical stability is desired. Exposed metal
at package corners is connected to the heat sink paddle.
Rev. A | Page 7 of 16
ADCMP580/ADCMP581/ADCMP582
TYPICAL PERFORMANCE CHARACTERISTICS
ꢀCCI = 5.0 ꢀ, ꢀEE = −5.0 ꢀ, ꢀCCO = 3.3 ꢀ, TA = 25°C, unless otherwise noted.
12
80
70
60
50
40
30
20
10
0
10
V
COMMON-MODE BIAS SWEEP
IN
8
6
4
2
0
–4
–2
0
2
4
1
10
100
1k
10k
COMMON-MODE (V)
R
HYS
CONTROL RESISTOR (Ω)
Figure 6. Bias Current vs. Common-Mode Voltage
Figure 9. Hysteresis vs. RHYS Control Resistor
–0.8
2.5
2.4
2.3
2.2
2.1
2.0
1.9
V
vs. TEMPERATURE
OH
–0.9
–1.0
–1.1
–1.2
–1.3
–1.4
–1.5
OUTPUT (NECL)
V
vs. TEMPERATURE
OUTPUT (PECL)
OH
V
vs. TEMPERATURE
OUTPUT (NECL)
OL
V
vs. TEMPERATURE
OUTPUT (PECL)
OL
–55
–5
45
TEMPERATURE (°C)
95
145
–55
–5
45
TEMPERATURE (°C)
95
145
Figure 7. ADCMP581 Output Voltage vs. Temperature
Figure 10. ADCMP582 Output Voltage vs. Temperature
80
70
60
50
40
30
20
10
0
8
7
6
5
4
3
2
1
0
+125°C COMMON-MODE OFFSET SWEEP
+25°C COMMON-MODE OFFSET SWEEP
–55°C COMMON-MODE OFFSET SWEEP
0
100
200
300
400
500
600
–2
0
2
4
–IHYST (µA)
COMMON-MODE (V)
Figure 8. Hysteresis vs. −IHYST
Figure 11. A Typical VOS vs. Common-Mode Voltage
Rev. A | Page 8 of 16
ADCMP580/ADCMP581/ADCMP582
5
4
45
43
41
39
37
35
33
31
29
27
25
3
2
1
0
–1
–2
–3
–4
–5
LOT2 CHAR1 RISE
LOT2 CHAR1 FALL
LOT3 CHAR1 RISE
LOT3 CHAR1 FALL
Q
RISE
Q
Q
Q
RISE
FALL
FALL
–2
–1
0
1
2
3
–55
–35
–15
5
25
45
65
85
105
125
V
(V)
TEMPERATURE (°C)
CM
Figure 12. ADCMP580 Propagation Delay Error vs. Common-Mode Voltage
Figure 15. ADCMP581 tR/tF vs. Temperature
M1
M1
M1
M1
5
Figure 16. ADCMP582 Eye Diagram at 2.5 Gbps
Figure 13. ADCMP580 Eye Diagram at 7.5 Gbps
18
16
14
12
10
8
6
OD DISPERSION FALL
4
2
0
OD DISPERSION RISE
0
50
100
150
200
250
OVERDRIVE (mV)
Figure 14. Dispersion vs. Overdrive
Rev. A | Page 9 of 16
ADCMP580/ADCMP581/ADCMP582
TYPICAL APPLICATION CIRCUITS
GND
V
TP
50Ω
50Ω
V
V
P
CML
ADCMP580
V
V
P
Q
Q
N
V
IN
N ADCMP580
V
TN
50Ω
50Ω
1kΩ
V
EE
LATCH
INPUTS
Figure 21. Disabling the Latch Feature on the ADCMP580
Figure 17. Zero-Crossing Detector with CML Outputs
V
TP
V
V
P
Q
Q
V
V
P
P
RSECL
ADCMP581
N ADCMP581
V
N
V
N
V
TN
50Ω
50Ω
50Ω
50Ω
750Ω
V
= –2V
TT
V
V
TT
TT
V
EE
LATCH
INPUTS
Figure 22. Disabling the Latch Feature on the ADCMP581
Figure 18. LVDS to a 50 Ω Back-Terminated (RS) ECL Receiver
V
P
RSPECL
ADCMP582
ADCMP580
V
N
HYS
50Ω
50Ω
50Ω
50Ω
0Ω TO 5kΩ
750Ω
V
V
V
= V
– 2V
CCO
CCO
EE
TT
Figure 19. Adding Hysteresis Using the HYS Control
Figure 23. Disabling the Latch Feature on the ADCMP582
GND
50Ω
50Ω
+
Q
Q
V
IN
ADCMP580
V
–
TH
LATCH
INPUTS
Figure 20. Comparator with −2 to +3 V Input Range
Rev. A | Page 10 of 16
ADCMP580/ADCMP581/ADCMP582
APPLICATION INFORMATION
GND
POWER/GROUND LAYOUT AND BYPASSING
The ADCMP58x family of comparators is designed for very
high speed applications. Consequently, high speed design
techniques must be used to achieve the specified performance.
It is critically important to use low impedance supply planes,
particularly for the negative supply (ꢀEE), the output supply
plane (ꢀCCO), and the ground plane (GND). Individual supply
planes are recommended as part of a multilayer board. Provid-
ing the lowest inductance return path for the switching currents
ensures the best possible performance in the target application.
50Ω
50Ω
Q
Q
16mA
It is also important to adequately bypass the input and output
supplies. A 1 μF electrolytic bypass capacitor should be placed
within several inches of each power supply pin to ground. In
addition, multiple high quality 0.1 μF bypass capacitors should
be placed as close as possible to each of the ꢀEE, ꢀCCI, and ꢀCCO
supply pins and should be connected to the GND plane with
redundant vias. High frequency bypass capacitors should be
carefully selected for minimum inductance and ESR. Parasitic
layout inductance should be strictly avoided to maximize the
effectiveness of the bypass at high frequencies.
V
EE
Figure 24. Simplified Schematic Diagram of the ADCMP580 CML Output Stage
GND/V
CCO
Q
Q
ADCMP58x FAMILY OF OUTPUT STAGES
Specified propagation delay dispersion performance is achieved
by using proper transmission line terminations. The outputs of
the ADCMP580 family comparators are designed to directly
drive 400 mꢀ into 50 Ω cable or microstrip/stripline transmis-
sion lines terminated with 50 Ω referenced to the proper return.
The CML output stage for the ADCMP580 is shown in the
simplified schematic diagram in Figure 24. Each output is
back-terminated with 50 Ω for best transmission line matching.
The outputs of the ADCMP581/ADCMP582 are illustrated in
Figure 25; they should be terminated to −2 ꢀ for ECL outputs of
ADCMP581 and ꢀCCO − 2 ꢀ for PECL outputs of ADCMP582.
As an alternative, Thevenin equivalent termination networks
can also be used. If these high speed signals must be routed
more than a centimeter, either microstrip or stripline techniques
are required to ensure proper transition times and to prevent
excessive output ringing and pulse width-dependent propagation
delay dispersion.
V
EE
Figure 25. Simplified Schematic Diagram of the
ADCMP581/ADCMP582 ECL/PECL Output Stage
USING/DISABLING THE LATCH FEATURE
LE
The latch inputs (LE/ ) are active low for latch mode and are
internally terminated with 50 Ω resistors to the ꢀTT pin. When
using the ADCMP580, ꢀTT should be connected to ground.
When using the ADCMP581, ꢀTT should be connected to −2 ꢀ.
When using the ADCMP582, ꢀTT should be connected externally
to ꢀCCO − 2 ꢀ, preferably with its own low inductance plane.
When using the ADCMP580, the latch function can be disabled
LE
by connecting the
pin to ꢀEE with an external pull-down
resistor and by leaving the LE pin to ground. To prevent excessive
power dissipation, the resistor should be 1 kΩ for the ADCMP580.
When using the ADCMP581 comparators, the latch can be
LE
disabled by connecting the
pin to ꢀEE with an external 750 Ω
resistor and leaving the LE pin connected to −2 ꢀ. The idea is to
create an approximate 0.5 ꢀ offset using the internal resistor as
half of the voltage divider. The ꢀTT pin should be connected as
recommended.
Rev. A | Page 11 of 16
ADCMP580/ADCMP581/ADCMP582
OPTIMIZING HIGH SPEED PERFORMANCE
COMPARATOR PROPAGATION DELAY DISPERSION
As with any high speed comparator, proper design and layout
techniques are essential to obtaining the specified performance.
Stray capacitance, inductance, inductive power, and ground
impedances or other layout issues can severely limit performance
and can cause oscillation. Discontinuities along input and output
transmission lines can also severely limit the specified pulse
width dispersion performance.
The ADCMP58x family of comparators has been specifically
designed to reduce propagation delay dispersion over a wide
input overdrive range of 5 mꢀ to 500 mꢀ. Propagation delay
dispersion is a change in propagation delays that results
from a change in the degree of overdrive or slew rate (how far
or fast the input signal exceeds the switching threshold). The
overall result is a higher degree of timing accuracy.
For applications in a 50 Ω environment, input and output
matching have a significant impact on data-dependent (or
deterministic) jitter (DJ) and pulse width dispersion
performance. The ADCMP58x family of comparators provides
internal 50 Ω termination resistors for both ꢀP and ꢀN inputs.
The return side for each termination is pinned out separately
with the ꢀTP and ꢀTN pins, respectively. If a 50 Ω termination
is desired at one or both of the ꢀP/ꢀN inputs, the ꢀTP and ꢀTN
pins can be connected (or disconnected) to (from) the desired
termination potential as appropriate. The termination potential
should be carefully bypassed using ceramic capacitors as dis-
cussed previously to prevent undesired aberrations on the input
signal due to parasitic inductance in the termination return
path. If a 50 Ω termination is not desired, either one or both
of the ꢀTP/ꢀTN termination pins can be left disconnected. In this
case, the open pins should be left floating with no external pull
downs or bypassing capacitors.
Propagation delay dispersion is a specification that becomes
important in critical timing applications, such as data commu-
nications, automatic test and measurement, instrumentation,
and event-driven applications, such as pulse spectroscopy,
nuclear instrumentation, and medical imaging. Dispersion
is defined as the variation in the overall propagation delay as
the input overdrive conditions are changed (see Figure 26 and
Figure 27). For the ADCMP58x family of comparators, disper-
sion is typically <25 ps, because the overdrive varies from 5 mꢀ
to 500 mꢀ, and the input slew rate varies from 1 ꢀ/ns to 10 ꢀ/ns.
This specification applies for both positive and negative signals
because the ADCMP58x family of comparators has almost
equal delays for positive- and negative-going inputs.
500mV OVERDRIVE
INPUT VOLTAGE
5mV OVERDRIVE
± V
For applications that require high speed operation but do not
have on-chip 50 Ω termination resistors, some reflections
should be expected, because the comparator inputs can no
longer provide matched impedance to the input trace leading
up to the device. It then becomes important to back-match the
drive source impedance to the input transmission path leading
to the input to minimize multiple reflections. For applications
in which the comparator is less than 1 cm from the driving
signal source, the source impedance should be minimized. High
source impedance in combination with parasitic input capaci-
tance of the comparator could cause undesirable degradation
in bandwidth at the input, thus degrading the overall response.
It is therefore recommended that the drive source impedance
should be no more than 50 Ω for best high speed performance.
V
N
OS
DISPERSION
Q/Q OUTPUT
Figure 26. Propagation Delay—Overdrive Dispersion
INPUT VOLTAGE
1V/ns
V
± V
OS
N
10V/ns
DISPERSION
Q/Q OUTPUT
Figure 27. Propagation Delay—Slew Rate Dispersion
Rev. A | Page 12 of 16
ADCMP580/ADCMP581/ADCMP582
The hysteresis pin can also be driven by a current source.
It is biased approximately 400 mꢀ above ꢀEE and has an
internal series resistance of approximately 600 Ω.
80
COMPARATOR HYSTERESIS
Adding hysteresis to a comparator is often desirable in a noisy
environment or when the differential inputs are very small or
slow moving. The transfer function for a comparator with
hysteresis is shown in Figure 28. If the input voltage approaches
the threshold from the negative direction, the comparator
switches from a low to a high when the input crosses +ꢀH/2.
The new switching threshold becomes −ꢀH/2. The comparator
remains in the high state until the threshold −ꢀH/2 is crossed
from the positive direction. In this manner, noise centered on
0 ꢀ input does not cause the comparator to switch states unless
it exceeds the region bounded by ꢀH/2.
70
60
50
40
30
20
10
0
The customary technique for introducing hysteresis into a
comparator uses positive feedback from the output back to
the input. A limitation of this approach is that the amount
of hysteresis varies with the output logic levels, resulting in
hysteresis that is not symmetric about the threshold. The
external feedback network can also introduce significant
parasitics that reduce high speed performance and can even
reduce overall stability in some cases.
1
10
100
1k
10k
R
CONTROL RESISTOR (Ω)
HYS
Figure 29. Comparator Hysteresis vs. RHYS Control Resistor
MINIMUM INPUT SLEW RATE REQUIREMENT
As with many high speed comparators, a minimum slew rate
requirement must be met to ensure that the device does not
oscillate as the input signal crosses the threshold. This oscil-
lation is due in part to the high input bandwidth of the comparator
and the feedback parasitics inherent in the package. A
minimum slew rate of 50 ꢀ/μs should ensure clean output
transitions from the ADCMP58x family of comparators.
–V
2
+V
2
H
H
0V
INPUT
1
The slew rate may be too slow for other reasons. The extremely
high bandwidth of these devices means that broadband noise
can be a significant factor when input slew rates are low. There
is 120 ꢁꢀ of thermal noise generated over the bandwidth of the
comparator by the two 50 ꢂ terminations at room temperature.
With a slew rate of only 50 ꢀ/ꢁs, the inputs are inside this noise
band for over 2 ps, rendering the comparator’s jitter performance of
200 fs irrelevant. Raising the slew rate of the input signal and/or
reducing the bandwidth over which that resistance is seen at the
input can greatly reduce jitter. Devices are not characterized this
way but simply bypassing a reference input close to the package
can reduce jitter 30% in low slew rate applications.
0
OUTPUT
Figure 28. Comparator Hysteresis Transfer Function
The ADCMP58x family of comparators offers a programmable
hysteresis feature that can significantly improve the accuracy
and stability of the desired hysteresis. By connecting an external
pull-down resistor from the HYS pin to ꢀEE, a variable amount
of hysteresis can be applied. Leaving the HYS pin disconnected
disables the feature, and hysteresis is then less than 1 mꢀ, as
specified. The maximum range of hysteresis that can be applied
by using this method is approximately 70 mꢀ.
Figure 29 illustrates the amount of applied hysteresis as a
function of the external resistor value. The advantage of
applying hysteresis in this manner is improved accuracy,
stability, and reduced component count. An external bypass
capacitor is not required on the HYS pin, and it would likely
degrade the jitter performance of the device.
Rev. A | Page 13 of 16
ADCMP580/ADCMP581/ADCMP582
OUTLINE DIMENSIONS
0.50
0.40
0.30
3.00
BSC SQ
0.60 MAX
PIN 1
INDICATOR
*
1.65
13
12
16
1
0.45
1.50 SQ
1.35
PIN 1
TOP
2.75
BSC SQ
EXPOSED
PAD
INDICATOR
VIEW
(BOTTOM VIEW)
4
9
8
5
0.50
BSC
0.25 MIN
1.50 REF
0.80 MAX
12° MAX
0.65 TYP
0.90
0.85
0.80
0.05 MAX
0.02 NOM
SEATING
0.30
PLANE
0.20 REF
0.23
0.18
*
COMPLIANT TO JEDEC STANDARDS MO-220-VEED-2
EXCEPT FOR EXPOSED PAD DIMENSION.
Figure 30. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
3 mm × 3 mm Body, Very Thin Quad
(CP-16-3)
Dimensions shown in millimeters
ORDERING GUIDE
Model
Temperature Range
Package Description
16-Lead LFCSP_VQ
16-Lead LFCSP_VQ
16-Lead LFCSP_VQ
16-Lead LFCSP_VQ
16-Lead LFCSP_VQ
16-Lead LFCSP_VQ
16-Lead LFCSP_VQ
16-Lead LFCSP_VQ
16-Lead LFCSP_VQ
16-Lead LFCSP_VQ
16-Lead LFCSP_VQ
16-Lead LFCSP_VQ
16-Lead LFCSP_VQ
16-Lead LFCSP_VQ
16-Lead LFCSP_VQ
16-Lead LFCSP_VQ
16-Lead LFCSP_VQ
16-Lead LFCSP_VQ
Evaluation Board
Package Option
CP-16-3
CP-16-3
CP-16-3
CP-16-3
CP-16-3
CP-16-3
CP-16-3
CP-16-3
CP-16-3
CP-16-3
CP-16-3
CP-16-3
CP-16-3
CP-16-3
CP-16-3
CP-16-3
CP-16-3
CP-16-3
Branding
G07
G07
G07
G12
G12
G12
G09
G09
G09
G11
G11
G11
G0B
G0B
G0B
G10
G10
G10
ADCMP580BCP-WP
ADCMP580BCP–R2
ADCMP580BCP–RL7
ADCMP580BCPZ-WP1
ADCMP580BCPZ–R21
ADCMP580BCPZ–RL71
ADCMP581BCP-WP
ADCMP581BCP–R2
ADCMP581BCP–RL7
ADCMP581BCPZ-WP1
ADCMP581BCPZ–R21
ADCMP581BCPZ–RL71
ADCMP582BCP-WP
ADCMP582BCP-R2
ADCMP582BCP-RL7
ADCMP582BCPZ-WP1
ADCMP582BCPZ-R21
ADCMP582BCPZ-RL71
EVAL-ADCMP580BCPZ1
EVAL-ADCMP581BCPZ1
EVAL-ADCMP582BCPZ1
−±0°C to +125°C
−±0°C to +125°C
−±0°C to +125°C
−±0°C to +125°C
−±0°C to +125°C
−±0°C to +125°C
−±0°C to +125°C
−±0°C to +125°C
−±0°C to +125°C
−±0°C to +125°C
−±0°C to +125°C
−±0°C to +125°C
−±0°C to +125°C
−±0°C to +125°C
−±0°C to +125°C
−±0°C to +125°C
−±0°C to +125°C
−±0°C to +125°C
Evaluation Board
Evaluation Board
1 Z = RoHS Compliant Part.
Rev. A | Page 1± of 16
ADCMP580/ADCMP581/ADCMP582
NOTES
Rev. A | Page 15 of 16
ADCMP580/ADCMP581/ADCMP582
NOTES
©2005–2007 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D04672-0-8/07(A)
Rev. A | Page 16 of 16
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